Silicon (Si) Dry Etching for Die-Wafer Thinning
Dry etching with fluorine-containing plasma addresses the limitations of conventional thinning methods by selectively reducing die thickness to 30 μm or less, enhancing electrical and thermal performance and enabling 3D integration.
Patent Information
- Application Number
- JP2025536254
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-12-21
- Filing Date
- 2023-12-21
- Publication Date
- 2025-12-19
AI Technical Summary
Current chip-to-wafer bonding processes are limited to dies thicker than 30 μm due to handling limitations and high failure rates, leading to issues like die breakage and warpage, and conventional thinning methods such as grinding and CMP cause undesirable damage and yield loss.
A method involving dry etching with a fluorine-containing plasma is used to selectively thin the die relative to the substrate, utilizing SF6, CF4, or C4F8 plasma to achieve a removal rate of at least 1 μm/min, with protective layers preventing damage to metal pads and maintaining the substrate at low temperatures.
This method effectively thins dies to 30 μm or less while minimizing damage, achieving improved electrical and thermal performance and enabling 3D integration by selectively removing the die surface without contacting metal pads.
Smart Images
Figure 2025541560000001_ABST
Abstract
Description
[Technical Field]
[0001] TECHNICAL FIELD Embodiments of the present disclosure relate generally to the field of semiconductor manufacturing processes, and more particularly to processes for thinning a die engaged with a substrate. [Background technology]
[0002] Current chip-to-wafer bonding is typically limited to chips or dies having heights or thicknesses greater than about 30 micrometers (μm) due to limitations in processes or equipment for handling thin dies, including limitations in die ejection failures that cause die breakage, high inherent die stresses that cause die warpage that results in failure to bond the chip to the wafer, and other such limitations.
[0003] However, the inventors have recognized that bonding relatively thin die, e.g., less than 30 μm, may be desirable to provide improved electrical and thermal performance and to reduce form factors. Other improvements include stacking relatively thin die, e.g., stacking relatively thin die in a dual stack of SRAM memory to achieve 3D integration. However, technical challenges remain in achieving a thinned die chip-wafer structure.
[0004] The present inventors have recognized that the use of relatively thin dies, less than 30 μm, in chip-wafer bonding can be achieved by utilizing a thicker die bonded to a wafer or substrate, which may then be processed to achieve a thin top die. However, the present inventors have recognized that conventional thinning processes, such as grinding or chemical-mechanical polishing (CMP), can cause undesirable problems that lead to yield loss. For example, grinding exposes the die to high temperatures, pressures, and high mechanical shear forces that can cause chipping, cracking, and / or delamination of the die from the substrate. CMP has a relatively low removal rate of less than about 1 μm / min and high cost. CMP is also limited by damage that can occur to the polishing pad due to the topological aspects of the die.
[0005] Accordingly, the present inventors have provided an improved method for thinning a die bonded to a substrate. Summary of the Invention
[0006] Provided herein is a method for thinning a die engaged with a substrate, in an embodiment, the method for thinning a die engaged with a substrate includes dry etching a top surface of the die with a fluorine-containing plasma to selectively remove the top surface of the die relative to the top surface of the substrate.
[0007] In an embodiment, a method for thinning a chip bonded to a wafer substrate includes dry etching a top surface of the chip with a fluorine-containing plasma formed from SF, CF, CF, or a combination thereof in a processing chamber to selectively remove the top surface of the chip relative to a top surface of the wafer substrate, wherein the chip comprises silicon, at least a portion of the top surface of the wafer substrate includes a protective layer, at least one metal pad is completely embedded within the chip bonded to the wafer substrate, the at least one metal pad is disposed below the protective layer, or both, and the fluorine-containing plasma does not contact the metal pad during the dry etching process.
[0008] In an embodiment, a non-transitory computer-readable medium has instructions stored thereon that, when executed, cause a processing chamber to perform a method for thinning a die engaged with a substrate, the method including dry etching a top surface of the die with a plasma comprising fluorine to selectively remove the top surface of the die relative to the top surface of the substrate.
[0009] Other and additional embodiments of the present disclosure are described below.
[0010] Embodiments of the present disclosure, briefly outlined above and discussed in more detail below, can be understood by reference to exemplary embodiments thereof as illustrated in the accompanying drawings. However, the accompanying drawings depict only typical embodiments of the present disclosure and are therefore not to be considered limiting in scope, as the present disclosure may embrace other embodiments that are equally effective. [Brief explanation of the drawings]
[0011] [Figure 1] 1 is a flow diagram of a method of thinning a die engaged with a substrate, according to an embodiment of the present disclosure, comprising dry etching a top surface of the die with a fluorine-containing plasma to selectively remove the top surface of the die relative to the top surface of the substrate. [Figure 2] FIG. 1 is a schematic diagram of an etching chamber having a die engaged with a substrate according to an embodiment of the present disclosure. [Figure 3A] FIG. 2 illustrates a die engaged with a substrate prior to dry etching, according to an embodiment of the present disclosure. [Figure 3B] FIG. 1 illustrates a die engaged with a substrate after dry etching according to an embodiment of the present disclosure. [Figure 3C] FIG. 2 illustrates a die engaged with a substrate prior to dry etching, according to an embodiment of the present disclosure. [Figure 3D] FIG. 1 illustrates a die engaged with a substrate after dry etching according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0012] To facilitate understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without additional description.
[0013] In an embodiment, a method for thinning a die engaged with a substrate includes dry etching a top surface of the die with a fluorine-containing plasma to selectively remove the top surface of the die relative to the top surface of the substrate.
[0014] In an embodiment, the fluorine-containing plasma is formed from SF6, CF4, C4F8, or a combination thereof. In an embodiment, the top surface of the die is removed at a rate of about 1 μm / min or greater.
[0015] In an embodiment, the die engaged with the substrate is a chip bonded to a wafer, the chip having a thickness of about 50 μm or more before dry etching of the top surface of the die, and the die having a thickness of about 30 μm or less after dry etching of the top surface of the die. In an embodiment, more than 50 μm of the die thickness is removed. In an embodiment, the substrate is maintained at a temperature of about 80° C. or less during the dry etching of the top surface.
[0016] In embodiments, the substrate further includes a protective layer disposed over at least a portion of the substrate. In embodiments, the protective layer includes SiN, SiCN, oxygen-doped silicon nitride, a metal oxide layer, or a combination thereof. In embodiments, the protective layer includes an organic photoresist.
[0017] In an embodiment, the die is bonded to a dielectric layer comprising a metal oxide, SiCN, SiN, or a combination thereof disposed over a substrate, and in an embodiment, the dielectric layer is a protective layer that prevents a fluorine-containing plasma from dry etching a portion of the substrate underlying the dielectric layer.
[0018] In an embodiment, the ratio of the rate at which the top surface of the die is removed to the rate at which the top surface of the substrate is removed is about 100:1 or greater.
[0019] In an embodiment, the die, the substrate, or both, include metal pads, and in an embodiment, the fluorine-containing plasma does not contact any portion of the metal pads.
[0020] In an embodiment, a method for thinning a chip bonded to a wafer substrate includes dry etching a top surface of the chip with a fluorine-containing plasma formed from SF, CF, C4F, or a combination thereof in a processing chamber to selectively remove the top surface of the chip relative to a top surface of the wafer substrate, wherein the chip comprises silicon, at least a portion of the top surface of the wafer substrate includes a protective layer, at least one metal pad is completely embedded in the chip bonded to the wafer substrate, the at least one metal pad is disposed below the protective layer, or both, and the fluorine-containing plasma does not contact the metal pad. In an embodiment, the protective layer includes SiN, SiCN, oxygen-doped silicon nitride, a metal oxide, or a combination thereof. In an embodiment, the protective layer includes photoresist.
[0021] In embodiments, the top surface of the chip is removed at a rate of about 1 μm / min or greater, and in embodiments, the chip has a thickness of about 50 μm or greater before dry etching the top surface of the chip with a fluorine-containing plasma, and the chip has a thickness of about 30 μm or less after dry etching the top surface of the chip.
[0022] In an embodiment, more than 50 μm of the thickness of the chip is removed during the method of thinning the chip bonded to the wafer substrate. In an embodiment, the wafer substrate is maintained at a temperature of about 80° C. or less.
[0023] The method is not limited by the method of bonding the die to the substrate, which may include direct bonding such as fusion bonding, which may include plasma activated fusion bonding, various hybrid bonding methods, anodic bonding, covalent wafer bonding, and / or the like.
[0024] 1 is a flow diagram of a method 100 according to an embodiment. In some implementations, the method 100 of FIG. 1 may be performed by an apparatus.
[0025] As shown in FIG. 1, method 100 may include dry etching top surface 33 of die 32 (see FIG. 2) with a plasma including fluorine radicals 54 to selectively remove top surface 33 of die 32 relative to the top surface of substrate 34 (block 102).
[0026] Although FIG. 1 illustrates exemplary blocks of method 100, in some implementations, method 100 may include additional blocks beyond those illustrated in FIG.
[0027] In an embodiment, method 100 (see FIG. 1 ) utilizes a plasma containing fluorine radicals that etch the silicon layer of the die at a much faster rate than silicon oxide or silicon nitride or other material on the surface of the substrate. Thus, the dry etch rate of the silicon surface of the die is much faster than the dry etch rate of the substrate. In an embodiment, the substrate may include an upper surface that includes a protective or passivation layer that has a relatively low etch rate compared to silicon in a plasma containing fluorine radicals.
[0028] FIG. 2 is a schematic diagram of an etching chamber having a die engaged with a substrate according to an embodiment of the present disclosure. As shown in FIG. 2, substrate 30 may be any suitable substrate for use in a semiconductor article and may include one or more of silicon (Si), silicon oxide (SiO), or the like. One or more die 32 are engaged with, e.g., bonded to, the substrate. In embodiments, multiple die 32 are bonded to substrate 30. In embodiments, die 32 are chips and substrate 30 is a wafer. In embodiments, substrate 30 may include multiple layers or consist essentially of a dielectric layer. In some embodiments, this dielectric layer may be disposed over one or more additional dielectric layers (not shown), such as silicon oxide, silicon nitride, silicon carbide, or the like.
[0029] In addition, substrate 30 may include additional layers of material or may have one or more completed or partially completed structures or devices formed in or on the substrate, such as one or more metal pads 38 disposed in the substrate. In some embodiments, a layer, such as a logic device or the like, or a portion of a device requiring electrical connectivity, such as a gate, a contact pad, a conductive line or via, or the like, may be disposed in substrate 30 and may be aligned with one or more features. As used herein, a "layer" need not be a continuous structure extending across the entire surface of substrate 30.
[0030] In embodiments, the substrate 30 may be, for example, a doped or undoped silicon substrate, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electroluminescent (EL) lamp display, a light emitting diode (LED) substrate, a solar cell array, a solar panel, or the like. In some embodiments, the substrate 30 may be a semiconductor wafer.
[0031] The substrate 30 is not limited to a particular size or shape. The substrate can be a circular wafer having a 200 mm diameter, a 300 mm diameter, or other diameter, such as 450 mm, among others. The substrate can also be any polygonal, square, rectangular, curved, or other shaped non-circular workpiece, such as a polygonal glass substrate used in the manufacture of flat panel displays.
[0032] 2, the etching process may include placing a substrate 30 including at least one die 32 bonded to a top surface 34 of the substrate 30 in a process chamber 52 and introducing a plasma including fluorine radicals 54 into an etching zone 50, and in embodiments, placing the substrate 30 in the process chamber 52 may include placing the substrate 30 on a carrier 60 or a chuck in the etching zone 50. In embodiments, the plasma including fluorine radicals 54 may be generated outside the process chamber 52, for example, by a remote plasma source 58 supplying a remote plasma including a fluorine-containing gas 59, or the plasma including fluorine radicals 54 may be generated inside the process chamber 52, for example, as an inductively coupled plasma (ICP) generated by process electrodes 56 a and 56 b. In embodiments, a plasma including fluorine radicals 54 is generated from a fluorine-containing gas 59 such as SF, CF, NF, C4F, CHF, and / or the like, which in embodiments may further include a diluent gas or gas mixture such as argon, nitrogen, helium, and / or the like.
[0033] In an embodiment, a plasma containing fluorine radicals 54 is maintained by passing a current having a frequency of about 400 kHz to about 15 MHz at a power level of about 50 Watts to about 2000 Watts to process electrodes 56a and 56b disposed around the etching zone 50. During the etching process, the substrate 30 is maintained at a temperature of about 80°C or less, or about 75°C or less, or about 70°C or less, or about 60°C or less, and about 20°C or more, or about 30°C or more, for example, a temperature of about 20°C to about 80°C.
[0034] In embodiments, the plasma containing fluorine radicals 54 etches the top surface 33 of the die 32 at a removal rate that is about 100:1 or more, or about 500:1 or more, or about 1000:1 or more, or about 5000:1 or more relative to the rate at which the top surface of the substrate 34 is removed.
[0035] In embodiments, the top surface 33 of the die 32 is removed at a rate of about 1 μm / min or greater, or about 1.5 μm / min or greater, or about 3 μm / min or greater, or about 5 μm / min or greater, or about 10 μm / min or greater.
[0036] In embodiments, more than 50 μm, or more than 100 μm, or more than 150 μm of thickness 36 of die 32 is removed.
[0037] In an embodiment, the die 32, the substrate 34, or both may include at least one metal pad 38. To prevent the plasma containing fluorine radicals 54 from contacting any portion of the metal pad 38 during dry etching of the substrate, in an embodiment, the metal pad 38 disposed within the substrate 30 is covered by a protective layer 40, as shown in FIG.
[0038] Figure 3A shows a die 33 engaged with a substrate 30 before a dry etching process, and Figure 3B shows the same die 33 engaged with the same substrate 30 as shown in Figure 3A after the dry etching process, according to one embodiment. In an embodiment, as shown in Figure 3A, the die 32 has an initial thickness 36 of about 50 μm or more, or about 70 μm or more, or about 100 μm or more, or about 200 μm or more before dry etching of the top surface 33 of the die 32 with a plasma including fluorine radicals 54, and as shown in Figure 3B, the die 32 has a thickness 36 of about 30 μm or less (also shown in Figure 2 by distance 37) after dry etching of the top surface 33 of the die 32.
[0039] 3C shows an embodiment in which the top surface of substrate 34 and sidewalls of 32 include a protective layer 40 comprising SiN, SiCN, oxygen-doped silicon nitride, a metal oxide other than silicon dioxide, or a combination thereof to prevent lateral Si removal during an isotropic Si etch. In another embodiment, the top surface of substrate 34 has a protective layer comprising an organic material, such as photoresist, to prevent removal of the top surface of substrate 34 during an anisotropic protective layer etch. As shown in FIG. 3D, die 32 has a thickness of about 30 μm or less after dry etching of top surface 33 of die 32.
[0040] The methods described herein may be performed in individual etch chambers, such as ICP plasma etch chambers, which may be provided in stand-alone configurations or as part of a cluster tool. Examples of processing chambers that may be adapted to benefit from embodiments of the present disclosure include the Sym3® Processing Chamber available from Applied Materials, Inc., Santa Clara, California.
[0041] Embodiment According to embodiments of the present disclosure, at least the following embodiments are contemplated. E1. A method of thinning a die engaged with a substrate, comprising dry etching a top surface of the die with a fluorine-containing plasma to selectively remove the top surface of the die relative to the top surface of the substrate. E2. The method of embodiment E1, wherein the fluorine-containing plasma is formed from SF6, CF4, C4F8, or a combination thereof, and the top surface of the die is removed at a rate of about 1 μm / min or greater. E3. The method of embodiment E1 or E2, wherein the die engaged with the substrate is a chip bonded to a wafer, the chip having a thickness of about 50 μm or more before dry etching of the top surface of the die, and the die having a thickness of about 30 μm or less after dry etching of the top surface of the die. E4. The method of any one of embodiments E1-E3, wherein more than 50 μm of the die thickness is removed. E5. The method of any one of embodiments E1-E4, wherein the substrate is maintained at a temperature of about 80° C. or less during the top surface dry etching. E6. The method of any one of embodiments E1-E5, wherein the substrate further comprises a protective layer disposed over at least a portion of the substrate. E7. The method of embodiment E6, wherein the protective layer comprises SiN, SiCN, oxygen-doped silicon nitride, a metal oxide layer, or a combination thereof. E8. The method of embodiment E6 or E7, wherein the protective layer comprises an organic photoresist. E9. The method of any one of embodiments E1-E8, wherein the die is bonded to a dielectric layer comprising a metal oxide, SiCN, SiN, or a combination thereof disposed over the substrate, and the dielectric layer is a protective layer that prevents the fluorine-containing plasma from dry etching a portion of the substrate underlying the dielectric layer. E10. The method of any one of embodiments E1-E9, wherein the ratio of the rate at which the top surface of the die is removed to the rate at which the top surface of the substrate is removed is greater than or equal to about 100:1. E11. The method of any one of embodiments E1-E10, wherein the die, the substrate, or both, include metal pads, and wherein the fluorine-containing plasma does not contact any portion of the metal pads. E12. A method for thinning a chip bonded to a wafer substrate, comprising: dry etching the top surface of the chip with a fluorine-containing plasma formed from SF, CF, CF, or a combination thereof in a processing chamber to selectively remove the top surface of the chip relative to the top surface of the wafer substrate; the chip comprises silicon; at least a portion of the top surface of the wafer substrate includes a protective layer; at least one metal pad is completely embedded within a chip bonded to a wafer substrate, at least one metal pad is disposed beneath a protective layer, or both; The method does not involve contact of the fluorine-containing plasma with the metal pad. E13. The method of embodiment E12, wherein the protective layer comprises SiN, SiCN, oxygen-doped silicon nitride, a metal oxide, or a combination thereof. E14. The method of embodiment E12 or E13, wherein the protective layer comprises a photoresist. E15. The method of embodiments E12-E14, wherein the top surface of the tip is removed at a rate of about 1 μm / min or greater. E16. The method of any one of embodiments E12-E15, wherein the chip has a thickness of about 50 μm or more before dry etching of the top surface of the chip with a plasma comprising fluorine, and the chip has a thickness of about 30 μm or less after dry etching of the top surface of the chip. E17. The method of embodiments E12-E16, wherein more than 50 μm of the thickness of the chip is removed. E18. The method of any one of embodiments E12-E17, wherein the wafer substrate is maintained at a temperature of about 80° C. or less. E19. A non-transitory computer-readable medium having instructions stored thereon that, when executed, cause a processing chamber to perform the method of embodiments E1-E18 for thinning a die engaged with a substrate. E20. The substrate-engaged die is a chip bonded to a wafer substrate; the fluorine-containing plasma is formed from SF6, CF4, C4F8, or a combination thereof; the chip comprises silicon; at least a portion of the top surface of the wafer substrate includes a protective layer; at least one metal pad is completely embedded within a chip bonded to a wafer substrate, at least one metal pad is disposed beneath a protective layer, or both; The non-transitory computer-readable medium of embodiment E19, wherein the fluorine-containing plasma does not contact the metal pads.
[0042] The present disclosure may be practiced using other semiconductor substrate processing systems, and those skilled in the art, using the teachings disclosed herein, may adjust process parameters to achieve acceptable performance without departing from the spirit of the present disclosure. While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof.
Claims
1. 1. A method for thinning a die engaged with a substrate, comprising: dry etching the top surface of the die with a fluorine-containing plasma to selectively remove the top surface of the die relative to the top surface of the substrate; A method comprising:
2. The fluorine-containing plasma is SF 6 , C.F. 4 , C 4 F 8 10. The method of claim 1, wherein the top surface of the die is formed from a molten metal, ... lead, or a combination thereof, and the top surface of the die is removed at a rate of about 1 μm / min or greater.
3. 10. The method of claim 1, wherein the die engaged with the substrate is a wafer-bonded chip, the chip having a thickness of about 50 μm or more before the dry etching of the top surface of the die, and the die having a thickness of about 30 μm or less after the dry etching of the top surface of the die.
4. The method of claim 1 , wherein more than 50 μm of the thickness of the die is removed.
5. The method of claim 1 , wherein the substrate is maintained at a temperature of about 80° C. or less during the dry etching of the top surface.
6. The method of claim 1 , wherein the substrate further comprises a protective layer disposed over at least a portion of the substrate.
7. The method of claim 6 , wherein the protective layer comprises SiN, SiCN, oxygen-doped silicon nitride, a metal oxide layer, or a combination thereof.
8. The method of claim 6 , wherein the protective layer comprises an organic photoresist.
9. 10. The method of claim 1, wherein the die is bonded to a dielectric layer disposed over the substrate, the dielectric layer comprising a metal oxide, SiCN, SiN, or a combination thereof, the dielectric layer being a protective layer that prevents the plasma comprising fluorine from dry etching a portion of the substrate underlying the dielectric layer.
10. 10. The method of claim 1, wherein the ratio of the rate at which the top surface of the die is removed to the rate at which the top surface of the substrate is removed is about 100:1 or greater.
11. 10. The method of claim 1, wherein the die, the substrate, or both, include metal pads, and the plasma comprising fluorine does not contact any portion of the metal pads.
12. 1. A method for thinning a chip bonded to a wafer substrate, comprising: In the processing chamber, SF 6 , C.F. 4 , C 4 F 8 or a combination thereof to selectively remove the top surface of the chip relative to the top surface of the wafer substrate; the chip comprises silicon; at least a portion of the top surface of the wafer substrate and / or the die sidewalls comprises a protective layer; at least one metal pad is completely embedded within the chip bonded to the wafer substrate, at least one metal pad is disposed beneath the protective layer, or both; the fluorine-containing plasma does not come into contact with metal pads; method.
13. 13. The method of claim 12, wherein the protective layer comprises SiN, SiCN, oxygen-doped silicon nitride, a metal oxide, or a combination thereof.
14. The method of claim 12 , wherein the protective layer comprises a photoresist.
15. The method of claim 12, wherein the top surface of the tip is removed at a rate of about 1 μm / min or greater.
16. 13. The method of claim 12, wherein the tip has a thickness of about 50 μm or more before the dry etching of the top surface of the tip with the plasma comprising fluorine, and the tip has a thickness of about 30 μm or less after the dry etching of the top surface of the tip.
17. The method of claim 12 wherein more than 50 μm of the thickness of the chip is removed.
18. The method of claim 12 , wherein the wafer substrate is maintained at a temperature of about 80° C. or less.
19. 12. A non-transitory computer readable medium having instructions stored thereon that, when executed, cause a processing chamber to perform a method according to any one of claims 1 to 11 for thinning a die engaged with a substrate.
20. 19. A non-transitory computer readable medium having instructions stored thereon that, when executed, cause a processing chamber to perform a method according to any one of claims 12 to 18 for thinning a chip bonded to a wafer substrate.