Calibration of quadrature receiver serial interface

Abstract

An improved quadrature receiver serial interface circuit and a method for calibrating a quadrature receiver serial interface circuit are provided. The quadrature receiver serial interface circuit includes a first phase rotator and a second phase rotator that generate quadrature clocks of the same frequency. Calibration of the quadrature receiver serial interface circuit uses a pseudorandom bit sequence (PRBS) received by the quadrature receiver serial interface circuit. During calibration, half of the received PRBS bits are sampled, and the phase rotators that generate in-phase 0-degree and 180-degree clock signals are adjusted to center the data eyes of the sampled half of the PRBS bits. Then, all data bits (even and odd data bits) of the received PRBS bits are sampled, and the phase rotators that generate quadrature 90-degree and 270-degree clock signals are adjusted to center the data eyes of all data bits of the PRBS bits to complete the calibration (see FIG. 2B).

Description

[Background technology]

[0001] The present invention relates to digital data processing, and more particularly to a method for calibrating a quadrature receiver serial interface circuit for a high-speed chip-to-chip serial communication system, and to a quadrature receiver serial interface circuit.

[0002] In high-speed chip-to-chip communications, quadrature sampling reduces the speed requirements of data samplers in the receive interface, allowing the receive interface to run faster. One problem associated with using quadrature data sampling is the difficulty of aligning with the quadrature clock. Another problem is that current quadrature receiver serial interface circuits use IQ generators, which typically require significant power, to provide the quadrature clocks. Also, the received data may experience different delays for even and odd bits due to transmitter duty cycle or other transmitter architecture imperfections. A new technique for calibrating quadrature receiver serial interface circuits is needed that can compensate for variations in the received data caused by static and dynamic factors, such as supply voltage, operating temperature, and the like. Summary of the Invention

[0003]

[0003] Embodiments of the present disclosure are directed to an improved quadrature receiving serial interface circuit and a method for calibrating the quadrature receiving serial interface circuit. The quadrature receiving serial interface circuit includes a first phase rotator and a second phase rotator that generate four quadrature clocks of the same frequency, where the first phase rotator generates in-phase 0-degree and 180-degree clock signals and the second phase rotator generates quadrature 90-degree and 270-degree clock signals. The in-phase 0-degree and 180-degree clock signals are provided to a first pair of first sampling latches, and the quadrature 90-degree and 270-degree clock signals are provided to a second pair of first sampling latches. The quadrature receiving serial interface circuit includes a pseudo random bit sequence (PRBS) checker.

[0004] A non-limiting method of one disclosed embodiment implements calibration of a quadrature receiver serial interface circuit. A pseudorandom bit sequence (PRBS) is transmitted to the quadrature receiver serial interface circuit to calibrate the quadrature receiver serial interface circuit. A PRBS checker of the quadrature receiver serial interface is configured to sample every other bit or half of the received PRBS data bits, for example, the even data bits of the PRBS. A first phase rotator, which generates in-phase 0-degree and 180-degree clock signals, is adjusted using the PRBS checker to center the data eye of the even data bits of the PRBS. The PRBS checker is then configured to sample all (even and odd) data bits of the PRBS. A second phase rotator, which generates quadrature 90-degree and 270-degree clock signals, is adjusted to center the data eye of all data bits of the PRBS. After calibration, a functional data stream is transmitted to the quadrature receiver serial interface circuit for normal data communication. [Brief explanation of the drawings]

[0005] [Figure 1]1 is a block diagram of an exemplary computing environment for use in conjunction with one or more embodiments for calibrating a quadrature receiving serial interface circuit;

[0006] [Figure 2A] providing a schematic block diagram illustrating one or more embodiment communication circuits for calibration of a quadrature receiving serial interface circuit; [Figure 2B] providing a schematic block diagram illustrating one or more embodiment communication circuits for calibration of a quadrature receiving serial interface circuit;

[0007] [Figure 3] 1 is a flowchart illustrating an exemplary operation of one or more embodiments for calibration of a quadrature receiving serial interface circuit; and

[0008] [Figure 4] 10 is a flowchart illustrating exemplary operational functions of one or more embodiments for calibration of a quadrature receiving serial interface circuit. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0006] Embodiments of the present disclosure provide an improved quadrature receiving serial interface circuit and a method for calibrating a quadrature receiving serial interface circuit. In one embodiment, the quadrature receiving serial interface circuit includes a first phase rotator and a second phase rotator that generate four quadrature clocks of the same frequency, where the first phase rotator generates in-phase 0-degree and 180-degree clock signals and the second phase rotator generates quadrature 90-degree and 270-degree clock signals. The in-phase 0-degree and 180-degree clock signals are provided to a first pair of first sampling latches, and the quadrature 90-degree and 270-degree clock signals are provided to a second pair of first sampling latches. Sampled data bits of the first sampling latches are provided to a deserializer and synchronized to the 0-degree phase. The quadrature receiving serial interface circuit includes a pseudorandom bit sequence (PRBS) checker coupled to the deserializer. The PRBS checker allows calibration of the quadrature receiver serial interface circuitry without requiring complex calibration pattern generation, extra circuitry, or modification of the PRBS or PRBS checker.

[0010] An improved method for calibrating a quadrature receiver serial interface circuit is provided, including transmitting a PRBS to the quadrature receiver serial interface circuit to calibrate the quadrature receiver serial interface circuit. A PRBS checker is configured to sample even data bits of the received PRBS. A first phase rotator, which generates in-phase 0-degree and 180-degree clock signals, is adjusted using the PRBS checker to center the data eyes of the even data bits of the PRBS. In one embodiment, the PRBS checker is configured to sample all (even and odd) data bits of the PRBS. In one embodiment, a second phase rotator, which generates quadrature 90-degree and 270-degree clock signals, is adjusted using the PRBS checker to center the data eyes of all data bits of the PRBS to complete the calibration. After calibration, a functional data stream is sent to the quadrature receiver serial interface circuit for normal data communication.

[0011] Some non-limiting advantages of the present disclosure include an improved quadrature receiver serial interface circuit that includes a pair of phase rotators that generate four quadrature clocks of the same frequency, with one phase rotator generating in-phase 0-degree and 180-degree clock signals and the other phase rotator generating quadrature 90-degree and 270-degree clock signals. The improved quadrature receiver serial interface circuit eliminates the need for an IQ generator in the receiver that generates the four quadrature clocks, reducing power requirements. The improved quadrature receiver serial interface circuit effectively and efficiently generates the four quadrature clocks using a pair of phase rotators. Calibration of the quadrature receiver serial interface circuit is based on sampled data bits of a received PRBS to compensate for fluctuations in the received data. In one embodiment, calibration of the quadrature receiver serial interface circuit includes first adjusting the phase rotators that generate the in-phase 0-degree and 180-degree clock signals to center the data eye based on half of the received PRBS bits, e.g., the even data bits of the received PRBS bits. The phase rotator, which generates quadrature 90-degree and 270-degree clock signals, is then adjusted to center the data eyes of all data bits (even and odd data bits) of the PRBS bits. Calibration of the quadrature receiver serial interface circuit uses a PRBS and a PRBS checker without requiring complex pattern generation. Calibration of the quadrature receiver serial interface circuit can be provided at power-on and dynamically, enabling effective and reliable operation of the quadrature receiver serial interface circuit. The quadrature receiver serial interface circuit eliminates the need for a conventional IQ generator in the receiver to provide the quadrature clock, significantly reducing power requirements.

[0012] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0013] Reference will be made below to the embodiments presented in this disclosure. However, the scope of the disclosure is not limited to the specific embodiments described. Instead, any combination of the following features and elements, whether associated with different embodiments, is contemplated for implementing and practicing the discussed embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of the disclosure. Accordingly, the following aspects, features, embodiments, and advantages are merely exemplary and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, references to "the present invention" should not be construed as a generalization of any inventive subject matter disclosed herein, nor should they be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0014] Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0015] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively contained in one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the above. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as pits / lands formed on the major surface of a punch card or disk), or any suitable combination of the above. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device transitory since the data is not transitory while it is stored.

[0016] 1 , a computing environment 100 includes an example environment for executing at least a portion of the computer code involved in performing the inventive method, such as a quadrature receiver serial interface calibration control component 182 in block 180. In addition to block 180, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a set of processors 110 (including processing circuitry 120 and cache 121), a communications fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 180 shown above), a set of peripheral devices 114 (including a set of user interface (UI) devices 123, storage 124, and a set of Internet of Things (IoT) sensors 125), and a network module 115. Remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0017] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 130. As is well understood in the field of computer technology, and depending on that technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. However, in this description of computing environment 100, for purposes of brevity, the detailed discussion focuses on a single computer, specifically computer 101. Although computer 101 is not shown in FIG. 1 within a cloud, it may be located within a cloud. However, computer 101 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0018] Processor set 110 includes one or more computer processors of any type now known or later developed. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple linked integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 110. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0019] Computer-readable program instructions are typically loaded onto computer 101 and cause processor set 110 of computer 101 to perform a series of operational steps, thereby realizing a computer-implemented method, such that the instructions so executed instantiate the method specified in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media described below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least some of the instructions for performing the methods of the present invention may be stored in block 180 within persistent storage 113.

[0020] Communications fabric 111 is the signal-conducting pathway that allows various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0021] Volatile memory 112 may be any type of volatile memory now known or later developed. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, although this is not required unless expressly stated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0022] Persistent storage 113 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data is maintained regardless of whether power is supplied to computer 101 and / or directly to persistent storage 113. While persistent storage 113 may be read-only memory (ROM), typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems employing a kernel or open-source Portable Operating System Interface-type operating systems. The code contained in block 180 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0023] Peripheral device set 114 includes a set of peripheral devices of computer 101. Data communication connections between peripheral devices and other components of computer 101 may be implemented in various forms, such as Bluetooth connections, near field communication (NFC) connections, connections made by cables (such as universal serial bus (USB)-type cables), insertion-type connections (e.g., Secure Digital (SD) cards), connections made through local area communication networks, and even connections made through wide area networks such as the Internet. In various embodiments, UI device set 123 may include components such as display screens, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 124 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (e.g., where computer 101 stores and manages a large database locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple, geographically distributed computers. IoT sensor set 125 consists of sensors that may be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0024] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software-Defined Networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention may be downloaded to computer 101 from an external computer or external storage device, typically through a network adapter card or network interface included in network module 115.

[0025] WAN 102 is any now known or later developed wide area network (e.g., the Internet) capable of communicating computer data between remote locations via any technology for communicating computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0026] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and may take any of the forms described above with respect to computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in a hypothetical case where computer 101 is designed to provide recommendations to the end user, the recommendations would typically be communicated from network module 115 of computer 101 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, and the like.

[0027] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 101 from remote database 130 of remote server 104.

[0028] A public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, particularly data storage (cloud storage) and computing capacity, without requiring direct, active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct, active management of the computing resources of the public cloud 105 is performed by computer hardware and / or software in a cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers comprising a host physical machine set 142, which is a universe of physical computers within and / or available to the public cloud 105. A virtual computing environment (VCE) typically takes the form of a virtual machine from a virtual machine set 143 and / or a container from a container set 144. It will be appreciated that these VCEs may be stored as images and may be transferred among and between various physical machine hosts, either as images or after instantiation of the VCE. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCE, and manages active instantiations of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that enables public cloud 105 to communicate over WAN 102.

[0029] Here, we provide some further explanation of virtualized computing environments (VCEs). A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances called containers. These isolated user space instances typically act as actual computers from the perspective of the programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as attached devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and the devices assigned to the container; this feature is known as containerization.

[0030] A private cloud 106 is similar to a public cloud 105, except that the computing resources are available only for use by a single enterprise. While the private cloud 106 is shown in communication with the WAN 102, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0031]

[0006] Embodiments of the present disclosure provide an improved quadrature receiver serial interface circuit for a communications interconnect system and a method for calibrating the quadrature receiver serial interface circuit. The improved quadrature receiver serial interface circuit includes a first phase rotator and a second phase rotator that generate four quadrature clocks of the same frequency. For example, the first phase rotator generates in-phase 0-degree and 180-degree clock signals, and the second phase rotator generates quadrature 90-degree and 270-degree clock signals. The quadrature receiver serial interface circuit has a data sampler including a plurality of first sampling latches. The quadrature receiver serial interface circuit includes a PRBS checker used to calibrate the quadrature receiver serial interface circuit for receiving a pseudorandom bit sequence (PRBS). The in-phase 0-degree and 180-degree clock signals are provided to a first pair of first sampling latches, and the quadrature 90-degree and 270-degree clock signals are provided to a second pair of first sampling latches. A pseudorandom bit sequence (PRBS) is transmitted to the quadrature receiving serial interface circuit to calibrate the quadrature receiving serial interface circuit. The calibration of the quadrature receiving serial interface circuit is based on sampled data bits of the received PRBS, and can compensate for fluctuations in the received data.

[0032] An improved method for calibrating a quadrature receiver serial interface circuit includes transmitting a pseudorandom bit sequence (PRBS) to be received by the quadrature receiver serial interface circuit. A phase rotator generating in-phase 0-degree and 180-degree clock signals is adjusted to center a data eye based on sampled half or every other bit of the received PRBS bits, e.g., the even data bits of the received PRBS bits. Then, a phase rotator generating quadrature 90-degree and 270-degree clock signals is adjusted to center the data eye of all data bits (even and odd data bits) of the PRBS bits. Calibration of the quadrature receiver serial interface circuit uses a PRBS and PRBS checker without requiring complex pattern generation. Calibration of the quadrature receiver serial interface circuit can be provided at power-on and dynamically, enabling effective and reliable functional operation of the quadrature receiver serial interface circuit. After calibration is complete, a functional data stream is transmitted to the quadrature receiver serial interface circuit for normal data communication.

[0033] 2A and 2B together illustrate an exemplary communications interconnect system 200 configured to implement calibration of the quadrature receiver serial interface circuit 206 of the disclosed embodiments. The communications interconnect system 200 enables high-speed chip-to-chip communications using quadrature sampling, reducing the speed requirements of the data sampler of the quadrature receiver serial interface circuit 206. The communications system 200 can be used, for example, in combination with the computer 101 and the quadrature receiver serial interface calibration control component 182 of FIG. 1 to implement the calibration control operations of the disclosed methods.

[0034] The communications interconnect system 200 includes a transmit serial interface circuit 204 and a quadrature receive serial interface circuit 206 connected by a bus 216 (e.g., a double data rate (DDR) bus). The transmit serial interface circuit 204 includes a clock divider and resynchronizer (Resync) 208 that receives an interface input C2 clock 209. The transmit serial interface circuit 204 includes an N:2 serializer 210 that receives and serializes parallel inputs to provide respective even and odd serial data inputs to a multiplexer 212. The clock divider and resynchronizer 208 provides a divided clock to the serializer 210 and a C2 clock Resync to the multiplexer 212. In one embodiment, a data driver 214 operating at double data rate (DDR) transfers data to the bus 216 on both the rising and falling edges of the C2 clock Resync signal. The DDR serial data transfers of the data driver 214 to the DDR bus 216 are received by the quadrature receive serial interface circuit 206. Interface input C2 clock 209 transmits the C2 clock signal via clock driver 217 and clock interface link or clock bus 218 to termination and divide-by-2 circuit 220. Clock termination and divide-by-2 circuit 220 provides a divided clock input to quadrature receive serial interface circuit 206.

[0035] For example, interface input C2 clock 209 provides a 20 GHz clock signal to clock divider and resynchronizer 208 of transmit serial interface circuit 204, which provides a divided clock input of the 10 GHz clock signal to serializer 210 and a 20 GHz C2 clock Resync signal to multiplexer 212. Interface input C2 clock 209 also provides a 20 GHz clock signal to termination and divide-by-2 circuit 220, which provides divided clock signal inputs of the in-phase and quadrature input (I+Q) clocks of the 10 GHz clock signal to quadrature receive serial interface circuit 206.

[0036] 2B, the quadrature receiving serial interface circuit 206 includes a termination and equalizer 226 connected to the bus 216. The termination and equalizer 226 receives and equalizes the serial data transfer from the driver 214 via the bus 216. The quadrature receiving serial interface circuit 206 includes a first phase rotator 228 and a second phase rotator 230 that receive the in-phase and quadrature input I+Q clocks input from the external termination and divide-by-two circuit 220.

[0037] The first phase rotator 228 and the second phase rotator 230 generate four quadrature clock signals of the same frequency, with the first phase rotator 228 generating in-phase 0-degree and 180-degree clock signals and the second phase rotator 230 generating quadrature 90-degree and 270-degree clock signals used for data sampling. A quadrature receive serial interface data sampler includes first sampling latches 232, #0-3 (one latch for each bit), which receive the quadrature 0-degree, 90-degree, 180-degree, and 270-degree clock signals, respectively. The sampled data bits of the first sampling latches are coupled to a deserializer 236, where, in one embodiment, all data bits are resynchronized to the 0-degree phase. The DDR serial data transfer from the data driver 214 received by the termination and equalizer 226 is provided to respective first sampling latches 232, #0-3, which receive quadrature 0 degree, 90 degree, 180 degree, and 270 degree clock signals, respectively.

[0038] As shown, the in-phase 0-degree and 180-degree clock signals of the first phase rotator 228 are applied to a first pair of even sampling latches 232, #0 and #2. The quadrature 90-degree and 270-degree clock signals of the second phase rotator 230 are applied to a second pair of odd sampling latches 232, #1 and #3. A deserializer 236 receives the sampled data bits of each of the first sampling latches at their respective data inputs, resynchronizes them to the 0-degree phase, and provides parallel output data. The quadrature receiver serial interface circuit includes a PRBS checker 238 coupled to the deserializer 236, which receives the PRBS output data during calibration. During calibration, the PRBS checker 238 checks for valid parallel PRBS output data received from the deserializer 236. The PRBS checker 238 is used during calibration to center a valid data eye of the sampled PRBS data bits.

[0039] During calibration, a PRBS is input to the serializer 210 and received by the quadrature receiver serial interface circuit 206. A first phase rotator 228, which generates in-phase 0-degree and 180-degree clock signals, is adjusted using a PRBS checker 238 to center the data eye of the first sampled half of the data bits of the PRBS, e.g., the even data bits of the PRBS. In one embodiment, after adjusting the first phase rotator 228, the PRBS checker 238 is set by the calibration control component 182 to sample all (both even and odd) data bits of the PRBS. A second phase rotator 230, which generates quadrature 90-degree and 270-degree clock signals, is adjusted using the PRBS checker 238 to center the data eye of all data bits of the PRBS. Then, once calibration is complete, the data stream is transmitted to the quadrature receiver serial interface circuit 206 for normal data communication.

[0040] 3 , exemplary operational functions of a method 300 of one or more embodiments for calibrating the quadrature receiving serial interface circuit 206 are shown. In block 302, a PRBS pattern for calibrating the quadrature receiving serial interface circuit is provided, and the calibration control component 182 configures the quadrature receiving serial interface circuit 206 to sample only half the data bits of the PRBS, e.g., the even data bits of the PRBS. For example, the PRBS checker 238 is configured by the calibration control component 182 to sample only half the data bits of the PRBS, e.g., the even data bits of the PRBS. The sampled half data bits of the PRBS provide a valid PRBS pattern and can save time required to adjust the first phase rotator 228. In block 304, the calibration control component 182 uses input from the PRBS checker 238 to adjust the first phase rotator 228, which generates in-phase 0-degree and 180-degree clock signals, to center the data eye of the sampled in-phase half data bits of the PRBS.

[0041] For example, the PRBS checker identifies good data at a first edge of the data eye, and the calibration control component 182 adjusts the first phase rotator 228 through the data eye to other edges of the data eye. The calibration control component 182 uses input from the PRBS checker 238 in block 304 to set the first phase rotator 228 to the center of the data eye for the good data. In one embodiment, the second phase rotator 230, which generates the quadrature 90-degree and 270-degree clock signals, is not adjusted in block 304.

[0042] In block 306, the calibration control component 182 configures the PRBS checker 238 of the quadrature receiver serial interface circuit 206 to sample all data bits of the PRBS. For example, the PRBS checker 238 is configured by the calibration control component 182 to sample all (both even and odd) data bits of the PRBS in block 306. In block 308, the PRBS checker 238 uses the input from the PRBS checker 238 to adjust the second phase rotator 230, which generates quadrature 90-degree and 270-degree clock signals, to center the data eyes of all data bits of the PRBS. In block 310, once calibration is complete, the input of the PRBS to the quadrature receiver serial interface circuit 206 is stopped, and a functional data stream is transmitted to the quadrature receiver serial interface circuit 206 for normal data communication.

[0043] Referring also to FIG. 4, a flow chart illustrating one or more embodiment methods 400 for calibrating a quadrature receiving serial interface circuit is shown.

[0044] As shown in block 402, the quadrature receiving serial interface circuit 206 is provided with a first phase rotator and a second phase rotator for generating four quadrature clocks of the same frequency. In block 404, the first phase rotator generates in-phase 0-degree and 180-degree clock signals that are provided to a first pair of first sampling latches 232, and the second phase rotator generates quadrature 90-degree and 270-degree clock signals that are provided to a second pair of first sampling latches 232. In block 406, the first sampling latches 232 sample received data bits to the quadrature receiving serial interface circuit 206, which are provided to the deserializer 236 and synchronized to the 0-degree phase. The deserializer 236 of the quadrature receiving serial interface circuit 206 is coupled to a pseudorandom bit sequence (PRBS) checker 238.

[0045] Calibration of the quadrature receiving serial interface circuit begins with the calibration control component 182 initiating a pseudorandom bit sequence (PRBS) at block 408, and the PRBS checker 238 sampling every other bit or half of the received PRBS. At block 410, the calibration control component 182 with the PRBS checker 238 adjusts the first phase rotator 228, which generates in-phase 0-degree and 180-degree clock signals, using the PRBS checker 238 to center the data eye of the sampled half PRBS data bits. For example, the PRBS checker 238 identifies good data at a first edge of the data eye, and the calibration control component 182 adjusts the first phase rotator 228 through the data eye to the other edges of the data eye, setting the first phase rotator 228 to the center of the data eye at block 410. At block 412, calibration control component 182, which includes PRBS checker 238, configures PRBS checker 238 to sample all (both even and odd) data bits of the PRBS. To complete the calibration at block 412, calibration control component 182 uses PRBS checker 238 to adjust second phase rotator 230, which generates quadrature 90-degree and 270-degree clock signals, to center the data eyes of all data bits of the PRBS. At block 414, after calibration is complete and the PRBS is stopped, a functional data stream is initiated and sent to the quadrature receiver serial interface circuit for normal data communication. While the above is directed to embodiments of the present invention, other and further embodiments of the present invention may be devised without departing from the basic scope thereof, the scope of which is defined by the following claims.

Claims

1. providing a quadrature receiving serial interface circuit including: a first phase rotator and a second phase rotator for generating quadrature clock signals of the same frequency; a plurality of first sampling latches for sampling received serial data, wherein the first phase rotator generates in-phase 0-degree and 180-degree clock signals and the second phase rotator generates quadrature 90-degree and 270-degree clock signals, the generated in-phase 0-degree and 180-degree clock signals being used as clock signals for a first pair of the first sampling latches; the generated quadrature 90-degree and 270-degree clock signals being used as clock signals for a second pair of the first sampling latches; and a pseudorandom bit sequence (PRBS) checker; receiving a pseudorandom bit sequence (PRBS) for calibrating the quadrature receiving serial interface circuit; configuring the PRBS checker to sample at least half of the received PRBS data bits; adjusting the first phase rotator to center a data eye of the received sampled half PRBS data bits; configuring the PRBS checker to sample all of the received PRBS data bits; and adjusting the second phase rotator to center the data eye of all the received sampled PRBS data bits to complete calibration of the quadrature receiving serial interface circuit. A method for providing

2. 2. The method of claim 1 , wherein the quadrature receiving serial interface circuit further includes a deserializer; the first sampling latch is coupled to the deserializer; the deserializer receives and synchronizes the sampled data bits to a 0 degree phase and provides output data of the quadrature receiving serial interface circuit.

3. 2. The method of claim 1, wherein configuring the PRBS checker to sample at least half of the received PRBS data bits comprises configuring the PRBS checker to sample an even number of bits of the received PRBS data bits.

4. 2. The method of claim 1, wherein configuring the PRBS checker to sample all of the received PRBS data bits comprises configuring the PRBS checker to sample even and odd data bits of the received PRBS data bits.

5. 2. The method of claim 1, wherein the quadrature receiver serial interface circuit further includes a deserializer that receives and deserializes sampled PRBS serial data bits and provides parallel PRBS output data to the PRBS checker.

6. 2. The method of claim 1, wherein adjusting the first phase rotator comprises checking valid parallel PRBS output data using the PRBS checker to identify valid data edges of the data eye, and adjusting the first phase rotator to center the data eye using the identified data edges.

7. 2. The method of claim 1, further comprising using the PRBS checker to adjust both the first phase rotator and the second phase rotator to center a data eye of received sampled PRBS data bits.

8. 2. The method of claim 1 , wherein providing the quadrature receiving serial interface circuit including the first phase rotator and the second phase rotator for generating four quadrature clocks reduces power required for the quadrature receiving serial interface circuit.

9. 10. The method of claim 1, wherein calibrating the quadrature receiving serial interface circuit is performed dynamically during system operation and upon system power-up.

10. 2. The method of claim 1, further comprising receiving a functional data stream for normal data communication of the quadrature receiving serial interface circuit for normal data communication after calibration is completed.

11. a first phase rotator; a second phase rotator; a plurality of first sampling latches for sampling received serial data, wherein the first phase rotator is configured to generate in-phase 0 degree and 180 degree clock signals and the second phase rotator is configured to generate quadrature 90 degree and 270 degree clock signals, the generated in-phase 0 degree and 180 degree clock signals being used as clock signals for a first pair of the first sampling latches; and the generated quadrature 90 degree and 270 degree clock signals being used as clock signals for a second pair of the first sampling latches; and a pseudorandom bit sequence (PRBS) checker configured to sequentially calibrate the first phase rotator and the second phase using sampled pseudorandom bit sequence (PRBS) data bits; A quadrature reception serial interface circuit comprising:

12. 12. The quadrature receiving serial interface circuit of claim 11, further comprising: a deserializer; the first sampling latch coupled to the deserializer; the deserializer receiving and synchronizing the sampled data bits to a 0 degree phase to provide output data of the quadrature receiving serial interface circuit.

13. 12. The quadrature receiving serial interface circuit of claim 11, wherein the first phase rotator is calibrated using at least half of the PRBS data bits.

14. 12. The quadrature receiving serial interface circuit of claim 11, wherein the second phase rotator is calibrated using all of the PRBS data bits.

15. 12. The quadrature receiving serial interface circuit of claim 11, wherein sampled PRBS data bits are used to calibrate the first phase rotator and the second phase to compensate for variations in the received data bits.

16. 1. A computer program product for calibrating a quadrature receiving serial interface circuit, the quadrature receiving serial interface circuit including: a first phase rotator and a second phase rotator for generating quadrature clock signals of the same frequency; a plurality of first sampling latches for sampling received serial data, wherein the first phase rotator generates in-phase 0-degree and 180-degree clock signals and the second phase rotator generates quadrature-phase 90-degree and 270-degree clock signals, the generated in-phase 0-degree and 180-degree clock signals being used as clock signals for a first pair of the first sampling latches; and the generated quadrature-phase 90-degree and 270-degree clock signals being used as clock signals for a second pair of the first sampling latches; and a pseudorandom bit sequence (PRBS) checker, the computer program product comprising: a computer-readable storage medium having computer-readable program code embodied thereon, the computer-readable program code being executable by one or more computer processors; receiving a pseudo-random bit sequence (PRBS) for calibrating the quadrature receiver serial interface circuit; configuring the PRBS checker to sample at least half of the received PRBS data bits; adjusting the first phase rotator to center a data eye of the received sampled half PRBS data bits; configuring the PRBS checker to sample all of the received PRBS data bits; and adjusting the second phase rotator to center the data eye of all the received sampled PRBS data bits to complete calibration of the quadrature receiving serial interface circuit; performing an action including A computer program product comprising:

17. 17. The computer program product of claim 16, wherein the quadrature receiving serial interface circuit further comprises a deserializer coupled to the first sampling latch, the deserializer receiving and synchronizing the sampled data bits to a 0 degree phase and providing output data for the quadrature receiving serial interface circuit.

18. 17. The computer program product of claim 16, wherein the act of configuring the PRBS checker to sample half of the received PRBS data bits comprises an act of configuring the PRBS checker to sample even bits of the received PRBS data bits.

19. 17. The computer program product of claim 16, wherein the act of configuring the PRBS checker to sample all of the received PRBS data bits comprises an act of configuring the PRBS checker to sample even and odd data bits of the received PRBS data bits.

20. 17. The computer program product of claim 16, further comprising an operation of using the PRBS checker to adjust both the first phase rotator and the second phase rotator to center a data eye of received sampled PRBS data bits.

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