Chiplet Interconnect Power State Management

Abstract

A disclosed device for power management of a chiplet interconnect includes a plurality of chiplets connected via a plurality of interconnects. The device also includes control circuitry that detects activity states of the chiplets and manages the power state of the interconnects based on the detected activity states. Various other methods, systems, and computer-readable media are also disclosed.

Description

[Background technology]

[0001] As computing demands increase, different types of processor architectures have enabled improved computing performance. For example, chiplet architectures can distribute a device's processing tasks across multiple chiplets, each of which can be specialized for a specific processing task (e.g., graphics processing). As power demands increase for improved performance, device power management involves managing the power state of the chiplets. However, the interconnects connecting the chiplets themselves can draw power.

[0002] The accompanying drawings illustrate several exemplary embodiments and are a part of this specification and, together with the following description, demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of an example system for chiplet interconnect power state management. [Figure 2] FIG. 1 is a block diagram of an exemplary chiplet interconnect architecture. [Figure 3A] 1 is a table of various power states of interconnects based on chiplet activity levels. [Figure 3B] 1 is a table of various power states of interconnects based on chiplet activity levels. [Figure 3C] 1 is a table of various power states of interconnects based on chiplet activity levels. [Figure 4] FIG. 1 is a flow diagram of an example method for chiplet interconnect power state management. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] The present disclosure is generally directed to managing the power state of chiplet interconnects. As described in more detail below, embodiments of the present disclosure may use the activity level of a chiplet to place the corresponding interconnect in an appropriate power state. By managing the interconnect power state, particularly during idle states, power consumption may be reduced without significantly degrading performance.

[0006] In one embodiment, a device for managing power states of chiplet interconnects includes a plurality of chiplets connected via a plurality of interconnects; and control circuitry configured to detect an activity state of at least one chiplet among the plurality of chiplets and manage a power state of the at least one interconnect among the plurality of interconnects based on the detected activity state.

[0007] In some examples, the control circuitry is configured to manage a power state of at least one of the plurality of interconnects by reducing a power state of the interconnect when a corresponding chiplet is idle. In some examples, the control circuitry is configured to increase a power state of the interconnect when a corresponding chiplet becomes active.

[0008] In some examples, the control circuitry is configured to manage the power state of at least one of the plurality of interconnects by placing the interconnect in a deep power state when the corresponding chiplet and chiplets communicating with the corresponding chiplet are idle. In some examples, the control circuitry is configured to increase the power state of the interconnect from the deep power state when at least one of the chiplets communicating with the corresponding chiplet becomes active.

[0009] In some examples, the control circuitry is configured to manage the power state of at least one of the plurality of interconnects by placing the interconnect in a shallow power state when the corresponding chiplet is idle and at least one chiplet communicating with the corresponding chiplet is active.

[0010] In some examples, the device further includes a second plurality of chiplets connected via a second plurality of interconnects, and the control circuitry is further configured to manage a power state of the second plurality of interconnects based on an activity state of the second plurality of chiplets. In some examples, the control circuitry manages the power state of the second plurality of interconnects independently of the activity state of the plurality of chiplets.

[0011] In some examples, the reduced power state of the interconnect limits probe traffic. In some examples, the control circuitry is configured to manage the power state of each of the plurality of interconnects based on a power management policy related to the activity state of the corresponding chiplet.

[0012] In one embodiment, a system for managing power states of chiplet interconnects includes a physical memory, at least one physical processor having a plurality of chiplets configured to intercommunicate over a plurality of interconnects, and control circuitry configured to detect an activity state of each of the plurality of chiplets and manage a power state of each of the plurality of interconnects based on the activity state of the corresponding chiplet.

[0013] In some examples, the control circuitry is configured to manage the power state of each of the plurality of interconnects by reducing the power state of the interconnect when the corresponding chiplet is idle and increasing the power state of the interconnect when the corresponding chiplet becomes active.

[0014] In some examples, the control circuitry is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a deep power state when the corresponding chiplet and chiplets communicating with the corresponding chiplet are idle, and increasing the power state of the interconnect from the deep power state when at least one of the chiplets communicating with the corresponding chiplet becomes active.

[0015] In some examples, the control circuitry is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a shallow power state when the corresponding chiplet is idle and at least one chiplet communicating with the corresponding chiplet is active.

[0016] In some examples, the system further includes a second plurality of chiplets connected via a second plurality of interconnects, and the control circuitry is further configured to manage the power state of each of the second plurality of interconnects based on the activity state of a corresponding chiplet of the second plurality of chiplets, independent of the activity state of the plurality of chiplets.

[0017] In some examples, the reduced power state of the interconnect limits probe traffic. In some examples, the control circuitry is configured to manage the power state of each of the plurality of interconnects based on a power management policy related to the activity state of the corresponding chiplet.

[0018] In one embodiment, a method for managing power states of chiplet interconnects includes: (i) detecting an activity state of one of a plurality of chiplets; (ii) applying a power management policy using the detected activity state to select a power state of one of a plurality of interconnects corresponding to the chiplet; and (iii) placing the interconnect in the selected power state.

[0019] In some examples, the power management policy includes selecting a shallow power state for the interconnect when the chiplet is idle and at least one chiplet communicating with the chiplet is active. In some examples, the power management policy includes selecting a deep power state when the chiplet and a chiplet communicating with the chiplet are idle.

[0020] Features of any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from the following detailed description read in conjunction with the accompanying drawings and claims.

[0021] Chiplet interconnect power state management is described in detail below with reference to Figures 1-4. A detailed description of an exemplary system for chiplet interconnect power state management is provided in conjunction with Figures 1 and 2. A detailed description of an exemplary chiplet interconnect power state management policy is provided in conjunction with Figures 3A-3C. A detailed description of a corresponding computer-implemented method is also provided in conjunction with Figure 4.

[0022] FIG. 1 is a block diagram of an example system 100 for chiplet interconnect power state management. System 100 corresponds to a computing device, such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and / or an electronic device. As shown in FIG. 1, system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium that may store data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, any variation or combination of one or more of these, and / or any other suitable storage memory.

[0023] 1, exemplary system 100 includes one or more physical processors, such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 accesses and / or modifies data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, chiplets (e.g., smaller, and in some instances more specialized, processing units that can cooperate as a single chip), microprocessors, microcontrollers, central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems on chips (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), portions of one or more of these, variations or combinations of one or more of these, and / or any other suitable physical processor.

[0024] 1 , processor 110 includes control circuitry 112, chiplets 114, and interconnects 116. Control circuitry 112 corresponds to one or more controllers for power management of the chiplet interconnects (e.g., interconnects 116) and includes circuitry and / or instructions for placing the chiplet interconnects in a desired power state. In some examples, control circuitry 112 may manage the power state of additional components, such as chiplets 114. Chiplets 114 may correspond to one or more chiplets of processor 110. Interconnects 116 correspond to one or more interconnects linking chiplets 114 to various other components of processor 110. In some examples, system 100 may correspond to a computing system, such as a server system, having multiple processors (e.g., processor 110 may correspond to multiple processors), each having chiplets (e.g., one or more chiplets 114) with interconnects (e.g., one or more interconnects 116). In some examples, the control circuitry 112 may correspond to multiple control circuits or controllers that, in some embodiments, may communicate with each other or otherwise cooperate for power management of the chiplet interconnect, as described herein.

[0025] FIG. 2 shows device 200 (corresponding to system 100) having a chiplet architecture that includes chiplet 214A (corresponding to an instance of chiplet 114), chiplet 214B (corresponding to another instance of chiplet 114), chiplet 214C (corresponding to another instance of chiplet 114, more specifically a graphics chiplet), chiplet 214D (corresponding to another instance of chiplet 114, more specifically another graphics chiplet), and IO chiplet 218. In some examples, a chiplet refers to a small integrated circuit designed for a particular function or subset of functions that can operate together as a single larger integrated circuit, and may individually and / or collectively correspond to one or more of a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application specific integrated circuit (ASIC), a system on a chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable physical processor.

[0026] IO chiplet 218 corresponds to a host die, such as an input / output die (IOD) or other central die, for coordinating the inputs and outputs of various chiplets, such as chiplets 214A-214D. In some examples, IO chiplet 218 may include control circuitry for power management (e.g., control circuit 112), while in other examples, the control circuitry may be separate. Although not shown in FIG. 2, IO chiplet 218 may connect to various other interfaces, peripherals, buses, etc.

[0027] FIG. 2 further illustrates chiplet link or interconnect 216A (corresponding to an instance of interconnect 116), interconnect 216B (corresponding to another instance of interconnect 116), interconnect 216C (corresponding to another instance of interconnect 116), and interconnect 216D (corresponding to another instance of interconnect 116). In some examples, a link or interconnect refers to a circuit or other communication path that enables direct communication between connected dies and / or chiplets. In FIG. 2, the interconnects (e.g., interconnects 216A-216D) respectively connect chiplets (e.g., chiplets 214A-214D) to a host die (e.g., IO chiplet 218), although in other examples, the interconnects may connect the chiplets themselves (e.g., connecting chiplet 214A to chiplet 214B, etc.). The interconnects may also enable communication between the respective caches of the chiplets, such as probes for the caches. When managing a cache hierarchy, probes are sent to maintain coherency between caches (eg, to prevent stale cache data from being operated on).

[0028] As described further herein, power management policies may be applied to interconnects based at least in part on their corresponding chiplets. In some examples, a global policy may be applied to all chiplets (e.g., chiplets 214A-214D), while other examples may use individual policies for groups of chiplets. For example, in FIG. 2, chiplets 214A and 214B may correspond to compute chiplets that may operate separately and / or independently from chiplets 214C and 214D (e.g., graphics chiplets). In other words, chiplets 214A and 214B do not necessarily share workload with chiplets 214C and 214D, such that the activity state of each group of chiplets is not relevant to the power management of the other groups. Thus, chiplets 214C and 214D and interconnects 216C and 216D may be managed with individual policies.

[0029] 3A-3C illustrate various tables, such as table 300, table 301, and table 302, respectively. Table 300, table 301, and table 302 each represent interconnect power state management policies and reference the chiplets and interconnects shown in FIG. 2. In some examples, a controller (e.g., control circuitry 112) may implement one or more of these policies, for example, by observing activity levels of the chiplets using various hardware and / or software tools and instructing the interconnects to enter desired power states.

[0030] Table 300 corresponds to a simple management policy that can place interconnects in either an on state or a lower power state (e.g., a shallow power state) based on the activity level (e.g., active or idle) of the corresponding chiplet. For example, if chiplet 214A is active, then corresponding interconnect 216A is on; if chiplet 214A is idle, then the controller reduces the power state of interconnect 216A to a shallow power state. More specifically, if both chiplet 214A and chiplet 214B are idle (e.g., chiplets that may communicate with each other for a particular processing task are both idle, indicating little or no current workload), then corresponding interconnects 216A and 216B may be placed in a shallow power state.

[0031] Placing the interconnect in a shallow power state rather than a deep power state may avoid the delay or latency overhead of powering up the interconnect when the corresponding chiplet becomes active. For example, when chiplet 214A becomes active and needs to communicate with chiplet 214B, interconnect 216A may be powered on more quickly than if interconnect 216A were in a deep power state. Exiting a low power state may incur latency that may affect probe traffic, for example, affecting the timeline of components requiring a probe to be serviced and the required bandwidth of components requiring a probe to the chiplet. Thus, in some examples, a shallow power state may further enable probes to be sent / received along the interconnect. In yet other examples, a shallow power state may pause probes from being sent / received along the interconnect for a shorter time than a deep power state. However, even in a shallow power state, the interconnect draws power unnecessarily even when the corresponding chiplet is idle.

[0032] Table 301 illustrates an improved power management policy. When both chiplet 214A and chiplet 214B are idle (indicating little or no current workload), no communication between the chiplets is expected. Therefore, interconnect 216A and interconnect 216B can be placed in a further reduced power state (e.g., a deep power state) to further reduce power consumption. In other words, because chiplet 214A and chiplet 214B are idle and themselves in a low-power state, there is minimal risk that the chiplets will need to communicate for workload (and require a rapid power-up of the interconnect). Additionally, because chiplet 214A and chiplet 214B are idle, their corresponding caches are also unused, and therefore probing these caches is unnecessary (e.g., the probe bandwidth for a flushed cache may be zero). Therefore, placing interconnects 216A and 216B in deep power states may further avoid wasting power on interconnects 216A and 216B when they are not being used by any coherence traffic, including probes.

[0033] Table 302 illustrates another improved power management policy. Table 302 includes an additional scenario in which chiplet 214A is active and chiplet 214B is idle. In this scenario, because chiplet 214A is active, interconnect 216A is kept on. Because chiplet 214B is idle, interconnect 216B is placed in a shallow power state. Rather than placing interconnect 216B in a deep power state, interconnect 216B is placed in a shallow power state to reduce the overhead of powering up interconnect 216B (e.g., compared to a deep power state) when chiplet 214A communicates with chiplet 214B. Thus, power savings are achieved over a simpler policy without significantly reducing performance.

[0034] In some embodiments, power management policies may be adjusted. For example, power management policies may be adjusted to prioritize performance (e.g., favor shallower power states) or for aggressive power conservation (e.g., favor deeper power states). In some embodiments, the controller may dynamically update power management policies, for example, by learning and / or otherwise determining which chiplets tend to communicate with which other chiplets to manage corresponding interconnects, detecting interconnect usage patterns related to the activity of the corresponding chiplets, etc. For example, power management policies may be updated to include different contexts between chiplets, such as adding scenarios, removing scenarios, etc., between chiplets 214C and / or 214D and chiplets 214A and / or 214B.

[0035] 3A-3C illustrate two chiplet / interconnect pairs and two low power states (e.g., shallow and deep) as simplified examples, in other examples, various permutations of chiplets and states (e.g., scenarios) may be combined with various other power states as desired. Furthermore, in other examples, power management policies may be defined by rules, heuristics, factor-based decisions, etc.

[0036] Figure 4 is a flow diagram of an example method 400 of chiplet interconnect power state management. The operations illustrated in Figure 4 may be performed by any suitable circuitry, computer-executable code, and / or computing system, including the systems illustrated in Figures 1 and / or 2. In one example, each of the operations illustrated in Figure 4 represents an algorithm whose structure includes and / or is represented by multiple sub-operations, examples of which are provided in more detail below.

[0037] 4, one or more of the systems described herein detect the activity of one of the plurality of chiplets in step 402. For example, control circuitry 112 detects or otherwise identifies the activity of chiplet 114.

[0038] The systems described herein may perform operation 402 in a variety of ways. In one example, control circuitry 112 may monitor the activity levels of chiplets 114 and / or read corresponding status registers.

[0039] In step 404, one or more of the systems described herein use the detected activity state to apply a power management policy to select a power state for an interconnect among the multiple interconnects corresponding to the chiplet. For example, control circuitry 112 may select a power state for interconnect 116 for applying a power management policy using the detected activity state of chiplet 114.

[0040] The systems described herein may perform operation 404 in various ways. In one example, the power management policy may include selecting a shallow power state for the interconnect when the chiplet is idle and at least one chiplet communicating with the chiplet is active (see, e.g., Table 302). In some examples, the power management policy may include selecting a deep power state when the chiplet and a chiplet communicating with the chiplet are idle (see, e.g., Table 302).

[0041] At step 406, one or more of the systems described herein place the interconnect in a selected power state. For example, control circuitry 112 may place interconnect 116 in a selected power state.

[0042] The systems described herein may perform step 406 in a variety of ways. In one example, control circuitry 112 may instruct interconnect 116 to enter a selected power state.

[0043] As described above, the systems and methods described herein provide power state management of chiplet interconnect links based on the activity levels of all chiplets. In a chiplet architecture, it is necessary to manage link states between chiplets. Chilet interconnect links can draw a large amount of power, and leaving the links running can increase probe request traffic. Therefore, it can be advantageous to reduce power consumption and limit probe requests through smart management of link power states. Additionally, this management can extend to having asymmetric power states between chiplets and interconnect links. While this chiplet interconnect power state management can contribute to power savings, it is necessary for an accelerated processing unit (APU) to avoid putting links into power states at non-optimal times that impact performance. Therefore, the systems and methods described herein monitor the activity of all chiplets and use it to influence the power states to which links transition.

[0044] Specifically, when all chiplets are inactive, the APU may save power by placing inactive chiplet interconnect links in a shallow power state. Because some chiplets are active, this means the APU is still doing work, but not at maximum capacity. A shallow power state is beneficial in this scenario because a moderate level of activity can quickly increase, requiring the resources of inactive chiplets. Thus, waking up interconnect links from a shallow power state limits the performance degradation caused by putting the links to sleep, while saving most of the power possible. Instead, if activity levels decrease, more individual chiplets may be placed in a shallow state until all chiplets are inactive. At this point, the APU may transition all chiplet interconnect links to a deep power state, which is considered idle and saves maximum power when maximum performance is not required. When the APU begins to see increased activity, all chiplet interconnect links may be returned to a shallow power state, with activity backing up as many links as necessary to fully wake up.

[0045] As noted above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those contained within the modules described herein. In their most basic configurations, these computing devices each include at least one memory device and at least one physical processor.

[0046] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium that may store data and / or computer-readable instructions. In one example, a memory device stores, loads, and / or maintains one or more of the modules and / or circuits described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drives (HDDs), solid-state drives (SSDs), optical disk drives, caches, variations or combinations of one or more of these, or any other suitable storage memory.

[0047] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor accesses and / or modifies one or more modules stored in the memory devices described above. Examples of physical processors include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more portions thereof, one or more variations or combinations thereof, or any other suitable physical processor.

[0048] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium that can store or carry computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, and non-transitory-type media such as magnetic storage media (e.g., hard disk drives, tape drives, floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), BLU-RAY disks), electronic storage media (e.g., solid-state drives and flash media), and other distribution systems.

[0049] The process parameters and order of steps described and / or illustrated herein are provided by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein are shown or discussed in a particular order, these steps do not necessarily have to be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein may omit one or more of the steps described or illustrated herein or may include additional steps in addition to those disclosed.

[0050] The above description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many changes and modifications are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0051] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect (i.e., via other elements or components) connections. Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising" and have the same meaning.

Claims

1. A device, a plurality of chiplets connected via a plurality of interconnects; a control circuit; The control circuit Detecting an activity state of at least one chiplet among the plurality of chiplets; managing a power state of at least one of the plurality of interconnects based on the detected activity state; configured to: device.

2. the control circuitry is configured to manage a power state of at least one of the plurality of interconnects by reducing a power state of the interconnect when a corresponding chiplet is idle. The device of claim 1.

3. the control circuitry is configured to increase the power state of the interconnect when the corresponding chiplet becomes active. The device of claim 2.

4. the control circuitry is configured to manage the power state of at least one of the plurality of interconnects by placing the interconnect in a deep power state when a corresponding chiplet and a chiplet communicating with the corresponding chiplet are idle. The device of claim 1.

5. the control circuitry is configured to increase the power state of the interconnect from the deep power state when at least one of the chiplets in communication with the corresponding chiplet becomes active. The device of claim 4.

6. the control circuitry is configured to manage a power state of at least one of the plurality of interconnects by placing the interconnect in a shallow power state when a corresponding chiplet is idle and at least one chiplet communicating with the corresponding chiplet is active. The device of claim 1.

7. the device comprises a second plurality of chiplets connected via a second plurality of interconnects; the control circuitry is configured to manage a power state of the second plurality of interconnects based on an activity state of the second plurality of chiplets. The device of claim 1.

8. the control circuitry manages the power state of the second plurality of interconnects independently of the activity state of the plurality of chiplets. The device of claim 7.

9. a reduced power state of the plurality of interconnects to limit probe traffic; The device of claim 1.

10. the control circuitry is configured to manage a power state of each of the plurality of interconnects based on a power management policy related to an activity state of a corresponding chiplet. The device of claim 1.

11. 1. A system comprising: Physical memory and at least one physical processor comprising a plurality of chiplets configured to communicate with each other via a plurality of interconnects; a control circuit; The control circuit detecting an activity state of each of the plurality of chiplets; managing a power state of each of the plurality of interconnects based on an activity state of a corresponding chiplet; configured to: system.

12. the control circuitry is configured to manage a power state of each of the plurality of interconnects by reducing a power state of the interconnect when the corresponding chiplet is idle and increasing a power state of the interconnect when the corresponding chiplet becomes active. The system of claim 11.

13. the control circuitry is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a deep power state when a corresponding chiplet and a chiplet communicating with the corresponding chiplet are idle, and increasing the power state of the interconnect from the deep power state when at least one of the chiplets communicating with the corresponding chiplet becomes active. The system of claim 11.

14. the control circuitry is configured to manage the power state of each of the plurality of interconnects by placing the interconnect in a shallow power state when a corresponding chiplet is idle and at least one chiplet communicating with the corresponding chiplet is active. The system of claim 11.

15. a second plurality of chiplets connected via a second plurality of interconnects; the control circuitry is configured to manage a power state of each of the second plurality of interconnects based on an activity state of the corresponding chiplet of the second plurality of chiplets, independent of an activity state of the plurality of chiplets. The system of claim 11.

16. a reduced power state of the plurality of interconnects to limit probe traffic; The system of claim 11.

17. the control circuitry is configured to manage a power state of each of the plurality of interconnects based on a power management policy associated with an activity state of the corresponding chiplet. The system of claim 11.

18. 1. A method comprising: Detecting an activity state of any one of the plurality of chiplets; applying a power management policy using the detected activity state to select a power state for one of a plurality of interconnects corresponding to the chiplet; placing the interconnect in a selected power state. method.

19. the power management policy includes selecting a shallow power state for the interconnect when the chiplet is idle and at least one chiplet communicating with the chiplet is active.

20. The method of claim 18.

20. the power management policy includes selecting a deep power state when the chiplet and chiplets communicating with the chiplet are idle; 20. The method of claim 18.

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