Display device and deposition mask

Abstract

To provide a display device capable of maintaining high optical characteristics while securing connectivity of a cathode, and to provide its manufacturing method and a deposition mask.SOLUTION: The display apparatus includes the pixel defining layer PDL overlapping the non-emission area NEA, the trenches SP1 and SP3 located in the boundary area BDA between the adjacent subpixels TRCH1 to TRCH2 and passing through the pixel defining layer PDL, the light emitting structure EMS disposed on portions of the trenches TRCH1 and TRCH2 and the pixel defining layer PDL, the cathode CE disposed on the light emitting structure EMS, and the auxiliary electrodes AXE disposed on a portion of the cathode CE overlapping the boundary area BDA.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a display device, a manufacturing method thereof, and a deposition mask. [Background technology]

[0002] 2. Description of the Related Art With the development of information technology, the importance of display devices, which are the connecting medium between users and information, is increasing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 10-2010-0006107 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a display device with improved cathode connectivity, a manufacturing method thereof, and a deposition mask.

[0005] However, the purpose of the present disclosure is not limited to the above purpose, and can be expanded in various ways without departing from the spirit and scope of the present disclosure. [Means for solving the problem]

[0006] A display device according to an embodiment may include a pixel defining layer overlapping a non-emitting region, a trench positioned in a boundary region between adjacent sub-pixels and penetrating the pixel defining layer, a light emitting structure disposed on a portion of the trench and the pixel defining layer, a cathode disposed on the light emitting structure, and an auxiliary electrode partially disposed on the cathode.

[0007] In one embodiment, the auxiliary electrode may be disposed on a portion of the cathode that overlaps the boundary region.

[0008] In one embodiment, the cathode may overlap a non-boundary region adjacent to the boundary region, and the auxiliary electrode may not overlap the non-boundary region.

[0009] In one embodiment, the auxiliary electrode may include a conductive material.

[0010] In one embodiment, the auxiliary electrode may include indium zinc oxide, aluminum, or silver.

[0011] According to an embodiment, a display device includes a pixel defining layer overlapping a non-light-emitting region, a trench positioned in a boundary region between adjacent sub-pixels and penetrating the pixel defining layer, a light-emitting structure disposed on a portion of the trench and the pixel defining layer, and a cathode disposed on the light-emitting structure, wherein a thickness of a portion of the cathode overlapping the boundary region may be greater than a thickness of a portion of the cathode overlapping a non-boundary region adjacent to the boundary region.

[0012] An evaporation mask according to an embodiment may include a frame, masking portions spaced apart from each other within the frame, a support portion for fixing the masking portions within the frame, and an opening positioned between the frame, the masking portions, and the support portion.

[0013] In one embodiment, the masking portion may correspond to a non-border area of ​​the sub-pixel.

[0014] In one embodiment, the openings may correspond to boundary regions of the sub-pixels.

[0015] In one embodiment, the opening allows the deposition material to pass through so that the deposition material is deposited on the cathode overlapping the boundary region. [Effects of the Invention]

[0016] According to the embodiment, it is possible to provide a display device that can maintain high optical characteristics while ensuring cathode connectivity, a manufacturing method thereof, and a deposition mask.

[0017] However, the effects of the present disclosure are not limited to the above-described effects, and can be expanded in various ways without departing from the spirit and scope of the present disclosure. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a block diagram of a display device according to an embodiment. [Figure 2] FIG. 2 is a block diagram of a sub-pixel according to an embodiment. [Figure 3] FIG. 2 is a plan view of a display panel according to an embodiment. [Figure 4] FIG. 2 is an exploded perspective view of a display panel according to an embodiment. [Figure 5] FIG. 2 is a plan view of a pixel according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line II' of FIG. 5 according to one embodiment. [Figure 7] FIG. 1 is a plan view of a deposition mask according to an embodiment. [Figure 8] FIG. 1 is a perspective view showing an application example of a deposition mask according to an embodiment. [Figure 9] 1 is a cross-sectional view of a light emitting structure according to an embodiment. [Figure 10] 1 is a cross-sectional view of a light emitting structure according to an embodiment. [Figure 11] FIG. 2 is a plan view of a pixel according to an embodiment. [Figure 12] FIG. 2 is a plan view of a pixel according to an embodiment. [Figure 13] FIG. 6 is a cross-sectional view taken along line II' of FIG. 5 according to one embodiment. [Figure 14] 5A to 5C are cross-sectional views showing a manufacturing process of a display device according to an embodiment. [Figure 15] 5A to 5C are cross-sectional views showing a manufacturing process of a display device according to an embodiment. [Figure 16] 5A to 5C are cross-sectional views showing a manufacturing process of a display device according to an embodiment. [Figure 17] 5A to 5C are cross-sectional views showing a manufacturing process of a display device according to an embodiment. [Figure 18] 5A to 5C are cross-sectional views showing a manufacturing process of a display device according to an embodiment. [Figure 19] 5A to 5C are cross-sectional views showing a manufacturing process of a display device according to an embodiment. [Figure 20] FIG. 1 is a block diagram of a display system according to an embodiment. [Figure 21] FIG. 21 is a perspective view illustrating an application example of the display system of FIG. 20 according to an embodiment. [Figure 22] 22 illustrates the head-mounted display device of FIG. 21 being worn by a user in accordance with one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operation of the present invention will be described, and descriptions of other parts will be omitted so as not to obscure the gist of the present disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein and may be embodied in other forms. The embodiments described herein are merely provided to provide a detailed description sufficient to enable those skilled in the art to easily implement the technical ideas of the present disclosure.

[0020] Throughout the specification, when a moiety is referred to as being "connected" to another moiety, this includes not only "directly connected" but also "indirectly connected" via an intervening element. Terms used herein are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. Throughout the specification, when a moiety "comprises" a certain element, this does not mean that it excludes other elements, but that it can further include other elements, unless otherwise specified. The terms "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, and one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the relevant elements.

[0021] Here, terms such as "first," "second," etc. may be used to describe various components, but such components are not limited to such terms. Such terms are used to distinguish one component from another. Therefore, a first component can be referred to as a second component within the scope of what is disclosed herein.

[0022] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe the relationship of one element or feature to another element or feature as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacture, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings were inverted, an element depicted as being "below" another element or feature would then be oriented "above" that other element or feature. Thus, in one embodiment, the term "below" can encompass both an orientation of above and below. Moreover, a device may be oriented otherwise (e.g., rotated 90 degrees or at another orientation), and the spatially relative terms used herein should be interpreted accordingly.

[0023] Various embodiments are described with reference to drawings that illustrate idealized embodiments. It is to be understood that variations in shape due, for example, to tolerances and / or manufacturing techniques, may occur. Therefore, the embodiments disclosed herein should not be construed as limited to the particular shapes illustrated, but should also be construed to include variations in shapes that result, for example, from manufacturing. Thus, the shapes illustrated in the drawings may not represent the actual shapes of regions of a device, and the embodiments are not limited thereto.

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] FIG. 1 is a block diagram of a display device according to an embodiment.

[0026] Referring to FIG. 1, a display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0027] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 via first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to the data driver 130 via first to n-th data lines DL1 to DLn.

[0028] Each of the subpixels SP may include at least one light-emitting element configured to generate light. This allows each subpixel SP to generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more of the subpixels SP may constitute one pixel PXL. For example, as shown in FIG. 1, three subpixels may constitute one pixel PXL.

[0029] The gate driver 120 may be connected to the sub-pixels SP arranged in a row direction via the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to gate control signals GCS. The gate control signals GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with the timing at which a data signal is applied, etc.

[0030] The first to m-th emission control lines EL1 to ELm may be further provided, connected to the sub-pixels SP in the row direction. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0031] The gate driver 120 may be arranged on one side of the display panel 110. However, embodiments are not necessarily limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such drivers may be arranged on one side of the display panel 110 and the other side of the display panel 110 opposite to the one side. In this manner, the gate driver 120 may be arranged around the periphery of the display panel 110 in various forms depending on the embodiment.

[0032] The data driver 130 may be connected to the sub-pixels SP arranged in a column direction via first to n-th data lines DL1 to DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. The data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0033] The data driver 130 can apply data signals having gray scale voltages corresponding to the video data DATA to the first to n-th data lines DL1 to DLn using the voltages from the voltage generator 140. When gate signals are applied to the first to m-th gate lines GL1 to GLm, the data signals corresponding to the video data DATA can be applied to the first to n-th data lines DL1 to DLn. This allows the corresponding sub-pixels SP to generate light corresponding to the data signals. This allows an image to be displayed on the display panel 110.

[0034] The gate driver 120 and the data driver 130 may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0035] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 can be configured to receive an input voltage from outside the display device 100, adjust the received voltage, and regulate the adjusted voltage to generate the plurality of voltages.

[0036] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first and second power supply voltages VDD and VSS may be provided to the subpixels SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. However, the embodiment is not necessarily limited thereto. For example, the first power supply voltage VDD or the second power supply voltage VSS may be provided by a device external to the display device 100.

[0037] Additionally, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the subpixel SP. For example, during a sensing operation for sensing electrical characteristics of the transistors and / or light emitting elements of the subpixel SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such reference voltage.

[0038] The controller 150 can control various operations of the display device 100. The controller 150 can receive input image data IMG from the outside and a control signal CTRL for controlling the display of the input image data IMG. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0039] The controller 150 can convert the input image data IMG to be compatible with the display device 100 or the display panel 110 and output the image data DATA. The controller 150 can align the input image data IMG to be compatible with the sub-pixels SP arranged in rows and output the image data DATA.

[0040] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be implemented in a single integrated circuit. As shown in FIG. 1 , the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In such a case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within a single driver integrated circuit DIC. However, embodiments are not necessarily limited thereto. For example, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a separate component from the driver integrated circuit DIC.

[0041] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense a temperature around the display panel 110 and generate temperature data TEP representing the sensed temperature. The temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0042] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. The controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust the data signal and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0043] FIG. 2 is a block diagram of a sub-pixel according to one embodiment.

[0044] In Figure 2, a subpixel SPij of the subpixels SP of Figure 1 arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0045] Referring to FIG. 2, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0046] The light emitting element LD may be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN, where the first power supply voltage node VDDN is a node that transfers the first power supply voltage VDD of FIG. 1 and the second power supply voltage node VSSN is a node that transfers the second power supply voltage VSS of FIG. 1.

[0047] The anode AE ​​of the light emitting element LD may be connected to a first power supply voltage node VDDN via the sub-pixel circuit SPC, and the cathode CE of the light emitting element LD may be connected to a second power supply voltage node VSSN. For example, the anode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0048] The sub-pixel circuit SPC may be connected to the ith gate line GLi among the first to mth gate lines GL1 to GLm in Fig. 1, the ith light-emitting control line ELi among the first to mth light-emitting control lines EL1 to ELm in Fig. 1, and the jth data line DLj among the first to nth data lines DL1 to DLn in Fig. 1. The sub-pixel circuit SPC may be configured to control the light-emitting element LD in response to signals received via these signal lines.

[0049] The sub-pixel circuit SPC may operate in response to a gate signal received via an ith gate line GLi. The ith gate line GLi may include one or more sub-gate lines. As shown in FIG. 2, the ith gate line GLi may include first and second sub-gate lines SGL1 and SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received via the first and second sub-gate lines SGL1 and SGL2. In this way, when the ith gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received via the corresponding sub-gate lines.

[0050] The sub-pixel circuit SPC may operate in response to a light-emitting control signal received via an i-th light-emitting control line ELi. The i-th light-emitting control line ELi may include one or more sub-light-emitting control lines. When the i-th light-emitting control line ELi includes two or more sub-light-emitting control lines, the sub-pixel circuit SPC may operate in response to a light-emitting control signal received via the corresponding sub-light-emitting control line.

[0051] The sub-pixel circuit SPC may receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of gate signals received via the first and second sub-gate lines SGL1 and SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN via the light emitting element LD according to the stored voltage in response to an emission control signal received via the ith emission control line ELi. This allows the light emitting element LD to generate light of a brightness corresponding to the data signal.

[0052] FIG. 3 is a plan view of a display panel according to an embodiment.

[0053] 3, a display panel DP according to an embodiment may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0054] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0055] When the display panel DP is used as a display screen for a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be located very close to the user's eyes. In such cases, a relatively high degree of integration of the subpixels SP may be required. To increase the integration of the subpixels SP, the substrate SUB may be a silicon substrate. The subpixels SP and / or the display panel DP may be formed on the silicon substrate SUB. A display device 100 (see FIG. 1 ) including the display panel DP formed on the silicon substrate SUB may be called an OLEDoS (OLED on Silicon) display device.

[0056] The sub-pixels SP may be arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not necessarily limited thereto. For example, the sub-pixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a PENTILE (registered trademark) TM The first direction DR1 may be the row direction, and the second direction DR2 may be the column direction.

[0057] Two or more sub-pixels among the plurality of sub-pixels SP can form one pixel PXL.

[0058] Components for controlling the sub-pixels SP may be arranged in the non-display area NDA on the substrate SUB. For example, wiring connected to the sub-pixels SP, such as the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn in FIG. 1, may be arranged in the non-display area NDA.

[0059] At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 in FIG. 1 may be integrated into the non-display area NDA of the display panel DP. The gate driver 120 in FIG. 1 is implemented in the display panel DP, but may be disposed in the non-display area NDA. However, the embodiment is not necessarily limited thereto. For example, the gate driver 120 may be realized as an integrated circuit separate from the display panel DP. The temperature sensor 160 may be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0060] Pads PD may be disposed in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP via wiring. For example, the pads PD may be connected to the sub-pixels SP via first to n-th data lines DL1 to DLn.

[0061] The pads PD may interface the display panel DP with other components of the display device 100 (see FIG. 1). Voltages and signals required for operation of the components included in the display panel DP may be provided from the driver integrated circuit DIC of FIG. 1 via the pads PD. For example, the first to n-th data lines DL1 to DLn may be connected to the driver integrated circuit DIC via the pads PD. For example, the first and second power supply voltages VDD and VSS may be received from the driver integrated circuit DIC via the pads PD. For example, if the gate driver 120 is implemented in the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pads PD.

[0062] The circuit board may be electrically connected to the pads PD via a conductive adhesive member such as an anisotropic conductive film. In this case, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board and electrically connected to the pads PD.

[0063] The display area DA can have various shapes. The display area DA can have a closed-loop shape including straight and / or curved sides. For example, the display area DA can have a polygonal, circular, semicircular, elliptical, or other shape.

[0064] The display panel DP may have a flat display surface. However, embodiments are not necessarily limited thereto. For example, the display panel DP may have an at least partially round display surface. The display panel DP may be bendable, foldable, or rollable. In such cases, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0065] FIG. 4 is an exploded perspective view of a display panel according to an embodiment.

[0066] In Figure 4, for clarity and simplicity of explanation, the portions of the display panel DP corresponding to two of the pixels PXL1, PXL2 of Figure 3 are shown schematically, and the portions of the display panel DP corresponding to the remaining pixels can be configured similarly.

[0067] 4, each of the first and second pixels PXL1 and PXL2 may include first to third sub-pixels SP1, SP2, and SP3. However, the embodiment is not necessarily limited thereto. For example, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0068] The first to third sub-pixels SP1, SP2, and SP3 may have a rectangular shape and the same size as each other when viewed in a third direction DR3 intersecting the first and second directions DR1 and DR2. However, the embodiment is not necessarily limited thereto. The first to third sub-pixels SP1, SP2, and SP3 may be modified to have various shapes.

[0069] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a sealing layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0070] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. However, embodiments are not necessarily limited thereto. For example, the substrate SUB may include a glass substrate or a polyimide (PI) substrate.

[0071] A pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a part of a circuit element, wiring, etc. The conductive pattern may include copper, although embodiments are not necessarily limited thereto.

[0072] The circuit elements may include subpixel circuits SPC (see FIG. 2) for the first to third subpixels SP1, SP2, and SP3, respectively. The subpixel circuits SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. When the substrate SUB is a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. When the substrate SUB is a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other in a plane defined by the first and second directions DR1 and DR2. For example, each capacitor may include electrodes spaced apart from each other in the third direction DR3 with an insulating layer sandwiched therebetween.

[0073] The wirings of the pixel circuit layer PCL may include signal lines, such as gate lines, emission control lines, and data lines, connected to the first to third sub-pixels SP1, SP2, and SP3, respectively. The wirings may further include a wiring connected to the first power supply voltage node VDDN of FIG. 2. The wirings may also include a wiring connected to the second power supply voltage node VSSN of FIG. 2.

[0074] The light emitting element layer LDL may include an anode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode CE.

[0075] The anode AE ​​may be disposed on the pixel circuit layer PCL. The anode AE ​​may be in contact with a circuit element of the pixel circuit layer PCL. The anode AE ​​may include an opaque conductive material that can reflect light, although embodiments are not necessarily limited thereto.

[0076] A pixel defining layer PDL may be disposed on the anode AE. The pixel defining layer PDL may include openings OP exposing portions of the anode AE. The openings OP in the pixel defining layer PDL may be understood to be light-emitting regions corresponding to the first to third sub-pixels SP1 to SP3, respectively.

[0077] The pixel defining layer PDL may include an inorganic material. In such a case, the pixel defining layer PDL may include multiple stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x However, the embodiment is not limited thereto. For example, the pixel defining layer PDL may include an organic material.

[0078] The light emitting structure EMS may be disposed on the anode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0079] The light emitting structure EMS may fill the opening OP of the pixel defining film PDL, but may be entirely disposed on top of the pixel defining film PDL. In other words, the light emitting structure EMS may extend across the first to third sub-pixels SP1 to SP3. In this case, at least a portion of a layer in the light emitting structure EMS may be cut or bent at the boundary between the first to third sub-pixels SP1 to SP3. However, the embodiment is not necessarily limited thereto. For example, portions of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of them may be disposed within the opening OP of the pixel defining film PDL.

[0080] The cathode CE may be disposed on the light emitting structure EMS. The cathode CE may extend across the first to third sub-pixels SP1 to SP3. In this manner, the cathode CE may serve as a common electrode for the first to third sub-pixels SP1 to SP3.

[0081] The cathode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode CE may be formed of a metal material to have a relatively thin thickness, or may be formed of a transparent conductive material. For example, the cathode CE may include at least one of various transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. However, examples are not necessarily limited thereto. For example, the cathode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof.

[0082] Any one of the anodes AE, a portion of the light emitting structure EMS overlapping it, and a portion of the cathode CE overlapping it can be understood to constitute one light emitting element LD (see FIG. 2). In other words, each of the light emitting elements of the first to third subpixels SP1 to SP3 includes one anode AE, a portion of the light emitting structure EMS overlapping it, and a portion of the cathode CE overlapping it. In each of the first to third subpixels SP1 to SP3, holes injected from the anode AE ​​and electrons injected from the cathode CE are transported into the light emitting layer of the light emitting structure EMS to form excitons. When the excitons transition from an excited state to a ground state, light can be generated. The brightness of the light can be determined depending on the amount of current flowing through the light emitting layer. The wavelength range of the generated light can be determined depending on the configuration of the light emitting layer.

[0083] An encapsulation layer TFE may be disposed on the cathode CE. The encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. The encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may be silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y For example, the organic film may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the embodiment is not necessarily limited thereto.

[0084] In order to improve the sealing efficiency of the sealing layer TFE, the sealing layer TFE is made of aluminum oxide (AlO x The thin film containing aluminum oxide may be located on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0085] The thin film including aluminum oxide may be formed by atomic layer deposition (ALD). However, embodiments are not limited thereto. The encapsulation layer TFE may further include a thin film formed from at least one of various materials suitable for improving encapsulation efficiency.

[0086] The optically functional layer OFL can be disposed on the encapsulation layer TFE. The optically functional layer OFL can include a color filter layer CFL and a lens array LA.

[0087] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter light emitted from the light emitting structures EMS to selectively output light of a wavelength range or color corresponding to each subpixel. The color filter layer CFL includes color filters CF corresponding to the first to third subpixels SP1 to SP3, respectively, and each of the color filters CF may transmit light of a wavelength range corresponding to the corresponding subpixel. For example, the color filter corresponding to the first subpixel SP1 may transmit red light, the color filter corresponding to the second subpixel SP2 may transmit green light, and the color filter corresponding to the third subpixel SP3 may transmit blue light. At least some of the color filters CF may be omitted depending on the light emitted from the light emitting structures EMS of each subpixel.

[0088] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. The lenses LS may include an organic material. For example, the lenses LS may include an acrylic material, but the embodiment is not necessarily limited thereto.

[0089] At least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first and second directions DR1 and DR2 relative to the apertures OP of the pixel definition layer PDL. Specifically, in the central region of the display area DA, the centers of the color filters and the lenses may be aligned with or overlap with the centers of the apertures OP of the corresponding pixel definition layer PDL when viewed from the third direction DR3. For example, in the central region of the display area DA, the apertures OP of the pixel definition layer PDL may completely overlap with the corresponding color filters of the color filter layer CFL and the corresponding lenses of the lens array LA. In a region adjacent to the non-display area NDA in the display area DA, the centers of the color filters and the lenses may be shifted in a planar direction relative to the centers of the apertures OP of the corresponding pixel definition layer PDL when viewed from the third direction DR3. For example, in a region adjacent to the non-display area NDA in the display area DA, the apertures OP of the pixel definition layer PDL may partially overlap with the corresponding color filters of the color filter layer CFL and the corresponding lenses of the lens array LA. As a result, light emitted from the light emitting structure EMS at the center of the display area DA can be efficiently output in the normal direction of the display surface, and light emitted from the light emitting structure EMS at the periphery of the display area DA can be efficiently output in a direction inclined at a predetermined angle with respect to the normal direction of the display surface.

[0090] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the underlying layers from foreign substances such as dust and moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OC may include epoxy, although examples are not necessarily limited thereto. The overcoat layer OC may have a lower refractive index than the lens array LA.

[0091] The cover window CW can be disposed on the overcoat layer OC. The cover window CW can be configured to protect layers underneath it. The cover window CW can have a higher refractive index than the overcoat layer OC. The cover window CW can include glass, although embodiments are not necessarily limited thereto. For example, the cover window CW can be encapsulation glass configured to protect components underneath it. In embodiments, the cover window CW can be omitted.

[0092] Figure 5 is a plan view of a pixel according to one embodiment. For clarity and simplicity, Figure 5 shows only a schematic representation of the first pixel PXL1 of the first and second pixels PXL1 and PXL2 shown in Figure 4. The remaining pixels may be configured similarly to the first pixel PXL1.

[0093] Referring to FIG. 5, the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0094] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0095] The first light-emitting region EMA1 may be a region where light is emitted from a portion of the light-emitting structure EMS (see FIG. 4) corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to FIG. 4, each light-emitting region can be understood as an opening OP in the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0096] FIG. 6 is a cross-sectional view taken along line II' of FIG. 5 according to one embodiment.

[0097] 6, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process, for example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0098] A pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for the first to third subpixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 for the first subpixel SP1, a transistor T_SP2 for the second subpixel SP2, and a transistor T_SP3 for the third subpixel SP3. The transistor T_SP1 for the first subpixel SP1 may be one of the transistors included in the subpixel circuit SPC for the first subpixel SP1 (see FIG. 2 ), the transistor T_SP2 for the second subpixel SP2 may be one of the transistors included in the subpixel circuit SPC for the second subpixel SP2, and the transistor T_SP3 for the third subpixel SP3 may be one of the transistors included in the subpixel circuit SPC for the third subpixel SP3. For clarity and conciseness, FIG. 6 shows only one of the transistors for each subpixel, and omits the remaining circuit elements.

[0099] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0100] The source region SRA and the drain region DRA may be disposed in a substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed spaced apart from each other in the well WL. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0101] The gate electrode GE may be disposed in the pixel circuit layer PCL, overlapping the channel region between the source region SRA and the drain region DRA. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0102] The pixel circuit layer PCL includes a plurality of layers, each of which includes an insulating layer and a conductive pattern disposed between the insulating layer, and the conductive pattern may include first and second conductive patterns CP1 and CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connector DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connector SRC that penetrates one or more insulating layers.

[0103] The gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or wiring, so that the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1.

[0104] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can each be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0105] In this way, the substrate SUB and the pixel circuit layer PCL can include the circuit elements of each of the first to third sub-pixels SP1 to SP3.

[0106] A via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL but may have an entirely flat surface. The via layer VIAL may be configured to flatten steps on the pixel circuit layer PCL. The via layer VIAL may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbon nitride (SiCN), but examples are not necessarily limited thereto.

[0107] The light emitting element layer LDL may be disposed on the via layer VIAL. The light emitting element layer LDL may include first to third reflective electrodes RE1 to RE3, a planarization layer PLNL, first to third anodes AE1 to AE3, a pixel defining layer PDL, a light emitting structure EMS, and a cathode CE.

[0108] First to third reflective electrodes RE1 to RE3 may be disposed on the via layer VIAL for the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 may be in contact with a circuit element disposed in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0109] The first to third reflective electrodes RE1 to RE3 may function as full mirrors that reflect light emitted from the light emitting structure EMS toward the display surface (or the cover window CW (see FIG. 4)). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. For example, the first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom, but embodiments are not necessarily limited thereto.

[0110] A connecting electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode may improve electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multi-layer structure. The multi-layer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. For example, the corresponding reflective electrode may be located between multiple layers of connecting electrodes.

[0111] A buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. By disposing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0112] The first to third reflective electrodes RE1 to RE3 may function as full mirrors, and the cathode CE may function as a half mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by at least partially traveling back and forth between the corresponding reflective electrodes and the cathode CE, and the amplified light may be output through the cathode CE. In this way, the distance between each reflective electrode and the cathode CE may be understood to be a resonance distance for the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0113] The first sub-pixel SP1 may have a shorter resonance distance than the other sub-pixels due to the buffer pattern BFP. The adjusted resonance distance may allow light in a specific wavelength range (e.g., red) to be effectively and efficiently amplified. As a result, the first sub-pixel SP1 may output light in the corresponding wavelength range effectively and efficiently.

[0114] 6, the buffer pattern BFP is provided in the first sub-pixel SP1 but not in the second and third sub-pixels SP2 and SP3, but this embodiment is not necessarily limited thereto. A buffer pattern may also be provided in at least one of the second and third sub-pixels SP2 and SP3 to adjust the resonance distance of at least one of the second and third sub-pixels SP2 and SP3. For example, the first to third sub-pixels SP1 to SP3 may correspond to red, green, and blue, respectively, and the distance between the first reflective electrode RE1 and the cathode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode CE, and the distance between the second reflective electrode RE2 and the cathode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode CE.

[0115] In order to flatten the steps between the first to third reflective electrodes RE1 to RE3, a flattening layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The flattening layer PLNL entirely covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL, but may have a flat surface. In an embodiment, the flattening layer PLNL may be omitted.

[0116] First to third anodes AE1 to AE3 may be disposed on the planarization layer PLNL, overlapping the first to third reflective electrodes RE1 to RE3, respectively. The first to third anodes AE1 to AE3 may have shapes similar to the first to third light-emitting regions EMA1 to EMA3 of FIG. 5 when viewed from the third direction DR3. The first to third anodes AE1 to AE3 may be connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode AE1 may be connected to the first reflective electrode RE1 through a first via VIA1 that penetrates the planarization layer PLNL. The second anode AE2 may be connected to the second reflective electrode RE2 through a second via VIA2 that penetrates the planarization layer PLNL. The third anode AE3 may be connected to the third reflective electrode RE3 through a third via VIA3 that penetrates the planarization layer PLNL.

[0117] The first to third anodes AE1 to AE3 may include a conductive material. For example, the first to third anodes AE1 to AE3 may include at least one of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, embodiments are not necessarily limited thereto. For example, the first to third anodes AE1 to AE3 may include titanium nitride.

[0118] An insulating layer may be further provided to adjust the height of one or more of the first to third anodes AE1 to AE3. The insulating layer may be disposed between one or more of the first to third anodes AE1 to AE3 and the corresponding reflective electrode. In such a case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively, and the distance between the first anode AE1 and the cathode CE may be shorter than the distance between the second anode AE2 and the cathode CE, which may be shorter than the distance between the third anode AE3 and the cathode CE.

[0119] A pixel defining film PDL may be disposed on portions of the first to third anodes AE1 to AE3 and the planarizing layer PLNL. The pixel defining film PDL may include openings OP that expose portions of the first to third anodes AE1 to AE3, respectively. The openings OP in the pixel defining film PDL may define light-emitting regions of the first to third sub-pixels SP1 to SP3, respectively. In this way, the pixel defining film PDL may be disposed in the non-light-emitting region NEA, thereby defining the first to third light-emitting regions EMA1 to EMA3.

[0120] The pixel definition layer PDL may include a plurality of inorganic insulating layers, each of which may be made of silicon oxide (SiO x ) and silicon nitride (SiN x ) may include at least one of. For example, the pixel defining film PDL includes first to third inorganic insulating layers stacked in sequence, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. The first to third inorganic insulating layers may have a stepped cross section in a region adjacent to the opening OP. However, the embodiment is not necessarily limited thereto. For example, the pixel defining film PDL may include an organic insulating layer.

[0121] A separator SPR may be provided in the boundary region BDA between adjacent subpixels. The separator SPR may cause a discontinuity to be formed in the light emitting structure EMS in the boundary region BDA. For example, the separator SPR may cause the light emitting structure EMS to be cut or bent in the boundary region BDA.

[0122] The separator SPR may be provided in or on the pixel defining film PDL. The pixel defining film PDL may include one or more trenches TRCH1, TRCH2 as separators SPR in the boundary region BDA. As shown in FIG. 6, one or more trenches TRCH1, TRCH2 may penetrate the pixel defining film PDL and have their bottoms in the planarization layer PLNL. However, embodiments are not necessarily limited thereto. For example, one or more trenches TRCH1, TRCH2 may penetrate the pixel defining film PDL and the planarization layer PLNL and have their bottoms in the via layer VIAL. For example, one or more trenches TRCH1, TRCH2 may have their bottoms in at least one of the planarization layer PLNL and the via layer VIAL, and a portion of the pixel defining film PDL may be disposed within one or more trenches TRCH1, TRCH2.

[0123] 6 shows two trenches TRCH1 and TRCH2 provided in the boundary region BDA. However, embodiments are not necessarily limited thereto. For example, the pixel definition layer PDL may include one trench in the boundary region BDA. For example, the pixel definition layer PDL may include three or more trenches in the boundary region BDA.

[0124] The first and second trenches TRCH1 and TRCH2 may form discontinuous portions, such as a first void VD1 and a second void VD2, in the boundary region BDA of the light emitting structure EMS. Some of the layers stacked in the light emitting structure EMS may be cut or bent by the first and second voids VD1 and VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be cut by the first and second voids VD1 and VD2. In this manner, the first and second trenches TRCH1 and TRCH2 may at least partially separate portions of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3. When viewed from the third direction DR3, the first and second trenches TRCH1 and TRCH2 may be formed in a closed shape, for example, a rectangle having sides parallel to the first direction DR1 and the second direction DR, respectively, and the first trench TRCH1 may be formed inside the second trench.

[0125] 6, first and second voids VD1 and VD2 are formed in the light emitting structure EMS at the boundary region BDA, but the embodiment is not necessarily limited thereto. For example, a concave valley may be formed in the light emitting structure EMS at the boundary region BDA. The discontinuities formed in the light emitting structure EMS may be variously changed depending on the shapes of the first and second trenches TRCH1 and TRCH2.

[0126] The light emitting structure EMS may be formed by a process such as vacuum deposition, inkjet printing, etc. In this case, the same material as the light emitting structure EMS may be located on the bottom surfaces adjacent to the via layers VIAL in the first and second trenches TRCH1 and TRCH2.

[0127] The separator SPR may be provided in various modified forms so that the light emitting structure EMS has a discontinuous portion at the boundary region BDA.

[0128] The light emitting structure EMS may be disposed on the anode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and be disposed entirely over the first to third sub-pixels SP1 to SP3. As described above, the light emitting structure EMS may be at least partially cut or bent in the boundary region BDA by the separator SPR. This reduces current flowing from each of the first to third sub-pixels SP1 to SP3 to its adjacent sub-pixel through the layer included in the light emitting structure EMS during operation of the display panel DP (see FIG. 3). Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0129] The cathode CE may be disposed on the light emitting structure EMS. The cathode CE may be provided commonly to the first to third sub-pixels SP1 to SP3. The cathode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0130] The first anode AE1, a portion of the light emitting structure EMS overlapping the first anode AE1, and a portion of the cathode CE overlapping the first anode AE1 may constitute a first light emitting element LD1. The second anode AE2, a portion of the light emitting structure EMS overlapping the second anode AE2, and a portion of the cathode CE overlapping the second anode AE2 may constitute a second light emitting element LD2. The third anode AE3, a portion of the light emitting structure EMS overlapping the third anode AE3, and a portion of the cathode CE overlapping the third anode AE3 may constitute a third light emitting element LD3.

[0131] The first and second trenches TRCH1 and TRCH2 provided in the boundary region BDA may reduce step coverage of the cathode CE, resulting in non-uniform deposition of the cathode CE. In other words, the cathode CE may have a partially uneven surface in the boundary region BDA. For example, the portion of the cathode CE overlapping the first and second trenches TRCH1 and TRCH2 (or the first and second voids VD1 and VD2) may have a relatively thin thickness and a steeply sloping valley shape. In this case, the connectivity of the cathode CE may be reduced, and in the worst case, the cathode CE may be disconnected.

[0132] An auxiliary electrode AXE may be partially disposed on the cathode CE. For example, the auxiliary electrode AXE may be disposed on a portion of the cathode CE overlapping the boundary region BDA. The auxiliary electrode AXE may cover the portion of the cathode CE overlapping the boundary region BDA but have a flat surface. The auxiliary electrode AXE may be disposed on the portion of the cathode CE having weak connectivity, thereby complementing the connectivity. This may improve the operational reliability of the first to third light emitting elements LD1 to LD3. Furthermore, the auxiliary electrode AXE may not affect brightness because it is disposed on the portion of the cathode CE overlapping the non-emitting region NEA. The auxiliary electrode AXE may include a conductive material. For example, the auxiliary electrode AXE may include indium zinc oxide, aluminum, or silver, but the embodiment is not limited thereto.

[0133] The auxiliary electrode AXE may not be disposed on a portion of the cathode CE overlapping the first to third non-boundary regions NBA1 to NBA3 adjacent to the boundary region BDA. The first non-boundary region NBA1 may be defined as a region including the first light-emitting region EMA1 and a portion of the non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second non-boundary region NBA2 may be defined as a region including the second light-emitting region EMA2 and a portion of the non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third non-boundary region NBA3 may be defined as a region including the third light-emitting region EMA3 and a portion of the non-light-emitting region NEA surrounding the third light-emitting region EMA3. In particular, since the auxiliary electrode AXE is not disposed on the cathode CE overlapping the first to third light-emitting regions EMA1 to EMA3, high optical characteristics can be maintained. If the auxiliary electrode AXE is disposed on the cathode CE overlapping the first to third light emitting regions EMA1 to EMA3, the thickness increases and the transmittance of the light emitted from the first to third light emitting regions EMA1 to EMA3 may decrease, which may result in a decrease in brightness and degradation of optical characteristics.

[0134] The thickness t2 of the conductive layer (ie, the cathode CE and the auxiliary electrode AXE) overlapping the boundary area BDA may be greater than the thickness t1 of the conductive layer (ie, the cathode CE) overlapping the first to third non-boundary areas NBA1 to NBA3.

[0135] According to an embodiment, the auxiliary electrode AXE may be made of the same material as the cathode CE. In this case, the auxiliary electrode AXE may be referred to as the cathode CE. Under this premise, the thickness t2 of the cathode CE overlapping the boundary area BDA may be greater than the thickness t1 of the cathode CE overlapping the first to third non-boundary areas NBA1 to NBA3. By thickening the thickness of the portion of the cathode CE with weak connectivity (i.e., t2) and thinning the thickness of the portion of the cathode CE that may cause a decrease in brightness (i.e., t1), it is possible to improve the connectivity of the cathode CE while maintaining high optical characteristics.

[0136] A sealing layer TFE may be disposed on the cathode CE and the auxiliary electrode AXE, and may prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0137] Fig. 7 is a plan view of a deposition mask according to an embodiment. Fig. 8 is a perspective view showing an application example of a deposition mask according to an embodiment. In Fig. 8, for clear and concise explanation, the auxiliary electrode AXE deposited on the first pixel PXL1 of the first and second pixels PXL1 and PXL2 in Fig. 4 is schematically shown.

[0138] 7 and 8, the deposition mask MK may be made of the same material as used in the deposition process of the auxiliary electrode AXE described in FIG. 6. For example, the deposition mask MK may be a fine metal mask (FMM) made of a metal material or a fine silicone mask (FSM) made of a silicon (Si) material. The deposition mask MK may include a frame portion FP, first to third masking portions MP1 to MP3, a supporting portion SP, and an opening HP.

[0139] The frame part (or frame) FP is a skeleton of the deposition mask MK and may be made of the above-mentioned metal material or silicon material.

[0140] The first to third masking portions MP1 to MP3 may serve to protect areas where the auxiliary electrode AXE must not be deposited. The first masking portion MP1 may have a shape corresponding to the first non-border area NBA1 of the first pixel PXL1. The second masking portion MP2 may have a shape corresponding to the second non-border area NBA2 of the first pixel PXL1. The third masking portion MP3 may have a shape corresponding to the third non-border area NBA3 of the first pixel PXL1. That is, the first to third masking portions MP1 to MP3 may prevent the auxiliary electrode AXE from being deposited on the cathode CE overlapping the first to third non-border areas NBA1 to NBA3. The structures of the first to third masking portions MP1 to MP3 may be changed depending on the structures of the first to third sub-pixels SP1 to SP3 (see FIG. 5) to be deposited.

[0141] The support portions SP may serve to fix the first to third masking portions MP1 to MP3 to the frame portion FP. The support portions SP may also serve to connect the first to third masking portions MP1 to MP3 to one another. For example, the support portions SP may be arranged above, below, left, and right of each of the first to third masking portions MP1 to MP3. However, the embodiment is not necessarily limited to this, and the number and arrangement of the support portions SP may be changed.

[0142] The supporting part SP can block deposition of the auxiliary electrode AXE, as can the first to third masking parts MP1 to MP3. For example, the auxiliary electrode AXE can be prevented from being deposited on the cathode CE that overlaps with the supporting part SP. Because the auxiliary electrode AXE is an auxiliary layer for complementing the connectivity of the cathode CE, even if a part of the auxiliary electrode AXE is missing, the first pixel PXL1 can still emit light normally.

[0143] The opening HP may be located between the frame portion FP, the first to third masking portions MP1 to MP3, and the support portion SP. The opening HP may serve to allow deposition of the auxiliary electrode AXE. For example, the opening HP may allow the auxiliary electrode AXE to be deposited on the cathode CE overlapping the boundary region BDA of the first pixel PXL1. The hatched region of the first pixel PXL1 may represent the region where the auxiliary electrode AXE is deposited. That is, the deposition material may pass through the opening HP and be deposited on the cathode CE overlapping the boundary region BDA of the first pixel PXL1 to form the auxiliary electrode AXE.

[0144] FIG. 9 is a cross-sectional view of a light emitting structure according to an embodiment.

[0145] 9, the light emitting structure EMS may have a tandem structure in which first and second light emitting units EU1 and EU2 are stacked. The light emitting structure EMS may be configured substantially the same in each of the first to third light emitting devices LD1 to LD3 of FIG.

[0146] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0147] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first and second hole transport units HTU1 and HTU2 may have the same structure or different structures.

[0148] Each of the first and second electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first and second electron transport units ETU1 and ETU2 may have the same configuration as each other or different configurations.

[0149] A connection layer, which may be provided in the form of a charge generation layer CGL, is disposed between the first light-emitting portion EU1 and the second light-emitting portion EU2 and can connect them to each other. The charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, embodiments are not necessarily limited thereto.

[0150] The first and second light-emitting layers EML1 and EML2 can generate light of different colors. The light emitted from the first and second light-emitting layers EML1 and EML2 can be mixed and viewed as white light. For example, the first light-emitting layer EML1 can generate blue light, and the second light-emitting layer EML2 can generate yellow light. The second light-emitting layer EML2 can include a stacked structure of a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light. The red and green light can be mixed to provide yellow light. In this case, an intermediate layer configured to transport holes and / or block electron transport may be further disposed between the first and second sub-light-emitting layers. However, the embodiment is not necessarily limited thereto. For example, the first and second light-emitting layers EML1 and EML2 can generate light of the same color.

[0151] FIG. 10 is a cross-sectional view of a light emitting structure according to an embodiment.

[0152] 10, the light emitting structure EMS′ may have a tem- porary structure in which the first to third light emitting units EU1′ to EU3′ are stacked. The light emitting structure EMS′ may be configured substantially the same in each of the first to third light emitting devices LD1 to LD3 of FIG.

[0153] Each of the first to third light-emitting units EU1' to EU3' may include a light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0154] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration as each other or different configurations.

[0155] Each of the first to third electron transport units ETU1' to ETU3' can include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration as each other or different configurations.

[0156] The first charge generation layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2', and the second charge generation layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0157] The first to third light emitting layers EML1' to EML3' can generate light of different colors. The light emitted from the first to third light emitting layers EML1' to EML3' can be mixed and viewed as white light. For example, the first light emitting layer EML1' can generate blue light, the second light emitting layer EML2' can generate green light, and the third light emitting layer EML3' can generate red light. However, the embodiment is not necessarily limited thereto. For example, two or more of the first to third light emitting layers EML1' to EML3' can generate light of the same color.

[0158] Unlike the illustrations of Figures 9 and 10, the light emitting structure EMS of Figure 6 may include one light emitting portion in each of the first to third light emitting elements LD1 to LD3. In this case, the light emitting portions included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light emitting portion of the first light emitting element LD1 may emit red light, the light emitting portion of the second light emitting element LD2 may emit green light, and the light emitting portion of the third light emitting element LD3 may emit blue light. In this case, unlike the illustration of Figure 6, the light emitting portions of the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of them may be disposed within an opening OP of the pixel defining layer PDL.

[0159] FIG. 11 is a plan view of a pixel according to an embodiment.

[0160] Referring to FIG. 11, the first pixel PXL1' may include first to third sub-pixels SP1' to SP3'.

[0161] The first sub-pixel SP1' may include a first light-emitting region EMA1' and a non-light-emitting region NEA' surrounding the first light-emitting region EMA1'. The second sub-pixel SP2' may include a second light-emitting region EMA2' and a non-light-emitting region NEA' surrounding the second light-emitting region EMA2'. The third sub-pixel SP3' may include a third light-emitting region EMA3' and a non-light-emitting region NEA' surrounding the third light-emitting region EMA3'.

[0162] The first sub-pixel SP1′ and the second sub-pixel SP2′ may be arranged in the second direction DR2, and the third sub-pixel SP3′ may be disposed in the first direction DR1 relative to each of the first and second sub-pixels SP1′ and SP2′.

[0163] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Thus, the second light-emitting region EMA2' may have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' may have a larger area than the second light-emitting region EMA2'. However, embodiments are not necessarily limited thereto. For example, the first and second sub-pixels SP1' and SP2' may have substantially the same area, and the third sub-pixel SP3' may have a larger area than the first and second sub-pixels SP1' and SP2'. As such, the areas of the first to third sub-pixels SP1' to SP3' may be variously modified depending on embodiments.

[0164] FIG. 12 is a plan view of a pixel according to an embodiment.

[0165] Referring to FIG. 12, the first subpixel SP1″ may include a first light-emitting region EMA1″ and a non-light-emitting region NEA″ surrounding the first light-emitting region EMA1″. The second subpixel SP2″ may include a second light-emitting region EMA2″ and a non-light-emitting region NEA″ surrounding the second light-emitting region EMA2″. The third subpixel SP3″ may include a third light-emitting region EMA3″ and a non-light-emitting region NEA″ surrounding the third light-emitting region EMA3″.

[0166] The first to third sub-pixels SP1" to SP3" may have a polygonal shape when viewed in the third direction DR3. For example, the first to third sub-pixels SP1" to SP3" may have a hexagonal shape as shown in FIG.

[0167] The first to third light-emitting regions EMA1'' to EMA3'' may have a circular shape when viewed from the third direction DR3. However, the embodiment is not necessarily limited thereto. For example, each of the first to third light-emitting regions EMA1'' to EMA3'' may have a polygonal shape.

[0168] The first and third sub-pixels SP1″ and SP3″ may be arranged in a first direction DR1. The second sub-pixel SP2″ may be arranged in a direction inclined at an acute angle (or diagonally) with respect to the first sub-pixel SP1″ with respect to the second direction DR2.

[0169] The subpixel arrangements shown in Figures 5, 11, and 12 are exemplary, and examples are not necessarily limited thereto. Each pixel includes two or more subpixels, and the subpixels can be arranged in various ways, each of the subpixels can have various shapes, and each of their light-emitting areas can also have various shapes.

[0170] Fig. 13 is a cross-sectional view taken along line II' in Fig. 5 according to one embodiment. Regarding Fig. 13, the description of the same content as Fig. 6 will be simplified or omitted.

[0171] Referring to FIG. 13, the cathode CE overlapping the first and second trench regions TRA1 and TRA2 may have a gentle slope. The first trench region TRA1 may refer to the region where the first trench TRCH1 is formed, and the second trench region TRA2 may refer to the region where the second trench TRCH2 is formed. In FIG. 6, the connectivity is enhanced by forming an auxiliary electrode AXE on a portion of the cathode CE with weak connectivity, while in FIG. 13, the connectivity can be enhanced by changing the shape of the portion of the cathode CE with weak connectivity. In this case, the thickness t2 of the cathode CE overlapping the first and second trench regions TRA1 and TRA2 may be smaller than the thickness t1 of the remaining portion of the cathode CE. This is because the cathode CE overlapping the first and second trench regions TRA1 and TRA2 is melted by irradiating it with a laser LS (see FIG. 19).

[0172] 14 to 19 are cross-sectional views showing the manufacturing process of a display device according to one embodiment. In Fig. 14 to 19, it is assumed that the substrate SUB, pixel circuit layer PCL, via layer VIAL, planarization layer PLNL, etc. are manufactured according to known manufacturing processes.

[0173] 14, first to third anodes AE1 to AE3 may be patterned on the planarization layer PLNL. The first to third anodes AE1 to AE3 may be patterned at positions corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third anodes AE1 to AE3 may be patterned to penetrate the planarization layer PLNL and be connected to the first to third reflective electrodes RE1 to RE3, respectively.

[0174] 15, a pixel defining layer PDL may be patterned on the planarizing layer PLNL and the first to third anodes AE1 to AE3. The pixel defining layer PDL may be partially patterned on the first to third anodes AE1 to AE3 to have openings OP. This may expose portions of the first to third anodes AE1 to AE3 corresponding to the openings OP.

[0175] 16, first and second trenches TRCH1 and TRCH2 may be patterned at positions overlapping the boundary region BDA. In the boundary region BDA, the first and second trenches TRCH1 and TRCH2 may be patterned to be spaced apart from each other and to penetrate portions of the pixel defining layer PDL and the planarizing layer PLNL.

[0176] 17, a light emitting structure EMS may be patterned on the first to third anodes AE1 to AE3 and the pixel defining layer PDL. During the patterning of the light emitting structure EMS, first and second voids VD1 and VD2 may be formed due to the first and second trenches TRCH1 and TRCH2. The first and second voids VD1 and VD2 may form discontinuous portions in the light emitting structure EMS. In addition, portions of the light emitting structure EMS overlapping the first and second trenches TRCH1 and TRCH2 may be unevenly deposited due to reduced step coverage, resulting in a valley shape.

[0177] 18, a cathode CE may be patterned on the light emitting structure EMS. As described in FIG. 6, the portions of the cathode CE overlapping the first and second trenches TRCH1 and TRCH2 may be unevenly deposited due to reduced step coverage, resulting in a steeply sloping valley shape.

[0178] Referring to FIG. 19, the cathode CE may be partially irradiated with a laser beam LS. For example, the laser beam LS may be irradiated on a portion of the cathode CE having weak connectivity, i.e., a portion of the cathode CE overlapping the first and second trench regions TRA1 and TRA2. In this case, the portion of the cathode CE overlapping the first and second trench regions TRA1 and TRA2 may melt and change shape. For example, the portion of the cathode CE irradiated with the laser beam LS may melt and fill a steep valley, thereby forming a gentle slope in the portion of the cathode CE overlapping the first and second trench regions TRA1 and TRA2. This may improve the connectivity of the cathode CE and reduce the risk of disconnection. The laser beam LS may be a laser used in a laser lift-off (LLO) process, but the embodiment is not limited thereto.

[0179] After the connectivity of the cathode CE is ensured, a sealing layer TFE (see FIG. 13) can be formed on the cathode CE.

[0180] FIG. 20 is a block diagram of a display system according to an embodiment.

[0181] Referring to FIG. 20, a display system 1000 may include a processor 1100 and one or more display devices 1210, 1220.

[0182] The processor 1100 can perform various tasks and calculations. The processor 1100 can include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be coupled to and control other components of the display system 1000 via a bus system.

[0183] 20, the display system 1000 is shown as including first and second display devices 1210, 1220. The processor 1100 may be coupled to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0184] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured similarly to the display device 100 described with reference to FIG. 1. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0185] Via the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be configured similarly to the display device 100 described with reference to FIG. 1. In such a case, the second image data IMG2 and the second control signal CTRL2 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0186] The display system 1000 may include a computing system that provides a video display function, such as a portable computer, a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system 1000 may also include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0187] FIG. 21 is a perspective view illustrating an application example of the display system of FIG. 20 according to an embodiment.

[0188] 21, the display system 1000 of FIG. 20 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0189] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device housing case 2200. The head-mounted band 2100 may be connected to the display device housing case 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may be configured to surround the sides of the user's head, and the vertical band may be configured to surround the top of the user's head. However, embodiments are not necessarily limited thereto. For example, the head-mounted band 2100 may be realized in the form of an eyeglass frame, a helmet, or the like.

[0190] The display device housing case 2200 can house the first and second display devices 1210 and 1220 of Figure 20. The display device housing case 2200 may further house the processor 1100 of Figure 20.

[0191] FIG. 22 illustrates the head-mounted display device of FIG. 21 being worn by a user according to one embodiment.

[0192] 22, a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220 may be arranged in the head-mounted display device 2000. The head-mounted display device 2000 may further include one or more lenses LLNS, RLNS.

[0193] Within the display device housing 2200, the right eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye, and the left eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0194] The image output from the first display panel DP1 can be viewed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to direct it toward the user's right eye. The right eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0195] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 to direct it toward the user's left eye. The left eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0196] Each of the right eye lens RLNS and the left eye lens LLNS may include an optical lens having a pancake-shaped cross section. Each of the right eye lens RLNS and the left eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel outputs images corresponding to the sub-regions of the multi-channel lens, and the output images pass through the corresponding sub-regions to be viewed by a user.

[0197] Although the present disclosure has been specifically described according to the above-mentioned examples, it should be noted that the above examples are for the purpose of explaining the present disclosure and are not intended to limit the scope of the present disclosure. A person skilled in the art to which the present disclosure pertains will understand that various modifications are possible within the scope of the technical idea of ​​the present disclosure.

[0198] The scope of the present disclosure should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Furthermore, all modifications and variations derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present disclosure.

Claims

1. a pixel defining film overlapping the non-emissive region; a trench located in a boundary region between adjacent sub-pixels and penetrating the pixel defining layer; a light emitting structure disposed on the trench portion and the pixel defining layer; a cathode disposed on the light emitting structure; an auxiliary electrode disposed on a portion of the cathode that overlaps the border region.

2. 2. The display device according to claim 1, wherein the auxiliary electrode is disposed on a portion of the cathode that overlaps the trench.

3. the cathode overlaps a non-boundary region adjacent to the boundary region; The display device according to claim 2 , wherein the auxiliary electrode does not overlap the non-boundary region.

4. The display device according to claim 1 , wherein the auxiliary electrode includes a conductive material.

5. The display device according to claim 4 , wherein the auxiliary electrode comprises indium zinc oxide, aluminum, or silver.

6. a pixel defining film overlying the non-emissive region; a trench located in a boundary region between adjacent sub-pixels and penetrating the pixel defining layer; a light emitting structure disposed on the trench portion and the pixel defining layer; a cathode disposed on the light emitting structure; A display device, wherein the thickness of the portion of the cathode overlapping the boundary region is greater than the thickness of the portion of the cathode overlapping a non-boundary region adjacent to the boundary region.

7. The frame and masking portions disposed in the frame and spaced apart from each other; a support portion that fixes the masking portion within the frame; an opening surrounded by the frame, the masking portion, and the support portion; The openings correspond to the positions of the auxiliary electrodes of the display device, and the mask is used for vapor deposition of the auxiliary electrodes.

8. The deposition mask according to claim 7 , wherein the masking portion corresponds to a non-border area adjacent to a border area between adjacent sub-pixels in a display device.

9. The deposition mask according to claim 8 , wherein the openings correspond to boundary regions of the sub-pixels.

10. The deposition mask according to claim 9 , wherein the opening allows the deposition material to pass through so that the deposition material is deposited on the cathode overlapping the boundary region.

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