Data recording system

Abstract

To provide a data recording system for improving the throughput of the entire system by effectively utilizing a plurality of memories whose writing speed is changed stepwise.SOLUTION: The data recording system 200 includes a first memory, a second memory, a third memory, a data acquisition unit that acquires periodic data to be recorded in the first memory, a first memory recording unit that records the acquired data in the first memory, a first capacity determination unit that determines whether the amount of recorded data has reached a predetermined capacity A, and a second memory recording unit that records the data recorded in the first memory in the second memory when a determination result indicates that the amount of recorded data has reached the predetermined capacity A. The data recording device includes: a second capacity determining unit which determines whether the amount of recorded data has reached a predetermined capacity (B); and a third memory recording unit which records the data recorded in the second memory in a third memory when the determination result indicates that the amount of recorded data has reached the predetermined capacity (B).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a data recording system configured such that when recording a large amount of data sent at high speed, a high-speed writable memory capable of recording all of the data sent is used as the first port of call, and when a certain amount of data has accumulated in this high-speed writable memory, a predetermined amount of data is transferred to a memory with the next fastest writing speed for recording, and when a predetermined amount of data has accumulated in the memory with the second fastest writing speed, a predetermined amount of data is transferred to a memory with the next fastest writing speed for recording. [Background technology]

[0002] Measuring instruments used in factories and laboratories are fed with large amounts of data indicating measurement results. In recent years, in order to improve the time resolution of measurement results and perform more precise measurements, large amounts of data are being sent at high speeds. Traditionally, in order to record large amounts of data sent at high speeds, large amounts of high-speed memory with a write speed that can keep up with the data transfer rate have been used. On the other hand, instead of using large amounts of high-speed memory, technologies have been proposed that combine SRAM, flash memory, and memory cards to improve data read / write speeds.

[0003] One example of such technology is the invention described in Patent Document 1. This invention controls data writing to a first nonvolatile memory in which the size of a physical block, which is the erase unit, is larger than the size of a physical page, which is the minimum write unit. It also generates logical-physical address management information representing the correspondence between physical page addresses and logical addresses in the write-target physical block into which data is written by the write control, and controls the logical-physical address management information to be stored in a second nonvolatile memory each time data is written to the first nonvolatile memory. This allows data with non-consecutive logical addresses to be written consecutively in a physical block in a recording device, thereby preventing frequent garbage collections and speeding up the acquisition of logical-physical address management information, thereby improving write / read speeds. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5874525 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above invention, logical and physical address management information is generated and written to the second non-volatile memory (NV memory 16) each time host data is written, which poses a major problem in that the load of the write process on the recording device (especially the CPU) is high. [Means for solving the problem]

[0006] In view of the above-mentioned problems, the present invention aims to provide a data recording system that can improve the throughput of the entire system by combining and effectively utilizing multiple memories with gradually different writing speeds, without using large amounts of high-speed, expensive memory.

[0007] Specifically, the present invention provides a data recording system comprising: a first memory, a second memory, a third memory; a data acquisition unit that acquires periodic data to be recorded in the first memory, wherein the write speeds of the first memory and the second memory are in the order of "first memory write speed > second memory write speed > third memory write speed"; a first memory recording unit that records the data acquired by the data acquisition unit in the first memory; a first capacity determination unit that determines whether the amount of data recorded by the first memory recording unit has reached a predetermined capacity A; a second memory recording unit that, if the first capacity determination unit determines that the predetermined capacity A has been reached, records at least a portion of the data recorded in the first memory in the second memory; a second capacity determination unit that determines whether the amount of data recorded by the second memory recording unit has reached a predetermined capacity B; and a third memory recording unit that, if the second capacity determination unit determines that the predetermined capacity B has been reached, records at least a portion of the data recorded in the second memory in the third memory.

[0008] In addition to the above features, the present invention also provides a data recording system in which the size of data that the second memory recording unit records in the second memory at one time is a predetermined capacity A, and the size of data that the third memory recording unit records in the third memory at one time is a predetermined capacity B.

[0009] In addition to the above features, the present invention also provides a data recording system that controls the writing process by the first memory recording unit, the writing process by the second memory recording unit, and the writing process by the third memory recording unit to be performed according to predetermined priorities.

[0010] In addition to the above features, the present invention also provides a data recording system in which the first memory is a volatile memory, the second memory is a flash memory, and the third memory is an SD card, and the specified capacity A is an integer multiple of the capacity of a page, which is the physical memory management unit of the second memory.

[0011] In addition to the above features, the present invention also provides a data recording system in which the first memory recording unit has a data accepting means for accepting a plurality of data of different periods, a recording area dividing means for dividing the recording area of ​​the first memory in accordance with the ratio of the periods, and a data writing means for writing data of the same period into each divided recording area.

[0012] Furthermore, to realize the above-mentioned data recording system, a method executed by a CPU in the data recording system, which is a computer, and an operating program for the data recording system written in a manner readable and executable by the data recording system, which is a computer, are provided.

[0013] Specifically, the present invention provides a method executed by a CPU in a data recording system that is a computer, the method comprising: a first memory, a second memory, a third memory; a data acquisition step for acquiring periodic data to be recorded in the first memory, wherein the respective write speeds are "first memory write speed > second memory write speed > third memory write speed"; a first memory recording step for recording the data acquired in the data acquisition step in the first memory; a first capacity determination step for determining whether the amount of data recorded by the first memory recording step has reached a predetermined capacity A; a second memory recording step for recording at least a portion of the data recorded in the first memory in the second memory if the determination result of the first capacity determination step is that the predetermined capacity A has been reached; a second capacity determination step for determining whether the amount of data recorded by the second memory recording step has reached a predetermined capacity B; and a third memory recording step for recording at least a portion of the data recorded in the second memory in the third memory if the determination result of the second capacity determination step is that the predetermined capacity B has been reached.

[0014] In addition to the above features, the present invention also provides a method executed by a CPU in a data recording system that is a computer, in which the size of data recorded at one time in the second memory in the second memory recording step is a predetermined capacity A, and the size of data recorded at one time in the third memory in the third memory recording step is a predetermined capacity B.

[0015] In addition to the above features, the present invention also provides a method for controlling the writing process by the first memory recording step, the writing process by the second memory recording step, and the writing process by the third memory recording step so that they are performed according to predetermined priorities.

[0016] In addition to the above features, the present invention also provides a method executed by a CPU in a data recording system that is a computer, wherein the first memory is a volatile memory, the second memory is a flash memory, and the third memory is an SD card, and the specified capacity A is an integer multiple of the capacity of a page, which is the physical memory management unit of the second memory.

[0017] In addition to the above-mentioned features, the present invention also provides a method executed by a CPU in a data recording system that is a computer, wherein the first memory recording step has a data reception substep of receiving multiple pieces of data with different periods, a recording area division substep of dividing the recording area of ​​the first memory in proportion to the periods, and a data writing substep of writing data with the same period into each divided recording area.

[0018] Specifically, the present invention provides an operating program for a data recording system that is written in a readable and executable manner for a data recording system that is a computer comprising a first memory, a second memory, a third memory, a data acquisition step for acquiring periodic data to be recorded in the first memory, wherein the write speeds of the first memory and the second memory are in the order of "first memory write speed > second memory write speed > third memory write speed", a first memory recording step for recording the data acquired in the data acquisition step in the first memory, a first capacity determination step for determining whether the amount of data recorded by the first memory recording step has reached a predetermined capacity A, a second memory recording step for recording at least a portion of the data recorded in the first memory in the second memory if the determination result of the first capacity determination step is that the predetermined capacity A has been reached, a second capacity determination step for determining whether the amount of data recorded by the second memory recording step has reached a predetermined capacity B, and a third memory recording step for recording at least a portion of the data recorded in the second memory in the third memory if the determination result of the second capacity determination step is that the predetermined capacity B has been reached.

[0019] In addition to the above features, the present invention also provides an operating program for a data recording system that is written in a readable and executable manner for a data recording system that is a computer, in which the size of data recorded at one time in the second memory in the second memory recording step is a predetermined capacity A, and the size of data recorded at one time in the third memory in the third memory recording step is a predetermined capacity B.

[0020] The present invention also provides an operating program for a data recording system that is written in a readable and executable manner for a data recording system that is a computer that controls the writing process by the first memory recording step, the writing process by the second memory recording step, and the writing process by the third memory recording step so that they are performed in accordance with predetermined priorities.

[0021] In addition to the above features, the present invention also provides an operating program for a data recording system that is written in a readable and executable manner for a data recording system that is a computer, wherein the first memory is a volatile memory, the second memory is a flash memory, and the third memory is an SD card, and the predetermined capacity A is an integer multiple of the capacity of a page, which is the physical memory management unit of the second memory.

[0022] In addition to the above features, the present invention also provides an operating program for a data recording system that is written in a readable and executable manner for a computer that includes a first memory recording step having a data reception substep of receiving a plurality of data items with different periods, a recording area division substep of dividing the recording area of ​​the first memory in accordance with the ratio of the periods, and a data writing substep of writing data with the same period into each divided recording area. [Effects of the Invention]

[0023] As described above, the present invention provides a data recording system that can improve the throughput of the entire system by combining and effectively utilizing multiple memories with gradually different writing speeds, without using large amounts of high-speed, expensive memory. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a diagram showing a hardware configuration applied to the present invention. [Figure 2] FIG. 1 is a diagram showing the functional configuration of a data recording system according to a first embodiment. [Figure 3] FIG. 1 is a diagram showing the hardware configuration of a data recording system according to a first embodiment. [Figure 4] FIG. 1 is a diagram showing a processing flow when the data recording system according to the first embodiment is used. [Figure 5] FIG. 10 is a diagram showing the functional configuration of a data recording system according to a second embodiment. [Figure 6] FIG. 10 is a diagram showing the hardware configuration of a data recording system according to a second embodiment. [Figure 7] FIG. 10 is a diagram showing a processing flow when using the data recording system according to the second embodiment. [Figure 8] FIG. 1 is a diagram showing an example of the overall configuration of a data recording system according to the present invention. [Figure 9] A diagram showing how the recording area of ​​the first memory in the data recording system of the present invention is divided. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of group data recorded in a second memory in the data recording system of the present invention. [Figure 11] FIG. 1 shows an example of recording area management by logical addresses of a second memory in the data recording system of the present invention. [Figure 12] FIG. 10 is a diagram showing an example of writing by physical address of the second memory in the data recording system of the present invention. [Figure 13a] FIG. 1 shows an example of writing to a second memory in the data recording system of the present invention. [Figure 13b] FIG. 1 shows an example of writing to a second memory in the data recording system of the present invention. [Figure 13c] FIG. 1 shows an example of writing to a second memory in the data recording system of the present invention. [Figure 13d] FIG. 1 shows an example of writing to a second memory in the data recording system of the present invention. [Figure 14] A diagram showing an example of writing to the third memory in the data recording system of the present invention. <Hardware that can constitute the present invention>

[0025] FIG. 1 is a diagram showing a hardware configuration applied to the present invention. The present invention is, in principle, an invention that utilizes a computer, but it can also be realized by software, hardware, or the combination of software and hardware. The hardware that realizes all or part of the constituent elements of the present invention is composed of the basic components of a computer, such as a CPU, memory, bus, input / output devices, various peripheral devices, and a user interface. The various peripheral devices include storage devices, internet interfaces, internet devices, displays, keyboards, mice, speakers, cameras, videos, televisions, various sensors for monitoring production status in laboratories or factories (e.g., flow rate sensors, temperature sensors, weight sensors, liquid volume sensors, infrared sensors, shipment counters, package counters, foreign body inspection devices, defective product counters, radiation inspection devices, surface condition inspection devices, circuit inspection devices, motion sensors, worker work status monitoring devices (e.g., video, ID, PC work volume)), CD drives, DVD drives, Blu-ray drives, USB memory, USB memory interfaces, removable hard disks, general hard disks, projectors, SSDs, telephones, fax machines, copiers, printers, movie editing devices, and various sensor devices. The system does not necessarily have to be configured in a single enclosure; it can also be configured by connecting multiple enclosures via communication. Communication can be via LAN, WAN, Wi-Fi, Bluetooth (registered trademark), infrared communication, or ultrasonic communication. Furthermore, some of the components may be installed across borders. Furthermore, each of the multiple units may be operated by a different entity, or may be operated by a single entity. The system of the present invention may be operated by a single entity or multiple entities. The invention may also be configured as a system that includes, in addition to the present system, a terminal used by a third party, and a terminal used by yet another third party. These terminals may also be installed across borders. Furthermore, in addition to the present system and the terminals, devices may be provided for storing related information about third parties, registering related persons, and creating a database for recording the contents of registration. These may be provided in the present system, or may be provided outside the present system so that the present system can be configured to utilize this information.

[0026] As shown in this diagram, the computer is configured on a motherboard and comprises a chipset, CPU, non-volatile memory, main memory, various buses, BIOS, various interfaces such as USB, HDMI (registered trademark), and LAN, a real-time clock, etc. These operate in cooperation with an operating system, device drivers (for various interfaces such as USB and HDMI (registered trademark), and various built-in devices such as cameras, microphones, speakers or headphones, and displays), various programs, etc. The various programs and data that make up the present invention are configured to efficiently utilize these hardware resources to execute various processes. Chipset

[0027] A "chipset" is a set of large-scale integrated circuits (LSI) mounted on a computer's motherboard that integrates a communication function, or bridge function, between the CPU's external bus and the standard bus that connects memory and peripheral devices. Two chipset configurations are used, or one chipset configuration. The northbridge is located on the side closest to the CPU and main memory, and the southbridge is located on the side farther away, which interfaces with relatively slow external I / O.

[0028] (Northbridge) The northbridge includes a CPU interface, memory controller, and graphics interface. Most of the functions of a conventional northbridge can be performed by the CPU. The northbridge connects to the main memory slot via a memory bus, and to the graphics card slot via a high-speed graphics bus (AGP, PCI Express).

[0029] (Southbridge) The southbridge connects to the PCI interface (PCI slot) via the PCI bus and handles I / O functions such as ATA (SATA), USB, and Ethernet interfaces, as well as sound functions. Incorporating circuits to support features such as PS / 2 ports, floppy disk drives, serial ports, parallel ports, and ISA buses, which do not require or are not capable of high-speed operation, would hinder the speed of the chipset itself, so these can be separated from the southbridge chip and placed in a separate LSI called a super I / O chip. Buses are used to connect the CPU (MPU) to peripheral devices and various control units. Buses are connected by the chipset. The memory bus used to connect to main memory may instead use a channel structure for increased speed. A serial bus or a parallel bus can be used as the bus. While a serial bus transfers data one bit at a time, a parallel bus transmits the original data or multiple bits extracted from the original data as a single block over multiple communication paths simultaneously. A dedicated line for the clock signal runs parallel to the data line, synchronizing data demodulation on the receiving side. It is also used as a bus to connect the CPU (chipset) to external devices, and includes GPIB, IDE / (Parallel) ATA, SCSI, PCI, etc. Because there is a limit to how fast it can be made, in PCI Express, an improved version of PCI, and Serial ATA, an improved version of Parallel ATA, the data line can be a serial bus.

[0030] CPU

[0031] A CPU sequentially reads, interprets, and executes a sequence of instructions called a program stored in main memory, outputting signal-based information to the main memory. The CPU functions as the center of computation within a computer. A CPU consists of a CPU core, which is the center of computation, and its peripheral components, including registers, cache memory, an internal bus connecting the cache memory to the CPU core, a DMA controller, a timer, and an interface with the bus connecting to the north bridge. A single CPU (chip) may have multiple CPU cores. Processing may also be performed by a graphics interface (GPU) or FPU in addition to the CPU. While the embodiments are described as being of a two-core type, this is not limiting. Programs may also be embedded within the CPU.

[0032] <Non-volatile memory>

[0033] (HDD)

[0034] The basic structure of a hard disk drive consists of a magnetic disk, a magnetic head, and an arm on which the magnetic head is mounted. The external interface can be SATA (formerly ATA). A high-performance controller, such as SCSI, is used to support communication between hard disk drives. For example, when copying a file to another hard disk drive, the controller can read the sectors, transfer them to the other hard disk drive, and write them. This does not access the host CPU's memory, so there is no increase in the CPU load.

[0035] <Main memory>

[0036] The CPU directly accesses and executes various programs in main memory. Main memory is volatile memory and uses DRAM. Programs in main memory are expanded from non-volatile memory to main memory upon receiving a program startup command. The CPU then executes the program according to various execution commands and execution procedures within the program.

[0037] Operating System (OS)

[0038] An operating system is used to manage computer resources for use by applications, to manage various device drivers, and to manage the computer itself (the hardware). In small computers, firmware is sometimes used as the operating system.

[0039] ≪BIOS≫

[0040] The BIOS causes the CPU to execute procedures for starting up the computer hardware and running the operating system. It is most typically the hardware that the CPU reads first when it receives a computer startup command. The BIOS contains the address of the operating system stored on the disk (non-volatile memory), and the BIOS loaded into the CPU sequentially loads the operating system into main memory, putting it into operation. The BIOS also has a check function that checks the presence or absence of various devices connected to the bus. The check results are stored in main memory and made available to the operating system as appropriate. The BIOS may also be configured to check for external devices, etc. The above applies to all embodiments.

[0041] As shown in the figure, the present invention can basically be configured with a general-purpose computer program and various devices. The computer basically operates by loading a program recorded in non-volatile memory into main memory, and then executing processing using the main memory, CPU, and various devices. Communication with devices is performed via an interface connected to a bus line. Possible interfaces include a display interface, keyboard, and communication buffer. Below, an embodiment of the present invention will be described with reference to the illustrated examples.

[0042] <Fulfillment of the Laws of Nature of the Invention>

[0043] The present invention relates to a data recording system that functions through the cooperation of a computer, communications equipment, and software. Specifically, when recording large amounts of data transmitted at high speed, a high-speed writable memory is used as the first port of call, capable of recording all data received. Once a certain amount of data has accumulated in the high-speed writable memory, a predetermined amount of data is transferred to a memory with the next-fastest write speed for recording. Once a predetermined amount of data has accumulated in the memory with the next-fastest write speed, a predetermined amount of data is transferred to a memory with the next-fastest write speed for recording. Therefore, from this perspective, when the claimed invention is assessed based on the computer and other resources described in the claims and specification and the common general knowledge related to those matters, the claimed invention as a whole utilizes a law of nature and is a computer software-related invention.

[0044] <The significance of utilizing the laws of nature required by patent law>

[0045] The Patent Act requires that an invention be industrially applicable and contribute to the development of industry. This requirement ensures that the invention is industrially applicable. In other words, the invention must be industrially useful; that is, the effects of the invention declared in the application must be reproducible with a certain degree of certainty through the practice of the invention. From this perspective, the application of the laws of nature is interpreted as the use of the laws of nature to achieve the functions of each of the invention's defining features (invention elements), which constitute the invention's effects. Furthermore, the effect of an invention is sufficient if it has the potential to provide a specific utility to users who use the invention, and should not be viewed in terms of how users feel or think about that utility. Therefore, even if the effect users gain from the system is a psychological effect, that effect itself does not fall within the scope of the required application of the laws of nature. DETAILED DESCRIPTION OF THE INVENTION

[0046] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The relationships between the embodiments and the claims are as follows: The explanation of embodiment 1 mainly relates to claims 1, 6, and 11, and the explanation of embodiment 2 mainly relates to claims 5, 10, and 15. The present invention should not be limited to these embodiments in any way, and may be embodied in various forms without departing from the spirit of the invention.

[0047] <Embodiment 1 (corresponding mainly to claims 1, 6, and 11)> <Outline of Embodiment 1> The invention in this embodiment is an invention in which, when the amount of data recorded in a first memory having the fastest write speed reaches a predetermined capacity A, at least a portion of the data recorded in the first memory is transferred to and recorded in a second memory having the second fastest write speed, and when the amount of data recorded in the second memory reaches a predetermined capacity B, at least a portion of the data recorded in the second memory is transferred to and recorded in a third memory having the third fastest write speed. <Supplementary Overview of Embodiment 1> In particular, in this embodiment, the data acquisition unit receives data packets at high speed, extracts information from the payload portion, and writes it to the first memory. Then, once the information from the payload portion has been accumulated, the accumulated data is collectively written to the second memory. Once the accumulated data written to the second memory is further accumulated, the data accumulated in the second memory is collectively written to the third memory. In other words, the accumulated data is sequentially collectively transferred to the next memory. Transferring the accumulated data increases data transfer efficiency compared to transferring individual, independent packet-based data chunks before accumulation to the next memory.

[0048] <Functional Configuration of Embodiment 1> 2 is a diagram showing the functional configuration of a data recording system in embodiment 1. In this embodiment, a data recording system 200 includes a first memory 201, a second memory 202, a third memory 203, a data acquisition unit 204, a data recording unit 205, a first memory recording unit 206, a first capacity determination unit 207, a second memory recording unit 208, a second capacity determination unit 209, and a third memory recording unit 210.

[0049] <Embodiment 1: Description of Configuration: First Memory> The "first memory" 201 is composed of a volatile memory capable of recording multiple data sets with different cycles (e.g., multiple types of data obtained by measuring the status of various devices or equipment to be monitored). For example, it is preferable to use a very high-speed static random access memory (SRAM) as the volatile memory. Assuming a typical SRAM has an access time of 10 nanoseconds and a data bus width of 32 bits, the data write speed can be calculated as approximately 381.47 MB / s, taking into account the number of writes per second, the amount of data that can be written per write, and the total amount of data written per second. Furthermore, the first memory uses the volatile memory as a queue, allowing it to record and hold data for several tens of seconds. While the present invention will be described assuming the use of a 512-kilobyte SRAM, this capacity is not necessarily limited.

[0050] <Embodiment 1: Description of Configuration: Second Memory> The "second memory" 202 is composed of a nonvolatile memory capable of transferring and recording multiple data items recorded in the first memory 201. For example, it is preferable to use a relatively high-speed flash memory (e.g., a NAND flash memory) as the nonvolatile memory. Assuming that a typical NAND flash memory has a write operation time of 200 μs and a page size of 8 kB, and taking into account the number of writes per second and the total amount of data written per second, the data write speed can be calculated as "approximately 39.06 MB / s." Furthermore, the second memory uses the nonvolatile memory as a queue, allowing it to record and retain data for several hours. While the present invention will be described assuming the use of a 64 MB flash memory, this capacity is not necessarily limited.

[0051] <Configuration of Embodiment 1: Third Memory> The "third memory" 203 is composed of a nonvolatile memory that can transfer multiple data recorded in the second memory 202, convert them into a predetermined file format, and write them. For example, it is preferable to use an SD card as the nonvolatile memory because it is portable, easy to use, and has a large capacity. SD cards are generally assigned a "class" that indicates their write speed. For example, a Class 2 SD card has a minimum write speed of 2 MB / s, and a Class 10 SD card has a minimum write speed of 10 MB / s. In other words, the actual write speed of a Class 10 SD card is "10 MB / s." Note that, while the present invention will be described assuming the use of an SD card with a maximum capacity of 32 GB, this capacity is not necessarily limited.

[0052] <Embodiment 1: Description of Configuration: Data Acquisition Unit> The 'data acquisition unit' 204 is configured to have the function of acquiring periodic data to be recorded in the first memory. For example, it is assumed that data with a cycle of 100 ms is measurement data such as "pressure" or "flow rate," and data with a cycle of 1 second (1000 ms) is measurement data such as "temperature." Here, measurement data such as "pressure" and "flow rate" often change instantaneously, and measurement data such as "temperature" often changes relatively slowly compared to "pressure" and "flow rate," so the data is configured to be acquired at such cycles.

[0053] <Embodiment 1: Description of Configuration: Data Recording Unit> The "data recording unit" 205 is composed of the above-mentioned first memory 201, second memory 202, third memory 203, and data acquisition unit 204 that acquires multiple periodic data to be recorded in the first memory, and is desirably configured so that the write speeds of each are "first memory write speed > second memory write speed > third memory write speed." For example, as described above, the write speed of the first memory is "approximately 381.47 MB / s," the write speed of the second memory is "approximately 39.06 MB / s," and the write speed of the third memory is "10 MB / s," so it can be seen that the configuration satisfies the relationship "first memory write speed > second memory write speed > third memory write speed."

[0054] <Embodiment 1: Description of Configuration: First Memory Recording Unit> The 'first memory recording unit' 206 is configured to have the function of recording the data acquired by the data acquisition unit 204 described above in the first memory 201 . Furthermore, as will be described later, when writing multiple periodic data to the first memory, the first memory recording unit 206 is designed to divide the recording area of ​​the first memory in proportion to the periods, and write data of the same period to each recording area. This point will be described in detail in the second embodiment described later.

[0055] <Configuration of Embodiment 1: First Capacity Determination Unit> The 'first capacity determination unit' 207 is configured to have the function of determining whether the amount of data recorded by the first memory recording unit 206 has reached a predetermined capacity A or not. For example, if the total capacity of the first memory is 512 kilobytes and the predetermined capacity A is set to 460 kilobytes, the first capacity determination unit 207 will determine whether the amount of data recorded by the first memory recording unit 206 has reached the predetermined capacity A (in this case, 460 kilobytes).

[0056] <Embodiment 1: Configuration: Second Memory Recording Unit> The "second memory recording unit" 208 is configured to have the function of recording at least a portion of the data recorded in the first memory 201 in the second memory 202 when the judgment result of the first capacity judgment unit 207 is that the predetermined capacity A has been reached. For example, when the data recorded by the first memory recording unit 206 reaches 480 kilobytes and the first capacity determination unit 207 determines that this has reached a predetermined capacity A (460 kilobytes in this case), the second memory recording unit 208 may be configured to transfer and record 400 kilobytes of the data recorded in the first memory 201 to the second memory 202. The second memory recording unit 208 may also be configured to transfer and record 460 kilobytes of data, which corresponds to the predetermined capacity A, at one time to the second memory 202. In other words, it is preferable to record the data recorded in the first memory 201 in the next second memory 202 before the data constantly arriving in the first memory 201 begins to overflow.

[0057] <Configuration of Embodiment 1: Second Capacity Determination Unit> The 'second capacity determination unit' 209 is configured to have the function of determining whether the amount of data recorded by the second memory recording unit 208 has reached a predetermined capacity B. For example, if the total capacity of the second memory 202 is 64 MB and the predetermined capacity B is set to 57.6 MB, the second capacity determination unit 209 will determine whether the amount of data recorded by the second memory recording unit 208 has reached the predetermined capacity B (57.6 MB in this case).

[0058] <Embodiment 1: Description of Configuration: Third Memory Recording Unit> The "third memory recording unit" 210 is configured to have the function of recording at least a portion of the data recorded in the second memory 202 in the third memory 203 when the judgment result of the second capacity judgment unit 209 is that the predetermined capacity B has been reached. For example, when the data recorded by the second memory recording unit 208 reaches 60 MB and the second capacity determination unit 209 determines that this has reached a predetermined capacity B (57.6 MB in this case), the third memory recording unit 210 may be configured to transfer and record 50 MB of the data recorded in the second memory 202 to the third memory 203. The third memory recording unit 208 may also be configured to record 57.6 MB of data, which corresponds to the predetermined capacity B, in the third memory 203 at one time. In other words, it is preferable to record the data recorded in the second memory 202 in the next third memory 203 before the data recorded in the first memory 202 begins to overflow.

[0059] Furthermore, it is desirable to configure the system so that the write process by the first memory recording unit 206, the write process by the second memory recording unit 208, and the write process by the third memory recording unit 210 are controlled according to a predetermined priority. In reality, since data acquisition is performed continuously, it is expected that the first memory 201 will reach a predetermined capacity during the write process from the second memory 202 to the third memory 203. In such a case, it is desirable to control the write process according to a predetermined priority. Specifically, it is possible to set the priority in descending order to the write process to the first memory 201 by the first memory recording unit 206, the write process to the second memory 202 by the second memory recording unit 208, and the write process to the third memory 203 by the third memory recording unit 210. In other words, the system controls the first memory 201, which has the fastest write speed, to transfer and write all data at once to the second memory 202, which has the next fastest write speed, before the data overflows the predetermined capacity. Furthermore, control is performed so that data is transferred and written all at once to the third memory 203, which has a faster writing speed, before the data in the second memory 202, which has the next fastest writing speed, exceeds a predetermined capacity. Alternatively, during the data write process in the first memory 201, the write process in the second memory 202 or the write process in the third memory 203 may be temporarily put on hold, and the data write process in the first memory 201 may be given top priority. By determining the priority in advance in this way, the data write process can be performed accurately and appropriately even if a problem is about to occur.

[0060] It is also desirable that the first memory 201 be composed of SRAM, which is a volatile memory, the second memory 202 be composed of flash memory, which is a nonvolatile memory, and the third memory be composed of an SD card, which is a nonvolatile memory. It is also desirable that the predetermined capacity A be an integral multiple of the capacity of a page, which is the physical memory management unit of the second memory 202. For example, if a flash memory is used as the second memory 202, the size of a "page," which is the physical memory management unit of the flash memory, varies depending on the type of flash memory, but generally, in a NAND-type flash memory, one page is 2,112 bytes (consisting of a 2,048-byte user data area and a 64-byte redundant area). Therefore, in the case of a flash memory with a capacity of 512 kilobytes, it will be divided into approximately 245 pages (512,000 bytes ÷ 2,112 bytes / page). In other words, it is preferable that the predetermined capacity A be an integral multiple of the page (2,112 bytes), which is the physical memory management unit of the second memory 202 (in this case, a NAND flash memory). This makes it easier to manage the data write process in this system.

[0061] FIG. 8 is a diagram showing an example of the overall configuration of a data recording system according to the present invention. For example, data A801 ​​is data (e.g., measurement data such as "pressure" or "flow rate") acquired at a period of 100 ms, while data B802 is data (e.g., measurement data such as "temperature") acquired at a period of 1 second. Then, the data A and data B are written to the first memory 803 (for example, an SRAM, which is a volatile memory). Here, the first memory 803 is used as a queue, and is configured to record and hold data for about several tens of seconds. The data recorded and held in the first memory 803 is then written to a second memory 804 (for example, a flash memory, which is a non-volatile memory). Here, the second memory 804 is used as a queue, and is configured to record and hold data for about several hours. The data recorded and held in the second memory 804 is converted into a file format and then written to the third memory 805 (for example, an SD card, which is a non-volatile memory).

[0062] FIG. 10 is a diagram showing an example of the configuration of group data recorded in the second memory in the data recording system of the present invention. Here, the information represented by "channel data" (e.g., CH1 to CHn) indicates the type of measurement data. For example, CH1 is pre-assigned information indicating "temperature," CH2 is pre-assigned information indicating "flow rate," and CH3 is pre-assigned information indicating "pressure." In this diagram, data A 1101 is composed of CH1 to CHn (n is a natural number up to 100), and data B 1102 represents a data group composed of CH1 to CHn. The user then registers the channel data by group and lumps them together as group data. Grouping data by group in this way makes it easier for the user to manage. Furthermore, group data 1 is composed only of data group A having a specific period, and cannot be mixed with data group B having a different period. In other words, one period's worth of data is read from first memory 201, arranged by group, and then transferred to second memory 202 for recording.

[0063] FIG. 11 is a diagram showing an example of recording area management by logical addresses of the second memory in the data recording system of the present invention. In this diagram, group data 1 (1201) is transferred and recorded in group 1 recording area 1204 of second memory 202 (e.g., NAND flash memory). Other group data are similarly transferred and recorded in the corresponding group recording areas. Note that the second memory 202 is configured to manage each group using a logical address. Also, each group recording area is fixed and allocated equally. This differs from the first memory 201. The reason is that group registration is often changed frequently by users, and if the length were variable, there is a risk that previously recorded data would be lost.

[0064] FIG. 12 is a diagram showing an example of writing using a physical address of the second memory in the data recording system of the present invention. In this diagram, group data 1 is written in predetermined page units to the second memory (for example, NAND flash memory) 1302. This is because the NAND flash memory, which is a nonvolatile memory, has a predetermined page size represented by a physical address, and is generally designed so that writing across pages is not possible.

[0065] FIG. 13a is a diagram showing an example of writing to the second memory in the data recording system of the present invention. As shown in this figure, one group data 1401 has a group data size 1402, and in the second memory (e.g., NAND flash memory) 1403, a write address 1404 and a page boundary size 1405 are determined by a physical address in page 1. For example, a process will be described when group data 1401 consisting of data with the same period is written to second memory 1403. Generally, the write process is performed using the following method. (1) First, calculate the group data size 1402. (2) Next, calculate the page boundary size from the current write address and the physical address of the page. (3) Then, calculate the number of pages and fractional data size based on the following formula: Number of pages = (group data size - page border size) / page size Fractional data size = (group data size - page boundary size) % page size (4) Furthermore, the group data for the page boundary size is written to the second memory 1403. Also, the group data for the number of pages is written into the second memory 1403 . Finally, the group data for the fractional data size is written into the second memory 1403. For ease of understanding, let us assume that the group data size is 1500 bytes, the write address is 300, and the page size is 500 bytes. In this case, the page boundary size=page size-write address=500-300=200 bytes. Furthermore, the number of pages = (1500 - 300) / 500 = 2, and the fractional size data (remainder) = 200 bytes.

[0066] FIG. 13b is a diagram showing an example of writing to the second memory in the data recording system of the present invention. As shown in this figure, in page 1 of the second memory (for example, NAND flash memory) 1403, 200 bytes of group data corresponding to the page boundary size 1405 are first written.

[0067] FIG. 13c is a diagram showing an example of writing to the second memory in the data recording system of the present invention. As shown in this figure, data equivalent to two pages of the group data is written to page 2 and page 3 of the second memory (for example, a NAND flash memory) 1403.

[0068] FIG. 13d is a diagram showing an example of writing to the second memory in the data recording system of the present invention. As shown in this figure, 200 bytes, which corresponds to the fractional data size (remainder) of the group data, are written to page 4 of the second memory (for example, NAND flash memory) 1403. As described above, writing of group data to the second memory (for example, NAND flash memory) is performed using a physical address. Furthermore, since the final address at which the current group data is written is used as the write address for the next group data, data can be written continuously without gaps, eliminating waste in the memory recording area.

[0069] FIG. 14 is a diagram showing an example of writing to the third memory in the data recording system of the present invention. As shown in this figure, group data is read from second memory 1101 (e.g., NAND flash memory), then converted into a file format compatible with the FAT (File Allocation Table) file system used in third memory 1102 (e.g., SD card), and then written to third memory 1102 as a single file.

[0070] Although the present embodiment has been described assuming data having two different periods, the present embodiment is not limited to this. For example, the present embodiment can be applied to data having three or four different periods in the same manner as described above.

[0071] To reiterate, it is desirable to configure the system so that the write process by the first memory recording unit 206, the write process by the second memory recording unit 208, and the write process by the third memory recording unit 210 are controlled according to a predetermined priority. In reality, since data acquisition is performed continuously, it is expected that the first memory 201 will reach a predetermined capacity during the write process from the second memory 202 to the third memory 203. In such a case, it is desirable to control the write process according to a predetermined priority. Specifically, the priority can be set in the order of highest to lowest in the write process to the first memory 201 by the first memory recording unit 206, the write process to the second memory 202 by the second memory recording unit 208, and the write process to the third memory 203 by the third memory recording unit 210. In other words, the first memory 201, which has the fastest write speed, is controlled to transfer and write data all at once to the second memory 202, which has the next fastest write speed, before the data overflows the predetermined capacity. Furthermore, control is performed so that data is transferred and written all at once to the third memory 203, which has a faster writing speed, before the data in the second memory 202, which has the next fastest writing speed, exceeds a predetermined capacity. Alternatively, during the data write process in the first memory 201, the write process in the second memory 202 or the write process in the third memory 203 may be temporarily put on hold, and the data write process in the first memory 201 may be given top priority. By determining the priority in advance in this way, the data write process can be performed accurately and appropriately even if a problem is about to occur.

[0072] <Embodiment 1: Data Recording System: Hardware Configuration> The hardware configuration of the data recording system according to this embodiment will be described with reference to the drawings.

[0073] 3 is a diagram showing the hardware configuration of a data recording system according to this embodiment. As shown in this diagram, the data recording system according to this embodiment comprises a "CPU (Central Processing Unit)" 301 that performs various types of arithmetic processing, and a "main memory" 302. It also comprises a "non-volatile memory" 303 that stores predetermined information, and a "network I / F (interface)" 304 that transmits and receives information to and from various devices and equipment that are external monitoring targets. These components are interconnected by a data communication path such as a "bus" 305, and perform the transmission and reception of information and processing.

[0074] Here, the "main memory" reads out programs that perform various processes to be executed by the "CPU," and also provides a work area for the programs. Furthermore, multiple addresses are assigned to the "main memory" and "non-volatile memory," and programs executed by the "CPU" can exchange data and perform processing by identifying and accessing these addresses. In this embodiment, the programs stored in the "main memory" include a data acquisition program, a data recording program, a first memory recording program, a first capacity determination program, a second memory recording program, a second capacity determination program, and a third memory recording program. Furthermore, the "main memory" and "non-volatile memory" store periodic data, a predetermined capacity A, a predetermined capacity B, and the like.

[0075] The "CPU" executes a data acquisition program stored in the "main memory" to acquire periodic data to be recorded in the first memory and store the periodic data in the "main memory" or the "non-volatile memory." The "CPU" also executes a data recording program stored in the "main memory" to set the following relationship: "first memory write speed > second memory write speed > third memory write speed." The "CPU" also executes a first memory recording program stored in the "main memory" to record data acquired by the data acquisition program in the first memory. The "CPU" also executes a first capacity determination program stored in the "main memory" to determine whether the amount of data recorded by the first memory recording program has reached a predetermined capacity A and stores the predetermined capacity A in the "main memory" or the "non-volatile memory." The "CPU" also executes a second memory recording program stored in the "main memory" to record at least a portion of the data recorded in the first memory in the second memory if the first capacity determination program determines that the predetermined capacity A has been reached. The "CPU" also executes a second capacity determination program stored in the "main memory" to determine whether the amount of data recorded by the second memory recording program has reached a predetermined capacity B and stores the predetermined capacity B in the "main memory" or the "non-volatile memory." In addition, a third memory recording program stored in the "main memory" is executed, and if the determination result of the second capacity determination program is that the predetermined capacity B has been reached, at least a portion of the data recorded in the second memory is recorded in the third memory.

[0076] <Embodiment 1 Data Recording System: Processing Flow> 4 is a diagram showing the processing flow when using the data recording system of this embodiment. As shown in the diagram, the processing method comprises a data acquisition step S401, a data recording step S402, a first memory recording step S403, a first capacity determination step S404, a second memory recording step S405, a second capacity determination step S406, and a third memory recording step S407. These processing methods are executed by a data recording system comprising a first memory, a second memory, a third memory, a data acquisition unit that acquires periodic data to be recorded in the first memory, a data recording unit whose respective write speeds are "first memory write speed > second memory write speed > third memory write speed", a first memory recording unit that records the data acquired by the data acquisition unit in the first memory, a first capacity determination unit that determines whether the amount of data recorded by the first memory recording unit has reached a predetermined capacity A, a second memory recording unit that records at least a portion of the data recorded in the first memory in the second memory when the first capacity determination unit determines that the predetermined capacity A has been reached, a second capacity determination unit that determines whether the amount of data recorded by the second memory recording unit has reached a predetermined capacity B, and a third memory recording unit that records at least a portion of the data recorded in the second memory in the third memory when the second capacity determination unit determines that the predetermined capacity B has been reached.

[0077] The "data acquisition step" S401 is a stage for acquiring periodic data to be recorded in the first memory.

[0078] The "data recording step" S402 is a step consisting of a first memory, a second memory, a third memory, and a data acquisition step for acquiring periodic data to be recorded in the first memory, and in which the write speeds of each are "first memory write speed > second memory write speed > third memory write speed."

[0079] The "first memory recording step" S403 is a stage in which the data acquired in the data acquisition step is recorded in the first memory.

[0080] The "first capacity determination step" S404 is a step for determining whether the amount of data recorded in the first memory recording step has reached a predetermined capacity A.

[0081] The "second memory recording step" S405 is a step in which, if the judgment result in the first capacity judgment step is that the predetermined capacity A has been reached, at least a portion of the data recorded in the first memory is recorded in the second memory.

[0082] The "second capacity determination step" S406 is a step for determining whether the amount of data recorded in the second memory recording step has reached a predetermined capacity B.

[0083] The "third memory recording step" S407 is a step in which, if the judgment result in the second capacity judgment step is that the predetermined capacity B has been reached, at least a portion of the data recorded in the second memory is recorded in the third memory.

[0084] <Summary> As described above, the present invention provides a data recording system that can improve the throughput of the entire system by combining and effectively utilizing multiple memories with gradually different write speeds, without using a large amount of high-speed, expensive memory. Furthermore, since data is written all at once rather than written each time, the write speed of the entire system is increased. Furthermore, since data is written without gaps using physical addresses for the second memory (e.g., NAND flash memory), no waste is created in the memory's recording area.

[0085] <Embodiment 2 (corresponding mainly to claims 5, 10, and 15)> <Outline of Embodiment 2> This embodiment is based on embodiment 1, and is characterized in that the first memory recording unit includes a data receiving means for receiving multiple pieces of data with different cycles, a recording area dividing means for dividing the recording area of ​​the first memory at the ratio of the cycles, and a data writing means for writing data with the same cycle to each divided recording area. From here on, descriptions of the functional configuration, hardware configuration, and processing flow that are the same as embodiment 1 will be omitted as appropriate.

[0086] <Functional Configuration of Second Embodiment> 5 is a diagram showing the functional configuration of a data recording system in embodiment 2. In this embodiment, the system comprises a data receiving unit 501, a recording area dividing unit 502, and a data writing unit 503.

[0087] <Configuration of Second Embodiment: Data Receiving Means> The "data receiving means" 501 is configured to have the function of receiving a plurality of data sets with different cycles. For example, it is assumed that data with a cycle of 100 ms is measurement data such as "pressure" or "flow rate," and data with a cycle of 1 second is measurement data such as "temperature." Measurement data such as "pressure" and "flow rate" often change instantaneously. On the other hand, measurement data such as "temperature" does not change as suddenly as "pressure" or "flow rate," and changes relatively slowly, so the system is configured to accept data with such cycles.

[0088] <Embodiment 2: Description of Configuration: Recording Area Dividing Means> The 'recording area dividing means' 502 is configured to have the function of dividing the recording area of ​​the first memory at the ratio of the period. FIG. 9 is a diagram showing how the recording area of ​​the first memory is divided in the data recording system of the present invention. For example, assume that data A 901 is acquired at a cycle of 100 ms, while data B 902 is acquired at a cycle of 1 second. In this case, "A" in the figure represents the cycle of data A, "B" in the figure represents the cycle of data B, and "C" in the figure represents the recording area capacity of first memory 903. In this case, the first memory 903 (such as a volatile memory such as an SRAM) will have its recording area divided based on the ratio of these periods. In other words, for data A901, a recording area 904 with a capacity expressed as "C x A / (A+B)" is divided and allocated, and for data B902, a recording area 905 with a capacity expressed as "C x B / (A+B)" is divided and allocated. Specifically, assuming that the period of data A is "100 ms", the period of data B is "1 second = 1000 ms", and the capacity C of the recording area of ​​first memory 903 is "512 kilobytes", the recording area of ​​data A will be approximately 47 kilobytes, and the recording area of ​​data B will be approximately 465 kilobytes.

[0089] For example, if each data of data A with a period (500 ms) and each data of data B with a period (1 sec = 1000 ms) are written without dividing the recording area as described above, the data arrangement will be as follows. 500 ms → Data A (e.g., measurement data such as "pressure" or "flow rate") 500msec → Data A (same as above) 1000 ms → Data B (e.g., measurement data such as "temperature") 500 ms → Data A (e.g., measurement data such as "pressure" or "flow rate") 500msec → Data A (same as above) 1000 ms → Data B (e.g., measurement data such as "temperature") In such cases, data will be mixed at 500ms and 1000ms, and even a slight deviation in the read timing will result in incorrect data being obtained. In such cases, in addition to the normal management method, it will be necessary to take extra measures such as adding special data for management purposes (such as type identification information that indicates the type of data) and accurately adjusting the read timing, which could result in an extremely time-consuming and inefficient system overall. On the other hand, in this embodiment, the recording area of ​​the first memory is divided according to the ratio of the periods and data is recorded therein, which makes management easier without mixing different types of data across multiple periods, and has the advantage of making the system very efficient overall.

[0090] <Embodiment 2: Description of Configuration: Data Writing Means> The "data writing means" 503 is configured to have the function of writing data of the same period into each divided recording area. For example, data at a cycle of 100 msec is written in the data A recording area divided by the above-mentioned recording area dividing means, and data at a cycle of 1 second is written in the data B recording area.

[0091] Although the present embodiment has been described on the assumption that data has two different periods, the present embodiment can also be applied to data having three or more different periods.

[0092] <Embodiment 2: Data Recording System: Hardware Configuration> The hardware configuration of the data recording system according to this embodiment will be described with reference to the drawings.

[0093] 6 is a diagram showing the hardware configuration of a data recording system according to this embodiment. As shown in this diagram, the data recording system according to this embodiment comprises a "CPU (Central Processing Unit)" 601 that performs various types of arithmetic processing, and a "main memory" 602. It also comprises a "non-volatile memory" 603 that stores predetermined information, and a "network I / F (interface)" 604 that transmits and receives information to and from various external devices and equipment that are targets of monitoring. These components are interconnected by a data communication path such as a "bus" 605, and perform the transmission and reception of information and processing.

[0094] Here, the "main memory" reads out programs that perform various processes to be executed by the "CPU," and also provides a work area for the programs. The "main memory" and "non-volatile memory" are each assigned multiple addresses, and programs executed by the "CPU" can exchange data and perform processing by identifying and accessing these addresses. In this embodiment, the programs stored in the "main memory" include a data reception subprogram, a recording area division subprogram, and a data writing subprogram. In addition to the same information as in embodiment 1, the "main memory" and "non-volatile memory" also store first memory size information, data A cycle information, data B cycle information, and the like.

[0095] The "CPU" executes a data reception subprogram stored in the "main memory" to receive multiple pieces of data with different cycles, and stores data A cycle information and data B cycle information in the "main memory" and the "non-volatile memory." It also executes a recording area division subprogram stored in the "main memory" to refer to the first memory size information, divide the recording area of ​​the first memory in accordance with the cycle ratio, and store the first memory size information in the "main memory" and the "non-volatile memory." It also executes a data writing subprogram stored in the "main memory" to write data with the same cycle into each divided recording area.

[0096] <Embodiment 2 Data Recording System: Processing Flow> 7 is a diagram showing the processing flow when using the data recording system of this embodiment. As shown in the diagram, the processing method comprises a data reception sub-step S701, a recording area division sub-step S702, and a data writing sub-step S703. These processing methods are executed by a data recording system in which the first memory recording unit has a data receiving means for receiving a plurality of data of different periods, a recording area dividing means for dividing the recording area of ​​the first memory in accordance with the ratio of the periods, and a data writing means for writing data of the same period into each divided recording area.

[0097] The "data reception substep" S701 is a stage for receiving a plurality of data sets with different cycles.

[0098] The "recording area dividing sub-step" S702 is a stage in which the recording area of ​​the first memory is divided at the ratio of the period.

[0099] The "data writing sub-step" S703 is a stage in which data of the same period is written into each divided recording area.

[0100] <Summary> As described above, in the present invention, by acquiring multiple pieces of data with different periods and dividing the recording area of ​​the first memory (e.g., SRAM) according to the ratio of those periods and recording the data, it becomes easier to manage without mixing multiple pieces of data with different periods, and it is possible to create a very efficient data recording system overall. [Explanation of symbols]

[0101] Data recording system: 200 First memory: 201 Second memory: 202 Third memory: 203 Data acquisition section: 204 Data recording unit: 205 First memory recording unit: 206 First capacity judgment section: 207 Second memory recording unit: 208 Second capacity judgment section: 209 Third memory recording unit: 210

Claims

1. a data recording unit that is composed of a first memory, a second memory, a third memory, and a data acquisition unit that acquires periodic data to be recorded in the first memory, and the write speeds of the first memory, second memory, and third memory are in the order of "first memory write speed > second memory write speed > third memory write speed"; a first memory recording unit that records the data acquired by the data acquisition unit in a first memory; a first capacity determination unit that determines whether the amount of data recorded by the first memory recording unit has reached a predetermined capacity A; a second memory recording unit that records at least a portion of the data recorded in the first memory in a second memory when the first capacity determination unit determines that the capacity has reached a predetermined capacity A; a second capacity determination unit that determines whether the amount of data recorded by the second memory recording unit has reached a predetermined capacity B; a third memory recording unit that records at least a part of the data recorded in the second memory in a third memory when the second capacity determination unit determines that the capacity has reached a predetermined capacity B; A data recording system having:

2. The data recording system of claim 1, wherein the size of data that the second memory recording unit records in the second memory at one time is a predetermined capacity A, and the size of data that the third memory recording unit records in the third memory at one time is a predetermined capacity B.

3. 3. A data recording system as described in claim 1 or claim 2, wherein the writing process by the first memory recording unit, the writing process by the second memory recording unit, and the writing process by the third memory recording unit are controlled to be performed according to predetermined priorities.

4. A data recording system as described in claim 1 or claim 2, wherein the first memory is a volatile memory, the second memory is a flash memory, and the third memory is an SD card, and the specified capacity A is an integer multiple of the capacity of a page, which is the physical memory management unit of the second memory.

5. The first memory recording unit data receiving means for receiving a plurality of data having different cycles; a recording area dividing means for dividing the recording area of ​​the first memory at the ratio of the period; a data writing means for writing data of the same period into each of the divided recording areas; 2. The data recording system of claim 1, comprising:

6. A method executed by a CPU in a data recording system that is a computer, comprising: a data recording step including a first memory, a second memory, a third memory, and a data acquisition step for acquiring periodic data to be recorded in the first memory, wherein the write speeds of the first memory, second memory, and third memory are in the order of "first memory write speed>second memory write speed>third memory write speed"; a first memory recording step of recording the data acquired in the data acquisition step in a first memory; a first capacity determination step of determining whether the amount of data recorded by the first memory recording step has reached a predetermined capacity A; a second memory recording step of recording at least a part of the data recorded in the first memory in a second memory when the determination result in the first capacity determination step is that the predetermined capacity A has been reached; a second capacity determination step of determining whether the amount of data recorded by the second memory recording step has reached a predetermined capacity B; a third memory recording step of recording at least a part of the data recorded in the second memory in a third memory when the determination result in the second capacity determination step is that the predetermined capacity B has been reached; A method having the following.

7. A method executed by a CPU in a data recording system that is a computer, comprising:

7. The method according to claim 6, wherein the size of data recorded at one time in the second memory in the second memory recording step is the predetermined capacity A, and the size of data recorded at one time in the third memory in the third memory recording step is the predetermined capacity B.

8. A method executed by a CPU in a data recording system that is a computer, comprising:

8. The method according to claim 6, wherein the writing process by the first memory recording step, the writing process by the second memory recording step, and the writing process by the third memory recording step are controlled to be performed in accordance with a predetermined priority.

9. A method executed by a CPU in a data recording system that is a computer, comprising: The method according to claim 6 or claim 7, wherein the first memory is a volatile memory, the second memory is a flash memory, and the third memory is an SD card, and the specified capacity A is an integer multiple of a page, which is the physical memory management unit of the second memory.

10. A method executed by a CPU in a data recording system that is a computer, comprising: The first memory recording step includes: a data receiving substep of receiving a plurality of data having different cycles; a recording area dividing sub-step of dividing the recording area of ​​the first memory at the ratio of the period; a data writing sub-step of writing data of the same cycle into each divided recording area; 7. The method of claim 6, comprising:

11. a data recording step including a first memory, a second memory, a third memory, and a data acquisition step for acquiring periodic data to be recorded in the first memory, wherein the write speeds of the first memory, second memory, and third memory are in the order of "first memory write speed>second memory write speed>third memory write speed"; a first memory recording step of recording the data acquired in the data acquisition step in a first memory; a first capacity determination step of determining whether the amount of data recorded by the first memory recording step has reached a predetermined capacity A; a second memory recording step of recording at least a part of the data recorded in the first memory in a second memory when the determination result in the first capacity determination step is that the predetermined capacity A has been reached; a second capacity determination step of determining whether the amount of data recorded by the second memory recording step has reached a predetermined capacity B; a third memory recording step of recording at least a part of the data recorded in the second memory in a third memory when the determination result in the second capacity determination step is that the predetermined capacity B has been reached; An operating program for a data recording system that is written in a readable and executable manner by a data recording system that is a computer having the program.

12. An operating program for a data recording system written in a manner readable and executable by a data recording system that is a computer as described in claim 11, wherein the size of data recorded at one time in the second memory in the second memory recording step is the predetermined capacity A, and the size of data recorded at one time in the third memory in the third memory recording step is the predetermined capacity B.

13. An operating program for a data recording system that is written in a readable and executable manner for a data recording system that is a computer as described in claim 11 or 12, which controls the writing process by the first memory recording step, the writing process by the second memory recording step, and the writing process by the third memory recording step to be performed in accordance with predetermined priorities.

14. An operating program for a data recording system written in a readable and executable manner for a data recording system that is a computer according to claim 11 or 12, wherein the first memory is a volatile memory, the second memory is a flash memory, and the third memory is an SD card, and the specified capacity A is an integer multiple of the capacity of a page, which is the physical memory management unit of the second memory.

15. The first memory recording step includes: a data receiving substep of receiving a plurality of data having different cycles; a recording area dividing sub-step of dividing the recording area of ​​the first memory at the ratio of the period; a data writing sub-step of writing data of the same cycle into each divided recording area; 12. An operating program for a data recording system, the operating program being written in a readable and executable manner by the data recording system that is a computer according to claim 11.

Images