Deposition mask and method for manufacturing electronic device

Abstract

To provide a vapor deposition mask capable of forming a vapor-deposited film having an excellent pattern dimension, and a method for manufacturing an electronic device using the vapor deposition mask.SOLUTION: According to an aspect of the present disclosure, there is provided a deposition mask including a semiconductor substrate having a first surface and a second surface opposite to the first surface and having a plurality of openings penetrating between the first surface and the second surface, wherein a side wall surface of each of the openings is formed in an uneven shape, the opening widths are smaller than 30 μ m, the unevenness ratio (mean value of unevenness height differences / opening widths) is 0.0001 or more and 0.0420 or less, the vapor deposition mask has a configuration in which a membrane having the openings is supported by a support substrate, the support substrate includes a Si layer and a side SiO2 layer, and the membrane has SiN.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a deposition mask and a method for manufacturing an electronic device. [Background technology]

[0002] For example, a deposition mask is known that is used to paint three RGB colors when manufacturing organic EL displays. Patent Documents 1 and 2 describe that the sidewall surface of each opening of the deposition mask has an uneven shape, and also specify the surface roughness of the unevenness. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-184708 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-189990 Summary of the Invention [Problem to be solved by the invention]

[0004] The uneven shape of the sidewall surface of the opening causes deposition material to accumulate on the sidewall surface, resulting in a problem of deterioration in the pattern dimensions of the deposited film.

[0005] An object of the present invention is to provide a deposition mask capable of forming a deposition film having excellent pattern dimensions, and a method for manufacturing an electronic device using the deposition mask. [Means for solving the problem]

[0006] The deposition mask of the present embodiment has a first surface and a second surface opposite to the first surface, and is formed with a plurality of openings penetrating between the first surface and the second surface, characterized in that the sidewall surfaces of the openings are formed with an uneven shape, the opening width is 30 μm or less, and the unevenness ratio (average unevenness height difference / opening width) is 0.0001 or more and 0.0420 or less. [Effects of the Invention]

[0007] According to the present invention, by controlling the size of the irregularities formed on the sidewall surfaces of the openings of the deposition mask by the ratio to the opening width, a deposition film having excellent pattern dimensions can be stably formed. Furthermore, the frequency of cleaning the deposition mask can be reduced, facilitating quality control of the deposition mask. Furthermore, the occurrence of clogging of the openings can be reduced, thereby extending the life of the deposition mask. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a cross-sectional view showing an example of a deposition mask according to the present embodiment. [Figure 2] 2 is an enlarged cross-sectional view of a part of the deposition mask shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a partially enlarged cross-sectional view showing a part of an opening of the deposition mask of the present embodiment. [Figure 4] 1A to 1C are cross-sectional views showing a method for manufacturing an electronic device using the vapor deposition mask of the present embodiment. [Figure 5] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a vapor deposition mask according to an embodiment of the present invention. [Figure 6] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a vapor deposition mask according to an embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 11] FIG. 10 is an image diagram showing deposition of a deposition material on a side wall surface of an opening. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. Furthermore, even when the same parts are shown between the drawings, the dimensional relationships and ratios between them may be different. In particular, the embodiments shown below are merely examples of structures for embodying the technical idea of ​​the present invention, and do not specify the technical idea of ​​the present invention. In the following description, elements having the same function and configuration are designated by the same reference numerals, and redundant description will be omitted. Furthermore, the lower and upper limits of numerical ranges include error ranges.

[0010] <Background to the Invention> Virtual reality / augmented reality (VR / AR) technology and the VR / AR-related market are growing rapidly. As this growth continues, display panels suitable for the VR / AR field are becoming smaller, with higher pixel counts (PPI), faster response times, and wider color gamuts. Silicon-based organic light-emitting diode (OLED) microdisplay panels are becoming increasingly popular as a driving force behind these technological advances.

[0011] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and higher PPI. To effectively prepare for AR and VR as high-value-added industries, it is expected to realize ultra-high resolution displays, for example, over 1000 ppi. As a result, there is a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.

[0012] The deposition mask has a plurality of openings corresponding to the deposited film, and the accuracy of the openings in the deposition mask is important for improving the pattern dimensions of the deposited film.

[0013] The deposition mask is placed between the substrate and the deposition source, and the deposition material passes from the deposition source through the openings in the deposition mask and reaches the surface of the substrate. If the deposition material accumulates on the sidewalls of the openings, the opening width becomes narrower than the actual width, making it difficult to form a deposition film with excellent pattern dimensions.

[0014] In Patent Document 1, the deposition material on the sidewall surface becomes foreign matter, which causes pixel defects and leads to chipping, and the objective is to form an opening that stabilizes the deposition of the deposition material. For example, Patent Document 1 specifies the opening width to be 100 μm (0.1 mm) or more.

[0015] On the other hand, when the opening width is reduced to less than 100 μm (specifically, 30 μm or less), assuming that the size of the unevenness on the sidewall surface of the opening is constant, the smaller the opening width, the greater the effect of deposition material accumulation, resulting in a decrease in the pattern dimensions of the deposited film. For this reason, it is not possible to obtain excellent pattern dimensions simply by adjusting the size of the unevenness, and it is necessary to determine the range in which a deposited film with excellent pattern dimensions can be formed, taking into account the relationship with the opening width.

[0016] As a result of extensive research, the inventors have focused on the ratio of the height difference between the irregularities on the sidewall surface to the opening width, and have developed a deposition mask that can increase the pattern dimensions of the deposited film.

[0017] <Outline of the deposition mask 1 according to the present embodiment> Fig. 1 is a cross-sectional view of a deposition mask 1 according to the present embodiment. Fig. 2 is a cross-sectional view showing an enlarged portion of the deposition mask shown in Fig. 1. Fig. 3 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask according to the present embodiment. Fig. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask according to the present embodiment.

[0018] The deposition mask 1 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably made of an SOI (Silicon on Insulator) substrate 9.

[0019] The semiconductor layer 2 is preferably a silicon single crystal layer, and is also called an active layer, a membrane, etc. The thickness of the semiconductor layer 2 is not limited, but is about 1 μm to 300 μm.

[0020] 1, the deposition mask 1 has a plurality of opening regions 15 and a surrounding region 16 located around the opening regions 15. The surrounding region 16 has a structure in which a semiconductor layer 2, an insulating layer 3, and a support substrate 4 are stacked. On the other hand, only the semiconductor layer 2 is disposed in the opening regions 15, that is, the insulating layer 3 and the support substrate 4 are removed, and each opening region 15 has a plurality of minute openings 5 ​​formed therein.

[0021] FIG. 2 is an enlarged view of the vicinity of one of the opening regions 15 shown in FIG. 2, the semiconductor layer 2 has a first surface 2a and a second surface 2b that face each other in the thickness direction. An insulating layer 3 and a support substrate 4 are provided on the second surface 2b side. As shown in FIG. 4, the first surface 2a is the surface facing the deposition target substrate 10, and the second surface 2b is the back surface facing the deposition source 11.

[0022] As shown in FIG. 2, a plurality of openings 5 ​​are formed in the semiconductor layer 2, penetrating between the first surface 2a and the second surface 2b. As shown in FIG. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the sidewall surface 6 of the opening 5 is inclined. Also, in FIG. 2, the opening width W1 is defined by the width dimension in the planar direction along the first surface 2a. Thus, in FIG. 2, the opening width W1 is illustrated at the point where the width dimension is narrowest. Note that in FIG. 2, the reference symbols for the opening width W1 and the sidewall surface 6 are illustrated for only one opening 5, but they also apply to the other openings 5 ​​in the same way. Note that the shape of the sidewall surface 6 of the opening 5 will be described in detail later.

[0023] The planar pattern of the openings 5 ​​(the shape when viewed from directly above the semiconductor layer 2 toward the first surface 2a) is not limited to any particular shape, and examples include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. All the openings 5 ​​may have the same planar pattern, or some of them may have different patterns. The openings 5 ​​may be arranged regularly, irregularly, or a mixture of regular and irregular patterns. Although there are no limitations on the interval between adjacent openings 5, the interval is about 1 μm to 20 μm when viewed from the first surface 2a side.

[0024] The outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer, and the diameter (the length of one side in the case of a rectangle) is not limited, but is preferably about 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 is large, the openings 5 ​​can be formed uniformly.

[0025] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, a silicon oxide (SiO2) layer. The insulating layer 3 is also called a BOX layer (Buried Oxide Layer). The thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 μm.

[0026] 2 is removed from the opening region facing the opening 5 of the semiconductor layer 2, and remains only in the surrounding region of the opening region on the second surface 2b of the semiconductor layer 2. The insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and the presence of the insulating layer 3 enables stable processing.

[0027] 2 is a semiconductor substrate, for example, a silicon substrate. The thickness of the support substrate 4 is not limited, but is, for example, about 100 μm to 1000 μm.

[0028] As shown in FIG. 1, the support substrate 4 can function as the columnar portions 16a and the peripheral frame 16b that surround the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be kept in a taut state by the support substrate 4, eliminating the need for a tensioning process. The deposition mask 1 of this embodiment can also be closely attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force. As shown in FIG. 1, the columnar portions 16a are located inside the peripheral frame 16b, and all of them have the same length (height). However, for example, the height of the columnar portions 16a may be lower than that of the peripheral frame. However, by making the heights uniform, greater strength can be maintained.

[0029] 1 and 2, an alignment mark for positioning can be formed in the peripheral region on the first surface 2a side of the semiconductor layer 2. The alignment mark can be formed, for example, in a recessed shape on the first surface 2a, and can be formed to a depth that reaches the insulating layer 3.

[0030] <Detailed Description of Openings 5 ​​in Vapor Deposition Mask 1 in the Present Embodiment> 3 is a partially enlarged cross-sectional view showing one opening 5 formed in the deposition mask 1, and shows the middle part of the opening 5 in the height direction (thickness direction of the semiconductor layer 2). Note that although reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side in the figure, the cross-sectional shape is symmetrical, and the side wall surface 6 on the right side in the figure has the same configuration.

[0031] 3, the side wall surface 6 of the opening 5 is formed with an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding inward of the opening 5 and concave portions 8 located between the convex portions 7 are formed continuously and repeatedly along the height direction of the opening 5. In this embodiment, the height difference between the protrusions and recesses of the opening 5 is calculated as follows.

[0032] [Calculation method for unevenness height difference] First, an SEM (scanning electron microscope) image was obtained of the cross section of the opening 5. Although the SEM is not limited to this, for example, a Regulus 8220 manufactured by Hitachi High-Technologies was used.

[0033] At a midpoint between the first surface 2a and the second surface 2b of the opening 5, exactly in the center of the thickness, adjacent irregularities are counted as one pitch, and measurements were taken over five pitches using an SEM. While not limited to five pitches, if the number of pitches is too small, parameter noise increases, and if the number of pitches is too large, it may not be possible to ensure the required number of pitches depending on the thickness, and parameter calculation becomes time-consuming and complicated. Therefore, it is preferable to use a number of pitches ranging from several to 10 pitches. In this embodiment, measurements are basically taken over five pitches, but if this is difficult, the number of pitches can be changed as appropriate.

[0034] Furthermore, instead of the concept of pitch described above, it is also possible to measure the height at, for example, five points at the center of the thickness in an SEM image. In this case, the points with height can be regarded as convex portions, and the areas between them can be regarded as concave portions.

[0035] In FIG. 3, only two pitches are shown and explained. In FIG. 3, the two convex portions 7 are denoted by the reference numerals 7a and 7b to distinguish them from each other. When viewed from each convex portion 7a, 7b, a half pitch is formed with the concave portion 8 located on the first surface 2a side (upper side in the figure). The two concave portions 8 are also denoted by the reference numerals 8a and 8b to distinguish them from each other. The convex portion 7a and the concave portion 8a form a first half pitch P1, and the convex portion 7b and the concave portion 8b form a second half pitch P2. Note that the pitch refers to the distance between convex portions or the distance between concave portions, and half that distance is defined as the half pitch.

[0036] As shown in Figure 3, an approximate line T1 was drawn connecting the lowest positions (bottoms A) of each recess 8a, 8b within the measurement range. Bottom A is, for example, the farthest position as seen from the center line O in the width direction of the opening 5. Approximate line T1 can be determined by the least squares method. Note that if an irregular recess 8 is formed within the measurement range (for example, if bottom A is located significantly lower than top B), the approximate line T1 can be drawn excluding that recess 8.

[0037] Next, as shown in FIG. 3, the highest position (apex) B of the convex portion 7a was determined at the first half pitch P1. The apex B was the closest position when viewed from the center line O of the opening 5 in the width direction. Then, as shown in FIG. 3, a straight line S1 was drawn perpendicular to the approximated line T1 so as to intersect with the apex B. The length of the straight line S1 from the approximated line T1 to the apex B was determined. The length of this straight line S1 was defined as the uneven height difference D1 at the first half pitch P1.

[0038] The unevenness height difference for the second half pitch P2 and other half pitches can be calculated in the same way as for the first half pitch P1. That is, the length of a straight line perpendicular to the approximate line T1 to the apex B of each convex portion is calculated, and this straight line length is used as the unevenness height difference for each pitch. Incidentally, Figure 3 shows the unevenness height difference D2 for the second half pitch P2.

[0039] In this way, multiple irregularity height differences can be determined. When five pitches are measured, five irregularity height differences Dn (n = 1 to 5) are calculated. Then, the average value Ave of these irregularity height differences Dn is calculated.

[0040] Although minute irregularities may be formed on the surfaces of the recesses 8a and 8b (or on the bottoms of the protrusions 7a and 7b), these minute irregularities can be ignored. For example, minute irregularities on the order of several nanometers in wavelength or smaller can be cut off, and a waviness curve can be created to determine the difference in irregularity height.

[0041] [How to calculate opening width W1] As shown in Fig. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. For this reason, as shown in Fig. 2, the opening width W1 was determined as the dimension in the planar direction along the first surface 2a, where it is narrowest. The opening width W1 can be determined from an SEM image obtained using eCD-2 manufactured by KLA-Tencor.

[0042] [Calculation method for the concave-convex ratio R] The unevenness ratio R was calculated from the average value Ave of the unevenness height difference Dn measured above and the opening width W1. That is, the unevenness ratio R was calculated by (average value Ave of the unevenness height difference Dn / opening width W1). A small unevenness ratio R means that if the average value Ave of the unevenness height difference Dn is constant, the opening width W1 is large, or if the opening width W1 is constant, the average value Ave of the unevenness height difference Dn is small. On the other hand, a large unevenness ratio R means that if the average value Ave of the unevenness height difference Dn is constant, the opening width W1 is small, or if the opening width W1 is constant, the average value Ave of the unevenness height difference Dn is large. In this way, in this embodiment, the average value Ave of the unevenness height difference Dn and / or the opening width W1 can be adjusted to control the unevenness ratio R to fall within a predetermined range.

[0043] [Method of calculating the taper angle θ1 of the opening 5 and the inclination angle θ4 of the side wall surface 6] In this embodiment, the taper angle θ1 of the opening 5 is determined as follows. That is, as shown in Fig. 2, a straight line is drawn between the end of the opening width W1 in the surface direction along the first surface 2a and the end of the opening width W2 in the surface direction along the second surface 2b, and the inclination angle between this line and the first surface 2a can be set as the taper angle θ1 of the opening 5. The taper angle θ1 was determined by measuring the length of an SEM image taken using a Hitachi High-Tech Regulus 8220.

[0044] As shown in FIG. 3, the inclination angle θ4 of the side wall surface 6 can be determined from the inclination angle between the approximate straight line T1 shown in FIG. 3 and the first surface 2a.

[0045] The taper angle θ1 and the inclination angle θ4 are the same or approximate, but depending on, for example, the state of the uneven shape of the side wall surface 6 and the pitch, the inclination of the approximate line T1 may change, and the taper angle θ1 and the inclination angle θ4 may deviate from each other. Therefore, the inclination of the side wall surface 6 is determined by measuring the taper angle θ1 of the opening 5.

[0046] [Calculation method for unevenness angles θ2 and θ3] As shown in Fig. 3, the unevenness angle θ2 can be determined as the angle between a straight line L1 connecting the apex B of the convex portion 7a and the lowest bottom A (farthest from the center line O in the width direction of the opening 5) of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximate line T1. Also, as shown in Fig. 3, the unevenness angle θ3 can be determined as the angle between a straight line L2 connecting the apex B of the convex portion 7a and the lowest bottom A (farthest from the center line O in the width direction of the opening 5) of the concave portion 8b located on the deposition source 11 side (lower side in the figure, see Fig. 4) as viewed from the convex portion 7a, and the approximate line T1.

[0047] Small concave-convex angles θ2 and θ3 mean that the height of the convex ridge portion 7 is low (the depth of the concave portion 8 is shallow) and the waviness of the side wall surface 6 is small.

[0048] <Characteristic Configuration of Aperture Parameters in the Present Embodiment> The deposition mask 1 in this embodiment is (1) The opening width W1 is 30 μm or less. (2) The unevenness ratio R (average value Ave of unevenness height difference Dn / opening width W1) is 0.0001 or more and 0.0420 or less.

[0049] In this embodiment, the opening width W1 is set to a range of 30 μm or less. This satisfies the needs of a deposition mask 1 having a semiconductor layer 2, and in particular, it is necessary to further reduce the opening width W1 for a deposition mask for separate RGB coloring used in the manufacturing process of an OLED microdisplay. In this embodiment, the opening width W1 is preferably 20 μm or less, and more preferably 10 μm or less. Moreover, the opening width W1 is preferably 1 μm or more, more preferably 2 μm or more, and even more preferably 3 μm or more.

[0050] Alternatively, the opening width W1 is preferably 1 μm or more and 30 μm or less, more preferably 2 μm or more and 20 μm or less, and even more preferably 3 μm or more and 10 μm or less.

[0051] The opening width W1 is preferably set as a width dimension in the planar direction along the first surface 2a facing the deposition target substrate 10.

[0052] In this embodiment, the concavo-convex ratio R is set to 0.0001 or more and 0.0420 or less. By adjusting the concavo-convex ratio R within this range, it is possible to set the pattern width of the vapor deposition film formed using the vapor deposition mask 1 to 80% or more of the opening width W1 of the vapor deposition mask 1.

[0053] FIG. 4 is a cross-sectional view of the deposition mask 1 of this embodiment arranged between a substrate 10 to be deposited and a deposition source 11, illustrating one step of a method for manufacturing an electronic device.

[0054] 4, deposition material (deposition particles) 12 from a deposition source 11 passes through the openings 5 ​​in the deposition mask 1 and reaches the surface 10a of the deposition target substrate 10, forming a deposition film 13. When the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, if the unevenness ratio R is such that the pattern width ratio ((pattern width W3 / opening width W1)×100(%)) is 80% or more, it is considered to be the present example, and if the unevenness ratio R is less than 80%, it is considered to be a comparative example.

[0055] The lower limit of the unevenness ratio R, 0.0001, is almost the manufacturing limit, and therefore the unevenness ratio R is set to 0.0001 or more. It has been found that when the unevenness ratio R exceeds the upper limit of 0.0420, the unevenness ratio R relative to the opening width W1 increases exponentially. In particular, when the unevenness ratio R exceeds 0.0425, the exponential increase becomes significant, and the impact on deposition becomes significantly greater. For example, even if the average value Ave of the unevenness height difference Dn is the same, when the unevenness ratio R exceeds 0.0420, even a slight shift in the opening width W1 in the direction of decreasing the unevenness ratio R significantly increases, thereby deteriorating the pattern width ratio of the deposited film 13. Therefore, the unevenness ratio R is set to 0.0420 or less to stably obtain a pattern width ratio of 80% or more. The reason why the required pattern width ratio is set to 80% or more is that if it is less than 80%, the deviation from the desired pattern width W3 of the vapor-deposited film 13 will be too large, leading to a decrease in yield, and also because it will lead to a decrease in the area that should emit light at the designed position, such as coordinate position accuracy, leading to a decrease in the brightness of the light-emitting element itself, or because it is a numerical value required to guarantee product quality. To improve production efficiency, the pattern width ratio is set to 85% or more, preferably 90% or more, and more preferably 95% or more.

[0056] In this embodiment, the concavo-convex ratio R is preferably set to 0.0380 or less, more preferably to 0.0350 or less, and even more preferably to 0.0300 or less.

[0057] In this embodiment, the lower limit of the unevenness ratio R can be set to about 0.0003 or 0.0005. Alternatively, the unevenness ratio R can be set to 0.0015 or more, or 0.0020 or more.

[0058] Furthermore, the average value Ave of the unevenness height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, even more preferably 0.175 μm or less, and most preferably 0.170 μm or less. Furthermore, the average value Ave of the unevenness height difference Dn is preferably 0.003 μm or more, more preferably 0.005 μm or more, and even more preferably 0.008 μm or more. By adjusting the average value Ave of the unevenness height difference Dn within the above range, it is easy to appropriately control the unevenness ratio R within a range of 0.0001 to 0.0420, and further within a preferred unevenness ratio R range. Furthermore, deposition of the deposition material 12 on the side wall surface 6 of the opening 5 can be reduced, which has the effect of reducing the number of times the deposition mask 1 needs to be cleaned.

[0059] For example, when the opening width is 5 μm or less, the average value Ave of the unevenness height difference Dn is preferably 0.003 μm or more and 0.165 μm or less, more preferably 0.160 μm or less, even more preferably 0.155 μm or less, even more preferably 0.150 μm or less, even more preferably 0.130 μm or less, and most preferably 0.100 μm or less.

[0060] Furthermore, for example, when the opening width is greater than 5 μm and less than or equal to 20 μm, the average value Ave of the unevenness height difference Dn is preferably greater than or equal to 0.003 μm and less than or equal to 0.200 μm, more preferably greater than or equal to 0.003 μm and less than or equal to 0.180 μm, and even more preferably greater than or equal to 0.003 μm and less than or equal to 0.175 μm.

[0061] Furthermore, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less. The smaller the opening width W1, the smaller the maximum value of the unevenness height difference Dn. For example, when the opening width W1 is 5 μm or less, the maximum value of the unevenness height difference Dn is preferably 0.300 μm or less, more preferably 0.250 μm or less, even more preferably 0.200 μm or less, and most preferably 0.100 μm or less. Note that there is no lower limit to the maximum value of the unevenness height difference Dn, but the maximum value of the unevenness height difference Dn is approximately 0.005 μm or more.

[0062] The concave-convex angles θ2 and θ3 described with reference to FIG. 3 are within a range of approximately 0.5° to 50°, preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By reducing the concave-convex angles θ2 and θ3, the protrusion height of the convex ridge portions 7 can be reduced, or the interval between adjacent convex ridge portions 7 can be increased (the range of the concave portions 8 can be increased), thereby suppressing deposition of the deposition material 12 on the side surfaces of the convex ridge portions 7. The most preferable range of the concave-convex angles θ2 and θ3 is approximately 0.5° to 2°. The concave-convex angle θ3 shown in FIG. 3 is preferably smaller than the concave-convex angle θ2. This suppresses deposition of the deposition material 12 on the side wall surfaces 6.

[0063] In this embodiment, the opening width of the opening 5 gradually narrows from the second surface 2b toward the first surface 2a. That is, as shown in FIG. 4 , the opening width W1 of the deposition mask 1 on the side facing the deposition substrate 10 is narrowed, and the side wall surface 6 of the opening 5 is formed as an inclined surface. This facilitates stable formation of a deposition film 13 having a desired pattern width W3. Furthermore, when the deposition material 12 deposited on the side wall surface 6 peels off from the side wall surface 6, it is less likely to fly toward the deposition substrate 10. From the viewpoint of manufacturing, inclining the side wall surface 6 of the opening 5 facilitates formation of the side wall surface 6. While not limited to this, the taper angle θ1 of the opening 5 is preferably 60° or greater, more preferably 70° or greater. Furthermore, the taper angle θ1 is preferably less than 90°, more preferably 85° or less, and even more preferably 80° or less. Therefore, the taper angle θ1 is most preferably 70° or greater and 80° or less. If the taper angle θ1 is less than 60°, the amount of deposition material 12 deposited on the sidewall surface 6 increases, and the pattern width ratio of the deposited film tends to be less than 80%. Furthermore, the taper angle θ1 can be set to approximately 90°, i.e., the sidewall surface 6 can be formed almost vertically. However, in this case, the influence of the unevenness height difference Dn on the sidewall surface 6 during deposition is thought to be greater. In particular, the narrower the opening width W1, the smaller the average value Ave and maximum value of the unevenness height difference Dn must be. The taper angle θ1 is also related to the thickness of the semiconductor layer 2. In other words, as the thickness of the semiconductor layer 2 increases, it becomes more difficult to form the sidewall surface 6 as a vertical surface. Therefore, in this embodiment, the taper angle θ1 is controlled to be less than 90°, preferably 85° or less, and more preferably 80° or less.

[0064] <Method of manufacturing the deposition mask 1 according to the present embodiment> 5A and 5B are process diagrams showing a first manufacturing method of the deposition mask 1 of the present embodiment. Here, the deposition mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later shows only the vicinity of one opening region 15, as in FIG. 2, but in reality, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously. In FIG. 5A, an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that description.

[0065] In the case of the SOI substrate 9, the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.

[0066] In FIG. 5(b), a mask layer 14 is patterned on the surface of the semiconductor layer 2. The mask layer 14 is preferably a resist, and can be patterned by exposure and development. A plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are an opening pattern for forming openings 5 ​​in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to be small, 30 μm or less.

[0067] Next, in FIG. 5(c), the semiconductor layer 2 exposed through the through-hole 14a of the mask layer 14 is dry-etched. In this embodiment, the semiconductor layer 2 is deep-etched. It is preferable to use a so-called Bosch process, for example, by repeatedly etching Si with SF6 and forming a polymer film with C4F8 to deeply etch the silicon, alternately protecting the sidewall and etching the bottom. The Bosch process results in an uneven sidewall surface 6 of the opening 5 formed in the semiconductor layer 2.

[0068] At this time, the composition and flow rate of the etching gas, the internal pressure of the etching chamber, the power of the high frequency power supply, etc. are appropriately adjusted so as to form an inverse tapered surface as shown in Figure 5(c). Furthermore, by adjusting these factors, the inclination angle of the inverse tapered surface (the taper angle θ1 of the opening 5) and the uneven height difference Dn can be controlled.

[0069] For example, the Bosch process was performed using a dry etching system, alternating between SF6 gas and C4F8 gas. Using the same gas as in the mode used for isotropic dry etching using fluorine radicals with SF6 gas, anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate being etched. The processing conditions were adjusted as follows: SF6 gas at 0-500 sccm, C4F8 gas at 0-300 sccm, platen LF at 0-1500 W, coil RF at 300-1500 W, and chamber pressure at 1-10 Pa.

[0070] By the Bosch process described above, a plurality of openings 5 ​​can be formed by deep digging in the semiconductor layer 2, and at this time, the taper angle θ1 of the openings 5 ​​and the height difference between the protrusions and recesses can be adjusted appropriately.

[0071] In this embodiment, in addition to adjusting the conditions in the etching process described above, reducing the unevenness height difference Dn can also be achieved by, for example, performing deep etching of silicon and then smoothing the unevenness height difference Dn by laser hydrogen annealing. 5(d), the mask layer 14 is removed, thereby completing the SOI substrate 9 in which a plurality of openings 5 ​​are formed in the semiconductor layer 2.

[0072] 5(e), a protective layer 20 is formed on the surface of the semiconductor layer 2. This makes it possible to appropriately protect the entire surface of the semiconductor layer 2. The protective layer 20 is, for example, a resist film, although it is not limited thereto.

[0073] Next, in the step shown in FIG. 5(f), a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9. Although not limited thereto, the mask layer 21 is a resist pattern. As shown in FIG. 5(f), the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, but is provided only in the peripheral region 16 (see also FIG. 1). The mask layer 21 may be formed together with the mask layer 14 in the step shown in FIG. 5(b).

[0074] 5(g), the support substrate 4 that is not covered with the mask layer 21 is removed by dry etching, and in the step shown in Fig. 4(h), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains the shape having the multiple openings 5. 5(i), the protective layer 20 and the mask layer 21 are removed, thereby completing the deposition mask 1.

[0075] 6A to 6C are process diagrams showing a second method for manufacturing the deposition mask 1 according to the present embodiment. In FIG. 6A, an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that explanation.

[0076] Although there is no limitation on the diameter of the SOI substrate 9, in this embodiment, it can accommodate a diameter up to about 500 mm.

[0077] 6(b), a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9. The mask layer 21 is, but is not limited to, a resist pattern. As in FIG. 5(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0078] Next, in the process shown in Figure 6(c), the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching, and in the process shown in Figure 6(d), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching.

[0079] 6(e), a mask layer 22 is formed on the back surface of the semiconductor layer 2. Although not limited to this, the mask layer 22 can be formed using a resist pattern. As shown in FIG. 6(e), a plurality of openings 22a are patterned in the mask layer 22 by exposure and development.

[0080] 6(f), the semiconductor layer 2 exposed from the opening 22a is etched. This etching is dry etching, and preferably, an etching gas containing a fluorine compound and oxygen, and optionally a rare gas, is used, although this is not limited thereto.

[0081] The fluorine compound may be, for example, one or more selected from CF4, SF6, NF3, BF3, PF5, and F2, and the rare gas may be one or more selected from helium and argon.

[0082] For example, etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus. The processing conditions were adjusted as follows: CF4 gas 10-100 sccm, O2 gas 0-100 sccm, Ar gas 0-200 sccm, IPC power 200-1000 W, RIE power 0-1000 W, and chamber pressure 1-10 Pa.

[0083] In the step of FIG. 6(f), openings 5 ​​whose widths gradually decrease with increasing distance from the mask layer 22 (toward the first surface 2a of the semiconductor layer 2) can be formed in the semiconductor layer 2. This allows the sidewall surfaces 6 of the openings 5 ​​to be formed as inclined surfaces. Then, in the step of FIG. 6(g), the mask layer 22 is removed. This completes the deposition mask 1.

[0084] In both the manufacturing method shown in Figure 5 and the manufacturing method shown in Figure 6, multiple openings 5 ​​can be formed in the semiconductor layer 2, and the side wall surfaces 6 of the openings 5 ​​can be formed as inclined surfaces so that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the deposition source 11 side toward the front surface (first surface 2a) facing the deposition substrate 10 side.

[0085] In this embodiment, although not limited thereto, the opening width W1 and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressure, power of the plasma generation source, and the like.

[0086] In the Bosch process described with reference to FIG. 5 , the semiconductor layer 2 is deeply etched to form the opening 5, resulting in a larger unevenness height difference Dn on the sidewall surface 6 than in the dry etching process described with reference to FIG. 6 . While not limiting, in the manufacturing process shown in FIG. 5 , the unevenness height difference Dn of the opening 5 formed in the semiconductor layer 2 is approximately 0.040 μm to 0.300 μm. On the other hand, in the manufacturing process shown in FIG. 6 , the unevenness height difference Dn of the opening 5 formed in the semiconductor layer 2 is approximately 0.003 μm to 0.020 μm. Therefore, it is preferable to apply the manufacturing method shown in FIG. 6 as the opening width W1 becomes narrower (for example, when the opening width W1 is 5 μm or less), and to apply the manufacturing method shown in FIG. 5 when the opening width W1 is 5 μm or more. However, even when the manufacturing method shown in FIG. 5 is applied, it is possible to reduce the unevenness height difference by, for example, laser hydrogen annealing, as described above.

[0087] <Method of Manufacturing Electronic Device According to the Present Embodiment> 4, the deposition mask 1 is placed between the deposition substrate 10 and the deposition source 11. At this time, the first surface 2a of the semiconductor layer 2 of the deposition mask 1 faces the deposition substrate 10, and the second surface 2b of the semiconductor layer 2 faces the deposition source 11. A plurality of openings 5 ​​are formed in the semiconductor layer 2, and the opening width is narrower on the first surface side than on the second surface side.

[0088] The deposition mask 1 is placed on a holder (not shown) of a deposition device, and an electrostatic chuck can be used to fix the deposition mask 1 and the deposition substrate 10. The deposition mask 1 and the deposition substrate 10 are rotated around the axis of the holder.

[0089] The deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 ​​of the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, whereby a deposition film 13 is formed.

[0090] In this embodiment, examples of the electronic device include an OLED microdisplay panel, a liquid crystal panel, and a solar cell, and the present invention is particularly suitable for a method of manufacturing an OLED microdisplay panel as an organic electronic device.

[0091] By using the deposition mask 1 of this embodiment, the pattern width W3 of the deposited film 13 can be ensured to be 80% or more of the opening width W1, preferably 85% or more, and more preferably 90% or more. In this way, the deposited film 13 with excellent pattern dimensions can be formed.

[0092] <Effects of using the deposition mask 1 of this embodiment> In this embodiment, by defining the unevenness ratio R (=average value Ave of unevenness height difference Dn / opening width W1) in the opening 5 of the deposition mask 1, it is possible to obtain a high pattern dimension of the deposition film 13.

[0093] In this embodiment, the opening width W1 is set to a range of 30 μm or less, and the concavo-convex ratio R is set to 0.0001 or more and 0.0420 or less, thereby making it possible to stably form a deposited film 13 having excellent pattern dimensions.

[0094] Conventionally, the unevenness of the sidewall surface of an opening has been uniformly specified based on the roughness that makes it difficult for the deposition material to deposit. However, the allowable unevenness varies depending on the opening width. Therefore, conventional control methods cannot stably form a deposited film 13 with high pattern dimensions, regardless of the opening width.

[0095] In contrast to this, in the present embodiment, a new factor called the unevenness ratio R is introduced, and by adjusting the average value Ave of the unevenness height difference Dn so that the unevenness ratio R is 0.0001 or more and 0.0420 or less, regardless of the size of the opening width W1, as long as the opening width W1 is in the range of 30 μm or less, it is possible to stably form a deposited film 13 having a pattern width W3 with a pattern width ratio of 80% or more.

[0096] Furthermore, by adjusting the average value Ave of the height difference Dn between the protrusions and recesses, it is possible to suppress the deposition of the deposition material 12, reduce the frequency of cleaning the deposition mask, and facilitate quality control of the deposition mask. Furthermore, it is possible to reduce clogging of the openings and extend the life of the deposition mask. Although the embodiments and modifications have been described, other embodiments may be combinations of the above embodiments and modifications in whole or in part.

[0097] Furthermore, the present invention is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the scope of the claims covers all embodiments that may fall within the scope of the technical idea.

[0098] An embodiment of a layer structure different from that of the deposition mask 1 shown in FIG. 1 will be described. 7, the membrane 31 may be formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 may be formed in the membrane 31 in the central region where the silicon substrate 30 has been removed, or alternatively, the membrane may have a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate). The membrane is formed by CVD, and it is preferable to use SiN from the viewpoint of ease of stress control.

[0099] 8 to 10, an SOI substrate 9 is used as in Fig. 1, but in Fig. 8, a SiN layer 33 is formed on the back side (support substrate 4 side, side facing deposition source 11) of the SOI substrate 9, in Fig. 9, a SiN layer 33 is formed on the front side (semiconductor layer 2 side, side facing deposition target substrate 10) of the SOI substrate 9, and in Fig. 10, a SiN layer 33 is formed on both the back side and front side of the SOI substrate 9. In the configuration in which the SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9, an opening 5 is formed continuous with the semiconductor layer 2, as shown in Figs. 9 and 10.

[0100] By providing the SiN layer 33, it is easy to control the stress of the deposition mask, and distortion and the like can be suppressed. Also, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9. Although not limited, the film thickness of the SiN layer 33 formed on the front surface side of the SOI substrate 9 is about 0.05 μm to 0.5 μm, and the film thickness of the SiN layer 33 formed on the back surface side of the SOI substrate 9 is about 0.05 μm to 3 μm. Since the semiconductor layer 2 is thinner than the support substrate 4 and a large number of openings 5 are also formed in the semiconductor layer 2, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9 in order to control stress well in a balanced manner between the front surface side and the back surface side.

Example

[0101] Hereinafter, the effects of the present invention will be described with reference to examples and comparative examples of the present invention. Note that the present invention is not limited by the following examples.

[0102] <SOI substrate> For the SOI substrate, a support substrate (625 μm) / insulating layer (0.5 μm) / semiconductor layer (15 μm or 5 μm) was used. The parentheses indicate the thickness. The support substrate was a Si substrate, the semiconductor layer was a Si layer, and the insulating layer was a SiO2 layer. The outer diameter of the SOI substrate was 200 mm. In the experiment, two types of SOI substrates with semiconductor layer thicknesses of 15 μm and 5 μm were prepared.

[0103] <Original master used> In the process (b) shown in FIG. 5 and the process (e) shown in FIG. 6, an opening pattern is formed in the mask layer (resist layer) by i-line exposure, and the opening width of the original master used when forming this opening pattern was adjusted within the range of 2.0 μm to 30 μm.

[0104] <Method for manufacturing deposition mask> A deposition mask 1 was fabricated using the manufacturing method shown in Figures 5 and 6. In the experiment, the opening width W1 was varied using the master described above. The opening width W1 and taper angle θ1 formed in the semiconductor layer 2 were adjusted by adjusting the gas flow rates, chamber pressure, and power of the plasma generation source. For example, in the dry etching shown in Figure 5(c), anisotropic dry etching using fluorine ions was performed using SF6 gas, the same gas as used in isotropic dry etching using fluorine radicals, by applying a bias to the substrate to be etched. The processing conditions were adjusted as follows: SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, platen LF at 0 to 1500 W, coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa.

[0105] In addition, for the dry etching shown in FIG. 6(f), various conditions were adjusted to CF gas at 10 to 100 sccm, O gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa.

[0106] <Dimensions of the opening 5 formed in the deposition mask 1> In the experiment, the opening width W1, the average value Ave of the unevenness height difference Dn, the maximum value of the unevenness height difference Dn, and the taper angle θ1 were determined. As shown in Figure 1, the opening width W1 was defined as the width dimension in the surface direction along the first surface 2a of the semiconductor layer 2. The opening width W1 can be determined from SEM images taken using an eCD-2 manufactured by KLA-Tencor.

[0107] The unevenness height difference Dn and taper angle θ1 were determined using the method described in Figure 2 from SEM images taken using a Hitachi High-Tech Regulus 8220. As described in Figure 2, they were determined by observing five pitches of unevenness formed on the side wall surface 6 at the center of the thickness at the midpoint of the opening height. For detailed methods for determining the unevenness height difference Dn and taper angle θ1, please refer to the descriptions of Figures 1 and 2. Note that only the odd-numbered experimental examples in Tables 1 and 2 were used to determine the unevenness height difference Dn. For the even-numbered experimental examples, five high-height points were determined at the center of the thickness, and the areas between them were considered to be recesses, and the unevenness height difference Dn and other values ​​were determined. The odd-numbered experimental examples were formed using the manufacturing method shown in Figure 5, which resulted in relatively large unevenness, making it easy to measure the pitch. However, the even-numbered experimental examples were formed using the manufacturing method shown in Figure 6, which resulted in small unevenness, making it difficult to determine the pitch. For this reason, for the even-numbered experimental examples, five locations that could be recognized as height were measured, and various parameters were measured using the measurement method in Figure 3.

[0108] Then, the unevenness ratio R (=average value Ave of unevenness height differences Dn / opening width W1) was calculated from the average value Ave of unevenness height differences Dn and the opening width W1.

[0109] <About determining deposition pattern dimensions> Using the multiple deposition masks formed above, a green light-emitting material, Alq3 (tris(8-hydroxyquinoline)aluminum), was deposited on the glass surface through the deposition masks by vacuum resistance heating deposition to form a patterned deposition film, which was then evaluated.

[0110] The pattern width W3 of the vapor-deposited film was measured using a laser microscope (model number VK-X210, manufactured by Keyence Corporation) to determine the pattern width ratio of the vapor-deposited film to the opening width W1 of the vapor-deposition mask ((W3 / W1) × 100(%)). Experimental examples with a pattern width ratio of less than 70% were marked with ×, experimental examples with a pattern width ratio of 70% to 80% with △, experimental examples with a pattern width ratio of 80% to 90% with ○, and experimental examples with a pattern width ratio of more than 90% with ◎.

[0111] The experimental results are shown in the "Deposition pattern dimension judgment" columns of Tables 1 and 2 below. Table 1 shows the experimental results when the semiconductor layer thickness was 15 μm, and Table 2 shows the experimental results when the semiconductor layer thickness was 5 μm.

[0112] The "taper angles" shown in Tables 1 and 2 are stated in increments of 10°, but these are representative values, and it was confirmed that all experimental examples fell within a range of ±3° from each representative value.

[0113] [Table 1]

[0114] [Table 2]

[0115] As shown in Tables 1 and 2, there were experimental examples No. 1 to No. 46, and the opening width W1 was set in the range of 3 μm to 20 μm. Experimental examples No. 1, 3, 5, 31, and 33 had deposition results of ×, and experimental examples No. 7 and 35 had deposition results of △, all of which are comparative examples. The remaining experimental examples had deposition results of ○ or ◎, and all correspond to examples.

[0116] This experiment revealed that by adjusting the unevenness ratio R within a range of 0.0001 to 0.0420 regardless of the opening width W1, deposition of the deposition material 12 on the sidewall surface 6 of the opening 5 can be suppressed, and a deposition film can be stably formed in which the pattern width W3 relative to the opening width W1 is 80% or more, preferably more than 90%. In this example, the opening width W1 was set to 30 μm or less, preferably 20 μm or less, to satisfy the needs of the deposition mask 1 including the semiconductor layer 2 and to be preferably used as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays. Furthermore, based on the experimental example, the opening width W1 was set to an even more preferable range of 3 μm or more and 20 μm or less.

[0117] In order to stably obtain a pattern width ratio of more than 90%, the unevenness ratio R is preferably set to 0.0400 or less, and more preferably set to 0.0380 or less.

[0118] The average value Ave of the unevenness height difference Dn is preferably 0.200 μm or less, more preferably 0.18 μm or less, and even more preferably 0.170 μm or less. The lower limit of the average value Ave of the unevenness height difference Dn is 0.001 μm or more, or 0.003 μm or more.

[0119] Furthermore, the maximum irregularity height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less.

[0120] Furthermore, experimental results showed that the taper angle is preferably 60° or more, and more preferably 70° or more. The lower limit of the taper angle can be less than 90°, or 85° or less, or 80° or less. Experimental examples have shown that the taper angle can be set in the range of 60° to 80°. An error of approximately ±3° is allowed for the taper angle.

[0121] 2 were approximately 11° to 41° in the odd-numbered experimental examples, and approximately 1.0° to 1.5° in the even-numbered experimental examples.

[0122] The smaller the concave-convex angles θ2 and θ3, the smaller the protrusion height of the convex portion 7 (see FIG. 3) can be, which is preferable because deposition of the deposition material 12 can be suppressed. Experimental examples have shown that the concave-convex angles θ2 and θ3 can be set within a range of approximately 0.5° to 50°, and when the opening width W1 is 5 μm or less, it is desirable to make the concave-convex angles θ2 and θ3 as small as possible, setting them to 10° or less, with the most preferable range being approximately 0.5° to 2°. Furthermore, it has been found that the concave-convex angle θ3 is smaller than the concave-convex angle θ2, which results in a form that can suppress deposition of the deposition material.

[0123] FIG. 11(a) is a conceptual diagram of deposition of the deposition material 19 when the semiconductor layer 2 has a thickness of approximately 3 to 5 μm, and FIG. 11(b) is a conceptual diagram of deposition of the deposition material 19 when the semiconductor layer 2 has a thickness of approximately 15 to 20 μm. FIGS. 11(a) and 11(b) show deposition of the deposition material 19 below the sidewall of the opening 5 from the top to the bottom. As shown in FIGS. 11(a) and 11(b), even if the thickness of the semiconductor layer 2 varies, the area where the deposition material 19 is deposited on the sidewall surface 6 of the opening 5 is approximately the same, and the deposition results are considered to be almost the same. Therefore, it is considered that the deposition results are not significantly different when the thickness of the semiconductor layer 2 is within the range of 2 to 20 μm. Therefore, although the above experimental examples were performed with semiconductor layer thicknesses of 15 μm and 5 μm, it is estimated that even for other thicknesses, a pattern width ratio of 80% or more can be achieved by adjusting the unevenness ratio R within the range of 0.0001 to 0.0420.

[0124] Note that if the thickness of the semiconductor layer is about 3 to 5 μm before the evaporation material is deposited on the sidewall surface of the opening, a pattern width ratio of more than 90% can be reliably obtained. [Explanation of symbols]

[0125] 1: Deposition mask 2: Semiconductor layer 2a: 1st page 2b: 2nd side 3: Insulating layer 4: Support substrate 5, 32: Aperture 6: Side wall 7, 7a, 7b: Convex part 8, 8a, 8b: recess 9: SOI substrate 10: Deposition substrate 11: Vapor deposition source 12, 19: Vapor deposition material 13: Vapor deposition film 14, 21, 22: Mask layers 20 :Protective layer 30: Silicon substrate 31:Membrane A: Bottom B:Top D1, D2: Height difference between concave and convex O: Center line P1: First half pitch P2: Second half pitch T1: Tangent W1, W2: Opening width W3: Pattern width θ1: Taper angle θ2, θ3: Uneven angle θ4: Inclination angle

Claims

1. a deposition mask having a first surface and a second surface opposite to the first surface, and having a plurality of openings formed therein and penetrating between the first surface and the second surface, The side wall surface of the opening is formed with an uneven shape, The opening width is 30 μm or less, The unevenness ratio (average unevenness height difference / opening width) is 0.0001 or more and 0.0420 or less. A deposition mask characterized by:

2. The concavo-convex ratio is 0.0380 or less.

2. The deposition mask according to claim 1.

3. When the deposition substrate side is the first surface and the deposition source side is the second surface, The opening width is defined by the opening width on the first surface side.

2. The deposition mask according to claim 1.

4. The opening width narrows from the second surface to the first surface.

4. The deposition mask according to claim 3.

5. The average height difference of the projections and recesses is 0.200 μm or less.

2. The deposition mask according to claim 1.

6. The opening width is 1 μm or more and 30 μm or less.

2. The deposition mask according to claim 1.

7. The maximum height difference between the projections and recesses is 0.500 μm or less.

2. The deposition mask according to claim 1.

8. the deposition mask has a structure in which a membrane having the opening is supported on a support substrate, a single-layer structure of a semiconductor substrate, or an SOI substrate; 2. The deposition mask according to claim 1.

9. 9. The deposition mask of claim 8, wherein the membrane comprises SiN.

10. The membrane has a plurality of opening regions each having a plurality of the openings, and a surrounding region located around each opening region; the support substrate includes a peripheral frame that supports the membrane in the peripheral region, and a columnar portion located inside the peripheral frame; The outer peripheral frame and the columnar portion are formed to have the same height.

10. The deposition mask according to claim 8 or claim 9.

11. the deposition mask according to claim 1 is disposed between a substrate to be deposited and a deposition source, so that the first surface faces the substrate to be deposited and the second surface faces the deposition source; A deposition material is deposited on the surface of the deposition substrate through the opening.

1. A method for manufacturing an electronic device comprising the steps of:

Images