Square root circuit

Abstract

To provide a square root circuit capable of generating a highly accurate output value by suppressing and reducing the influence of a base current error.SOLUTION: In the square root circuit, a translinear circuit is configured by the first transistor 1 to the fourth transistor 4 using NPN bipolar transistors, and the fifth transistor 5 to the seventh transistor 7 using NMOS transistors are provided so that a base current error of the first transistor 1 to the fourth transistor 4 does not directly appear in the output current IOUT, and even if there is a base current error, the output current IOUT accurately proportional to the square root of the input current IIN is obtained.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a square root circuit, and more particularly to one which aims to improve the accuracy and reliability of the output. [Background technology]

[0002] BACKGROUND ART Circuits that generate and output a square root signal for an input signal based on the so-called translinear principle have been well known (see, for example, Non-Patent Documents 1 and 2). FIG. 2 shows a conventional example of such a square root circuit, and the conventional circuit will be generally described below with reference to this figure. This conventional circuit is configured such that a so-called translinear loop is formed by four NPN bipolar transistors (hereinafter referred to as "transistors") Q1p to Q4p.

[0003] To outline the circuit operation, first, it is assumed that the base current amplification factor of each of the four transistors Q1p to Q4p is sufficiently large and the base current is zero. Under these conditions, the collector current IC1p of transistor Q1p becomes equal to the emitter current IE1p of transistor Q1p, and flows unchanged to the first current terminal T1X. In Figure 2, the input current flowing to the first current terminal T1X is denoted as "IINp" for convenience, but specifically, as mentioned above, IINp = IC1p = IE1p.

[0004] Furthermore, the current IBIASp flowing through the second current terminal T2X is equal to the collector current IC2p of the transistor Q2p, i.e., IBIASp=IC2p. Furthermore, the current IOUTp flowing through the output terminal T3X is equal to the collector current IC3p of the transistor Q3p, as well as to the emitter current IE3p of the transistor Q3p and the collector current IC4p of the transistor Q4p.

[0005] As is well known, the following relational expression holds true for an NPN bipolar transistor:

[0006] IC=χ×IS×exp(VBE / VT)...Equation 1a

[0007] IC=βIB...Formula 1b

[0008] IC+IB=IE···Equation 1c

[0009] where IC is the collector current, χ is the normalized emitter area ratio, IS is the saturation current, VBE is the base-emitter voltage, β is the current gain, IB is the base current, and IE is the emitter current. VT is a thermal voltage, which can be calculated as VT=k×T / q using Boltzmann's constant k, absolute temperature T, and elementary charge q.

[0010] On the other hand, in Figure 2, if the base-emitter voltage of transistor Q1p is VBE1p, the base-emitter voltage of transistor Q2p is VBE2p, the base-emitter voltage of transistor Q3p is VBE3p, and the base-emitter voltage of transistor Q4p is VBE4p, then according to Kirchhoff's voltage law, the following relational expression 2 holds:

[0011] VBE1p+VBE2p-VBE3p-VBE4p=0...Equation 2

[0012] By applying the relational expression VBE=VT·ln(IC / IS / χ), which is obtained by transforming the previous equation 1a, to this equation 2, the relational expression 3 shown below is obtained.

[0013] IC3p=(IC1p) 1 / 2 (IC2p) 1 / 2 ...Formula 3

[0014] Equation 3 confirms that the collector current IC3p, which is the current IOUTp flowing through the output terminal T3X, is proportional to the square root of the input current IC1p.

[0015] As described above, conventional square root circuits are based on the premise that the base current amplification factor is sufficiently large, and when using an NPN bipolar transistor with a base current amplification factor of approximately 100 to 200, the above prerequisites are fully met. [Prior art documents] [Non-patent literature]

[0016] [Non-Patent Document 1] Kunihiro Asada and Yuzuru Nagata (eds.), PR Gray, PJ Hulst, SH Levis, and RG Meyer (co-authors), "Analog Integrated Circuit Design Techniques for System LSI (Basics) (Applications)", Baifukan Publishing, 2004 [Non-patent document 2] Willy Sansen, Rudy J. Van De Plassche, Johan H. Huijing, "Analog Circuuit Design, MOST RF Circuuits, Sigma-Delata Converters and Translinear Circuits, 1996 Summary of the Invention [Problem to be solved by the invention]

[0017] However, in recent NPN bipolar transistors fabricated using high-voltage CMOS processes, the base current amplification factor has fallen to single digits, making it difficult to assume that the base current is zero as in the past. That is, assuming that the base current amplification factor of the NPN transistor in FIG. 2 is βnp, when calculating IC3p, which is the output current described above, if this base current amplification factor βnp is taken into consideration, the above-mentioned Equation 3 becomes as shown in Equation 4 below.

[0018] IC3p≒{βnp / (1+βnp)} 1 / 2 (IC1p) 1 / 2 (IC2p) 1 / 2 ...Formula 4

[0019] Ultimately, Equation 4 means that if the base current amplification factor cannot be ignored, an accurate current proportional to the square root of the input current cannot be obtained.

[0020] The present invention has been made in view of the above circumstances, and provides a square root circuit that can suppress and reduce the influence of base current errors and generate highly accurate output values. [Means for solving the problem]

[0021] In order to achieve the above object of the present invention, the square root circuit according to the present invention comprises: A square root circuit configured to be able to output a square root signal for an input signal by a translinear circuit, first to fourth transistors using NPN bipolar transistors; fifth to seventh transistors using NMOS transistors; a collector of the first transistor is connected to a first input terminal, an emitter of the first transistor is connected to ground, and a base of the first transistor is connected to the emitter of the second transistor; the collector of the second transistor is connected to a second input terminal, while the base of the second transistor is connected to the base of the third transistor; the collector of the third transistor is connected to an output terminal, the emitter of the third transistor is connected to the collector and base of the fourth transistor, and the emitter of the fourth transistor is connected to ground; a gate of the fifth transistor is connected to the first input terminal, a drain of the fifth transistor is connected to a power supply voltage, and a source of the fifth transistor is connected to a gate of the sixth transistor and a base of the first transistor; The drain of the sixth transistor is connected to the emitter of the second transistor, while the source of the sixth transistor is connected to ground; The gate of the seventh transistor is connected to the second input terminal, the drain of the seventh transistor is adapted to receive the power supply voltage, and the source of the seventh transistor is connected to the base of the second transistor. [Effects of the Invention]

[0022] According to the present invention, by configuring the circuit using an NMOS transistor so that the base current error of the NPN bipolar transistor does not appear on the output side, it is possible to suppress or reduce the influence of the base current error, and it is possible to provide a square root circuit that can generate a highly accurate output value. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a square root circuit according to an embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram showing an example of the circuit configuration of a conventional square root circuit. [Figure 3] FIG. 4 is a characteristic diagram showing the relationship between input current and output current. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The components, arrangements, etc. described below do not limit the present invention, and various modifications can be made within the scope of the present invention. First, a square root circuit according to an embodiment of the present invention will be described with reference to FIG. The square root circuit in the embodiment of the present invention is similar to the conventional circuit in that it is based on a circuit configuration based on the so-called translinear principle, but differs from the conventional circuit in that it is configured to be able to suppress and reduce base current errors by also using MOS transistors, as will be described later.

[0025] Such a square root circuit is configured mainly from first to fourth transistors 1 to 4 (represented as "Q1," "Q2," "Q3," and "Q4," respectively in FIG. 1) that use NPN bipolar transistors, and fifth to seventh transistors 5 to 7 (represented as "Mn1," "Mn2," and "Mn3," respectively in FIG. 1) that use NMOS transistors.

[0026] The circuit configuration will be specifically described below. First, the collector of the first transistor 1 is connected to a first input terminal (denoted as "T1" in FIG. 1) 11, and the emitter is connected to ground. The base of the first transistor 1 is connected to the emitter of the second transistor 2, the source of the fifth transistor 5, and the gate and drain of the sixth transistor 6. The source of the sixth transistor 6 is connected to ground. The power supply voltage VCC is applied to the drain of the fifth transistor 5. The first input terminal 11 is supplied with an input current IIN.

[0027] The collector of the second transistor 2 is connected to a second input terminal (denoted as "T2" in FIG. 1) 12 and is also connected to the gate of the seventh transistor 7. The base of the second transistor 2 is also connected to the base of the third transistor 3 and is also connected to the source of the seventh transistor 7. The power supply voltage VCC is applied to the drain of the seventh transistor 7. A bias current IBIAS is supplied to the second input terminal 12.

[0028] The third transistor 3 has a collector connected to an output terminal (denoted as “T3” in FIG. 1) 13, and an emitter connected to the collector of the fourth transistor 4. The fourth transistor 4 has its base and collector connected to each other, and its emitter connected to the ground, so that it is provided in a so-called diode-connected state. The output terminal 13 outputs an output current IOUT.

[0029] Next, the circuit operation in the above configuration will be described. First, the input current IIN flowing into the first input terminal 11 is equal to the collector current IC1 of the first transistor 1, since the gate of the fifth transistor 5 is made of an insulator and no current flows into the gate of the fifth transistor 5. Furthermore, the sum of the base current of the first transistor 1 and the drain current of the sixth transistor 6 is equal to the sum of the source current of the fifth transistor 5 and the emitter current of the second transistor 2 .

[0030] In addition, the bias current IBIAS flowing into the second input terminal 12 is equal to the collector current IC2 of the second transistor 2, since the gate of the seventh transistor 7 is made of an insulator and no current flows into the gate of the seventh transistor 7. On the other hand, the base currents of the second and third transistors 2 and 3 are supplied with the source current of the seventh transistor 7 .

[0031] Furthermore, the emitter current IE3 of the third transistor 3 is branched to the collector and base of the fourth transistor 4, respectively. If the third transistor 3 and the fourth transistor 4 have the same characteristics, the collector current and base current of both transistors will be equal. That is, the collector current IC4 of the fourth transistor 4 will be equal to the collector current IC3 of the third transistor 3, and the base current of the fourth transistor 4 will be equal to the base current of the third transistor 3. In other words, IC3 = IC4.

[0032] Here, if the base-emitter voltage of the first transistor 1 is VBE1, the base-emitter voltage of the second transistor 2 is VBE2, the base-emitter voltage of the third transistor 3 is VBE3, and the base-emitter voltage of the fourth transistor 4 is VBE4, then according to Kirchhoff's voltage law, the following relational expression (5) holds:

[0033] VBE1+VBE2-VBE3-VBE4=0...Equation 5

[0034] As with the conventional circuit, by applying the relational expression VBE=VT·ln(IC / IS / χ), which is obtained by transforming the previous equation 1a, to this equation 5, the relational expression shown in the following equation 6 is obtained.

[0035] IC3=(IC1) 1 / 2 (IC2) 1 / 2 ...Formula 6

[0036] This equation 6 shows that in the square root circuit of an embodiment of the present invention, even if there is a base current error in the first to fourth transistors 1 to 4, which are NPN bipolar transistors, it is possible to obtain an output current IC3 proportional to the square root of the input current IC1.

[0037] FIG. 3 shows the results of a simulation of the output characteristics of the output current versus the input current, and this figure will be explained below. The simulation results are obtained when the bias current IBIAS of the second input terminal 12 is set to 1 μA and the base current amplification factor is set to 5. First, in FIG. 3, the horizontal axis indicates the input current IIN and the vertical axis indicates the output current IOUT, both of which are logarithmic axes. In addition, in FIG. 3, the results of a simulation of the output characteristics of the output current relative to the input current in the square root circuit according to the embodiment of the present invention are shown by a solid characteristic line.

[0038] 3, ideal values ​​of the output current vs. input current characteristics are shown as multiple black dots, and the simulation results of the square root circuit according to the embodiment of the present invention, shown by the solid characteristic line, almost coincide with each of these ideal values. This confirms that the square root circuit according to the embodiment of the present invention can obtain a highly accurate square root output without being affected by base current errors. In Figure 3, the results of a similar simulation for a conventional circuit are shown by the dashed characteristic line, but the entire characteristic line is below the ideal value described above. This confirms that with a conventional circuit, the output value always contains an error, making it impossible to obtain the desired, accurate square root output. [Industrial Applicability]

[0039] This can be applied to square root circuits where the influence of base current errors is suppressed or reduced and a highly accurate output value is desired. [Explanation of symbols]

[0040] 1...first transistor 2...Second transistor 3...Third transistor 4...Fourth transistor 5...fifth transistor 6...6th transistor 7...7th transistor 11...First input terminal 12...Second input terminal 13...Output terminal

Claims

[Claim 1] A square root circuit configured to be able to output a square root signal for an input signal by a translinear circuit, first to fourth transistors using NPN bipolar transistors; fifth to seventh transistors using NMOS transistors; a collector of the first transistor is connected to a first input terminal, an emitter of the first transistor is connected to ground, and a base of the first transistor is connected to the emitter of the second transistor; the collector of the second transistor is connected to a second input terminal, while the base of the second transistor is connected to the base of the third transistor; the collector of the third transistor is connected to an output terminal, the emitter of the third transistor is connected to the collector and base of the fourth transistor, and the emitter of the fourth transistor is connected to ground; a gate of the fifth transistor is connected to the first input terminal, a power supply voltage can be applied to a drain of the fifth transistor, and a source of the fifth transistor is connected to a gate of the sixth transistor and a base of the first transistor; The drain of the sixth transistor is connected to the emitter of the second transistor, while the source of the sixth transistor is connected to ground; a gate of the seventh transistor connected to the second input terminal, a drain of the seventh transistor to which the power supply voltage can be applied, and a source of the seventh transistor connected to the base of the second transistor.

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