Radio frequency silicon-on-insulator structure with superior performance, stability and manufacturability

Abstract

To provide a semiconductor-on-insulator structure having excellent radiofrequencydeviceperformance, and to provide a method of manufacturing the same.SOLUTION: The method of making the semiconductor-on-insulator composite structure 20 is based on depositing an undoped polycrystalline silicon film 28 on a high resistivity silicon substrate 22 and forming a stack of an oxide (e.g., a buried oxide layer 24) and a top silicon layer 26 on the polycrystalline silicon film 28. The polysilicon layer 28 serves as a high-defectivity layer between the silicon substrate 22 and the buried oxide layer 24.SELECTED DRAWING: Figure 2

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 697,474, filed July 13, 2018, the disclosure of which is incorporated herein by reference as if set forth in its entirety. [Technical Field]

[0002] FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor wafer fabrication, and more particularly to a method for fabricating semiconductor-on-insulator (e.g., silicon-on-insulator) structures, and relates to semiconductor-on-insulator structures having superior radio frequency device performance. [Background technology]

[0003] BACKGROUND OF THE INVENTION Semiconductor wafers are typically prepared from single-crystal ingots (e.g., silicon ingots) that are trimmed and polished to have one or more flats or notches for proper orientation of the semiconductor wafer during subsequent processing. The ingot is then sliced ​​into individual wafers. While this specification refers to semiconductor wafers derived from silicon, semiconductor wafers can also be prepared using other materials. For example, semiconductor wafers can be prepared using germanium, silicon carbide, silicon-germanium, gallium arsenide, alloys of Group III and Group V elements, such as gallium nitride or indium phosphide, or alloys of Group II and Group VI elements, such as cadmium sulfide or zinc oxide.

[0004] Semiconductor wafers (e.g., silicon wafers) can be used in the preparation of composite layer structures. Composite layer structures, such as semiconductor-on-insulator (SOI) structures, typically comprise a handle wafer or handle layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Typically, the device layer has a thickness of 0.01 to 20 μm, e.g., 0.05 to 20 μm. A thick device layer (or thick film device layer) can have a device layer thickness of about 1.5 μm to about 20 μm. A thin device layer (or thin film device layer) can have a thickness of about 0.01 μm to about 0.20 μm. Typically, composite layer structures such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz are formed by bringing two wafers into close contact, thereby initiating bonding through van der Waals forces, hydrogen bonding, or both, followed by a thermal treatment to strengthen the bond. Annealing converts terminal silanol groups into siloxane bonds between the two interfaces, thereby strengthening the bond.

[0005] After thermal annealing, the bonded structure undergoes further processing to remove a significant portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques such as etching or grinding can be used, often referred to as bond and etch SOI (i.e., BESOI) or bond and grind SOI (i.e., BGSOI). In such BESOI or BGSOI, a silicon wafer is bonded to a handle wafer and then slowly etched away until only a thin layer of silicon remains on the handle wafer. See, e.g., U.S. Pat. No. 5,189,500, which is incorporated herein by reference in its entirety. However, such methods are time-consuming and costly, waste one of the substrates, and generally do not provide adequate thickness uniformity for layers thinner than a few microns.

[0006] Another common method for achieving layer transfer utilizes hydrogen implantation followed by thermally induced layer splitting. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specific depth beneath the front surface of the donor wafer. The implanted particles form a cleavage plane within the donor wafer at the specific implantation depth. The donor wafer surface is cleaned to remove organic compounds or other contaminants (e.g., boron compounds or other particulate matter) that may have deposited on the wafer during the implantation process.

[0007] The front side of the donor wafer is then bonded to the handle wafer via a hydrophilic bonding process to form a bonded wafer (or bonded wafer). Prior to bonding, the donor wafer and / or handle wafer are activated by exposing the wafer surfaces to, for example, an oxygen- or nitrogen-containing plasma. Plasma exposure modifies the surface structure in a process often referred to as surface activation, which renders one or both surfaces of the donor and handle wafers hydrophilic. The wafer surfaces can be additionally chemically activated with a wet treatment, such as SC1 clean. The wet treatment and plasma activation can be performed in either order, or the wafers can be subjected to only one treatment. The wafers are then pressed together, forming a bond between them. This bond is relatively weak due to van der Waals forces and must be strengthened prior to further processing.

[0008] In some processes, the hydrophilic bond (or hydrophilic bond) between the donor wafer and the handle wafer (i.e., the bonded wafer or bonded wafers) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding can occur at low temperatures, such as approximately 300°C to 500°C. At lower bonding temperatures, the bridging layers of adsorbed water vapor on the surfaces are reduced, increasing the density of hydrogen bonds between the silanol groups on each wafer surface. In some processes, wafer bonding can occur at higher temperatures, such as approximately 800°C to 1100°C. At higher temperatures, covalent bonds are formed between the adjacent surfaces of the donor and handle wafers, e.g., converting silanol hydrogen bonds into covalent siloxane bonds, thereby strengthening the bond between the donor and handle wafers. Concurrent with the heating or annealing of the bonded wafers, particles implanted earlier by the donor wafer weaken the cleavage plane.

[0009] A portion of the donor wafer is then separated (i.e., cleaved) from the bonded wafer along the cleavage plane, forming an SOI wafer. Cleaving can be accomplished by placing the bonded wafers in a fixture, where a mechanical force is applied perpendicular to opposite sides of the bonded wafers, pulling (or peeling) the portion of the donor wafer away from the bonded wafer. According to some methods, the mechanical force is applied using a suction cup. Separation of the portion of the donor wafer is initiated by applying a mechanical force to the edge of the bonded wafer at the cleavage plane to initiate crack propagation along the cleavage plane. The mechanical force applied by the suction cup then pulls (or peels) the portion of the donor wafer away from the bonded wafer, forming an SOI wafer.

[0010] Alternatively, the bonded pair may instead be exposed to high temperatures for a period of time, thereby separating a portion of the donor wafer from the bonded wafer. High-temperature exposure initiates and propagates cracks along the cleavage plane, resulting in the separation of a portion of the donor wafer. Cracks form due to void formation from the implanted ions, which grow by Ostwald ripening. The voids fill with hydrogen and helium. The voids form platelets. Pressurized gas in the platelets propagates microcavities and microcracks, which weaken the silicon at the implant plane. If the annealing is stopped in a timely manner, the weakened bonded wafer can be cleaved by mechanical processes. However, if the heat treatment is continued for a longer period of time and / or at a higher temperature, the microcrack propagation reaches a level where all cracks merge along the cleavage plane, resulting in the separation of a portion of the donor wafer. This method provides better uniformity of the transferred layer and allows for recycling of the donor wafer, but typically requires heating the implanted and bonded pairs to temperatures approaching 500 °C.

[0011] The use of high-resistivity semiconductor-on-insulator (e.g., silicon-on-insulator) wafers for RF-related devices such as antenna switches offers significant advantages over conventional substrates in terms of cost and integration. Although not sufficient, the use of conductive substrates for high-frequency applications necessitates the use of high-resistivity substrate wafers to reduce parasitic power losses and minimize inherent harmonic distortion. Therefore, the resistivity of handle wafers for RF devices is typically greater than approximately 500 Ω·cm. Referring now to Figure 1, a silicon-on-insulator structure 2 comprises a very high-resistivity silicon wafer 4, a buried oxide (BOX) layer 6, and a silicon device layer 10. Such substrates are prone to the formation of a highly conductive charge inversion or accumulation layer 12 at the BOX / handle interface, which causes the generation of free carriers (electrons or holes), which reduces the effective resistivity of the substrate and results in parasitic power losses and device nonlinearity when the device is operated at RF frequencies. Such inversion / accumulation layers can result from BOX fixed charges, oxide trapped charges, interface trapped charges, and even DC bias applied to the device itself.

[0012] Therefore, a method is needed to suppress the formation of induced inversion or accumulation layers and maintain high substrate resistivity even in the very near surface region. It is known that a trap-rich layer between a high-resistivity handle substrate and a buried oxide (BOX) can improve the performance of RF devices fabricated using SOI wafers. Methods for forming these high-interface trap layers have been proposed. For example, as shown in Figure 2, one method for creating a semiconductor-on-insulator multilayer structure 20 (e.g., silicon-on-insulator, or SOI) with a trap-rich layer for RF device applications is based on depositing an undoped polycrystalline silicon film 28 on a high-resistivity silicon substrate 22 and then forming a stack of an oxide (e.g., buried oxide layer 24) and a top silicon layer 26 on the polycrystalline silicon film 28. The polycrystalline silicon layer 28 serves as a high-defectivity layer between the silicon substrate 22 and the buried oxide layer 24. See Figure 2. 2 shows a polycrystalline silicon film used as a trap-rich layer 28 between a high resistivity substrate 22 and a buried oxide layer 24 in a silicon-on-insulator multilayer structure 20. An alternative method is heavy ion implantation to create a near surface damage layer. Devices, such as radio frequency devices, are integrated into the top silicon layer 26.

[0013] Academic studies have shown that a polycrystalline silicon layer between the oxide and substrate improves device isolation, reduces transmission line losses, and reduces harmonic distortion. For example, HSGamble et al. “Low-loss CPW lines on surface stabilized high resistivity silicon,” Microwave Guided Wave Lett., 9(10), pp.395-397, 1999, D. Lederer, R. Lobet and J.-P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf., pp.46-47, 2004, D.Lederer and J.-P.Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity,” IEEE Electron Device Letters, vol.26, no.11, pp.805-807, 2005, D.Lederer, B.Aspar, C.Laghae and J.-P.Raskin, “Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI See, for example, Daniel C. Kerr et al., “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer,” Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008. Summary of the Invention

[0014] Summary of the Invention Briefly, the present invention is directed to the following multilayer structure (or structures): a single crystal silicon wafer handle substrate comprising two substantially parallel main surfaces, a circumferential edge, and a central surface, one of the two substantially parallel main surfaces being a front-side surface of the single crystal silicon wafer handle substrate, and the other of the two substantially parallel main surfaces being a back-side surface of the single crystal silicon wafer handle substrate; a trap rich layer in interfacial contact with the front-side surface of the single crystal silicon wafer handle substrate; a dielectric layer in interfacial contact with the trap rich layer; and a single crystal semiconductor device layer in interfacial contact with the dielectric layer; In the monocrystalline silicon wafer handle substrate, the peripheral edge connects (or joins) the front and back surfaces of the monocrystalline silicon wafer handle substrate, and the central plane of the monocrystalline silicon wafer handle substrate is between the front and back surfaces of the monocrystalline silicon wafer handle substrate; The single crystal silicon wafer handle substrate has a bulk resistivity of at least about 5000 Ω cm and a resistivity of about 1×10 16 atoms / cm 3 and an interstitial oxygen concentration of at least about 1×10 13 atoms / cm 3 and a nitrogen concentration of [Brief explanation of the drawings]

[0015] [Figure 1]FIG. 1 shows a silicon-on-insulator wafer comprising a high resistivity substrate and a buried oxide layer. [Figure 2] Figure 2 shows a silicon-on-insulator wafer, an SOI wafer with a polycrystalline silicon trap-rich layer between a high resistivity substrate and a buried oxide layer. [Figure 3] Figure 3 shows the harmonic distortion as a function of substrate resistivity for HR-SOI structures using trap-rich layers. [Figure 4] Figure 4 is a graph showing the resistivity depth profile of a float-zone grown handle wafer and a Czochralski grown handle wafer after SOI processing using a trap-rich layer. [Figure 5] Figure 5 is a graph showing the average resistivity of the first 90 microns below the BOX / handle interface of a float-zone grown handle wafer after SOI processing using a trap-rich layer. [Figure 6] Figure 6 is a graph showing a comparison of slip window on SOI multilayer structures where the handle substrate is created using the float zone method or the Czochralski method. [Figure 7] FIG. 7 is a graph showing the resistivity of SOI multilayer structures in which the handle substrate is fabricated using the float zone method under varying annealing conditions. [Figure 8] FIG. 8 is a graph showing a comparison of harmonic distortion (HD2) vs. pin for an SOI multilayer structure where the handle substrate is fabricated using the float zone method and a graph showing harmonic distortion (HD2) vs. pin for an SOI multilayer structure where the handle substrate is fabricated using the Czochralski method. DETAILED DESCRIPTION OF THE INVENTION

[0016] Detailed Description of Embodiments of the Invention In accordance with the present invention, methods and structures are provided for fabricating semiconductor-on-insulator (e.g., silicon-on-insulator) structures that enable superior radio frequency (RF) device performance, device stability, and device manufacturability. In the present invention, a high resistivity (e.g., very high resistivity or ultrahigh resistivity) float-zone (FZ) silicon base wafer (handle wafer) and a trap-rich layer are integrated (or integrated) into the semiconductor-on-insulator (e.g., silicon-on-insulator) structure.

[0017] Radio frequency (RF) chip designs benefit greatly from higher substrate resistivity levels. Improved quality factors for passive elements such as inductors and capacitors, reduced transmission line attenuation, and substrate electrical isolation between integrated digital, RF, and analog elements are achieved with higher resistivity silicon substrates. The industry standard is for handle substrate resistivities greater than 1000 Ω·cm, with even higher resistivities being preferred. Integrating high-resistivity substrates into semiconductor-on-insulator (e.g., silicon-on-insulator) structures (HRSOI) further improves RF functionality by improving device isolation, reducing conductive coupling to the substrate wafer, and lowering junction capacitance.

[0018] Growing ultra-high resistivity Czochralski (CZ) crystals to resistivity values ​​above 7500 Ω·cm poses severe challenges. Because the concentration of added electrically active dopants is significantly reduced, increased emphasis must be placed on controlling dopants (e.g., boron and phosphorus) introduced by all raw materials and components used in the CZ crystal puller. These materials and components include the polysilicon source material and quartz crucible. Furthermore, due to the very low dopant levels in the melt, controlling dopant mass transport to and through the boundary layer at the melt-solid interface becomes critical to achieving acceptable radial resistivity variation. Another key challenge in growing higher resistivity Czochralski silicon ingots is controlling the behavior of interstitial oxygen incorporated during crystal growth. The interstitial oxygen concentration (or interstitial oxygen concentration) in Czochralski-grown silicon is typically 5×10 17 atoms / cm 3 (10PPMA New ASTM) is higher, for example, up to about 1 × 10 18 atoms / cm 3 (20 PPMA new ASTM). The source of such interstitial oxygen is the dissolution of the SiO2 crucible during crystal growth. For high resistivity CZ silicon, oxygen is added at about 5 PPMA (2.5 x 10 17 atoms / cm 3 ), and a lower concentration, for example, about 2 PPMA (1 × 10 17 atoms / cm 3 ), approximately 3PPMA (1.5 × 10 17 atoms / cm 3 ) and approximately 4 PPMA (2 × 10 17 atoms / cm 3) can be controlled. However, even at low concentrations, interstitial oxygen can agglomerate into electrically active thermal donors, with the agglomeration rate strongly dependent on both the interstitial oxygen concentration and the annealing time / temperature between 350 and 500°C. At agglomeration levels greater than four oxygen atoms, thermal donors become electrically active and act as double donors. The formation of such donors reaches a maximum at approximately 450°C, then decreases, and can dissociate and return to an electrically inactive state upon annealing above approximately 550°C. However, with longer annealing times and higher annealing temperatures, such as 550°C to 850°C, so-called new thermal donors can form. Peak new thermal donor formation occurs at temperatures between 750°C and 800°C. We recently discovered another class of excess donors in high-resistivity silicon subjected to high-temperature thermal processing. A fast-diffusing species, as yet unidentified, is introduced into silicon wafers by a very high T anneal and then quenched by wafer cooling. Upon subsequent heating to 450°C–650°C, these species rapidly complex with interstitial oxygen in the wafer, forming electrically active “excess donors.” These excess donors dissociate when heated above approximately 1050°C–1100°C. Oxygen thermal double donors, new donors, and excess thermal donors contribute to electron conduction, which changes the wafer’s resistivity and type depending on the number of donors generated versus the wafer’s background carrier concentration. In p-type silicon, the thermal donor concentration increases the wafer’s resistivity to a point where it exceeds the p-type carrier concentration, converting the wafer to n-type. Further thermal donors then result in increasingly lower resistivity for n-type wafers. Resistivity changes during or at the end of the device fabrication process can disrupt resistivity-sensitive fabrication processes and degrade device performance.Although thermal donors can in principle be annihilated by high-T anneals (above about 550°C for thermal double donors and about 1050°C to about 1100°C for new and excess donors), in practice most of these donors are formed by low-temperature annealing steps (which can occur at temperatures around 450°C) that occur later in the integrated circuit fabrication flow ("back-of-the-line, or BEOL") after metallization. Once metal is deposited, the wafer cannot be heated to a T above about 500°C, so none of the thermal donor species formed in the BEOL can be annihilated. While thermal donors formed at 350-500°C can be removed in short high-temperature anneals, the presence of excess thermal donors is particularly pronounced in high-resistivity silicon (resistivity above 4000 Ω·cm) and even greater in materials with resistivities above 7500 Ω·cm. In such materials, the dopant concentration is 1.8×10. 12 / cm 3 (p-type) or N d <5×10 11 / cm 3 For comparison, the excess thermal donor concentration is about 1 × 10 for materials annealed at temperatures between about 1100 and 1125 °C. 12 / cm 3 and the excess thermal donor concentration is low in the material annealed at about 1000 °C, about 1 × 10 11 / cm 3 Given comparable dopant material (e.g., boron, arsenic, phosphorus, etc.) concentrations and excess thermal donor concentrations, materials identified as having high resistivity may suffer from resistivity variability and even an apparent shift from p-type to n-type.

[0019] Float-zone (FZ) silicon is an ultra-high-purity alternative to CZ silicon. FZ can be produced at resistivity levels exceeding 5000 Ω·cm, and resistivity levels exceeding 7500 Ω·cm, 10000 Ω·cm, and even 20000 Ω·cm can be produced. The float-zone process minimizes oxygen incorporation into the growing single crystal, advantageously minimizing oxygen thermal double donor formation, new thermal donor formation, and excess thermal donor formation. The concomitant reduction in thermal donor formation minimizes axial and radial resistivity variations in the ingot and wafers sliced ​​from it. This can both improve device performance and resistivity stabilization.

[0020] HRSOI wafers suffer from parasitic conduction at the interface between the buried oxide layer (BOX) and the high-resistivity substrate, which can extend more than 10 microns into the underlying high-resistivity substrate. This is caused by a combination of normal oxide charge within the BOX and a very low doping concentration in the substrate. The effect of parasitic surface conduction (referred to in the literature as PSC), shown in Figure 1, lowers the effective substrate resistivity and increases RF losses, substrate nonlinearities, and crosstalk. Placing a trap-rich layer 28 (see Figure 2) between the BOX 24 and the high-resistivity substrate 22 prevents the formation of the parasitic conduction layer 12 (see Figure 1) by trapping free carriers attracted to the BOX / substrate interface, suppressing the formation of accumulation or inversion layers. Combining a trap-rich layer with a stable float-zone silicon handle wafer with a resistivity greater than 5000 Ω·cm, greater than 7500 Ω·cm, even greater than 10000 Ω·cm, even greater than 20000 Ω·cm, or even greater than 30000 Ω·cm can achieve superior RF performance, such as second harmonic distortion (HD2) values ​​better than -80 dBm, better than -90 dBm, better than -100 dBm, or better than -110 dBm. See Figure 3, which shows the harmonic distortion as a function of substrate resistivity for HR-SOI structures with a trap-rich layer. As shown, higher resistivity wafers exhibit better HD2 values. More specifically, second harmonic distortion or HD2 values ​​of better than -100 dBm or better than -110 dBm can be achieved in SOI structures with float-zone handle substrates having resistivity values ​​greater than 20,000 Ω·cm or greater than 30,000 Ω·cm.

[0021] The use of float-zone handle wafers is intended to solve several problems: 1) the FZ provides a manufacturable crystal growth path to target resistivities of greater than 5000 Ω·cm, greater than 7500 Ω·cm, even greater than 10000 Ω·cm, even greater than 20000 Ω·cm, or even greater than 30000 Ω·cm, which, when combined with a trap-rich layer, enables improved RF performance; 2) the FZ has an oxygen content below the detection limit, which reduces or eliminates the formation of electrically active thermal donors and excess thermal donors, thereby preventing resistivity shifts that can degrade RF electrical performance and hinder wafer processing on device fabrication lines. Float-zone silicon is grown by vertical zone melting / purification of high-purity polycrystalline rods. A seed crystal is placed at one end of the rod to initiate single-crystal growth. This process avoids the use of a containment vessel, which significantly reduces the introduction of oxygen-containing impurities. In ultra-high resistivity silicon, it is essential to eliminate oxygen effects such as thermal donor formation. Nitrogen is typically intentionally added during the growth of the free-zone to control point defect formation and improve mechanical strength. The doping level and dopant type of the ultra-high resistivity free-zone depend on the purity of the polycrystalline source rod.

[0022] (I) Float Zone Handle Wafer According to the present invention, wafers sliced ​​from a float-zone grown monocrystalline silicon ingot are integrated into a semiconductor-on-insulator (e.g., silicon-on-insulator) multilayer structure 20 having the structure shown in Figure 2 as a high-resistivity handle structure. That is, the semiconductor-on-insulator (e.g., silicon-on-insulator) multilayer structure 20 comprises a float-zone high-resistivity handle structure 22 (or a highly resistive float-zone handle structure (e.g., semiconductor handle substrate 22)), a trap-rich layer 28, a dielectric layer 24, and a device layer 26.

[0023] Substrates used in the present invention include semiconductor handle substrates (e.g., monocrystalline semiconductor handle wafers) and semiconductor donor substrates (e.g., monocrystalline semiconductor donor wafers). The semiconductor device layer 26 in the semiconductor-on-insulator multilayer structure 20 originates from the monocrystalline semiconductor donor wafer. The semiconductor device layer 26 may be transferred onto the semiconductor handle substrate 22 by wafer thinning techniques such as etching the semiconductor donor substrate or by cleaving the semiconductor donor substrate including a damaged surface.

[0024] Generally, a single-crystal semiconductor handle wafer and a single-crystal semiconductor donor wafer have two substantially parallel major surfaces (or main surfaces or principal surfaces). One of the substantially parallel major surfaces is the front surface (or front face) of the substrate, and the other is the back surface (or back face) of the substrate. The substrate has a peripheral edge connecting the front and back surfaces, a bulk region between the front and back surfaces, and a central plane (or mid-plane) between the front and back surfaces. Additionally, the substrate has an imaginary central axis perpendicular to the central plane and a radial length extending from the central axis to the peripheral edge. Additionally, semiconductor substrates such as silicon wafers typically have total thickness variation (TTV), warp, and bow, so that the midpoints between all points on the front surface and all points on the back surface may not lie exactly within a plane. However, as a practical matter, TTV, bowing, and warpage are typically very slight, and the midpoint can be approximated as lying in an imaginary central plane that is approximately equidistant between the front and back surfaces.

[0025] Prior to the operations described herein, the front and back surfaces of a substrate may be substantially identical. For convenience only, a surface is referred to as the "front surface" or the "back surface" to distinguish between the surfaces on which the operations of the method of the present invention are performed. In the context of the present invention, the "front surface" of a monocrystalline semiconductor handle substrate (e.g., a monocrystalline silicon handle wafer) refers to the main surface of the substrate that will be the inner surface of the bonding structure. A trap-rich layer is formed on such a front surface. Therefore, the "back surface" of a monocrystalline semiconductor handle substrate (e.g., a handle wafer) refers to the main surface that will be the outer surface of the bonding structure. Similarly, the "front surface" of a monocrystalline semiconductor donor substrate (e.g., a monocrystalline silicon donor wafer) refers to the main surface of the monocrystalline semiconductor donor substrate that will be the inner surface of the bonding structure. The front surface of a monocrystalline semiconductor donor substrate often comprises a dielectric layer, such as a silicon dioxide layer, that will form part or all of the buried oxide (BOX) layer in the final structure. The "backside" of a single-crystal semiconductor donor substrate (e.g., a single-crystal silicon donor wafer) refers to the major surface that will be the exterior facing of the bonded structure. After conventional bonding and wafer thinning steps are completed, the single-crystal semiconductor donor substrate will comprise the semiconductor device layer of a semiconductor-on-insulator (e.g., silicon-on-insulator) composite structure.

[0026] The handle wafer comprises a material, such as silicon, derived from a float-zone grown ingot. Single-crystal silicon handle wafers sliced ​​from a float-zone grown ingot typically have a nominal diameter of at least about 20 mm, at least about 50 mm, at least about 100 mm, at least about 150 mm, or at least about 200 mm (e.g., a diameter of about 150 mm or about 200 mm). Surface tension limitations during the growth process commonly result in diameters of 250 mm or less, or about 200 mm or less. The thickness of the handle wafer can vary from about 100 micrometers to about 5000 micrometers, e.g., from about 100 micrometers to about 1500 micrometers, from about 250 micrometers to about 1500 micrometers, from about 300 micrometers to about 1000 micrometers, etc., and preferably from about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness can be about 725 micrometers, and in some embodiments, the wafer thickness can be about 775 micrometers.

[0027] In some embodiments, the float zone crystalline ingot, and the single crystal semiconductor handle substrates sliced ​​therefrom, have a bulk resistivity of at least about 5000 Ω·cm, at least about 7500 Ω·cm, such as at least about 10000 Ω·cm, at least about 15000 Ω·cm, at least about 20000 Ω·cm, at least about 25000 Ω·cm, or at least about 30000 Ω·cm. In some embodiments, the single crystal semiconductor handle substrate has a bulk resistivity of less than about 100000 Ω·cm. High resistivity wafers can include electrically active dopants such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type), typically at very low concentrations (e.g., less than 1×10 12 atoms / cm 3 Less than, or even 1×10 11 atoms / cm 3The method for preparing high resistivity wafers from float-zone monocrystalline silicon ingots is known in the art, and such high resistivity wafers may be obtained from commercial suppliers such as GlobalWafers, Inc. of Taiwan.

[0028] Silicon handle wafers derived from float-zone-grown ingots can more reliably target ultra-high resistivity values ​​with approximately double the minimum-to-maximum variation. For example, wafer resistivity can accept two-sided minimum-to-maximum specifications of 10,000–20,000 Ω·cm or greater, unlike UHR Cz wafers, where such specifications are typically single-sided, such as 7,500 Ω·cm or greater. A tolerance of ±30–50% around the target value can be tolerated. This not only allows end users to achieve improved RF electrical performance levels (e.g., as shown in Figure 3), but also results in greater predictability and less variability compared to Czochralski-grown silicon. The fundamental reason for this solution is that float-zone-grown silicon handle wafers have oxygen concentrations below the detection limit, avoiding thermal donor formation and the excessive thermal donor formation that causes variability in ultra-high resistivity Czochralski-grown silicon. In some embodiments, the float-zone grown silicon handle wafer has a surface roughness of, for example, about 2.5×10 by metrology. 16 atoms / cm 3 Less than (0.5PPMA, new ASTM standard), approximately 2 x 10 16 atoms / cm 3 Less than (0.4 PPMA, new ASTM standard), approximately 1 x 10 16 atoms / cm 3 Less than 0.2 PPMA (new ASTM standard), or approximately 1 x 10 15 atoms / cm 3The silicon handle wafer has an oxygen level below the detection limit, such as less than 0.02 ppm (as per the new ASTM standard), eliminating the presence of oxygen thermal donors and excess donors formed in Czochralski-grown silicon wafers (wafers with detectable oxygen concentrations). In some embodiments, the silicon handle wafer has an oxygen concentration of 1 x 10 11 Donor / cm 3 Less than or 5 x 10 10 Donor / cm 3 In some embodiments, the oxygen concentration is so low that the double donor thermal donor concentration, the new thermal donor concentration, and / or the excess thermal donor concentration are below the detectable limit; to a first approximation, the concentration of such donors is at least an order of magnitude less than the concentration of p-type acceptors or n-type donors. In other words, the double donor thermal donor concentration, the new thermal donor concentration, and / or the excess thermal donor concentration, or the sum of the double donor thermal donor concentration, the new thermal donor concentration, and / or the excess thermal donor concentration, is at least an order of magnitude less than the p-type acceptor or n-type donor concentration, i.e., less than one-tenth the concentration of p-type or n-type dopants. In the CZ, the thermal donors and excess donors can be below or above the background doping concentration, depending on the oxygen concentration and the details of the thermal cycle. The thermal double donor concentration in CZ Si continues to increase with annealing time up to 450 °C, reaching very large values. The concentration eventually saturates at a value that depends on Oi. For large Oi of ~15 nppm, the saturation concentration is ~1 × 10 16 / cm 3or even greater. The saturation (maximum) TDD concentration decreases with decreasing Oi, which may be much larger than the actual dopant concentration associated with HR Si. The lower donor concentration in FZ wafers reduces RF performance variability, reduces the impact of resistivity variations on device fabrication processes sensitive to wafer resistivity (electrostatic chucking), and eliminates sensitivity to new thermal donor formation, another source of variability in ultra-high resistivity / low-oxygen Czochralski-grown silicon wafers.

[0029] Additionally, the spreading resistance profile (SRP) of Czochralski-grown silicon handle wafers is rarely flat over the first few tens of microns below the BOX / handle interface, for example, after a 450°C anneal. The SRP of Czochralski-grown silicon handle wafers is often affected by TD formation and excess donors, resulting in significant profile changes, as shown in Figure 4. However, the SRP of float-zone-grown silicon handle wafers is very flat, demonstrating the complete absence of thermal donors and excess donors in 450°C and 600°C tests. See Figure 4. In the graph in Figure 4, the diamond (◆) line shows the resistivity per depth of the float-zone handle wafer before the 450°C donor generation anneal (DGA), and the X (X) line shows the resistivity per depth of the float-zone handle wafer after the 450°C DGA anneal. Furthermore, in this graph, the square (■) line shows the resistivity per depth of p-type Czochralski-grown handle wafers after a 450°C DGA anneal. And in this graph, the triangular (▲) line shows the resistivity per depth of n-type Czochralski-grown handle wafers after a 450°C DGA anneal. See also Figure 5. Figure 5 shows the average resistivity for the first 90 microns below the BOX / handle interface for float-zone-grown handle wafers (wafers with resistivities greater than 5000 Ω·cm and greater than 10000 Ω·cm) after SOI processing using a trap-rich layer. The profile is very flat, indicating the complete absence of thermal donors in both the 450°C and 600°C tests.

[0030] If float-zone grown silicon handle wafers have oxygen below the detectable limit, such wafers may be more prone to slip during thermal processing. However, nitrogen may be added during float-zone crystal growth to control point defect formation and add strength against slip. Special doping techniques, such as core doping, pill doping, and gas doping with nitrogen or ammonia gas, may be used to incorporate a uniform concentration of impurities. In some embodiments, the nitrogen concentration in float-zone grown silicon handle wafers is at least about 1×10 13 atoms / cm 3 , e.g., at least 0.5 × 10 14 atoms / cm 3 , at least about 1 x 10 14 atoms / cm 3 In some embodiments, the nitrogen concentration of the float-zone grown silicon handle wafer is about 3×10 15 atoms / cm 3 Less than 1 x 10 15 atoms / cm 3 Less than 7 x 10 14 atoms / cm 3 Less than, or about 3 × 10 14 atoms / cm 3 In some embodiments, the nitrogen concentration in the float-zone grown silicon handle wafer is at least about 0.5×10 14 atoms / cm 3 may be about 3 x 10 14 atoms / cm 3 Demonstration of nitrogen-doped float-zone grown silicon handle wafers on an SOI fabrication line showed acceptable slip performance nearly equivalent to that of Czochralski-grown silicon handle wafers.

[0031] In this regard, float-zone-grown and Czochralski-grown silicon handle wafers were subjected to oxidation at 800°C, followed by a 2-hour anneal cycle at 1100°C, and slip tests were performed. No slip was observed for either wafer type. Therefore, nitrogen-doped float-zone handle wafers can withstand the thermal cycles associated with trap-rich layer deposition and subsequent SOI wafer fabrication without slip. In a separate furnace push test, the furnace was heated to 1000°C, and float-zone-grown and Czochralski-grown silicon handle wafers were rapidly pushed through the furnace. Both wafer types exhibited similar behavior in this slip test.

[0032] In some embodiments, the front side, the back side, or both the front side and the back side of the single crystal semiconductor handle substrate can be subjected to a process such as an oxidation process to grow a dielectric layer, such as a semiconductor oxide layer, a semiconductor nitride layer, or a semiconductor oxynitride layer. In some embodiments, the dielectric layer comprises silicon dioxide (or silicon dioxide), which can be formed by oxidizing the front side of the silicon handle substrate. This can be achieved by thermal oxidation (thermal oxidation resulting in the consumption of a portion of the deposited semiconductor material film) and / or CVD oxide deposition and / or atomic layer deposition. In some embodiments, the semiconductor handle substrate can be thermally oxidized in a furnace such as an ASM A400. In the oxidizing environment, the temperature can range from 750°C to 1100°C. The oxidizing environment atmosphere can be a mixture of O2 and an inert gas such as Ar or N2. The oxygen content can vary from 1 to 10% or higher. In some embodiments, the oxidizing environment atmosphere can be up to 100% oxygen ("dry oxidation"). In some embodiments, the oxidizing ambient atmosphere is oxygen and ammonia, which is suitable for the deposition of silicon oxynitride (or silicon oxynitride). In some embodiments, the ambient atmosphere may include a mixture of an inert gas such as Ar or N, an oxidizing gas such as O, and water vapor ("wet oxidation"). In some embodiments, the ambient atmosphere may include a mixture of an inert gas such as Ar or N, an oxidizing gas such as O, water vapor ("wet oxidation"), and a nitriding gas such as ammonia. In some embodiments, the ambient atmosphere may comprise a mixture of an inert gas such as Ar or N and a nitriding gas such as ammonia, which is suitable for the deposition of silicon nitride (or silicon nitride). In an exemplary embodiment, a semiconductor handle wafer may be loaded into a vertical furnace such as an A400. The temperature is raised to the oxidation temperature using a mixture of N and O. At the desired temperature, water vapor is introduced into the gas flow. Once the desired oxide thickness is obtained, the water vapor and O are turned off, the furnace temperature is reduced, and the wafer is removed from the furnace.The oxide layer on the front side, the back side, or both may be about 100 angstroms to about 100,000 angstroms, about 100 angstroms to about 10,000 angstroms, about 100 angstroms to about 1,000 angstroms, for example, about 100 angstroms to about 700 angstroms, about 100 angstroms to about 500 angstroms, or about 100 angstroms to about 250 angstroms.

[0033] In some embodiments, the oxidation layer is relatively thin, about 5 Å to about 25 Å, for example, about 10 Å to about 15 Å. Thin oxide layers can be obtained on both sides of semiconductor wafers by exposure to standard cleaning solutions, such as an SC1 / SC2 cleaning solution. In some embodiments, the SC1 solution comprises 5 parts deionized water, 1 part aqueous NHOH (ammonium hydroxide, 29% NH by weight), and 1 part aqueous HO (hydrogen peroxide, 30%). In some embodiments, the handle substrate may be oxidized by exposure to an aqueous solution containing an oxidizing agent, such as an SC2 solution. In some embodiments, the SC2 solution comprises 5 parts deionized water, 1 part aqueous HCl (hydrochloric acid, 39% by weight), and 1 part aqueous HO (hydrogen peroxide, 30%).

[0034] (II) Trap-rich layer In the method of the present invention, a trap-rich layer comprising a polycrystalline or amorphous semiconductor material is deposited on the exposed front surface of a monocrystalline semiconductor handle wafer. Semiconductor materials suitable for use in forming a trap-rich layer in semiconductor-on-insulator devices favorably allow for the formation of a highly defective layer in the fabricated device. Such materials include polycrystalline and amorphous semiconductor materials. Polycrystalline or amorphous materials include silicon (Si), silicon-germanium (SiGe), carbon-doped silicon (SiC), and germanium (Ge). Polycrystalline silicon refers to a material comprising small silicon crystals with random crystal orientation. Polycrystalline silicon grains can be as small as about 20 nanometers in size. In the method of the present invention, the smaller the crystal grain size of the deposited polycrystalline silicon, the higher the defect rate in the trap-rich layer. Amorphous silicon includes a non-crystalline, allotropic form of silicon lacking short-range and long-range order. Silicon particles with a crystallinity of about 10 nanometers or less can also be considered amorphous in nature. Silicon-germanium includes alloys of silicon (or silicon) and germanium in any molar ratio. Carbon-doped silicon includes compounds of silicon and carbon, which may have different molar ratios of silicon to carbon. The resistivity of the polycrystalline silicon trap rich layer is at least 100 Ω·cm, at least about 500 Ω·cm, at least about 1000 Ω·cm, or even at least about 3000 Ω·cm, for example, from about 100 Ω·cm to about 100,000 Ω·cm, or from about 500 Ω·cm to about 100,000 Ω·cm, or from about 1,000 Ω·cm to about 100,000 Ω·cm, or from about 500 Ω·cm to about 10,000 Ω·cm, or from about 750 Ω·cm to about 10,000 Ω·cm, or from about 1,000 Ω·cm to about 10,000 Ω·cm, or from about 2,000 Ω·cm to about 10,000 Ω·cm, or from about 3,000 Ω·cm to about 10,000 Ω·cm, or from about 3,000 Ω·cm to about 8,000 Ω·cm.

[0035] Materials for deposition on the optionally oxidized front side of the monocrystalline semiconductor handle wafer may be deposited by means known in the art. For example, semiconductor materials may be deposited using metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors for LPCVD or PECVD include, among others, methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), and silicon tetrachloride (SiCl4). For example, polycrystalline silicon may be deposited on the surface oxide layer by thermal decomposition of silane (SiH4) at a temperature range of about 550°C to about 690°C (e.g., about 580°C to about 650°C). Chamber pressures may range from about 70 to about 400 mTorr. Amorphous silicon may be deposited by plasma-enhanced chemical vapor deposition (PECVD) at temperatures generally ranging from about 75°C to about 300°C. Silicon germanium, particularly amorphous silicon germanium, may be deposited by chemical vapor deposition at temperatures up to about 300°C using organogermanium compounds such as isobutylgermane, alkylgermanium trichloride, and dimethylaminogermanium trichloride. Carbon-doped silicon may be deposited by thermal plasma chemical vapor deposition in an epitaxial reactor using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include methylsilane, methane, ethane, and ethylene, among others. For LPCVD deposition, methylsilane is a particularly preferred precursor because it provides both carbon and silicon. For PECVD deposition, preferred precursors include silane and methane. In some embodiments, the silicon layer may comprise a carbon concentration of at least about 1% on an atomic basis, such as from about 1% to about 10% on an atomic basis.

[0036] In some embodiments, deposition of the semiconductor material of the trap-rich layer may be temporarily interrupted, at least once, and preferably more than once, to prepare a multilayer of trap-rich material. An interim surface of the semiconductor material film may be exposed to an inert, oxidizing, nitriding, or passivating atmosphere to poison or passivate the deposited semiconductor material. In other words, the method of the present invention may comprise depositing a multilayer of trap-rich semiconductor material by a cyclic process in which a semiconductor material is deposited, deposition is interrupted, the layer of semiconductor material is poisoned or passivated, and a next layer of semiconductor material is deposited. In some embodiments, a multilayer may be formed comprising one passivated semiconductor layer, and one additional semiconductor layer may be deposited to form the trap-rich layer. In some embodiments, the multilayer may comprise two or more passivated semiconductor layers and one additional semiconductor layer in the trap-rich layer. By depositing trap-rich layers in this manner, for example, a multilayer comprising one or more passivation layers of semiconductor material, or two or more passivation layers, e.g., at least three passivation layers of semiconductor material, or at least four passivation layers of semiconductor material, is deposited on the handle substrate, e.g., a multilayer comprising 4 to about 100 passivation layers, or 4 to about 60 passivation layers, or 4 to about 50 passivation layers, or 4 to about 25 passivation layers, or 6 to about 20 passivation layers, is deposited on the handle substrate. The number of semiconductor layers that can be deposited is limited, in part, by throughput requirements and the minimum practical layer thickness that can be deposited, which is currently about 20 nanometers. Each of these layers of semiconductor material is poisoned or passivated such that, during the high-temperature process of semiconductor-on-insulator fabrication, grain growth in each layer of the multilayer is limited by the thickness of the passivated multilayer, rather than by the overall trap-rich layer thickness as in conventional processes. In some embodiments, the semiconductor layer may be passivated by exposing the first semiconductor layer to an atmosphere comprising a nitrogen-containing gas, such as nitrogen, nitrous oxide, ammonia (NH), nitrogen plasma, and any combination thereof.In this regard, the atmosphere in which the semiconductor layer is deposited may include a nitrogen-containing gas, such as nitrogen, and termination of the deposition process and subsequent exposure to the gas may be sufficient to form a thin passivation layer on the semiconductor layer. In some embodiments, the chamber may be evacuated of deposition gases and purged with a nitrogen-containing gas to effect passivation of the previously deposited semiconductor layer. The nitrogen exposure may, for example, nitridize the deposited semiconductor layer, resulting in the formation of a thin layer of silicon nitride, e.g., only a few angstroms thick. Alternative passivation methods may also be used. For example, the semiconductor layer may be passivated by exposing the first semiconductor layer to an atmosphere containing an oxygen-containing gas, such as oxygen, ozone, water vapor, or any combination thereof. According to such embodiments, a thin layer of semiconductor oxide may be formed on the semiconductor layer and sufficient to passivate the layer. For example, a thin layer of silicon oxide may be formed between each layer in a multilayer structure. The oxide layer may have a thickness of only a few angstroms, such as between about 1 angstrom and about 20 angstroms, or between about 1 angstrom and about 10 angstroms. In some embodiments, air, which comprises both nitrogen and oxygen, may be used as the passivation gas. In some embodiments, the semiconductor layer may be passivated by exposing the first semiconductor layer to a liquid selected from the group consisting of water, peroxide (e.g., hydrogen peroxide solution), or SC1 solution (NH3:H2O2:H2O).

[0037] The total thickness of the trap rich layer can be from about 0.3 micrometers to about 5 micrometers, such as from about 0.3 micrometers to about 3 micrometers, or from about 0.3 micrometers to about 2 micrometers, or from about 2 micrometers to about 3 micrometers.

[0038] In some embodiments, following deposition of the trap rich layer, a dielectric layer is formed on the surface of the trap rich layer. In some embodiments, a single semiconductor handle substrate (e.g., a single crystal silicon handle substrate) is oxidized to form a semiconductor oxide (e.g., silicon dioxide) film on the trap rich layer. In some embodiments, the trap rich layer (e.g., a polycrystalline film) may be thermally oxidized (which results in consumption of a portion of the deposited semiconductor material film), or a semiconductor oxide (e.g., silicon dioxide) film may be grown by CVD oxide deposition. An oxide layer (e.g., a silicon dioxide layer) in contact with a polycrystalline or amorphous trap rich layer (e.g., a polycrystalline or amorphous silicon trap rich layer) may have a thickness of about 0.1 micrometers to about 10 micrometers, such as about 0.1 micrometers to about 4 micrometers, about 0.1 micrometers to about 2 micrometers, or about 0.1 micrometers to about 1 micrometer. The oxidation process further oxidizes the backside of the single crystal semiconductor handle wafer, advantageously reducing bowing and warping potentially caused by the different thermal expansion coefficients of silicon and silicon dioxide.

[0039] (III) Preparation of bond structure A single-crystal semiconductor handle wafer, such as a single-crystal silicon handle wafer prepared according to a float-zone process, is then bonded to a single-crystal semiconductor donor wafer prepared according to a conventional layer transfer process. In a preferred embodiment, the single-crystal semiconductor donor wafer comprises a material selected from the group consisting of silicon (or silicon), silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. The donor wafer may be sliced ​​from an ingot prepared by the float-zone process or the Czochralski process. The wafer thickness may vary between about 100 micrometers and about 5000 micrometers, e.g., between about 100 micrometers and about 1500 micrometers, between about 250 micrometers and about 1500 micrometers, and preferably between about 500 micrometers and about 1000 micrometers, such as between about 300 micrometers and about 1000 micrometers. In some specific embodiments, the wafer thickness may be approximately 725 micrometers. In some embodiments, the wafer thickness may be approximately 775 micrometers. Depending on the desired characteristics of the final integrated circuit device, the single-crystal semiconductor (e.g., silicon) donor wafer may comprise electrically active dopants such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), or arsenic (n-type). The resistivity of the single-crystal semiconductor (e.g., silicon) donor wafer may range from 1 to 100 Ω·cm, 1 to 50 Ω·cm, or 5 to 25 Ω·cm. The single-crystal semiconductor donor wafer may undergo standard process steps, including oxidation, implantation, and post-implantation cleaning. The etched, polished, and optionally oxidized single-crystal semiconductor donor wafer is then subjected to ion implantation to form a damage layer in the donor substrate.

[0040] In some embodiments, the monocrystalline semiconductor donor wafer comprises a dielectric layer. The dielectric layer may comprise one or more insulating layers formed on the front side of the monocrystalline semiconductor donor wafer. The insulating layer may comprise a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the insulating layer may comprise a material selected from the group consisting of Al2O3, AlN, or combinations thereof. In some embodiments, the dielectric layer comprises multiple layers of insulating material, although other configurations are within the scope of the present invention. Each insulating layer may comprise a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the dielectric layer comprises three layers of insulating material, in that order: silicon dioxide, silicon nitride, and silicon dioxide. The thickness of each insulating layer may be at least about 10 nanometers, for example, about 10 nanometers to about 10,000 nanometers, about 10 nanometers to about 5,000 nanometers, 50 nanometers to about 400 nanometers, or about 100 nanometers to about 400 nanometers, for example, about 50 nanometers, 100 nanometers, or 200 nanometers.

[0041] Ion implantation may be performed by commercially available equipment, such as an Applied Materials Quantum II, Quantum H, Quantum LEAP, or Quantum X. The implanted ions may include He, H, H2, or combinations thereof. The ion implantation is performed at a density and duration sufficient to form a damage layer in the semiconductor donor substrate. The implantation density is approximately 10 12 ions / cm 2 ~about 10 17 ions / cm 2 may be, for example, about 10 14 ions / cm 2 ~about 10 17 ions / cm 2 , or about 1015 ions / cm 2 ~about 10 17 ions / cm 2 , or about 10 16 ions / cm 2 ~about 10 17 ions / cm 2 The implantation energy may be in the range of about 1 keV to about 3000 keV, such as about 10 keV to about 3000 keV. The implantation energy may be about 1 keV to about 3000 keV, for example, about 5 keV to about 1000 keV, about 5 keV to about 200 keV, or about 5 keV to about 100 keV, or about 5 keV to about 80 keV. The implantation depth determines the thickness of the single-crystal semiconductor device layer transferred to the handle in the SOI process. Ions may be implanted to a depth of about 100 angstroms to about 30,000 angstroms, for example, about 200 angstroms to about 20,000 angstroms, about 2,000 angstroms to about 15,000 angstroms, or about 15,000 angstroms to about 30,000 angstroms. In some embodiments, after implantation, it may be desirable to subject the single crystal semiconductor donor wafer (e.g., single crystal silicon donor wafer) to a cleaning, which in some preferred embodiments may include a Piranha clean followed by a DI water rinse and an SC1 / SC2 clean.

[0042] In some embodiments of the present invention, He + , H + , H2 +A single-crystal semiconductor donor wafer having an ion-implanted region formed by ion implantation of, for example, ZnO, ZnCl, or any combination thereof, is annealed at a temperature sufficient to form a thermally activated cleavage plane in the single-crystal semiconductor donor substrate. An example of a suitable tool may include a simple box furnace, such as a Blue M model. In some preferred embodiments, the ion-implanted single-crystal semiconductor donor substrate is annealed at a temperature between about 200°C and about 350°C, between about 225°C and about 325°C, and preferably about 300°C. The thermal annealing may be performed for a period of about 2 hours to about 10 hours (e.g., between about 2 hours and about 8 hours). Thermal annealing in these temperature ranges is sufficient to form a thermally activated cleavage plane. After thermal annealing to activate the cleavage plane, the single-crystal semiconductor donor substrate surface is optionally cleaned.

[0043] In some embodiments, the ion-implanted, optionally cleaned, and optionally annealed single-crystal semiconductor donor wafer is subjected to oxygen and / or nitrogen plasma surface activation. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as the EVG® 810LT Low Temp Plasma Activation System available from EV Group. The ion-implanted and optionally cleaned single-crystal semiconductor donor wafer is loaded into a chamber. The chamber is evacuated and backfilled with O2 to a subatmospheric pressure, thereby generating a plasma. The single-crystal semiconductor donor wafer is exposed to the plasma for a desired time, which may range from about 1 second to about 120 seconds. Oxygen plasma surface oxidation is performed to render the front surface of the single-crystal semiconductor donor substrate hydrophilic and amenable to bonding to a single-crystal semiconductor handle substrate prepared according to the method described above.

[0044] The hydrophilic front side of the monocrystalline semiconductor donor wafer and the front side of the monocrystalline semiconductor handle wafer are then brought into intimate contact to form a bonded structure. In the method of the present invention, the front side of the monocrystalline semiconductor donor wafer and the front side of the monocrystalline semiconductor handle wafer may each comprise one or more insulating layers. The insulating layers constitute the dielectric layers of the bonded structure.

[0045] Because the mechanical bond may be relatively weak, the bonded structure may be further annealed to solidify the bond between the single crystal semiconductor donor wafer and the single crystal semiconductor handle wafer. In some embodiments of the present invention, the bonded structure is annealed at a temperature sufficient to form a thermally activated cleavage plane in the single crystal semiconductor donor wafer. An example of a suitable tool may be a simple box furnace, such as a Blue M model. In some embodiments, the bonded structure is annealed at a temperature between about 200°C and about 400°C, between about 300°C and about 400°C, e.g., between about 350°C and about 400°C.

[0046] In some embodiments, annealing is performed at relatively high pressures, such as from about 0.5 MPa to about 200 MPa, e.g., from about 0.5 MPa to about 100 MPa, from about 0.5 MPa to about 50 MPa, from about 0.5 MPa to about 10 MPa, or from about 0.5 MPa to about 5 MPa. Conventional bonding methods are prone to temperature limitation due to thermal cleavage, which occurs when the platelet pressure at the implanted surface exceeds the external isostatic pressure. Therefore, conventional annealing may be limited to bonding temperatures of from about 350°C to about 400°C due to thermal cleavage. After implantation and bonding, the wafers are weakly held together; however, the gap between the wafers is sufficient to prevent gas intrusion or leakage. While the weak bond can be strengthened by heat treatment, the cavity formed during implantation fills with gas. During heating, the gas in the cavity is pressurized. It is estimated that the pressure can reach 0.2-1 GPa, depending on the implant dose (Cherkashin et al., J. Appl. Phys. 118, 245301 (2015)). Above a critical pressure, the layers delaminate. This is called thermal cleave. This prevents higher temperatures or longer annealing times. In some embodiments of the invention, bonding occurs at high pressures, e.g., from about 0.5 MPa to about 200 MPa, e.g., from about 0.5 MPa to about 100 MPa, or from about 0.5 MPa to about 50 MPa, or from about 0.5 MPa to about 10 MPa, or from about 0.5 MPa to about 5 MPa, thereby enabling bonding at higher temperatures. In some embodiments, the bonded structure is annealed at a temperature between about 300°C and about 700°C, between about 400°C and about 600°C, e.g., between about 400°C and about 450°C, between about 450°C and about 600°C, or between about 350°C and about 450°C. Increasing the thermal budget can have a positive effect on bond strength. The thermal annealing can be performed for a time between about 0.5 hours and about 10 hours, e.g., between about 0.5 hours and about 3 hours, preferably about 2 hours. Thermal annealing within these temperature ranges is sufficient to form thermally activated cleavage planes.In conventional bonding annealing, roll-off can cause the edges of both the handle and donor wafers to move apart significantly. In such regions, there is no layer transfer, which is called a terrace. Pressurized bonding is expected to reduce this terrace and extend the SOI layer further towards the edge. This mechanism is based on trapped air pockets compressing and "zipping" outwards. After a thermal anneal to activate the cleave planes, the bonded structure can be cleaved.

[0047] After thermal annealing, the bond between the monocrystalline semiconductor donor wafer and the monocrystalline semiconductor handle wafer is strong enough to initiate layer transfer through cleaving of the bonded structure at the cleavage plane. Cleaving may be performed according to techniques known in the art. In some embodiments, the bonded structure may be placed in a conventional cleaving station, where one side is attached to a stationary suction cup and the other side is attached to a hinged arm by an additional suction cup. A crack initiates near the suction cup attachment, and the movable arm rotates about the hinge to cleave the wafer. Cleaving removes a portion of the semiconductor donor wafer, thereby leaving a monocrystalline semiconductor device layer 26 (preferably a silicon device layer) on the semiconductor-on-insulator composite structure 20. See FIG. 2.

[0048] After cleaving, the cleaved structure may be subjected to a high temperature anneal to further strengthen the bond between the transferred device layers 26 and the monocrystalline semiconductor handle wafer 22. An example of a suitable tool may be a vertical furnace such as an ASM A400. In some preferred embodiments, the bonded structure is annealed at a temperature between about 1000°C and about 1200°C, preferably about 1000°C. The thermal anneal may be performed for a period of about 0.5 hours to about 8 hours, preferably about 4 hours. Thermal annealing in these temperature ranges is sufficient to strengthen the bond between the transferred device layers and the monocrystalline semiconductor handle wafer.

[0049] After cleaving and high-temperature annealing, the bonded structure may be subjected to a cleaning process designed to remove thin thermal oxide from the surface and clean any grain. In some embodiments, the single-crystal semiconductor device layer may be subjected to a gas-phase HCl etch process in a horizontal flow single-wafer epitaxial reactor using H as the carrier gas to achieve a desired thickness and smoothness. In some embodiments, the semiconductor device layer 26 may have a thickness of about 20 nanometers to about 3 micrometers, such as about 20 nanometers to about 2 micrometers, e.g., about 20 nanometers to about 1.5 micrometers, or about 1.5 micrometers to about 3 micrometers.

[0050] In some embodiments, an epitaxial layer may be deposited on the transferred monocrystalline semiconductor device layer 26. The deposited epitaxial layer may have substantially the same electrical properties as the underlying monocrystalline semiconductor device layer 26. Alternatively, the epitaxial layer may have different electrical properties than the underlying monocrystalline semiconductor device layer 26. The epitaxial layer may comprise a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending on the desired characteristics of the final integrated circuit device, the epitaxial layer may comprise an electrically active dopant, such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The resistivity of the epitaxial layer may be 1 to 1050 Ω·cm, 1 to 50 Ω·cm, and typically 5 to 25 Ω·cm. In some embodiments, the epitaxial layer may have a thickness of about 20 nanometers to about 3 micrometers, such as about 20 nanometers to about 2 micrometers, about 20 nanometers to about 1.5 micrometers, or about 1.5 micrometers to about 3 micrometers.

[0051] The completed SOI multilayer structure may comprise a single-crystal semiconductor handle wafer 22, a trap-rich layer 28, a dielectric layer 24, and a semiconductor device layer 26, and may then be subjected to end-of-line metrology testing and final cleaning using a typical SC1-SC2 process. Thus, the present invention is directed to an SOI multilayer structure comprising a trap-rich layer and a handle substrate made of nitrogen-doped, high-resistivity (resistivity greater than 20 kΩ·cm) float-zone material. Float-zone wafers exhibit better resistivity stability over typical back-end-of-line (BEOL) anneals than standard Czochralski handle wafers. The higher resistivity achievable using the FZ process allows for step-change improvements in substrate RF loss, crosstalk, and harmonic distortion that are not readily achievable with traditional CZ silicon materials. We report the first demonstration of a FZ CTLSOI substrate with an HD2 of -110 dBm in our CPW structure.

[0052] The present invention is further illustrated by the following examples, which should not be construed as limiting the invention.

[0053] Example 1. Float Zone Wafer The tests used wafers from commercially grown 200 mm high resistivity nitrogen-doped float-zone crystals. The resistivity of the wafers was greater than 20 kΩ·cm. The oxygen concentration in the wafers was 1×10 16 atoms / cm 3 Wafers with different levels of nitrogen were evaluated for their mechanical strength, and the nitrogen concentration was found to be less than 0.5×10 14 / cm 3 ~3×10 14 / cm 3The FZ wafers then had a trap-rich layer deposited on top of them. The wafers were then processed into SOI wafers under a high-volume manufacturing (HVM) process flow. At the end of the SOI wafer fabrication flow, the wafers underwent standard quality inspection, including surface inspection using a KLA-Tencor SP1, flatness, shape measurement using an ADE9700, and slip inspection.

[0054] Example 2. Slip stress test SOI wafers fabricated with float-zone-prepared handle substrates with low and higher nitrogen concentrations were subjected to enhanced thermal stress tests by varying the radial thermal gradient across the wafer to mimic rapid thermal processing (RTP) thermal cycles. The purpose of these thermal stress tests was to intentionally induce slip in the wafers and to test the mechanical robustness of SOI structures with FZ handle substrates and SOI wafers with Czochralski (CZ) handle substrates. SOI structures fabricated on CZ wafers with ~3.5 ppma (new ASTM) interstitial oxygen Oi were included as control wafers. The UHR SOI structures with FZ handle substrates exhibited a slip-free "window" of induced thermal gradients deemed suitable for safe handling in the subsequent device fabrication process flow, although the window was not nearly as wide as that for the higher-oxygen CZ wafers. See Figure 6. Figure 6 compares slip windows on SOI multilayer structures where the handle substrate is fabricated using the float-zone or Czochralski techniques. Within the nitrogen range tested on such wafers, slight improvements are seen at higher N concentrations.

[0055] Example 3. Resistivity stability Spreading resistance profile (SRP) measurements were performed at the end of the line to examine the resistivity stability of the wafers. The resistivity of SOI wafers with oxygen-containing Czochralski (CZ) handle substrates exhibits thermal double donor formation at temperatures between 350 and 500 °C, with a strong peak at approximately 450 °C. This can lead to a decrease in resistivity in the handle wafer during back-end metal annealing processes, which often fall within this temperature range. SOI structures with FZ handle substrates are virtually oxygen-free and therefore not susceptible to such resistivity changes. See Figure 7. Figure 7 shows that, as expected, the resistivity of the SOI structures with FZ handle substrates remains the same before and after a 1-hour anneal at 450 °C. Additionally, because the FZ handle substrates are nitrogen-doped, a 1-hour anneal at 600 °C was performed to confirm the absence of NO-related donors, which would be expected in CZ silicon if oxygen and nitrogen were present.

[0056] Example 4. Harmonic Distortion Radio frequency (RF) testing was performed on several SOI structures with FZ handle substrates. The top silicon layer of the SOI wafer was removed (through wet chemical etching), and coplanar waveguide structures were fabricated directly on the BOX layer. Second-harmonic distortion (HD2) and third-harmonic distortion (HD3) were measured for input powers up to 35 dBm. Devices were tested across the wafer diameter to determine the radial uniformity of the results. Results were then compared with similarly fabricated planar waveguide structures on SOI wafers with Czochralski-prepared handle substrates.

[0057] Figure 8 shows the HD2 performance of our first- and second-generation SOI wafers with handle substrates prepared by the Czochralski method. The HD2 performance at Pin = 15 dBm for these wafers is −80 dBm and −90 dBm, respectively. Meanwhile, the HD2 of the SOI structures with FZ handle substrates shows a dramatic improvement of 20 dBm, to a value of −110 dBm at Pin = 15 dBm. The performance difference is caused by the resistivity difference between typical CZ and Z wafers. HD2 was measured at multiple sites on the wafer, but no strong radial variation in HD2 was observed. The SOI structures with FZ handle substrates consistently performed better than the SOI wafers with handle substrates prepared by the Czochralski method.

[0058] When referring to elements of the disclosure or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive, meaning that there may be additional elements other than the listed elements.

[0059] It is intended that all matter contained in the above description and shown in the drawings be interpreted as illustrative and not in a limiting sense, as various changes may be made in the matter described above without departing from the scope of the present disclosure.

Claims

1. A multi-layer structure, a monocrystalline silicon wafer handle substrate having two substantially parallel major surfaces, a peripheral edge, and a central surface, one of the two substantially parallel major surfaces being a front-side surface of the monocrystalline silicon wafer handle substrate, and the other of the two substantially parallel major surfaces being a back-side surface of the monocrystalline silicon wafer handle substrate; a trap rich layer in interfacial contact with the front side of the single crystal silicon wafer handle substrate; a dielectric layer in interfacial contact with the trap rich layer; a single crystal semiconductor device layer in interfacial contact with the dielectric layer; and In the monocrystalline silicon wafer handle substrate, the peripheral edge connects the front side and the back side of the monocrystalline silicon wafer handle substrate, and the central plane of the monocrystalline silicon wafer handle substrate is between the front side and the back side of the monocrystalline silicon wafer handle substrate; The single crystal silicon wafer handle substrate has a bulk resistivity of at least about 5000 Ω cm and a resistivity of about 1×10 １６ atoms / cm ３ and an interstitial oxygen concentration of at least about 1×10 １３ atoms / cm ３ and a nitrogen concentration of

2. 10. The multi-layer structure of claim 1, wherein the single crystal semiconductor handle substrate comprises a silicon wafer sliced ​​from a float-zone grown single crystal silicon ingot.

3. 3. The multi-layer structure of claim 2, wherein the silicon wafers sliced ​​from the float-zone grown single crystal silicon ingot have a diameter of at least about 150 mm.

4. 3. The multi-layer structure of claim 2, wherein the silicon wafers sliced ​​from the float-zone grown single crystal silicon ingot have a diameter of at least about 200 mm.

5. The multilayer structure of any one of claims 1 to 4, wherein the single crystal semiconductor handle substrate has a bulk resistivity of at least about 7500 ohm-cm.

6. The multilayer structure of any one of claims 1 to 4, wherein the monocrystalline semiconductor handle substrate has a bulk resistivity of at least about 10000 ohm-cm.

7. The multilayer structure of any one of claims 1 to 4, wherein the monocrystalline semiconductor handle substrate has a bulk resistivity of at least about 15000 ohm-cm.

8. The multilayer structure of any one of claims 1 to 4, wherein the monocrystalline semiconductor handle substrate has a bulk resistivity of at least about 20000 ohm-cm.

9. The multilayer structure of any one of claims 1 to 4, wherein the monocrystalline semiconductor handle substrate has a bulk resistivity of less than about 100,000 ohm-cm.

10. The single crystal semiconductor handle substrate is 1×10 １１ Donor / cm ３ 10. The multilayer structure of claim 1, having an excess thermal donor concentration of less than .

11. The single crystal semiconductor handle substrate is 5×10 １０ Donor / cm ３ 10. The multilayer structure of claim 1, having an excess thermal donor concentration of less than .

12. The single crystal semiconductor handle substrate is 1×10 １２ atoms / cm ３ a p-type dopant at a concentration of less than 12. The multilayer structure of claim 1, further comprising a concentration of oxygen thermal double donors, new donors, excess thermal donors or any combination thereof that is at least one order of magnitude less than the concentration of the p-type dopant.

13. The single crystal semiconductor handle substrate is 1×10 １１ atoms / cm ３ a p-type dopant at a concentration of less than 12. The multilayer structure of claim 1, further comprising: a concentration of oxygen thermal double donors, new donors, and excess thermal donors, or any combination thereof, that is at least one order of magnitude less than the concentration of the p-type dopant.

14. The single crystal semiconductor handle substrate is 1×10 １２ atoms / cm ３ an n-type dopant at a concentration of less than 12. The multilayer structure of claim 1, further comprising a concentration of oxygen thermal double donors, new donors, excess thermal donors or any combination thereof that is at least one order of magnitude less than the concentration of the n-type dopant.

15. The single crystal semiconductor handle substrate is 1×10 １１ atoms / cm ３ an n-type dopant at a concentration of less than 12. The multilayer structure of claim 1, further comprising a concentration of oxygen thermal double donors, new donors, excess thermal donors or any combination thereof that is at least one order of magnitude less than the concentration of the n-type dopant.

16. The single crystal semiconductor handle substrate has a thickness of about 1×10 １５ atoms / cm ３ 16. The multilayer structure of any one of claims 1 to 15, having an interstitial oxygen concentration of less than 1000 .mu.m.

17. The single crystal semiconductor handle substrate has a thickness of at least about 1×10 １４ atoms / cm ３ 17. The multilayer structure of claim 1, having a nitrogen concentration of

18. The single crystal semiconductor handle substrate has a thickness of about 3×10 １５ atoms / cm ３ The multilayer structure of any one of claims 1 to 16, having a nitrogen concentration of less than 1000 ppm.

19. The single crystal semiconductor handle substrate has a thickness of about 1×10 １５ atoms / cm ３ The multilayer structure of any one of claims 1 to 16, having a nitrogen concentration of less than 1000 ppm.

20. The single crystal semiconductor handle substrate has a thickness of about 7×10 １４ atoms / cm ３ The multilayer structure of any one of claims 1 to 16, having a nitrogen concentration of less than 1000 ppm.

21. The single crystal semiconductor handle substrate has a thickness of about 5×10 １４ atoms / cm ３ and about 2 x 10 １５ atoms / cm ３ 17. The multilayer structure of claim 1, having a nitrogen concentration between 0.1 and 0.

5.

22. 22. The multi-layer structure of any one of claims 1 to 21, wherein the trap rich layer comprises one or more polycrystalline semiconductor layers, each of the one or more polycrystalline semiconductor layers comprising a material selected from the group consisting of silicon, SiGe, SiC, and Ge.

23. 22. The multi-layer structure of any one of claims 1 to 21, wherein the trap rich layer comprises one or more amorphous semiconductor layers, each of the one or more amorphous semiconductor layers comprising a material selected from the group consisting of silicon, SiGe, SiC, and Ge.

24. The multi-layer structure of any one of claims 1 to 23, wherein the trap rich layer has a resistivity greater than about 1000 ohm-cm.

25. The multi-layer structure of any one of claims 1 to 23, wherein the trap rich layer has a resistivity greater than about 3000 ohm-cm.

26. 24. The multi-layer structure of any one of claims 1 to 23, wherein the trap rich layer has a resistivity between about 2000 ohm-cm and about 10000 ohm-cm.

27. 24. The multi-layer structure of any one of claims 1 to 23, wherein the trap rich layer has a resistivity between about 3000 ohm-cm and about 10000 ohm-cm.

28. 24. The multi-layer structure of any one of claims 1 to 23, wherein the trap rich layer has a resistivity between about 3000 ohm-cm and about 5000 ohm-cm.

29. 29. The multi-layer structure of any one of claims 1 to 28, wherein the trap rich layer has a thickness between about 0.1 micrometers and about 50 micrometers.

30. 29. The multi-layer structure of any one of claims 1 to 28, wherein the trap rich layer has a thickness between about 0.1 micrometers and about 20 micrometers.

31. 29. The multi-layer structure of any one of claims 1 to 28, wherein the trap rich layer has a thickness between about 0.1 micrometers and about 10 micrometers.

32. 29. The multi-layer structure of any one of claims 1 to 28, wherein the trap rich layer has a thickness between about 0.5 micrometers and about 5 micrometers.

33. 33. The multilayer structure of any one of claims 1 to 32, wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, aluminum oxide, aluminum nitride, and any combination thereof.

34. 33. The multilayer structure of any one of claims 1 to 32, wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.

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