Process control for ion energy delivery using multiple generators and phase control

Abstract

To provide a method and system for enabling process control for ion energy delivery using multiple generators and phase control.SOLUTION: A method for applying RF power in a plasma processing chamber, comprising generating first, second and third RF signals, wherein the first, second and third RF signals are generated at different frequencies. The method also includes combining the first, second, and third RF signals to generate a combined RF signal. The wave shape of the combined RF signal approximates a tilted square wave shape. The method further includes applying the combined RF signal to a chuck within the plasma processing chamber.SELECTED DRAWING: None

Description

[Technical Field]

[0001] 1. Field of Disclosure The present disclosure relates to semiconductor device manufacturing. [Background technology]

[0002] 2. Description of Related Technology Plasma etching processes are often used in the fabrication of semiconductor devices on semiconductor wafers. In plasma etching processes, semiconductor wafers containing semiconductor devices under fabrication are exposed to plasma generated within a plasma processing volume. The plasma interacts with materials on the semiconductor wafer to remove material from the semiconductor wafer and / or modify that material to enable subsequent removal from the semiconductor wafer. Plasma can be generated using specific reactive gases, whereby constituents of the plasma interact with materials to be removed / modified from the semiconductor wafer without significantly interacting with other materials on the wafer that are not to be removed / modified. Plasma is generated by using radio frequency signals to energize specific reactive gases. These radio frequency signals are transmitted through a plasma processing volume containing the reactive gases while the semiconductor wafer is exposed to the plasma processing volume. The transmission path of the radio frequency signal through the plasma processing volume can affect how the plasma is generated within the plasma processing volume. For example, the reactive gases may be energized more in regions of the plasma processing volume where more radio frequency signal power is transmitted, causing spatial non-uniformity in the plasma characteristics throughout the plasma processing volume. Spatial non-uniformities in plasma characteristics can manifest as spatial non-uniformities in ion density, ion energy, and / or reactive constituent density, among other plasma characteristics. Spatial non-uniformities in plasma characteristics correspondingly cause spatial non-uniformities in plasma processing results on semiconductor wafers. Thus, the manner in which radio frequency signals are transmitted through a plasma processing volume can have an impact on the uniformity of plasma processing results on semiconductor wafers. It is in this context that the present disclosure is made. Summary of the Invention

[0003] Generally, embodiments of the present disclosure provide methods and systems for enabling process control for ion energy delivery using multiple generators and phase control.

[0004] In some embodiments, a method for applying RF power in a plasma processing chamber is provided, the method including generating a first RF signal, generating a second RF signal, and generating a third RF signal, wherein the first, second, and third RF signals are generated at different frequencies, and the method further includes combining the first, second, and third RF signals to generate a combined RF signal, wherein a waveform of the combined RF signal is configured to approximate a ramped square wave shape, and applying the combined RF signal to a chuck in the plasma processing chamber.

[0005] In some embodiments, the first RF signal is generated at a fundamental frequency, the second RF signal is generated at a first predetermined harmonic frequency of the fundamental frequency, and the third RF signal is generated at a second predetermined harmonic frequency of the fundamental frequency.

[0006] In some embodiments, the first or second predetermined harmonic frequency is an even or odd harmonic of the fundamental frequency.

[0007] In some embodiments, generating the second RF signal includes adjusting a phase of the second RF signal relative to a phase of the first RF signal, and generating the third RF signal includes adjusting a phase of the third RF signal relative to a phase of the first RF signal, and adjusting the phase of the second and third RF signals adjusts the amount of slope of the waveform of the combined RF signal.

[0008] In some embodiments, the waveform of the combined RF signal is configured to compensate for the capacitance of the chuck so that the combined RF signal reaching a wafer supported by the chuck has a waveform that approximates a non-tilted square wave shape.

[0009] In some embodiments, the waveform of the combined RF signal is configured to concentrate the ion energy distribution function of ions directed from the plasma by application of the combined RF signal.

[0010] In some embodiments, converging the ion energy distribution function increases the directionality of the ions and reduces bowing of features etched by the ions.

[0011] In some embodiments, the waveform of the combined RF signal is configured such that the peaks of the waveform exhibit a positive slope and the valleys of the waveform exhibit a negative slope.

[0012] In some embodiments, the waveform of the combined RF signal is configured to ensure verticality of high aspect ratio features during etching.

[0013] In some embodiments, the first RF signal is generated at a frequency in the range of approximately 50 to 500 kHz.

[0014] In some embodiments, a system for applying RF power in a plasma processing chamber is provided, the system including a first generator that generates a first RF signal, a second generator that generates a second RF signal, and a third generator that generates a third RF signal, wherein the first, second, and third RF signals are generated at different frequencies, the first, second, and third RF signals are combined to generate a combined RF signal, a waveform of the combined RF signal configured to approximate a ramped square wave shape, and the combined RF signal is configured to be applied to a chuck in the plasma processing chamber.

[0015] In some embodiments, the first RF signal is generated at a fundamental frequency, the second RF signal is generated at a first predetermined harmonic frequency of the fundamental frequency, and the third RF signal is generated at a second predetermined harmonic frequency of the fundamental frequency.

[0016] In some embodiments, the first or second predetermined harmonic frequency is an even or odd harmonic of the fundamental frequency.

[0017] In some embodiments, the second RF signal is generated by adjusting the phase of the second RF signal relative to the phase of the first RF signal, and the third RF signal is generated by adjusting the phase of the third RF signal relative to the phase of the first RF signal, and adjusting the phase of the second and third RF signals adjusts the amount of slope of the waveform of the combined RF signal.

[0018] In some embodiments, the waveform of the combined RF signal is configured to compensate for the capacitance of the chuck so that the combined RF signal reaching a wafer supported by the chuck has a waveform that approximates a non-tilted square wave shape.

[0019] In some embodiments, the waveform of the combined RF signal is configured to concentrate the ion energy distribution function of ions directed from the plasma by application of the combined RF signal.

[0020] In some embodiments, converging the ion energy distribution function increases the directionality of the ions and reduces bowing of features etched by the ions.

[0021] In some embodiments, the waveform of the combined RF signal is configured such that the peaks of the waveform exhibit a positive slope and the valleys of the waveform exhibit a negative slope.

[0022] In some embodiments, the waveform of the combined RF signal is configured to ensure verticality of high aspect ratio features during etching.

[0023] In some embodiments, the first RF signal is generated at a frequency in the range of approximately 50 to 500 kHz.

[0024] In some embodiments, the system further includes an impedance matching system that combines the first, second, and third RF signals to generate a combined RF signal. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a conceptual diagram illustrating a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, according to an embodiment of the present disclosure.

[0026] [Figure 2] 1 illustrates a vertical cross section through a plasma processing system for use in semiconductor chip manufacturing, according to some embodiments.

[0027] [Figure 3] 1A-1C conceptually illustrate various low frequency RF waveforms that approximate a ramped square waveform, according to embodiments of the present disclosure.

[0028] [Figure 4] 1A-1C conceptually illustrate various metrics for quantifying a low frequency RF signal having a tilted rectangular waveform, according to an embodiment of the present disclosure.

[0029] [Figure 5] 10 is a graph conceptually illustrating etch rate versus radius for various waveforms on a blanket wafer, in accordance with an embodiment of the present disclosure.

[0030] [Figure 6A] 1A-1C conceptually illustrate bowing present in features etched with different waveforms, according to embodiments of the present disclosure. [Figure 6B] 1A-1C conceptually illustrate bowing present in features etched with different waveforms, according to embodiments of the present disclosure. [Figure 6C] 1A-1C conceptually illustrate bowing present in features etched with different waveforms, according to embodiments of the present disclosure.

[0031] [Figure 7] 1 is an exemplary electrical schematic diagram of an impedance matching system according to some embodiments.

[0032] [Figure 8] 3 is an exemplary schematic diagram of the control system of FIG. 2, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0033] In the following description, numerous specific details are set forth in order to provide an understanding of embodiments of the present disclosure. However, as will be apparent to one skilled in the art, embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0034] In plasma etching systems for semiconductor wafer fabrication, such as the system described herein, a semiconductor wafer is placed on an electrode from which a radio frequency signal radiates to generate a plasma in a plasma generating region above the semiconductor wafer, the plasma having controlled characteristics such that a defined etching process occurs on the semiconductor wafer. To achieve improved anisotropic etching of high aspect ratio features without unwanted bowing effects, high energy ions that are also highly directionally coherent are required. However, achieving such a narrow ion energy distribution at high energies is difficult because high voltages are used to generate such high energy ions, and to date, the industry has struggled to generate a narrow ion energy distribution that gives the high energy ions the ideal narrow angular distribution to ensure verticality of high aspect ratio etches.

[0035] FIG. 1 conceptually illustrates a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, according to an embodiment of the present disclosure. The plasma processing system 100 includes a chamber 101 in which plasma processing is performed on a substrate, such as, in some embodiments, a wafer W. An electrostatic chuck (ESC) 102 is disposed within the chamber 101 and configured to support the wafer W during processing. More specifically, the ESC 102 may include an electrode 109 (shown in FIG. 2 ), which receives high-frequency and low-frequency RF power, as described in further detail below, and which, in some embodiments, is formed of aluminum. A ceramic layer 110 (shown in FIG. 2 ) may be formed on an upper surface of the electrode 109, the ceramic layer 110 of the ESC 102 configured to receive and support the wafer W during plasma processing operations on the wafer W. As will be appreciated, in some embodiments, the ceramic layer 110, the electrode 109, and associated components within the chamber 101 define the electrostatic chuck (ESC) 102.

[0036] A first radio frequency (RF) signal generator 147 (or a high frequency RF generator, e.g., ∼60 MHz) is configured to provide high frequency RF power to the electrode 109 via an impedance matching system 143. A second radio frequency signal generator 149 (or a low frequency RF subsystem including multiple individual low frequency RF generators, e.g., ∼400 kHz) is configured to provide low frequency RF power to the electrode 109 via an impedance matching system 143. Application of the radio frequency power to gaseous species introduced into the process space above the wafer generates a plasma 180 for wafer processing, such as for etching.

[0037] In plasma processing for reactive ion etching (RIE), a key challenge is how to achieve high ion energy with a narrow ion energy distribution. Because high-energy ions accelerated in the same direction are less susceptible to scattering, a narrow distribution of high-energy ions is desirable because it results in a narrow angular distribution of ions. Therefore, a narrow high-energy ion source provides more directional ions to enable etching of high-aspect ratio features, since the ions are less likely to attack the sidewalls of the features and cause unwanted bowing within the features being etched.

[0038] In view of the above, it has been discovered that a ramped square waveform generated by the low-frequency RF subsystem 149 can provide a narrow distribution of energetic ions for etching. To approximate the ramped square waveform, according to embodiments of the present disclosure, the low-frequency RF subsystem 149 includes at least three separate low-frequency RF generators 151, 153, and 155, each generating an individual RF signal that, when combined, is configured to provide (at least approximately) the ramped square waveform. In some embodiments, one or more of the individual RF signals generated by each of the separate low-frequency RF generators 151, 153, and 155 are sinusoidal RF signals. Furthermore, in some embodiments, the RF signal generated by the first low-frequency RF generator 151 is generated at a fundamental frequency, and the RF signals generated by the second and third low-frequency RF generators 153 and 155 are harmonics of the fundamental frequency. In some embodiments, the phase of the individual RF signals is adjusted to adjust the slope of the ramped square waveform. For example, the phase of the harmonics is adjusted relative to the fundamental frequency so that the phase offset of each harmonic from the fundamental frequency is configured to provide a ramped rectangular waveform when the individual RF signals are combined. Additionally, the weights of the various waveforms are also adjusted to provide the desired final waveform shape.

[0039] As explained in more detail below, but without being limited by any particular theory of operation, it is believed that the slope of the ramped square waveform is configured to compensate for the charging of the ceramic of the ESC 102 (and any stray capacitance), thereby optimizing the ion energy distribution and ion angular distribution. The capacitance of the ESC 102 tends to lower the potential at the wafer relative to the potential applied to the RF signal supply rod 137 due to a "capacitor charging" effect resulting from the capacitance of the ESC 102. In other words, the potential from the applied RF reaching the wafer decreases over the course of a wave cycle due to the ESC capacitance. This causes the potential difference between the plasma and the wafer W to fluctuate over the course of a given RF cycle as the capacitor charging lowers the potential on the wafer. This results in a wider, more diffuse ion energy distribution with more intermediate energy ions, resulting in a wider angular distribution of ions, which is not suitable for etching high aspect ratio features.

[0040] FIG. 2 shows a vertical cross-section through a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments. The system 100 includes a chamber 101 formed by walls 101A, an upper member 101B, and a lower member 101C. The walls 101A, the upper member 101B, and the lower member 101C collectively form an interior region 103 within the chamber 101. The lower member 101C includes an exhaust port 105 through which exhaust gases from plasma processing operations are directed. In some embodiments, during operation, a suction force is applied to the exhaust port 105, such as by a turbo pump or other vacuum device, to draw process exhaust gases from the interior region 103 of the chamber 101. In some embodiments, the chamber 101 is formed of aluminum. However, in various embodiments, the chamber 101 can be formed of essentially any material that provides sufficient mechanical strength, acceptable thermal performance, and is chemically compatible with other materials that are in contact with and exposed to during plasma processing operations within the chamber 101, such as stainless steel, among others. At least one wall 101A of the chamber 101 includes a door 107 through which semiconductor wafers W are transferred in and out of the chamber 101. In some embodiments, the door 107 is configured as a slit valve door.

[0041] In some embodiments, a semiconductor wafer W is a semiconductor wafer undergoing a manufacturing procedure. For ease of explanation, the semiconductor wafer W will be referred to hereinafter as a wafer W. However, it should be understood that in various embodiments, a wafer W can be essentially any type of substrate undergoing a plasma-based manufacturing process. For example, in some embodiments, a wafer W referred to herein can be a substrate formed of silicon, sapphire, GaN, GaAs, or SiC, or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymeric materials, etc. Also, in various embodiments, a wafer W referred to herein can vary in form, shape, and / or size. For example, in some embodiments, a wafer W referred to herein can correspond to a circular semiconductor wafer on which integrated circuit devices are fabricated. In various embodiments, a circular wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or other sizes. Also, in some embodiments, a wafer W referred to herein can correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, etc., among other shapes.

[0042] The plasma processing system 100 includes an electrode 109 disposed on a facility plate 111. In some embodiments, the electrode 109 and facility plate 111 are formed of aluminum. However, in other embodiments, the electrode 109 and facility plate 111 may be formed of other electrically conductive materials that have sufficient mechanical strength and compatible thermal and chemical performance characteristics. A ceramic layer 110 is formed on the upper surface of the electrode 109. In some embodiments, the ceramic layer has a vertical thickness measured perpendicular to the upper surface of the electrode 109 of about 1.25 millimeters (mm). However, in other embodiments, the ceramic layer 110 may have a vertical thickness greater or less than 1.25 mm. The ceramic layer 110 is configured to receive and support a wafer W during plasma processing operations on the wafer W. In some embodiments, the upper surface of the electrode 190, which is located radially outward of the ceramic layer 110, and the peripheral side surface of the electrode 109 are coated with a ceramic spray coat.

[0043] The ceramic layer 110 includes an arrangement of one or more clamping electrodes 112 for generating an electrostatic force to hold the wafer W against the upper surface of the ceramic layer 110. In some embodiments, the ceramic layer 110 includes an arrangement of two clamping electrodes 112 operating bipolarly to apply a clamping force to the wafer W. The clamping electrodes 112 are connected to a direct current (DC) power supply 117 that generates a controlled clamping voltage to hold the wafer W against the upper surface of the ceramic layer 110. Electrical wires 119A, 119B are connected between the DC power supply 117 and the equipment plate 111. Electrical wires / conductors are routed through the equipment plate 111 and the electrode 109 to electrically connect the electrical wires 119A, 119B to the clamping electrodes 112. The DC power supply 117 is connected to a control system 120 through one or more signal conductors 121.

[0044] The electrode 109 also includes an arrangement of temperature control fluid channels 123 through which a temperature control fluid is flowed to control the temperature of the electrode 109 and, therefore, the temperature of the wafer W. The temperature control fluid channels 123 are plumbed (fluidly connected) to ports on the equipment plate 111. Temperature control fluid supply and return lines are connected to these ports on the equipment plate 111, as indicated by arrows 126, and to a temperature control fluid circulation system 125. The temperature control fluid circulation system 125 includes a temperature control fluid source, a temperature control fluid pump, and a heat exchanger, among other devices, to provide a controlled flow of temperature control fluid through the electrode 109 to obtain and maintain a defined wafer W temperature. The temperature control fluid circulation system 125 is connected to the control system 120 through one or more signal conductors 127. In various embodiments, various types of temperature control fluids, such as water or cooling liquids / gases, may be used. Also, in some embodiments, the temperature control fluid channels 123 are configured to allow spatially varying control of the temperature of the wafer W, such as in two dimensions (x and y) across the wafer W.

[0045] Ceramic layer 110 also includes an arrangement of backside gas supply ports (not shown) fluidly connected to corresponding backside gas supply channels in electrode 109. The backside gas supply channels in electrode 109 are routed through electrode 109 to the interface between electrode 109 and facility plate 111. One or more backside gas supply lines are connected to ports on facility plate 111, as indicated by arrow 130, and to a backside gas supply system 129. Facility plate 111 is configured to supply backside gas from the one or more backside gas supply lines to the backside gas supply channels in electrode 109. Backside gas supply system 129 includes, among other devices, a backside gas source, a mass flow controller, and a flow control valve to provide a controlled flow of backside gas through the arrangement of backside gas supply ports in ceramic layer 110. In some embodiments, backside gas supply system 129 also includes one or more components for controlling the temperature of the backside gas. In some embodiments, the backside gas is helium. Also, in some embodiments, a backside gas supply system 129 may be used to supply clean dry air (CDA) to a location of backside gas supply ports in the ceramic layer 110. The backside gas supply system 129 is connected to the control system 120 through one or more signal conductors 131.

[0046] Three lift pins 132 extend through the fixture plate 111, the electrode 109, and the ceramic layer 110 to provide for vertical movement of the wafer W relative to the upper surface of the ceramic layer 110. In some embodiments, the vertical movement of the lift pins 132 is controlled by respective electromechanical and / or pneumatic lift devices 133 connected to the fixture plate 111. The three lift devices 133 are connected to the control system 120 through one or more signal conductors 134. In some embodiments, the three lift pins 132 are positioned with substantially equal azimuthal spacing about a vertical centerline of the electrode 109 / ceramic layer 110 that extends perpendicular to the upper surface of the ceramic layer 110. It should be understood that the lift pins 132 are raised to accept and remove a wafer W from the chamber 101. The lift pins 132 are also lowered to allow the wafer W to rest on the upper surface of the ceramic layer 110 during processing of the wafer W.

[0047] Also, in various embodiments, one or more of the electrode 109, facility plate 111, ceramic layer 110, clamp electrode 112, lift pins 132, or essentially any other components associated therewith, may be equipped to include one or more sensors, such as sensors for temperature, voltage, and current measurements, among others. Any sensors disposed within the electrode 109, facility plate 111, ceramic layer 110, clamp electrode 112, lift pins 132, or essentially any other components associated therewith, are connected to the control system 120 via electrical wires, optical fibers, or through a wireless connection.

[0048] Facility plate 111 is seated within an opening in, and supported by, ceramic support 113. Ceramic support 113 is positioned on support surface 114 of cantilever arm assembly 115. In some embodiments, ceramic support 113 has a substantially annular shape such that ceramic support 113 substantially circumscribes the radial periphery of facility plate 111 while also providing support surface 116 on which a bottom peripheral surface of facility plate 111 rests. Cantilever arm assembly 115 extends through wall 101A of chamber 101. In some embodiments, a sealing mechanism 135 is provided within wall 101A of chamber 101, where cantilever arm assembly 115 is positioned to provide for sealing interior region 103 of chamber 101 while also allowing cantilever arm assembly 115 to move up and down in the z-direction in a controlled manner.

[0049] The cantilever arm assembly 115 has an open area 118 through which various devices, wires, cables, and tubing are routed to support the operation of the system 100. The open area 118 within the cantilever arm assembly is exposed to ambient atmospheric conditions outside the chamber 101, such as air composition, temperature, pressure, and relative humidity. Also, a radio frequency signal feed rod 137 is disposed inside the cantilever arm assembly 115. More specifically, the radio frequency signal feed rod 137 is disposed inside a conductive tube 139 such that the radio frequency signal feed rod 137 is spaced from the inner wall of the tube 139. The sizes of the radio frequency signal feed rod 137 and the tube 139 can vary. The area inside the tube 139 between the inner wall of the tube 139 and the radio frequency signal feed rod 137 is occupied by air along the entire length of the tube 139. In some embodiments, the outer diameter (D rod ) and the inner diameter of the pipe 139 (D tube ) is related to the relation ln(D tube / D rod )≧e 1 is set to satisfy

[0050] In some embodiments, the radio frequency signal feed rod 137 is substantially centered within the tube 139 such that a substantially uniform radial thickness of air exists between the radio frequency signal feed rod 137 and the inner wall of the tube 139 along the length of the tube 139. However, in some embodiments, the radio frequency signal feed rod 137 is not centered within the tube 139, but an air gap exists within the tube 139 between the radio frequency signal feed rod 137 and the inner wall of the tube 139 at all locations along the length of the tube 139. The delivery end of the radio frequency signal feed rod 137 is electrically and physically connected to the lower end of the radio frequency signal feed shaft 141. In some embodiments, the delivery end of the radio frequency signal feed rod 137 is bolted to the lower end of the radio frequency signal feed shaft 141. The upper end of the radio frequency signal feed shaft 141 is electrically and physically connected to the bottom of the equipment plate 111. In some embodiments, the upper end of the radio frequency signal feed shaft 141 is bolted to the bottom of the equipment plate 111. In some embodiments, radio frequency signal feed rod 137 and radio frequency signal feed shaft 141 are both formed of copper. In some embodiments, radio frequency signal feed rod 137 is formed of copper, aluminum, or anodized aluminum. In some embodiments, radio frequency signal feed shaft 141 is formed of copper, aluminum, or anodized aluminum. In other embodiments, radio frequency signal feed rod 137 and / or radio frequency signal feed shaft 141 are formed of other conductive materials that provide for the transmission of radio frequency electrical signals. In some embodiments, radio frequency signal feed rod 137 and / or radio frequency signal feed shaft 141 are coated with a conductive material (such as silver or other conductive material) that provides for the transmission of radio frequency electrical signals. Also, in some embodiments, radio frequency signal feed rod 137 is a solid rod. However, in other embodiments, radio frequency signal feed rod 137 is a tube. It should also be understood that area 140 surrounding the connection between radio frequency signal feed rod 137 and radio frequency signal feed shaft 141 is occupied by air.

[0051] The feed end of the radio frequency signal feed rod 137 is electrically and physically connected to an impedance matching system 143. The impedance matching system 143 is connected to a first radio frequency signal generator 147 and a low frequency RF subsystem 149. The impedance matching system 143 is also connected to the control system 120 through one or more signal conductors 144. The first radio frequency signal generator 147 is also connected to the control system 120 through one or more signal conductors 148. The low frequency RF subsystem 149 is also connected to the control system 120 through one or more signal conductors 150. The impedance matching system 143 includes an arrangement of inductors and capacitors sized and connected to provide impedance matching so that radio frequency power can be transmitted along the radio frequency signal feed rod 137, along the radio frequency signal feed shaft 141, through the equipment plate 111, through the electrode 109, and into the plasma processing region 182 above the ceramic layer 110. In some embodiments, first radio frequency signal generator 147 is a high-frequency radio frequency signal generator, and low-frequency RF subsystem 149 is a low-frequency radio frequency signal generator. In some implementations, low-frequency RF subsystem 149 can include three or more individual signal generators, whose signals / waveforms are combined to generate the low-frequency RF signal generated by low-frequency RF subsystem 149 according to the principles described herein. In some embodiments, first radio frequency signal generator 147 generates a radio frequency signal in a range ranging from about 50 megahertz (MHz) to about 70 MHz, or in a range ranging from about 54 MHz to about 63 MHz, or at about 60 MHz. In some embodiments, first radio frequency signal generator 147 provides radio frequency power in a range ranging from about 5 kilowatts (kW) to about 25 kW, or in a range ranging from about 10 kW to about 20 kW, or in a range ranging from about 15 kW to about 20 kW, or about 10 kW, or about 16 kW.In some embodiments, low-frequency RF subsystem 149 generates radio frequency signals in a range ranging from about 50 kilohertz (kHz) to about 500 kHz, or in a range ranging from about 330 kHz to about 440 kHz, or at about 400 kHz. In some embodiments, low-frequency RF subsystem 149 provides radio frequency power in a range ranging from about 15 kW to about 100 kW, or in a range ranging from about 30 kW to about 50 kW, or about 34 kW, or about 50 kW. In one exemplary embodiment, first radio frequency signal generator 147 is configured to generate a radio frequency signal having a frequency of about 60 MHz, and low-frequency RF subsystem 149 is configured to generate a radio frequency signal having a frequency of about 400 kHz.

[0052] A coupling ring 161 is configured and arranged to extend around the radial outer periphery of the electrode 109. In some embodiments, the coupling ring 161 is formed of a ceramic material. A quartz ring 163 is configured and arranged to extend around the radial outer periphery of both the coupling ring 161 and the ceramic support 113. In some embodiments, the coupling ring 161 and the quartz ring 163 are configured to have substantially aligned upper surfaces when the quartz ring 163 is disposed around both the coupling ring 161 and the ceramic support 113. In some embodiments, the substantially aligned upper surfaces of the coupling ring 161 and the quartz ring 163 are substantially aligned with the upper surface of the electrode 109, and the upper surface is outside the radial periphery of the ceramic layer 110. In some embodiments, the cover ring 165 is configured and arranged to extend around the radial outer periphery of the upper surface of the quartz ring 163. In some embodiments, the cover ring 165 is formed of quartz. In some embodiments, the cover ring 165 is configured to extend vertically above the upper surface of the quartz ring 163. In this way, the cover ring 165 provides a peripheral boundary within which the edge ring 167 is disposed.

[0053] The edge ring 167 is configured to facilitate extension of the plasma sheath radially outward beyond the peripheral edge of the wafer W to improve process results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed of a conductive material such as crystalline silicon, polycrystalline silicon (polysilicon), boron-doped single crystal silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide, or a silicon carbide layer on an aluminum oxide layer, or an alloy of silicon, or a combination thereof, among other materials. It should be understood that the edge ring 167 is formed as an annular structure, e.g., a ring-like structure. The edge ring 167 can perform many functions, including shielding components below the edge ring 167 from being damaged by ions of the plasma 180 formed in the plasma processing region 182. The edge ring 167 also improves the uniformity of the plasma 180 at and along the outer periphery of the wafer W.

[0054] A fixed outer support flange 169 is attached to the cantilever arm assembly 115. The fixed outer support flange 169 is configured to extend around the outer vertical side of the ceramic support 113, around the outer vertical side of the quartz ring 163, and around the lower outer vertical side of the cover ring 165. The fixed outer support flange 169 has a circular ring shape that circumscribes the assembly of the ceramic support 113, the quartz ring 163, and the cover ring 165. The fixed outer support flange 169 has an L-shaped vertical cross section including a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross section of the fixed outer support flange 169 has an inner vertical surface that is positioned relative to the outer vertical side of the ceramic support 113, the outer vertical side of the quartz ring 163, and the lower outer vertical side of the cover ring 165. In some embodiments, the vertical portion of the L-shaped cross section of the fixed outer support flange 169 extends over the entire outer vertical side surface of the ceramic support 113, the entire outer vertical side surface of the quartz ring 163, and the entire lower outer vertical side surface of the cover ring 165. In some embodiments, the cover ring 165 extends radially outward above the upper surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169. Also, in some embodiments, the upper outer vertical side surface of the cover ring 165 (located above the upper surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169) is substantially vertically aligned with the outer vertical surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169. The horizontal portion of the L-shaped cross section of the fixed outer support flange 169 is positioned on and fixed to the support surface 114 of the cantilever arm assembly 115. The fixed outer support flange 169 is formed of a conductive material. In some embodiments, the fixed outer support flange 169 is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 may be formed of other conductive materials, such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross section of the fixed outer support flange 169 is bolted to the support surface 114 of the cantilever arm assembly 115.

[0055] The articulating outer support flange 171 is configured and arranged to extend around the outer vertical surface 169D of the vertical portion of the L-shaped cross section of the fixed outer support flange 169 and around the upper outer vertical side surface of the covering ring 165. The articulating outer support flange 171 has a circular ring shape that circumscribes both the vertical portion of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering ring 165. The articulating outer support flange 171 has an L-shaped vertical cross section including a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross section of the articulating outer support flange 171 has an inner vertical surface that is adjacent to and spaced apart from both the outer vertical side surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering ring 165. In this manner, the articulating outer support flange 171 is movable vertically (in the z-direction) along both the vertical portion of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering ring 165. The articulating outer support flange 171 is formed of an electrically conductive material. In some embodiments, the articulating outer support flange 171 is formed of aluminum or anodized aluminum. However, in other embodiments, the articulating outer support flange 171 may be formed of other electrically conductive materials, such as copper or stainless steel.

[0056] A number of conductive straps 173 are connected between the articulating outer support flange 171 and the fixed outer support flange 169 around the radial circumference of both the articulating outer support flange 171 and the fixed outer support flange 169. In the exemplary embodiment, the conductive straps 173 are shown as having an "outward" configuration, in that the conductive straps 173 curve outward, away from the fixed outer support flange 169. In some embodiments, the conductive straps 173 are formed from stainless steel. However, in other embodiments, the conductive straps 173 may be formed from other conductive materials, such as aluminum or copper, among others.

[0057] In some embodiments, several conductive straps 173 are distributed substantially equally spaced around the radial circumference of the articulating outer support flange 171 and the fixed outer support flange 169. However, it should be understood that the number of conductive straps 173 may vary in different embodiments. In some embodiments, the number of conductive straps 173 is within a range ranging from about 24 to about 80, or from about 36 to about 60, or from about 40 to about 56. In some embodiments, the number of conductive straps 173 is fewer than 24. In some embodiments, the number of conductive straps 173 is greater than 80. The number of conductive straps 173 may have an effect on the ground return path for radio frequency signals around the periphery of the plasma processing region 182 and therefore on the uniformity of process results across the wafer W. Also, the size of the conductive straps 173 may vary in different embodiments.

[0058] In some embodiments, the conductive straps 173 are connected to the fixed outer support flange 169 by a clamping force applied by fastening a clamp ring 175 to the top surface of the horizontal portion of the L-shaped cross section of the fixed outer support flange 169. In some embodiments, the clamp ring 175 is bolted to the fixed outer support flange 169. In some embodiments, the bolts securing the clamp ring 175 to the fixed outer support flange 169 are positioned between the conductive straps 173. However, in some embodiments, one or more bolts securing the clamp ring 175 to the fixed outer support flange 169 may be positioned to extend through the conductive straps 173. In some embodiments, the clamp ring 175 is formed of the same material as the fixed outer support flange 169. However, in other embodiments, the clamp ring 175 and the fixed outer support flange 169 may be formed of different materials.

[0059] In some embodiments, the conductive straps 173 are connected to the articulating outer support flange 171 by a clamping force applied by securing a clamp ring 177 to the bottom surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171. Alternatively, in some embodiments, a first end of each of the plurality of conductive straps 173 is connected to the top surface of the horizontal portion of the articulating outer support flange 171 by the clamp ring 177. In some embodiments, the clamp ring 177 is bolted to the articulating outer support flange 171. In some embodiments, the bolts securing the clamp ring 177 to the articulating outer support flange 171 are located between the conductive straps 173. However, in some embodiments, one or more bolts securing the clamp ring 177 to the articulating outer support flange 171 may be located to extend through the conductive straps 173. In some embodiments, the clamp ring 177 is formed of the same material as the articulating outer support flange 171. However, in other embodiments, the clamp ring 177 and the articulating outer support flange 171 may be formed of different materials.

[0060] A set of support rods 201 are disposed around the cantilever arm assembly 115 so as to extend vertically through the horizontal portion 169B of the L-shaped cross section of the fixed outer support flange 169. The upper ends of the support rods 201 are configured to engage with the bottom surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171. In some embodiments, the lower end of each of the support rods 201 engages with a resistance mechanism 203. The resistance mechanism 203 is configured to apply an upward force to the corresponding support rod 201 that resists downward movement of the support rod 201 while allowing some downward movement of the support rod 201. In some embodiments, the resistance mechanism 203 includes a spring for applying the upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material, e.g., a spring and / or rubber, having a sufficient spring constant to apply an upward force to the corresponding support rod 201. It should be understood that as the articulating outer support flange 171 moves downward into engagement with the set of support rods 201, the set of support rods 201 and corresponding resistance mechanisms 203 exert an upward force on the articulating outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and corresponding resistance mechanisms 203. In some embodiments, the support rods 201 are arranged at substantially equal azimuthal intervals relative to the vertical centerline of the electrode 109. However, in other embodiments, the support rods 201 are arranged at unequal azimuthal intervals relative to the vertical centerline of the electrode 109. Also, in some embodiments, more than three support rods 201 and corresponding resistance mechanisms 203 are provided to support the articulating outer support flange 171.

[0061] Continuing to refer to FIG. 2 , plasma processing system 100 further includes a C-shroud member 185 disposed above electrode 109. C-shroud member 185 is configured to contact articulating outer support flange 171. Specifically, seal 179 is disposed on an upper surface of the horizontal portion of the L-shaped cross section of articulating outer support flange 171 such that seal 179 engages C-shroud member 185 when articulating outer support flange 171 is moved upward toward C-shroud member 185. In some embodiments, seal 179 is electrically conductive to help establish electrical conduction between C-shroud member 185 and articulating outer support flange 171. In some embodiments, C-shroud member 185 is formed of polysilicon. However, in other embodiments, C-shroud member 185 is formed of other types of electrically conductive materials that are chemically compatible with processes performed in plasma processing region 182 and have sufficient mechanical strength.

[0062] The C-shroud is configured to extend around the plasma processing region 182 and provide radial extension of the plasma processing region 182 volume into a region defined within the C-shroud member 185. The C-shroud member 185 includes a lower wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C-shroud member 185 are solid, imperforate members, and the lower wall 185A of the C-shroud member 185 includes a number of vent holes 186 through which process gases from within the plasma processing region 182 flow. In some embodiments, a throttle member 196 is disposed below the vent holes 186 of the C-shroud member 185 to control the flow of process gases through the vent holes 186. More specifically, in some embodiments, the throttle member 196 is configured to move up and down perpendicular to the z-direction relative to the C-shroud member 185 to control the flow of process gas through the vent 186. In some embodiments, the throttle member 196 is configured to engage and / or enter the vent 186.

[0063] The upper wall 185C of the C shroud member 185 is configured to support the upper electrodes 187A / 187B. In some embodiments, the upper electrodes 187A / 187B include an inner upper electrode 187A and an outer upper electrode 187B. Alternatively, in some embodiments, the inner upper electrode 187A is present and the outer upper electrode 187B is absent, with the inner upper electrode 187A extending radially to cover the position that would otherwise be occupied by the outer upper electrode 187B. In some embodiments, the inner upper electrode 187A is formed of single-crystal silicon and the outer upper electrode 187B is formed of polysilicon. However, in other embodiments, the inner upper electrode 187A and the outer upper electrode 187B may be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the processes performed in the plasma processing region 182. The inner upper electrode 187A includes several through-ports 197, defined as holes extending through the entire vertical thickness of the inner upper electrode 187A. Through ports 197 are distributed throughout the inner upper electrode 187A relative to the xy plane to provide for the flow of process gases from the plenum region 188 above the upper electrodes 187A / 187B to the plasma processing region 182 below the upper electrodes 187A / 187B.

[0064] It should be understood that the distribution of the through ports 197 throughout the inner upper electrode 187A may be configured differently for different embodiments. For example, the total number of through ports 197 in the inner upper electrode 187A and / or the spatial distribution of the through ports 197 within the inner upper electrode 187A may vary between different embodiments. Also, the diameter of the through ports 197 may vary between different embodiments. In general, it is important to reduce the diameter of the through ports 197 to a size small enough to prevent intrusion of the plasma 180 from the plasma processing region 182 into the through ports 197. In some embodiments, as the diameter of the through ports 197 decreases, the total number of through ports 197 within the inner upper electrode 187A increases in order to maintain a defined overall flow rate of process gas from the process gas plenum region 188 through the inner upper electrode 187A to the plasma processing region 182. Also, in some embodiments, the upper electrodes 187A / 187B are electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode 187A and / or the outer upper electrode 187B are electrically connected to either a respective direct current (DC) power source or a respective radio frequency power source via a corresponding impedance matching system.

[0065] A plenum region 188 is defined by a top member 189. One or more gas supply ports 192 are formed through the chamber 101 and the top member 189 to fluidly communicate with the plenum region 188. The one or more gas supply ports 192 are fluidly connected (plumbed) to a process gas supply system 191. The process gas supply system 191 includes one or more process gas sources, one or more mass flow controllers, one or more flow control valves, among other devices, to provide a controlled flow of one or more process gases through the one or more gas supply ports 192 to the plenum region 188, as indicated by arrows 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling the temperature of the process gases. The process gas supply system 191 is connected to the control system 120 through one or more signal conductors 194.

[0066] The process gap (g1) is defined as the vertical (z-direction) distance measured between the top surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the process gap (g1) can be adjusted by moving the cantilever arm assembly 115 vertically (z-direction). As the cantilever arm assembly 115 moves upward, the articulating outer support flange 171 eventually engages the lower wall 185A of the C-shroud member 185, at which point the articulating outer support flange 171 moves along the fixed outer support flange 169, at which point the cantilever arm assembly 115 continues moving upward until a set of support rods 201 engages the articulating outer support flange 171 and the defined process gap (g1) size is achieved. To subsequently reverse this movement to remove the wafer W from the chamber, the cantilever arm assembly 115 is moved downward until the articulating outer support flange 171 clears the lower wall 185A of the C-shroud member 185. In various embodiments, the size of the processing gap (g1) during plasma processing of the wafer W is controlled to within a range of about 10 centimeters or less, or within a range of about 8 centimeters or less, or within a range of about 5 centimeters or less. It should be understood that Figure 2 shows the system 100 in a closed configuration, with the wafer W positioned on the ceramic layer 110 for plasma processing.

[0067] During plasma processing operations in the plasma processing system 100, one or more process gases are supplied to the plasma processing region 182 via the process gas supply system 191, the plenum region 188, and the through-ports 197 in the inner upper electrode 187A. Additionally, a radio frequency signal is transmitted through the first and second radio frequency signal generators 147, 149, the impedance matching system 143, the radio frequency signal supply rod 137, the radio frequency signal supply shaft 141, the fixture plate 111, the electrode 109, through the ceramic layer 110, and into the plasma processing region 182. The radio frequency signal converts the process gases into a plasma 180 in the plasma processing region 182. Ions and / or reactive constituents of the plasma interact with one or more materials on the wafer W, causing changes in the composition and / or shape of certain materials present on the wafer W. Exhaust gases from the plasma processing region 182 flow through vent holes 186 in the C-shroud member 185, through the interior region 103 in the chamber 101, and to the exhaust port 105 under the influence of a suction force applied to the exhaust port 105, as shown by arrows 195.

[0068] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, the diameter of the electrode 109 is enlarged to increase the surface of the electrode 109 upon which the edge ring 167 rests. In some embodiments, a conductive gel 226 is disposed between the bottom of the edge ring 167 and the top of the electrode 109 and / or between the bottom of the edge ring 167 and the top of the coupling ring 161. In these embodiments, the increased diameter of the electrode 109 provides a larger surface area over which the conductive gel is disposed between the edge ring 167 and the electrode 109.

[0069] It should be understood that the combination of the articulating outer support flange 171, the conductive straps 173, and the fixed outer support flange 169 are electrically at a reference ground potential and collectively form a ground return path for radio frequency signals transmitted from the electrode 109 through the ceramic layer 110 and into the plasma processing region 182. The azimuthal uniformity of this ground return path around the periphery of the electrode 109 can have an effect on the uniformity of process results on the wafer W. For example, in some embodiments, the uniformity of the etch rate across the wafer W can be affected by the azimuthal uniformity of the ground return path around the periphery of the electrode 109. To this end, it should be understood that the number, configuration, and placement of the conductive straps 173 around the periphery of the electrode 109 can affect the uniformity of process results across the wafer W.

[0070] Referring again to FIG. 2 , an adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within the coupling ring 161. The TES system also includes several TES radio frequency signal supply pins 413 physically and electrically connected to the TES electrode 415. Each TES radio frequency signal supply pin 413 extends through a corresponding insulator feedthrough member 421 configured to electrically isolate the TES radio frequency signal supply pin 413 from surrounding structures, such as from the ceramic support 113 and cantilever arm assembly 115 structure. In some embodiments, O-rings 417 and 419 are disposed to ensure that the area inside the insulator feedthrough member 421 is not exposed to any materials / gases present within the plasma processing region 182. In some embodiments, the TES radio frequency signal supply pins 413 are formed of copper, aluminum, or anodized aluminum, among others.

[0071] The TES radio frequency signal supply pins 413 extend into the open region 118 inside the cantilever arm assembly 115, where each of the TES radio frequency signal supply pins 413 is electrically connected to the TES radio frequency signal supply conductor 409 through a corresponding TES radio frequency signal filter 411. In some embodiments, three TES radio frequency signal supply pins 413 are positioned to physically and electrically connect to the TES electrodes 415 at substantially equally spaced azimuthal positions about the centerline of the electrode 109. However, it should be understood that other embodiments may have more than three TES radio frequency signal supply pins 413 physically and electrically connect to the TES electrodes 415. Also, some embodiments may have either one or two TES radio frequency signal supply pins 413 physically and electrically connect to the TES electrodes 415. Each TES radio frequency signal supply pin 413 is electrically connected to a corresponding TES radio frequency signal filter 411, which is electrically connected to the TES radio frequency signal supply conductor 409. In some embodiments, each TES radio frequency signal filter 411 is configured as an inductor. For example, in some embodiments, each TES radio frequency signal filter 411 is configured as a wound conductor, such as a metal coil wrapped around a dielectric core structure. In various embodiments, the metal coil may be formed of a solid copper rod, copper tube, aluminum rod, or aluminum tube, among others. Also, in some embodiments, each TES radio frequency signal filter 411 may be configured as a combination of inductive and capacitive structures. To improve plasma processing result uniformity across the wafer W, each of the TES radio frequency signal filters 411 has substantially the same configuration.

[0072] In some embodiments, the TES radio frequency signal feed conductor 409 is formed as a ring-like (annular) structure extending around the inner open region 118 of the cantilever arm assembly 115 to enable physical and electrical connection between the azimuthally distributed TES radio frequency signal filters 411 and the TES radio frequency signal feed conductor 409. In some embodiments, the TES radio frequency signal feed conductor 409 is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES radio frequency signal feed conductor 409 is formed as a tubular structure. In some embodiments, the TES radio frequency signal feed conductor 409 is formed of copper, aluminum, or anodized aluminum, among others.

[0073] The TES radio frequency signal feed conductor 409 is electrically connected to the TES radio frequency feed cable 407. Additionally, a capacitor 408 is connected between the TES radio frequency signal feed conductor 409 and a reference ground potential, such as the structure of the cantilever arm assembly 115. More specifically, the capacitor 408 has a first terminal electrically connected to both the TES radio frequency feed cable 407 and the TES radio frequency signal feed conductor 409, and the capacitor 408 has a second terminal electrically connected to the reference ground potential. In some embodiments, the capacitor 408 is a variable capacitor. In some embodiments, the capacitor 408 is a fixed capacitor. In some embodiments, the capacitor 408 is configured to have a capacitance within a range ranging from approximately 10 picofarads to approximately 100 picofarads. The TES radio frequency feed cable 407 is connected to the TES impedance matching system 401. The TES impedance matching system 401 is connected to the TES radio frequency signal generator 403. The radio frequency signal generated by the TES radio frequency signal generator 403 is transmitted through the TES impedance matching system 401 to the TES radio frequency feed cable 407, then to the TES radio frequency signal feed conductors 409, and then through the TES radio frequency signal filters 411 to respective TES radio frequency signal feed pins 413 and to the TES electrodes 415 in the coupling ring 161. In some embodiments, the TES radio frequency signal generator 403 is configured and operative to generate a radio frequency signal within a frequency range ranging from about 50 kilohertz to about 27 MHz. In some embodiments, the TES radio frequency signal generator 403 provides a radio frequency power within a range ranging from about 50 watts to about 10 kilowatts. The TES radio frequency signal generator 403 is also connected to the control system 120 through one or more signal conductors 405.

[0074] The TES impedance matching system 401 includes an arrangement of inductors and capacitors sized and connected to provide impedance matching so that radio frequency power can be transmitted from the TES radio frequency signal generator 403, along the TES radio frequency supply cable 407, along the TES radio frequency signal supply conductors 409, through the TES radio frequency signal filter 411, through respective TES radio frequency signal supply pins 413, to the TES electrode 415 in the coupling ring 161 and into the plasma processing region 182 above the edge ring 167.

[0075] By transmitting radio frequency signals / power through the TES electrodes 415 disposed (embedded) in the coupling ring 161, the TES system can control the properties of the plasma 180 near the peripheral edge of the wafer W. For example, in some embodiments, the TES system operates to control the properties of the plasma 180 sheath near the edge ring 167, such as by controlling the shape and / or size of the plasma 180 sheath (either increasing the sheath thickness or decreasing the sheath thickness). Also, in some embodiments, controlling the shape of the plasma 180 sheath near the edge ring 167 can control various properties of the bulk plasma 180 above the wafer W. Also, in some embodiments, the TES system operates to control the density of the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system operates to either increase or decrease the density of the plasma 180 near the edge ring 167. Additionally, in some embodiments, the TES system operates to control a bias voltage present on the edge ring 167, which in turn controls / affects the movement of ions and other charged constituents in the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system operates to control a bias voltage present on the edge ring 167 to attract more ions from the plasma 180 toward the edge of the wafer W. Additionally, in some embodiments, the TES system operates to control a bias voltage present on the edge ring 167 to repel ions from the plasma 180 away from the edge of the wafer W. It should be understood that the TES system may operate to perform a variety of different functions, either separately or in combination, as described above, among others.

[0076] In some embodiments, the coupling ring 161 is formed of a dielectric material such as quartz, or ceramic, or alumina (Al 2 O 3 ), or a polymer, among others.

[0077] The bottom surface of the edge ring 167 has a portion bonded to the top surface of the coupling ring 161 through a layer of thermally and electrically conductive gel to dissipate heat from the coupling ring 161 to the edge ring 167. The bottom surface of the edge ring 167 also has another portion bonded to the top surface of the electrode 109 through a layer of thermally and electrically conductive gel. Examples of thermally and electrically conductive gels include polyimide, polyketone, polyetherketone, polyethersulfone, polyethylene terephthalate, fluoroethylene propylene copolymer, cellulose, triacetate, and silicone, among others. In some embodiments, an example of the thermally and electrically conductive gel is formed as double-sided tape. In some embodiments, the edge ring 167 has an inner diameter sized closely to the outer diameter of the ceramic layer 110.

[0078] In various embodiments, the TES electrode 415 is formed of a conductive material such as platinum, steel, aluminum, or copper, among others. During operation, capacitive coupling occurs between the TES electrode 415 and the edge ring 167, causing the edge ring 167 to be powered to affect processing of the wafer W near the periphery of the wafer W.

[0079] FIG. 3 conceptually illustrates various low-frequency RF waveforms approximating a tilted square waveform, according to embodiments of the present disclosure. In some embodiments, multiple low-frequency RF signals (e.g., at least three RF signals) are combined to at least approximately generate a tilted square waveform. The following description of the illustrated embodiments is provided by way of example and not limitation to illustrate the principles of the present disclosure. A tilted square waveform is understood to be a square wave in which the peaks and valleys (or tops and bottoms, respectively) exhibit some non-zero slope, rather than having a zero slope as in an ideal square wave. In some embodiments, for a given tilted square wave provided in accordance with the principles of the present disclosure, the peaks of the tilted square wave exhibit a positive / rising slope, while the valleys / bottoms of the tilted square wave exhibit a negative / falling slope.

[0080] In the illustrated embodiment, three harmonics are combined to approximate a ramped square waveform. The three harmonics include a fundamental frequency (first harmonic), a third harmonic frequency, and a fifth harmonic frequency. In the illustrated embodiment, the power ratio of the first to third to fifth harmonics is approximately 0.8:0.15:0.05. However, in other embodiments, the power ratio may be different. In some embodiments, the fundamental frequency is at 400 kHz, resulting in the third harmonic having a frequency of 1.2 MHz and the fifth harmonic having a frequency of 2 MHz. However, in other embodiments, the frequencies may be different.

[0081] A pure sinusoidal waveform is exemplified by signal 431, which can be represented by the following equation:

[0082] Y=sin(φ)

[0083] A square wave is approximated by the sum of the third and fifth harmonics exemplified by signal 433, which is given by:

[0084] Y=A×sin(φ)+B×sin(3×φ)+C×(5φ)

[0085] where A, B, and C are weights (fractional power ratios) of the fundamental frequency, the third harmonic, and the fifth harmonic, whose sum is 1 (A+B+C=1). For example, in some implementations, A=0.8, B=0.15, and C=0.05 (approximately).

[0086] To achieve a ramped square waveform, the phase of the harmonics is adjusted relative to the fundamental frequency. Thus, a ramped square waveform is generated by adjusting the phase of the harmonics, which is represented by an equation of the form:

[0087] Y=A×sin(φ)+B×sin(3×φ-(360-3Δφ))+C×(5φ-(360-5Δφ))

[0088] where Δφ is the phase adjustment (or phase change) in degrees.

[0089] Various examples of waveforms produced using different values ​​for Δφ are shown in the illustrated embodiment. As can be seen, as Δφ increases, the amount of slope of the resulting waveform also increases, and the waveform changes from an approximately square wave at Δφ=0 to a square wave of increasing slope as Δφ increases. In the illustrated embodiment, signals 435, 437, 439, 441, 443, and 445 illustrate the resulting waveforms when Δφ=6, 9, 12, 15, 20, and 30 degrees, respectively, and when A=0.8, B=0.15, and C=0.05 (approximately).

[0090] It will be understood that, while specific values ​​are described, such values ​​are provided by way of example, without limitation, to illustrate the principles of the present disclosure. For example, in some embodiments, the phase adjustment Δφ is in the range of approximately 3 to 15 degrees, in some embodiments, in the range of approximately 6 to 12 degrees, and in some embodiments, in the range of approximately 8 to 10 degrees. In some embodiments, weight A is in the range of approximately 0.7 to 0.9, weight B is in the range of approximately 0.1 to 0.2, and weight C is in the range of approximately 0.02 to 0.1.

[0091] In the above embodiment, three harmonics are combined to form the low-frequency RF signal. However, in other embodiments, more than three harmonics can be combined to form the low-frequency RF signal. Generally, the more harmonics there are, the better the approximation of the rectangular and ramped-rectangular waveforms can be achieved. Furthermore, by mixing odd harmonics, the resulting waveform has symmetrical positive and negative halves, while mixing odd and even harmonics can change the distribution of the positive and negative halves of the waveform. For example, in some embodiments, even and odd harmonics are mixed to provide a waveform in which the negative half of the waveform is stretched while the positive portion of the waveform is shortened.

[0092] 4 conceptually illustrates various metrics for quantifying a low-frequency RF signal having a ramped rectangular waveform, according to an embodiment of the present disclosure. In the illustrated embodiment, a low-frequency RF signal 451 having a ramped rectangular waveform is shown. The ramped rectangular waveform of the low-frequency RF signal 451 is achieved according to the above-described embodiments, more specifically, by combining sinusoidal harmonics to generate the desired waveform.

[0093] The total peak-to-peak voltage drop of the signal during one period is V pk-pk However, (Δt b The bottom of the waveform (during the period) is considered to compensate for the charging of the capacitance of the ESC, so that the maximum ion energy is then approximately determined by the voltage drop from the initial upper peak to the first middle peak, which is the voltage drop V drop (As will be appreciated, for pure (ideal) sine waves and rectangular (non-ramp) waveforms, V pk-pk =V drop , and there is no separate bottom slope.)

[0094] The amount of intermediate ion energy produced is determined primarily by how much voltage is provided between the initial upper peak and the first intermediate peak, which is V drop In other words, an approximate metric for the amount of intermediate ion energy is V drop / Δt s The slope of the initial voltage drop is expressed as drop / Δt s A steeper slope produces fewer intermediate ion energies, while a shallower slope produces more intermediate ion energies.

[0095] The bottom of the signal exhibits a slope that is believed to compensate for the charging of the ESC capacitance and therefore the voltage drop V bottom Therefore, the slope of the bottom V bottom / Δt b indicates the degree of charge compensation produced by the waveform.

[0096] As explained, but without being limited by a particular theory of operation, a flat / constant potential applied to the RF signal will exhibit a decrease over time as measured at the wafer due to charging of the ESC capacitance. Thus, for example, the flat bottom of a square wave applied to the RF signal supply rod 137 will produce a decreasing potential at the wafer because the potential of the RF signal reaching the wafer will decrease over the course of the RF period due to charging of the ESC capacitance. To compensate for this effect, the slope of the bottom of the RF signal 451 will increase the potential applied to the RF signal supply rod 137 over time Δt b By configuring the slope of the bottom of the RF signal to increase over this period, the resulting potential at the wafer remains approximately constant during this portion of the RF signal period. When the slope of the bottom of the RF signal is optimally adjusted to provide such a constant potential at the wafer surface, the ion energy distribution function is better optimized to provide a narrow distribution at high ion energies because ions are accelerated by a sustained, substantially constant potential difference between the wafer surface and the plasma.

[0097] Thus, the sloped rectangular shape of the waveform is believed to compensate for the "charging capacitor" effect, thereby providing a flat potential on the wafer that allows for an optimized ion energy distribution function (IEDF), e.g., a potential with primarily two fundamental peaks, one high and one low, with substantially no intermediate energies. An optimized IEDF also results in a much tighter angular distribution function because, since high-energy ions are less susceptible to scattering, most ions are pushed to high energies instead of intermediate ion energies, and the angular distribution function becomes narrower at higher ion energies. A narrow ion energy distribution function results in ions that are more directional, hitting more of the bottom of the feature being etched and fewer ions hitting the sidewalls during etching. Therefore, optimizing the IEDF can improve the verticality of etching of high aspect ratio features by achieving a more focused angular distribution function and further achieving a more directional etch.

[0098] According to the above, harmonics can be added to change the basic low frequency RF waveform from a sine wave to a rectangular shape, and then the addition of a phase change can be performed to change the waveform from a rectangular shape to a tilted rectangular shape.

[0099] 5 is a graph conceptually illustrating etch rate versus radius for various waveforms on a blanket wafer, according to an embodiment of the present disclosure. Curve 501 shows the etch rate for a simple sinusoidal waveform, while curve 503 shows the etch rate for a square waveform. As shown, the sinusoidal waveform provides the lowest etch rate, while the square waveform provides an increased etch rate.

[0100] The etch rate can be further increased by adjusting the slope, as illustrated by curve 505, which shows the results for an optimized ramped square waveform. Curve 505 achieves the highest etch rate because the slope is adjusted to compensate for the chuck capacitance, thereby providing an optimized IEDF.

[0101] However, adjusting the slope too much can reduce the etch rate, as illustrated by curve 507. Curve 507 shows the results for a ramped square waveform with a larger slope than curve 505. In this case, too much slope reduces the etch rate results, lower than that of the square waveform shown by curve 503.

[0102] 6A, 6B, and 6C conceptually illustrate bowing present in features etched using different waveforms according to embodiments of the present disclosure. As described above, optimizing the waveform to compensate for capacitance charging can lead to a reduced potential at the wafer, resulting in a narrower IEDF dominated by energetic ions. This improves ion directionality, making the ions less likely to scatter and etch the sidewalls of the feature (thereby creating unwanted "bowing" of the sidewalls). Therefore, improved anisotropic etching is achieved, which is important for etching high-aspect-ratio features. In some embodiments, high-aspect-ratio features are defined as features having a depth-to-width aspect ratio of about 25:1 or greater. In some embodiments, a high aspect ratio is defined as 30, 40, 50, or 60:1 or greater.

[0103] 6A conceptually illustrates a cross section of a portion of a wafer showing a feature etched using a sinusoidal low-frequency RF waveform. As shown, the feature 600 exhibits bowing of its sidewalls 602 due to a non-optimized IEDF such that a significant number of intermediate energy ions are produced, which results in a more diffuse angular distribution of ions and produces the bowing shown.

[0104] 6B conceptually illustrates a cross section of a portion of a wafer showing features etched using a rectangular-shaped low-frequency RF waveform (no ramp). As shown, the features 604 exhibit more pronounced bowing of their sidewalls 606 than with a sinusoidal-shaped waveform. As noted above, while a rectangular-shaped waveform provides an increased etch rate over a sinusoidal-shaped waveform, the rectangular-shaped waveform does not compensate for charging the capacitance of the ESC and actually exacerbates bowing in the etched features.

[0105] 6C conceptually illustrates a cross section of a portion of a wafer showing features etched using a tilted rectangular-shaped low-frequency RF waveform. More specifically, the tilt of the rectangular-shaped waveform is adjusted to compensate for charging the capacitance of the ESC, providing a more focused, high-energy IEDF and a narrower ion angular distribution. As a result, features 608 exhibit significantly reduced bowing of their sidewalls 610 compared to both the sinusoidal and rectangular-shaped waveform scenarios.

[0106] Generally, embodiments of the present disclosure are directed to providing an optimized low frequency RF waveform that can compensate for the capacitance of the ESC. It should be understood that various parameters of the waveform are also important in combination to achieve an optimized IEDF.

[0107] Typically, at least three different low-frequency waveforms are generated and combined to generate a square wave, and the phases of the waveforms are adjusted relative to each other to adjust the slope of the square wave to achieve a tilted square wave shape. In some embodiments, the frequencies utilized consist of a fundamental frequency and at least two harmonics of the fundamental. To achieve an optimized shape, at least three frequencies and appropriate phase relationships are realized to achieve a narrow ion angular distribution function and improved verticality of etching of high aspect ratio features.

[0108] In some embodiments, more than three frequencies are combined (eg, four, five, six, etc.).

[0109] In some embodiments, different frequencies are combined, including combinations of fundamental frequencies and odd or even harmonics, or mixtures thereof.

[0110] Obtaining an ion source with a narrow IEDF has been difficult for applications such as high aspect ratio etching, due to the significantly higher voltage required than for other applications. As will be appreciated, the voltage depends on the weights of the fundamental and harmonics, and therefore the weights of the fundamental and harmonics are adjusted to provide a high voltage in accordance with embodiments of the present disclosure.

[0111] In some embodiments, the voltage is highly dependent on the first fundamental frequency that generates the fundamental voltage in the plasma, so the fundamental frequency primarily determines the maximum voltage of the final RF signal. Generally, in some embodiments, for a given power output, frequency is inversely related to voltage, so that lower frequencies provide higher voltages and higher frequencies provide lower voltages. For example, at a power output of about 15 kW and a fundamental frequency of about 400 kHz, a voltage in the range of about 10-11 kV peak-to-peak is achieved.

[0112] Then, depending on the fundamental frequency selected, the weights and phases of the harmonics can be adjusted to optimize the overall waveform shape, as described above.

[0113] As can be seen, both frequency and waveform shape, in combination, are important to achieving a narrow IEDF because the ion angular distribution depends on how ions are accelerated within the plasma sheath. Because the plasma sheath has a certain width and ions have certain velocities, they may respond differently to different frequencies. Therefore, achieving an optimal narrow IEDF is difficult and depends on the combination of frequency and waveform shape.

[0114] 7 shows an exemplary electrical schematic diagram of an impedance matching system according to some embodiments. Components of impedance matching system 143 according to embodiments of the present disclosure are shown. As shown, impedance matching system 143 is configured to process separately generated RF signals from RF signal generators 151, 153, and 155, which are combined to generate a substantially or approximately ramped rectangular waveform as described above according to embodiments of the present disclosure.

[0115] It should be understood that any of the methods described in this disclosure may be implemented to operate automatically by control system 120. In some embodiments, parameters for generating low frequency RF signals according to implementations of the present disclosure are editable through a user interface.

[0116] 8 shows an exemplary schematic diagram of the control system 120 of FIG. 2 , according to some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling a semiconductor manufacturing process performed within the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a storage hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, the storage HU 1403, the input HU 1405, the output HU 1407, the I / O interface 1409, the I / O interface 1411, and the NIC 1413 are in data communication with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communication from several external devices. Examples of input HUs 1405 include a data acquisition system, a data acquisition card, etc. Output HUs 1407 are configured to transmit data to some external device. An example of output HUs 1407 is a device controller. Examples of NICs 1413 include a network interface card, a network adapter, etc. Each of I / O interfaces 1409 and 1411 is defined to provide compatibility between different hardware units coupled to the I / O interface. For example, I / O interface 1409 may be defined to convert signals received from input HUs 1405 to a format, amplitude, and / or speed compatible with data communication bus 1415. Also, I / O interface 1407 may be defined to convert signals received from data communication bus 1415 to a format, amplitude, and / or speed compatible with output HUs 1407. Although various operations are described herein as being performed by processor 1401 of control system 120, it should be understood that in some embodiments, various operations may be performed by multiple processors of control system 120 and / or by multiple processors of multiple computing systems in data communication with control system 120.

[0117] In some embodiments, the control system 120 is used to control various wafer fabrication system devices based in part on the sensed values. For example, the control system 120 may control one or more of the valves 1417, filter heater 1419, wafer support structure heater 1421, pump 1423, and other devices 1425 based on the sensed values ​​and other control parameters. The valves 1417 may include valves associated with controlling the backside gas supply system 129, the process gas supply system 191, and the temperature control fluid circulation system 125. The control system 120 receives sensed values ​​from, for example, a pressure manometer 1427, a flow meter 1429, a temperature sensor 1431, and / or other sensors 1433, such as voltage sensors, current sensors, etc. The control system 120 may also be used to control process conditions within the plasma processing system 100 during plasma processing operations on wafers W. For example, the control system 120 can control the type and amount of process gas supplied from the process gas supply system 191 to the plasma processing region 182. The control system 120 can also control the operation of the first radio frequency signal generator 147, the low frequency RF subsystem 149, the impedance matching system 143, the TES radio frequency signal generator 403, and the TES impedance matching system 401. The control system 120 can also control the operation of the DC power supply 117 relative to the clamp electrode 112. The control system 120 can also control the operation of the lifting device 133 relative to the lift pins 132 and the operation of the door 107. The control system 120 also controls the operation of the backside gas supply system 129 and the temperature control fluid circulation system 125. The control system 120 also controls the vertical movement of the cantilever arm assembly 115. The control system 120 also controls the operation of the throttle member 196 and a pump that controls the suction at the exhaust port 105. The control system 120 also controls the operation of the restraint control mechanism 913 of the restraint rod 911 of the TES system 1000. The control system 120 also receives input from the temperature probe of the TES system 1000.It should be understood that the control system 120 is equipped to provide for programmatic and / or manual control of any function within the plasma processing system 100 .

[0118] In some embodiments, the control system 120 is configured to execute a computer program including a set of instructions for controlling process timing, process gas delivery system temperature and pressure differentials, valve positions, process gas mixture, process gas flow rates, backside cooling gas flow rates, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequency, RF pulsing, impedance match system 143 settings, cantilever arm assembly position, bias power, and other parameters of a particular process. Other computer programs stored on a memory device associated with the control system 120 may be used in some embodiments. In some embodiments, there is a user interface associated with the control system 120. The user interface includes a display 1435 (e.g., a display screen and / or graphical software representation of equipment and / or process conditions) and a user input device 1437, such as a pointing device, keyboard, touch screen, microphone, etc.

[0119] Software for directing the operation of the control system 120 can be designed or configured in many different ways. Computer programs for directing the operation of the control system 120 to perform various wafer fabrication processes in a process sequence can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. Compiled object code or script is executed by the processor 1401 to perform the tasks identified in the program. The control system 120 can be programmed to control various process control parameters related to process conditions, such as filter pressure differential, process gas composition and flow rate, backside cooling gas composition and flow rate, plasma conditions such as temperature, pressure, RF power level and RF frequency, bias voltage, cooling gas / fluid pressure, and chamber wall temperature, among others. Examples of sensors that can be monitored during the wafer fabrication process include, but are not limited to, mass flow control modules, pressure sensors such as pressure manometers 1427, and temperature sensors 1431. Appropriately programmed feedback and control algorithms can be used with data from these sensors to control / adjust one or more process control parameters to maintain desired process conditions.

[0120] In some embodiments, control system 120 is part of a broader manufacturing control system. Such manufacturing control systems may include semiconductor processing equipment, including processing tools, chambers, and / or platforms for wafer processing, and / or specific processing components such as wafer pedestals, gas flow systems, etc. These manufacturing control systems may be integrated with electronics for controlling their operation before, during, and after wafer processing. Control system 120 may control various components or sub-portions of the manufacturing control system. Depending on wafer processing requirements, control system 120 may be programmed to control any of the processes disclosed herein, including process gas delivery, backside cooling gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfers in and out of tools and other transfer tools and / or load locks connected to or in contact with specific systems.

[0121] Generally, control system 120 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable wafer processing operations, enable endpoint measurements, etc. The integrated circuits may include firmware that stores program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or chips in the form of one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions communicated to control system 120 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on wafers W in system 100. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to perform one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0122] Control system 120, in some embodiments, may be part of, coupled to, or a combination of, a computer integrated with, coupled to, or otherwise networked to plasma processing system 100. For example, control system 120 may reside in the "cloud" of all or part of a fab host computer system, which may enable remote access of wafer processing. The computer may enable remote access to system 100 to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, and examine trends or performance metrics from multiple manufacturing operations in order to change parameters of a current process, set up processing steps subsequent to a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to system 100 over a network, which may include a local network or the Internet.

[0123] The remote computer can include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system 100. In some examples, the control system 120 receives instructions in the form of data, which specifies parameters for each of the processing steps performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed within the plasma processing system 100. Thus, as noted above, the control system 120 may be distributed, such as by comprising one or more individual controllers networked together and functioning toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes may be one or more integrated circuits of the plasma processing system 100 in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control the processes performed on the plasma processing system 100.

[0124] Without limitation, exemplary systems with which control system 120 may interface may include a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a clean chamber or module, a chamfered edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the manufacturing and / or fabrication of semiconductor wafers. As noted above, depending on one or more process steps performed by the tool, control system 120 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, other controllers, or tools used in material transport carrying containers of wafers to and from tool locations and / or load ports within a semiconductor fabrication factory.

[0125] The embodiments described herein may also be practiced with various computer system configurations, including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics devices, minicomputers, mainframe computers, and the like. The embodiments described herein may also be practiced with distributed computing environments in which tasks are performed by remote processing hardware units linked through a network. It should be understood that the embodiments described herein, particularly those related to control system 120, may use various computer-implemented operations involving data stored in computer systems. These operations are operations requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to hardware units or apparatuses for performing these operations. An apparatus may be specially constructed for a special-purpose computer. When defined as a special-purpose computer, the computer may also perform other processes, program executions, or routines that are not part of its special purpose, while still being capable of operating for that special purpose. In some embodiments, operations may be processed by a general-purpose computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or retrieved over a network. If the data is obtained over a network, the data may be processed by other computers on the network, for example, a cloud of computing resources.

[0126] Various embodiments described herein may be implemented through process control instructions embodied as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit that can store data, which can then be read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. A non-transitory computer-readable medium may include a computer-readable tangible medium distributed across network-coupled computer systems such that the computer-readable code is stored and executed in a distributed manner.

[0127] Although the above disclosure includes some details for the purpose of clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features of any other embodiment disclosed herein. Therefore, the present embodiments should be considered illustrative and not restrictive, and the claims should not be limited to the details provided herein, but may be varied within the scope and equivalents of the described embodiments.

Claims

1. 1. A method for applying RF power in a plasma processing chamber, comprising: generating a first RF signal; generating a second RF signal; generating a third RF signal; The first, second, and third RF signals are generated at different frequencies, and the method further comprises: combining the first, second, and third RF signals to generate a combined RF signal, wherein a waveform of the combined RF signal is configured to approximate a ramped square wave shape; applying the combined RF signal to a chuck within the plasma processing chamber; A method comprising:

2. 10. The method of claim 1, the first RF signal is generated at a fundamental frequency; the second RF signal is generated at a first predetermined harmonic frequency of the fundamental frequency; The method wherein the third RF signal is generated at a second predetermined harmonic frequency of the fundamental frequency.

3. 3. The method of claim 2, wherein the first or second predetermined harmonic frequency is an even or odd harmonic of the fundamental frequency.

4. 10. The method of claim 1, generating the second RF signal includes adjusting a phase of the second RF signal relative to a phase of the first RF signal; generating the third RF signal includes adjusting a phase of the third RF signal relative to the phase of the first RF signal; The method, wherein the adjusting the phase of the second and third RF signals adjusts the amount of slope of the waveform of the combined RF signal.

5. 10. The method of claim 1, wherein the waveform of the combined RF signal is configured to compensate for the capacitance of the chuck, such that the combined RF signal reaching a wafer supported by the chuck has a waveform that approximates a non-tilted square wave shape.

6. 10. The method of claim 1, wherein the waveform of the combined RF signal is configured to concentrate an ion energy distribution function of ions directed from a plasma by the application of the combined RF signal.

7. 7. The method of claim 6, wherein the convergence of the ion energy distribution function increases the directionality of the ions and reduces bowing of features etched by the ions.

8. 2. The method of claim 1, wherein the waveform of the combined RF signal is configured such that peaks of the waveform exhibit a positive slope and valleys of the waveform exhibit a negative slope.

9. 10. The method of claim 1, wherein the waveform of the combined RF signal is configured to ensure verticality of high aspect ratio features during etching.

10. 10. The method of claim 1, wherein the first RF signal is generated at a frequency in the range of approximately 50 to 500 kHz.

11. 1. A system for applying RF power in a plasma processing chamber, comprising: a first generator for generating a first RF signal; a second generator for generating a second RF signal; a third generator for generating a third RF signal; Equipped with the first, second, and third RF signals are generated at different frequencies; the first, second, and third RF signals are combined to generate a combined RF signal, the waveform of the combined RF signal being configured to approximate a ramped square wave shape; The system is configured such that the combined RF signal is applied to a chuck within the plasma processing chamber.

12. 12. The system of claim 11, the first RF signal is generated at a fundamental frequency; the second RF signal is generated at a first predetermined harmonic frequency of the fundamental frequency; The system wherein the third RF signal is generated at a second predetermined harmonic frequency of the fundamental frequency.

13. 13. The system of claim 12, wherein the first or second predetermined harmonic frequency is an even or odd harmonic of the fundamental frequency.

14. 12. The system of claim 11, the second RF signal is generated by adjusting the phase of the second RF signal relative to the phase of the first RF signal; the third RF signal is generated by adjusting the phase of the third RF signal relative to the phase of the first RF signal; The system, wherein the adjustment of the phase of the second and third RF signals adjusts the amount of slope of the waveform of the combined RF signal.

15. 12. The system of claim 11, wherein the waveform of the combined RF signal is configured to compensate for capacitance of the chuck such that the combined RF signal reaching a wafer supported by the chuck has a waveform that approximates a non-tilted square wave shape.

16. 12. The system of claim 11, wherein the waveform of the combined RF signal is configured to concentrate an ion energy distribution function of ions directed from a plasma by the application of the combined RF signal.

17. 17. The system of claim 16, wherein the convergence of the ion energy distribution function increases directionality of the ions and reduces bowing of features etched by the ions.

18. 12. The system of claim 11, wherein the waveform of the combined RF signal is configured such that peaks of the waveform exhibit a positive slope and valleys of the waveform exhibit a negative slope.

19. 12. The system of claim 11, wherein the waveform of the combined RF signal is configured to ensure verticality of high aspect ratio features during etching.

20. 12. The system of claim 11, wherein the first RF signal is generated at a frequency in the range of approximately 50 to 500 kHz.

21. 12. The system of claim 11, an impedance matching system that combines the first, second, and third RF signals to generate the combined RF signal; The system further comprises:

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