Oscillation circuit

Abstract

To stably output an oscillation signal with less noise.SOLUTION: There are provided a resonator (1), inverters (2, 2A, 2B) connected in parallel with the resonator (1) and configured to be able to adjust a gain, a temperature detection unit (6) configured to detect an ambient temperature, and gain adjustment units (5, 5A, 5B) configured to adjust the gains of the inverters (2, 2A, 2B), and the gain adjustment units (5, 5A, 5B) adjust the gains of the inverters (2, 2A,) based on the temperature detected by the temperature detection unit (6). 2B.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an oscillator circuit. [Background technology]

[0002] Oscillator circuits are widely used in electronic circuits. An oscillator circuit has a quartz crystal unit and an inverter connected in parallel to the quartz crystal unit. The current output from the inverter is returned to the quartz crystal unit, causing the quartz crystal unit to vibrate and output an oscillation signal (see Patent Document 1, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4026825

[0004] [overview] In oscillator circuits, the amplitude of the oscillation signal can fluctuate due to temperature, circuit variations, etc., resulting in unstable oscillation. To prevent such cases, the amplitude of the oscillation signal is increased to ensure oscillation stability. However, increasing the amplitude of the oscillation signal also increases phase noise. In recent years, there has been an increasing demand for oscillator circuits that output stable oscillation signals with less noise.

[0005] An oscillator circuit according to one aspect of the present disclosure includes an oscillator, an inverter connected in parallel with the oscillator and configured to adjust the gain, a temperature detection unit configured to detect the ambient temperature, and a gain adjustment unit configured to adjust the gain of the inverter, wherein the gain adjustment unit is configured to adjust the gain of the inverter based on the temperature detected by the temperature detection unit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing a schematic configuration of an oscillation circuit according to a first embodiment. [Figure 2]FIG. 2 is a circuit diagram showing the configuration of an inverter used in the oscillation circuit. [Figure 3] FIG. 3 is a flowchart showing the output of the gain adjustment signal output from the gain adjustment unit. [Figure 4] FIG. 4 is a circuit diagram showing a schematic configuration of an inverter according to a first modified example. [Figure 5] FIG. 5 is a flowchart showing a gain adjustment procedure performed by the gain adjustment unit. [Figure 6] FIG. 6 is a circuit diagram showing a schematic configuration of an inverter according to the second modified example. [Figure 7] FIG. 7 is a flowchart showing a gain adjustment procedure performed by the gain adjustment unit. [Figure 8] FIG. 8 is a circuit diagram showing a schematic configuration of an oscillation circuit according to the second embodiment. [Figure 9] FIG. 9 is a flowchart showing a gain adjustment procedure performed by the gain adjustment unit. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Detailed explanation]

[0008] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. A MOS field effect transistor may also be simply referred to as a MOS transistor. A P-channel MOS transistor will be referred to as a PMOS transistor, and an N-channel MOS transistor will be referred to as an NMOS transistor.

[0009] When referring to multiple parts that form a circuit, such as any elements or lines, the term "connection" includes mechanical connection as well as electrical connection, i.e., a state in which electricity flows. In other words, "connect" includes "electrical connection."

[0010] First Embodiment 1 is a circuit diagram showing a schematic configuration of an oscillator circuit 100 according to a first embodiment. As shown in FIG. 1, the oscillator circuit 100 includes a vibrator 1, an inverter 2, a load capacitor 31, a load capacitor 32, a gain adjuster 5, and a temperature detector 6.

[0011] The resonator 1 is an element that vibrates at a natural frequency. In the oscillator circuit 100 of this embodiment, it is, for example, a quartz crystal resonator. The inverter 2 is connected in parallel with the resonator 1. That is, a first end of the resonator 1 is connected to an input terminal of the inverter 2, and a second end of the resonator 1 is connected to an output terminal of the inverter 2.

[0012] The inverter 2 is configured so that the gain is adjusted based on information from the gain adjustment unit 5. In the oscillation circuit 100, the gain adjustment unit 5 adjusts the gain of the inverter 2 so as to keep constant the amplitude of the oscillation signal output from the oscillation circuit 100. The gain adjustment unit 5 will be described in detail later.

[0013] The first ends of the load capacitance 31 and the load capacitance 32 are attached to the first and second ends of the vibrator 1. The first ends of the load capacitance 31 and the load capacitance 32 are connected to the input terminal and the output terminal of the inverter 2, and the second ends are grounded.

[0014] The temperature detection unit 6 detects the temperature of the oscillation circuit 100. The temperature detection unit 6 is mainly arranged to detect the temperature of the vibrator 1. The temperature detection unit 6 supplies the gain adjustment unit 5 with temperature information Th1 corresponding to the detected temperature of the vibrator 1.

[0015] The gain adjustment unit 5 adjusts the gain of the inverter 2 based on the temperature information Th1 from the temperature detection unit 6. The gain adjustment unit 5 outputs a gain adjustment signal GC that adjusts the gain of the inverter 2 according to the temperature information Th1 of the inverter 2 acquired from the temperature detection unit 6 so that the amplitude of the oscillation signal SOUT output from the oscillation circuit 100 becomes a predetermined amplitude. The inverter 2 is configured to be adjusted so that the gain corresponds to the gain adjustment signal GC.

[0016] The inverter 2 will be described in detail with reference to the drawings, and a method for adjusting the gain of the inverter 2 will be further described. FIG. 2 is a circuit diagram showing the configuration of the inverter 2 used in the oscillation circuit 100. As shown in FIG. 2, the inverter 2 is configured using a CMOS (Complementary MOS). The inverter 2 has bridge circuits 21_1 to 21_4, a capacitor 22, a capacitor 23, a resistor 24, and a resistor 25.

[0017] The inverter 2 is configured to have four bridge circuits 21_1 to 21_4, but the number of bridge circuits is not limited to four. It may be two, three, or five or more. The bridge circuit 21_1 has a high-side switching element 211, a low-side switching element 212, a first switching element 213, and a second switching element 214.

[0018] The high-side switching element 211 is a PMOS transistor, and the low-side switching element 212 is an NMOS transistor. The source of the high-side switching element 211 is connected to a power supply VIN. The drain of the low-side switching element 212 is connected to ground.

[0019] The first switching element 213 and the second switching element 214 are both NMOS transistors. The source of the first switching element 213 and the drain of the second switching element 214 are connected at a connection point P1. The drain of the first switching element 213 is connected to the drain of the high-side switching element 211. In addition, the source of the second switching element 214 is connected to the drain of the low-side switching element 212.

[0020] The gate of the first switching element 213 and the gate of the second switching element 214 are connected to each other, and a gain adjustment signal GC1 output from the gain adjustment unit 5 (to be described later) is supplied thereto.

[0021] Furthermore, the capacitor 22 and the capacitor 23 are connected in series between the gate of the high-side switching element 211 and the gate of the low-side switching element 212. A connection point P2 between the capacitor 22 and the capacitor 23 is connected to the input terminal IN of the inverter 2.

[0022] Resistors 24 and 25 are connected to the gate of the high-side switching element 211 and the gate of the low-side switching element 212, respectively. Bias voltages Vb1 and Vb2 are applied to the gate of the high-side switching element 211 and the gate of the low-side switching element 212 via resistors 24 and 25. The operating points of the high-side switching element 211 and the low-side switching element 212 are adjusted by resistors 24 and 25, and the gain of the inverter 2 is adjusted. In the oscillation circuit 100, the gain of the inverter 2 is set to 1 or more in order to keep the vibrator 1 oscillating.

[0023] In the bridge circuit 21_1 of the inverter 2, the gain adjustment signal GC1 is a signal that takes a high level or a low level. When the gain adjustment signal GC1 is at a low level, the first switching element 213 and the second switching element 214 are both off. When the gain adjustment signal GC1 is at a high level, the first switching element 213 and the second switching element 214 are both on. In the inverter 2, when the gain adjustment signal GC1 is at a high level, the bridge circuit 21_1 is configured to be able to output an output current. Hereinafter, the state of the bridge circuit that is able to output an output current is referred to as an active state.

[0024] The bridge circuits 21_2, 21_3, and 21_4 are different from the bridge circuit 21_1 in that gain adjustment signals GC2, GC3, and GC4 are supplied to them, respectively, but other than this, they have the same configuration as the bridge circuit 21_1.

[0025] In the inverter 2, the high-side switching elements 211 and the low-side switching elements 212 of the bridge circuits 21_1 to 21_4 are connected to each other and to an input terminal IN. The connection points P2 of the bridge circuits 21_1 to 21_4 are connected to each other and to an output terminal OUT.

[0026] In inverter 2, an input signal input from input terminal IN is superimposed on bias voltage Vb1 and input to the gate of high-side switching element 211. At the same time, the input signal is superimposed on bias voltage Vb2 and input to the gate of low-side switching element 212. By being superimposed on bias voltages Vb1 and Vb2 in this way, the high-side switching element 211 and low-side switching element 212 can be stably operated by the input signal.

[0027] In the inverter 2, an input signal is input to the high-side switching element 211 and the low-side switching element 212 of all of the bridge circuits 21_1 to 21_4. Meanwhile, only the first switching element 213 and the second switching element 214 of the active bridge circuit are turned on. Therefore, a current is supplied from the connection point P1 of the active bridge circuit to the output terminal OUT, and a current obtained by combining these currents is output.

[0028] That is, by adjusting the active bridge circuit, the current value from the output terminal OUT is adjusted. In this way, by adjusting the current flowing into the output terminal OUT, the gain of the inverter 2 is adjusted. Then, in the oscillation circuit 100, the output current of the inverter 2 is supplied to the vibrator 1. By increasing or decreasing the current supplied to the vibrator 1, the vibration of the vibrator 1 changes, and as a result, the amplitude of the oscillation signal SOUT output from the oscillation circuit 100 changes. That is, in the oscillation circuit 100, by adjusting the gain of the inverter 2, the current value supplied from the inverter 2 to the vibrator 1 can be adjusted, and the amplitude of the oscillation signal SOUT can be adjusted.

[0029] In the oscillation circuit 100, the gain adjustment unit 5 increases the number of bridge circuits 21 that are activated when increasing the gain of the inverter 2, and decreases the number of bridge circuits 21 that are activated when decreasing the gain. For example, in the oscillation circuit 100, the gain of the inverter 2 is minimum when only the gain adjustment signal GC1 is at a high level, and is maximum when all the gain adjustment signals GC1 to GC4 are at a high level.

[0030] The adjustment of the gain of the inverter 2 by the gain adjustment unit 5 will be described with reference to the drawings. Fig. 3 is a flowchart showing the output of the gain adjustment signals GC1 to GC4 output from the gain adjustment unit 5.

[0031] The oscillator circuit 100 operates at temperatures equal to or higher than T1 and equal to or lower than T5. As shown in Fig. 3, the gain adjustment unit 5 acquires the temperature t of the vibrator 1 based on the temperature information Th1 from the temperature detection unit 6. When the temperature t is equal to or higher than T1 and equal to or lower than T2 (Yes in step S101), the gain adjustment unit 5 supplies a high-level gain adjustment signal GC1 and low-level gain adjustment signals GC2, GC3, and GC4 to the inverter 2 (step S102). Thereafter, the gain adjustment unit 5 continues to receive the temperature information Th1.

[0032] If the temperature t is higher than the temperature T2 (No in step S101), the process proceeds to step S103. If the temperature t is higher than the temperature T2 and equal to or lower than the temperature T3 (Yes in step S103), the gain adjustment unit 5 supplies high-level gain adjustment signals GC1 and GC2 and low-level gain adjustment signals GC3 and GC4 to the inverter 2 (step S104). Thereafter, the gain adjustment unit 5 continues to receive the temperature information Th1.

[0033] If the temperature t is higher than the temperature T3 (No in step S103), the process proceeds to step S105. If the temperature t is higher than the temperature T3 and equal to or lower than the temperature T4 (Yes in step S105), the gain adjustment unit 5 supplies high-level gain adjustment signals GC1, GC2, and GC3, and a low-level gain adjustment signal GC4 to the inverter 2 (step S106). Thereafter, the gain adjustment unit 5 continues to receive the temperature information Th1.

[0034] Furthermore, when the temperature t is greater than the temperature T4 and equal to or less than the temperature T5 (No in step S105), the gain adjustment unit 5 supplies all of the gain adjustment signals GC1, GC2, and GC3 and the low-level gain adjustment signal GC4 as high-level signals to the inverter 2 (step S107). Thereafter, the gain adjustment unit 5 continues to receive the temperature information Th1.

[0035] The gain adjustment unit 5 is configured to switch the gain adjustment signals GC1 to GC4 from low level to high level or from high level to low level when the temperature detected by the temperature detection unit 6 falls within a predetermined range based on the temperature information Th1. The gain adjustment unit 5 may also be provided with a table (not shown) that associates the temperature of the inverter 2 with the gain, and output the gain adjustment signals GC1 to GC4 according to the temperature information Th1.

[0036] In the inverter 2, the switching elements constituting the bridge circuits 21_1 to 21_4 may have the same configuration, or may have different configurations so that each bridge circuit outputs with a different gain. By configuring in this way, it is possible to widen the adjustment range of the gain.

[0037] Furthermore, the gain adjustment signal output from the gain adjustment unit 5 may be a digital signal, and each bridge circuit may decode the digital signal to generate information for switching on or off the first switching element 213 and the second switching element 214. For example, when the gain adjustment unit 5 outputs a gain adjustment signal to an inverter having four bridge circuits 21_1 to 21_4, the gain adjustment unit 5 may supply a 4-bit gain adjustment signal to all of the bridge circuits 21_1 to 21_4.

[0038] In the oscillator circuit 100, an oscillation margin determined by the amplitude of the oscillation signal SOUT is set. The oscillation margin is a parameter indicating the stability of the operation of the oscillator circuit 100 to output the oscillation signal SOUT, and if the oscillation margin becomes low, the operation of the oscillator circuit 100 may become unstable. Therefore, it is preferable that the amplitude of the oscillation signal SOUT is equal to or greater than a certain amplitude.

[0039] On the other hand, in the oscillator circuit 100 having the above-described configuration, if the amplitude of the oscillation signal SOUT is large, the phase noise becomes large at frequencies close to the frequency of the oscillation point. In order to reduce such phase noise, it is preferable that the amplitude of the oscillation signal SOUT is not too large.

[0040] In the oscillation circuit 100, the amplitude of the oscillation signal SOUT decreases as the temperature rises. Therefore, in the oscillation circuit 100, it is possible to adjust the amplitude of the oscillation signal SOUT by adjusting the gain of the inverter 2. Therefore, the oscillation circuit 100 is set so that it can output the oscillation signal SOUT with an amplitude that provides an oscillation margin that enables stable output of the oscillation signal SOUT at a certain set temperature. Then, the oscillation circuit 100 adjusts the gain of the inverter 2 according to the temperature detected by the temperature detection unit 6, and outputs the oscillation signal SOUT with an amplitude that allows stable output when operating at the current temperature.

[0041] In the oscillator circuit 100 according to this embodiment, the amplitude of the oscillation signal SOUT is adjusted according to the temperature, and therefore, when operating at the set temperature and when operating at a temperature higher than the set temperature, there is sufficient oscillation margin and the phase noise at frequencies close to the frequency of the oscillation point can be reduced.

[0042] <First Modification> It is also possible to use an inverter having a configuration different from that described above in the oscillation circuit 100. An inverter 2A according to a first modified example will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a schematic configuration of the inverter 2A of the first modified example. The inverter 2A of the first modified example has a first bias adjustment switching element 26 and a second bias adjustment switching element 27 for adjusting the bias voltage Vb1 and the bias voltage Vb2. The inverter 2A also has a bridge circuit 21A instead of the bridge circuits 21_1 to 21_4. Other than this, the inverter 2A has the same configuration as the inverter 2, and parts of the inverter 2A that are substantially the same as those of the inverter 2 are assigned the same reference numerals, and detailed description of the same parts will be omitted.

[0043] 4, the inverter 2A has a CMOS structure similar to the inverter 2. The inverter 2A includes a bridge circuit 21A, a capacitor 22, a capacitor 23, a resistor 24, a resistor 25, a first bias adjustment switching element 26, a second bias adjustment switching element 27, a first current adjustment unit 28, and a second current adjustment unit 29.

[0044] The bridge circuit 21A has a configuration in which the drain of a high-side switching element 211 and the drain of a low-side switching element 212 are connected at a connection point P3.

[0045] The first bias adjustment switching element 26 is a PMOS transistor. The first bias adjustment switching element 26 has a diode-connected configuration with its gate and drain connected. The source of the first bias adjustment switching element 26 is connected to a power supply VIN, its gate is connected to the resistor 24, and its drain is connected to a first current adjustment unit 28. The first current adjustment unit 28 passes a current I1 from the drain of the first bias adjustment switching element 26 to the ground. The first current adjustment unit 28 is configured to be able to change the current value of the current I1 based on a gain adjustment signal GD1 supplied from the gain adjustment unit 5.

[0046] When the first current adjustment unit 28 causes the current I1 to flow, the first bias adjustment switching element 26 turns on and current is drawn from the gate, thereby generating the bias voltage Vb1 supplied to the high-side switching element 211.

[0047] The second bias adjustment switching element 27 is an NMOS transistor. The second bias adjustment switching element 27 has a diode-connected configuration with its gate and drain connected. The source of the second bias adjustment switching element 27 is grounded, its gate is connected to the resistor 25, and its drain is connected to the second current adjustment unit 29. The second current adjustment unit 29 passes a current I2 from the power supply VIN to the drain of the second bias adjustment switching element 27. The second current adjustment unit 29 is configured to be able to change the current value of the current I2 based on a gain adjustment signal GD2 supplied from the gain adjustment unit 5.

[0048] When the second current adjustment unit 29 causes the current I2 to flow, the second bias adjustment switching element 27 is turned on, and a current flows from the gate to the resistor 25. This generates the bias voltage Vb2 that is supplied to the high-side switching element 211.

[0049] The adjustment of the gain of the inverter 2A by the gain adjustment unit 5A will be described with reference to the drawings. Fig. 5 is a flowchart showing the gain adjustment procedure by the gain adjustment unit 5A.

[0050] The oscillator circuit 100 operates at temperatures equal to or higher than T1 and equal to or lower than T5. As shown in Fig. 5, the gain adjuster 5A acquires the temperature t of the vibrator 1 based on the temperature information Th1 from the temperature detector 6. When the temperature t is equal to or higher than T1 and equal to or lower than T2 (Yes in step S201), the gain adjuster 5A outputs the gain adjustment signals GD1 and GD2 that change the current I1 flowing through the first current adjuster 28 to I11 and the current I2 flowing through the second current adjuster 29 to I21 (step S202). Thereafter, the gain adjuster 5A continues to receive the temperature information Th1.

[0051] If the temperature t is higher than the temperature T2 (No in step S201), the process proceeds to step S203. If the temperature t is higher than the temperature T2 and equal to or lower than the temperature T3 (Yes in step S203), the gain adjuster 5A outputs the gain adjustment signals GD1 and GD2 that change the current I1 flowing in the first current adjuster 28 to I12 and the current I2 flowing in the second current adjuster 29 to I22 (step S204). Thereafter, the gain adjuster 5A continues to receive the temperature information Th1.

[0052] If the temperature t is higher than the temperature T3 (No in step S203), the process proceeds to step S205. If the temperature t is higher than the temperature T3 and equal to or lower than the temperature T4 (Yes in step S205), the gain adjuster 5A outputs the gain adjustment signals GD1 and GD2 that change the current I1 flowing in the first current adjuster 28 to I13 and the current I2 flowing in the second current adjuster 29 to I23 (step S206). Thereafter, the gain adjuster 5A continues to receive the temperature information Th1.

[0053] Furthermore, when the temperature t is greater than the temperature T4 and equal to or less than the temperature T5 (No in step S205), the gain adjuster 5A outputs the gain adjustment signals GD1 and GD2 that change the current I1 flowing through the first current adjuster 28 to I14 and the current I2 flowing through the second current adjuster 29 to I24 (step S207). Thereafter, the gain adjuster 5A continues to receive the temperature information Th1.

[0054] The gain adjustment unit 5 is configured to switch the gain adjustment signals GC1 to GC4 from low level to high level or from high level to low level when the temperature detected by the temperature detection unit 6 falls within a predetermined range based on the temperature information Th1. The gain adjustment unit 5 may also be provided with a table (not shown) that associates the temperature of the inverter 2 with the gain, and output the gain adjustment signals GD1 and GD2 according to the temperature information Th1.

[0055] In the inverter 2A, the currents I1 and I2 are adjusted by the gain adjustment signals GD1 and GD2, and the bias voltages Vb1 and Vb2 are adjusted. The bias voltages Vb1 and Vb2 are adjusted to adjust the operating points of the high-side switching element 211 and the low-side switching element 212. As a result, the current value of the current flowing from the connection point P3 to the output terminal OUT can be adjusted.

[0056] Even in the oscillation circuit 100 using such an inverter 2A, the gain of the inverter 2A can be adjusted depending on the temperature of the resonator 1. Therefore, in the oscillation circuit 100, regardless of the temperature of the resonator 1, a sufficient oscillation margin can be maintained and phase noise near the oscillation point can be reduced.

[0057] <Second Modification> An inverter 2B according to a second modified example will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a schematic configuration of the inverter 2B of the second modified example. The inverter 2B of the second modified example has a first bias adjustment switching element 24B and a second bias adjustment switching element 25B for adjusting the bias voltage Vb1 and the bias voltage Vb2. The inverter 2B also has a bridge circuit 21A. Other than this, the inverter 2B has the same configuration as the inverter 2A, and parts of the inverter 2B that are substantially the same as those of the inverter 2A are assigned the same reference numerals, and detailed description of the same parts will be omitted.

[0058] The first bias adjustment switching element 24B and the second bias adjustment switching element 25B are both NMOS transistors. The source of the first bias adjustment switching element 24B is connected to the gate of the high-side switching element 211, the bias voltage Vb1 is applied to the drain, and the gain adjustment signal GE1 from the gain adjustment unit 5B is supplied to the gate.

[0059] A resistance R1 between the drain and source of the first bias adjustment switching element 24B is adjusted by a gain adjustment signal GE1 from the gain adjustment unit 5B. The bias voltage Vb1 is adjusted by a voltage drop due to the resistance R1 between the drain and source of the first bias adjustment switching element 24B and is supplied to the gate of the high-side switching element 211.

[0060] The source of the second bias adjustment switching element 25B is connected to the gate of the high-side switching element 211, the bias voltage Vb2 is applied to the drain, and the gain adjustment signal GE2 from the gain adjustment unit 5B is supplied to the gate.

[0061] A resistance R2 between the drain and source of the second bias adjustment switching element 25B is adjusted by a gain adjustment signal GE2 from the gain adjustment unit 5B. The bias voltage Vb2 is adjusted by the voltage drop caused by the resistance R2 between the drain and source of the second bias adjustment switching element 25B and is supplied to the gate of the high-side switching element 211.

[0062] The adjustment of the gain of the inverter 2B by the gain adjuster 5B will be described with reference to the drawing. Fig. 7 is a flowchart showing the gain adjustment procedure by the gain adjuster 5B.

[0063] The oscillator circuit 100 operates at temperatures equal to or higher than T1 and equal to or lower than T5. As shown in FIG. 7, the gain adjuster 5B acquires the temperature t of the oscillator 1 based on the temperature information Th1 from the temperature detector 6. When the temperature t is equal to or higher than T1 and equal to or lower than T2 (Yes in step S301), the gain adjuster 5B outputs the gain adjustment signals GE1 and GE2 that change the drain-source resistance R1 of the first bias adjustment switching element 24B to R11 and the drain-source resistance R2 of the second bias adjustment switching element 25B to R12 (step S302). Thereafter, the gain adjuster 5B continues to receive the temperature information Th1.

[0064] If the temperature t is higher than the temperature T2 (No in step S301), the process proceeds to step S303. If the temperature t is higher than the temperature T2 and equal to or lower than the temperature T3 (Yes in step S303), the gain adjuster 5B outputs gain adjustment signals GE1 and GE2 that change the resistor R1 to R12 and the resistor R2 to R22 (step S304). Thereafter, the gain adjuster 5B continues to receive the temperature information Th1.

[0065] If the temperature t is higher than the temperature T3 (No in step S303), the process proceeds to step S305. If the temperature t is higher than the temperature T3 and equal to or lower than the temperature T4 (Yes in step S305), the gain adjuster 5B outputs the gain adjustment signals GE1 and GE2 that change the resistor R1 to R13 and the resistor R2 to R23 (step S306). Thereafter, the gain adjuster 5B continues to receive the temperature information Th1.

[0066] Furthermore, when the temperature t is greater than the temperature T4 and equal to or less than the temperature T5 (No in step S305), the gain adjuster 5B outputs the gain adjustment signals GE1 and GE2 that change the resistor R1 to R14 and the resistor R2 to R24 (step S307). After that, the gain adjuster 5B continues to receive the temperature information Th1.

[0067] In the inverter 2B, the bias voltages Vb1 and Vb2 are adjusted by adjusting the gain adjustment signals GE1 and GE2 from the gain adjustment unit 5B. The operating points of the high-side switching element 211 and the low-side switching element 212 are adjusted by adjusting the bias voltages Vb1 and Vb2. As a result, the current value of the current flowing from the connection point P3 to the output terminal OUT can be adjusted.

[0068] Even in the oscillation circuit 100 using such an inverter 2B, the gain of the inverter 2B can be adjusted depending on the temperature of the resonator 1. Therefore, in the oscillation circuit 100, regardless of the temperature of the resonator 1, a sufficient oscillation margin can be maintained and phase noise near the oscillation point can be reduced.

[0069] Second Embodiment Fig. 8 is a circuit diagram showing a schematic configuration of an oscillation circuit 300 of the second embodiment. The oscillation circuit 300 shown in Fig. 8 differs from the oscillation circuit 100 in that it does not include a temperature detection unit 6 and has a gain adjustment unit 7 instead of the gain adjustment unit 5. The other parts of the oscillation circuit 300 have the same configuration as the oscillation circuit 100. Therefore, parts of the oscillation circuit 300 that are substantially the same as those of the oscillation circuit 100 are given the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0070] As shown in FIG. 8, the gain adjustment unit 7 of the oscillation circuit 300 includes a feature detection unit 71 and a difference acquisition unit 72. The feature detection unit 71 is a circuit that detects a feature value of the oscillation signal SOUT. For example, the feature detection unit 71 can be configured to use a peak hold circuit that detects the peak value of the oscillation signal SOUT as the feature value and outputs the peak value. The feature detection unit 71 then generates an amplitude from the peak value and outputs the amplitude. Note that the feature detection unit 71 may also acquire an effective value (RMS: root mean square) instead of the amplitude of the oscillation signal SOUT. The feature detection unit 71 detects the feature value of the oscillation signal SOUT and supplies oscillation information IS including information about the feature value to the difference acquisition unit 72.

[0071] Oscillation information IS is input to the difference acquisition unit 72. The oscillation information IS is voltage information, and a reference voltage Vref separate from the oscillation information IS is supplied to the difference acquisition unit 72. The difference acquisition unit 72 acquires a difference value ΔV between the voltage value of the oscillation information IS and the reference voltage Vref. The difference acquisition unit 72 then supplies the inverter 2 with a gain adjustment signal GC that sets the difference value to zero. The inverter 2 adjusts its gain in accordance with the gain adjustment signals GC1 to GC4. The method for adjusting the gain of the inverter 2 is as described above.

[0072] The gain adjustment unit 7 outputs gain adjustment signals GC1 to GC4 that adjust the gain of the inverter 2 so that the oscillation signal SOUT satisfies certain conditions. The inverter 2 has a configuration shown in Fig. 8, and the bridge circuits 21_1 to 21_4 to be activated are determined according to the gain adjustment signals GC1 to GC4, thereby adjusting the gain of the inverter 2.

[0073] The oscillation circuit 300 is set so that it can output an oscillation signal SOUT with an amplitude that provides an oscillation margin that allows oscillation to continue under set conditions including temperature conditions. After the oscillation circuit 300 starts operating in this state, the characteristic detection unit 71 detects the amplitude of the oscillation signal SOUT. Then, the difference acquisition unit 72 acquires the difference between the detected amplitude and a predetermined amplitude, and outputs gain adjustment signals GC1 to GC4 to the inverter 2 so that the difference value remains constant.

[0074] The adjustment of the gain of the inverter 2 by the gain adjuster 7 will be described with reference to the drawings. Fig. 9 is a flowchart showing the gain adjustment procedure by the gain adjuster 7.

[0075] 9, the feature detection unit 71 outputs oscillation information IS corresponding to the oscillation signal SOUT to the difference acquisition unit 72. The difference acquisition unit 72 acquires a difference value ΔV between the voltage value of the oscillation information IS and the reference voltage Vref (step S401). The difference value ΔV is the value obtained by subtracting the reference voltage Vref from the voltage value of the oscillation information IS.

[0076] If the difference value ΔV is "0" (Yes in step S402), gain adjustment is not necessary, and the process returns to step S401 to acquire the difference value ΔV.

[0077] Furthermore, when the difference value ΔV is not "0" (No in step S402), it is determined whether or not the difference value ΔV is greater than "0" (step S403). When the difference value ΔV is greater than "0" (Yes in step S403), the current gain of the inverter 2 is high. Therefore, the gain adjustment unit 7 outputs the gain adjustment signals GC1 to GC4 so as to reduce the gain of the inverter 2. When changing the gain adjustment signals GC1 to GC4 so as to reduce the gain, for example, the gain adjustment signals GC1 to GC4 are output so as to switch the number of active bridge circuits 21_1 to 21_4 one by one. Thereafter, the process returns to step S401, and the difference value ΔV is acquired.

[0078] Furthermore, when the difference value ΔV is less than "0" (No in step S403), the current gain of the inverter 2 is low. Therefore, the gain adjustment unit 7 outputs gain adjustment signals GC1 to GC4 to increase the gain of the inverter 2. Thereafter, the process returns to step S401, and the difference value ΔV is acquired.

[0079] In this way, the oscillation circuit 300 can maintain a constant amplitude of the oscillation signal SOUT even if the oscillation signal SOUT varies due to temperature, noise, variations in the circuit itself, etc. Therefore, in the oscillation circuit 300, the gain adjustment unit 7 adjusts the gain of the inverter 2 so that the amplitude of the oscillation signal SOUT remains constant, so that the amplitude can be kept constant even if conditions such as variations in the oscillation circuit 300 itself, the effects of noise, and temperature changes change. Therefore, the oscillation circuit 300 can maintain a sufficient oscillation margin regardless of the operating conditions, and can reduce phase noise near the oscillation point.

[0080] In this embodiment, the oscillator circuit 300 is configured using the inverter 2 shown in FIG. 2, but is not limited to this. For example, the oscillator circuit 300 may be configured using the inverter 2A shown in FIG. 4. In this case, the difference acquisition unit 72 of the gain adjustment unit 7 is configured to output gain adjustment signals GD1 and GD2. Furthermore, for example, the oscillator circuit 300 may be configured using the inverter 2B shown in FIG. 6. In this case, the difference acquisition unit 72 of the gain adjustment unit 7 is configured to output gain adjustment signals GE1 and GE2.

[0081] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0082] <Additional Notes> The oscillator circuit (100) described above has the following features: An oscillator (1), Inverters (2, 2A, 2B) connected in parallel with the oscillator (1) and configured to be gain adjustable; a temperature detection unit (6) configured to detect the ambient temperature; a gain adjustment unit (5, 5A, 5B) configured to adjust the gain of the inverter (2, 2A, 2B); In this configuration (first configuration), the gain adjustment unit (5, 5A, 5B) adjusts the gain of the inverter (2, 2A, 2B) based on the temperature detected by the temperature detection unit (6).

[0083] The oscillator circuit (300) described above has the following features: An oscillator (1), Inverters (2, 2A, 2B) connected in parallel with the oscillator (1) and configured to be gain adjustable; The second configuration has a gain adjustment unit (7) configured to detect the amplitude of an oscillation signal (SOUT) generated by an oscillator and adjust the gain of the inverters (2, 2A, 2B) so that the oscillation information (IS) of the oscillation signal (SOUT) becomes predetermined oscillation information (Vref).

[0084] In the oscillator circuit (300) of the second configuration, the gain adjustment unit (5, 5A, 5B, 7) includes a feature detection unit (71) configured to detect information on the oscillation of the oscillation signal (SOUT) as oscillation information (IS); a difference acquisition unit (72) that acquires a difference value (ΔV) between the detected oscillation information (71) and a predetermined reference value (Vref), This is a configuration (third configuration) in which the gain of the inverters (2, 2A, 2B) is adjusted based on the difference value (ΔV) acquired by the difference acquisition unit (72) so that the oscillation information (IS) and the reference value (Vref) become the same.

[0085] In the oscillator circuit (100, 300) having any one of the first to third configurations, the inverter (2, 2A, 2B) has a configuration including a bridge circuit (21_1, 21_2, 21_3, 21_4, 21A) in which a high-side switching element (211) and a low-side switching element (212) are connected in series between a power supply terminal and a ground terminal; The gain adjustment section (5, 5A, 5B, 7) is configured (fourth configuration) to adjust the characteristics of at least one of the bridge circuits (21_1, 21_2, 21_3, 21_4, 21A).

[0086] In the oscillation circuit (100, 300) of the fourth configuration, the inverter (2) has a plurality of bridge circuits (22_1, 22_2, 22_3, 22_4) and is configured so that outputs of the bridge circuits (22_1, 22_2, 22_3, 22_4) are combined and output; The gain adjustment unit (5) is configured to switch on / off each of the bridge circuits (21_1, 21_2, 21_3, 21_4, 21A) (fifth configuration).

[0087] In the oscillation circuit (100, 300) of the fourth configuration, The high-side switching element (211) and the low-side switching element (212) are configured with MOS transistors, The gain adjustment units (5A, 5B, 7) are configured to adjust the gate voltages of the high-side switching element (211) and the low-side switching element (212) (sixth configuration).

[0088] In the oscillator circuit (100, 300) of the sixth configuration, a first bias adjustment switching element (26) configured to supply a bias voltage (Vb1) to the gate of the high-side switching element (211); a first current adjusting section (28) configured to adjust a current flowing through a first bias adjusting switching element (26); a second bias adjustment switching element (27) configured to supply a bias voltage (Vb2) to the gate of the low-side switching element (212); a second current adjusting section (29) configured to adjust a current flowing through a second bias adjusting switching element (27), the first bias adjustment switching element (26) is a diode-coupled MOS transistor, connected in series with the first current adjustment unit (28) between the power supply terminal and the ground terminal, and has a gate connected to the gate of the high-side switching element (211); the second bias adjustment switching element (27) is a diode-coupled MOS transistor, connected in series with the second current adjustment unit (29) between the power supply terminal and the ground terminal, and its gate is connected to the gate of the low-side switching element (212); The gain adjuster (5A, 7) is configured to control at least one of the first current adjuster (28) and the second current adjuster (29) (seventh configuration).

[0089] In the oscillator circuit (100, 300) of the sixth configuration, a first bias adjustment switching element (24B) arranged on a wiring that supplies a bias voltage (Vb1) to the gate of the high-side switching element (211); a second bias adjustment switching element (25B) configured to be disposed on a wiring that supplies a bias voltage (Vb2) to the gate of the low-side switching element (212); The gain adjustment section (5B, 7) is configured (eighth configuration) to control so as to adjust the resistance value of at least one of the first bias switching element (24B) and the second bias switching element (25B). [Explanation of symbols]

[0090] 100, 300 oscillator circuit 1 transducer 21_1~21_4, 21A bridge circuit 211 High-side switching element 212 Low-side switching element 213 First switching element 214 second switching element 2, 2A, 2B inverter 22, 23 Capacitor 24 Resistance 24B, 26 First bias adjustment switching element 25 Resistance 25B, 27 Second bias adjustment switching element 28 1st current adjustment section 29 2nd current adjustment section 31, 32 Load capacity 5, 5A, 5B Gain adjustment section 6 Temperature detection unit 7 Gain adjustment section 71 Feature detection unit 72 Difference acquisition part IN input terminal IS Oscillation Information OUT output terminal P1 connection point P2 connection point P3 connection point SOUT oscillation signal Th1 temperature information VIN power supply Vb1, Vb2 bias voltage Vref Reference voltage

Claims

1. an oscillator; an inverter connected in parallel with the oscillator and configured to be gain adjustable; a temperature detection unit configured to detect an ambient temperature; a gain adjustment unit configured to adjust the gain of the inverter, The oscillation circuit is configured so that the gain adjustment unit adjusts the gain of the inverter based on the temperature detected by the temperature detection unit.

2. an oscillator; an inverter connected in parallel with the oscillator and configured to be gain adjustable; and a gain adjustment unit configured to acquire oscillation information indicating characteristics of oscillation of an oscillation signal generated by the oscillator, and to adjust a gain of the inverter so that the oscillation information of the oscillation signal becomes the determined oscillation information.

3. the gain adjustment unit includes a feature detection unit configured to detect information about vibrations of the oscillation signal as oscillation information; a difference acquisition unit that acquires a difference value between the detected oscillation information and a predetermined reference value, The oscillation circuit according to claim 2 , configured to adjust a gain of the inverter based on the difference value acquired by the difference acquisition unit so that the oscillation information and the reference value become equal.

4. the inverter has a configuration including a bridge circuit in which a high-side switching element and a low-side switching element are connected in series between a power supply terminal and a ground terminal, 3. The oscillation circuit according to claim 1, wherein the gain adjustment section is configured to adjust the characteristics of the bridge circuit.

5. the inverter has a plurality of bridge circuits and is configured so that outputs of the bridge circuits are combined and output; The oscillation circuit according to claim 4 , wherein the gain adjustment section is configured to switch each bridge circuit on or off.

6. the high-side switching element and the low-side switching element are configured by MOS transistors, The oscillation circuit according to claim 4 , wherein the gain adjustment unit is configured to adjust gate voltages of the high-side switching element and the low-side switching element.

7. a first bias adjustment switching element configured to supply a bias voltage to a gate of the high-side switching element; a first current adjusting unit configured to adjust a current flowing through the first bias adjustment switching element; a second bias adjustment switching element configured to supply a bias voltage to a gate of the low-side switching element; a second current adjusting unit configured to adjust a current flowing through the second bias adjustment switching element, the first bias adjustment switching element is a diode-coupled MOS transistor, and is connected in series with the first current adjustment unit between a power supply terminal and a ground terminal, and has a gate connected to a gate of the high-side switching element; the second bias adjustment switching element is a diode-coupled MOS transistor, and is connected in series with the second current adjustment unit between a power supply terminal and a ground terminal, and has a gate connected to a gate of the low-side switching element; The oscillation circuit according to claim 5 , wherein the gain adjustment section is configured to control at least one of the first current adjustment section and the second current adjustment section.

8. a first bias adjustment switching element disposed on a wiring that supplies a bias voltage to the gate of the high-side switching element; a second bias adjustment switching element arranged on a wiring that supplies a bias voltage to the gate of the low-side switching element, 6. The oscillation circuit according to claim 5, wherein the gain adjustment section is configured to control so as to adjust a resistance value of at least one of the first bias adjustment switching element and the second bias adjustment switching element.

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