Memory device

Abstract

To improve detection accuracy of a void defect on a joint surface of a memory device having a joint structure.SOLUTION: A memory device of an embodiment has a bonding surface. The memory device includes a substrate, a first circuit layer, a second circuit layer, and a wiring layer. The first circuit layer is provided between the substrate and the bonding surface and includes a first circuit. The second circuit layer is provided above the bonding surface and includes a second circuit. The interconnect layer is provided above the second circuit layer and includes a plurality of first interconnects SL and PL and a plurality of second interconnects SH each extending in the first direction. The multiple first interconnects are electrically connected to at least one of the first circuit or the second circuit. The multiple second interconnects are electrically connected to each other. The first wiring and the second wiring are alternately arranged in a second direction intersecting with the first direction and along a substrate surface of the substrate.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-193108 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention improves the accuracy of detecting void defects on the junction surface of a memory device having a junction structure. [Means for solving the problem]

[0005] A memory device according to an embodiment has a bonding surface. The memory device includes a substrate, a first circuit layer, a second circuit layer, and a wiring layer. The first circuit layer is disposed between the substrate and the bonding surface and includes a first circuit. The second circuit layer is disposed above the bonding surface and includes a second circuit. The wiring layer is disposed above the second circuit layer and includes a plurality of first wirings and a plurality of second wirings, each extending in a first direction. The plurality of first wirings are electrically connected to at least one of the first circuit and the second circuit. The plurality of second wirings are electrically connected to each other. The first wirings and the second wirings are alternately arranged in a second direction that intersects the first direction and runs along the substrate surface of the substrate. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device according to an embodiment. [Figure 2]FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the embodiment. [Figure 3] FIG. 1 is a perspective view showing an example of the appearance of a memory device according to an embodiment. [Figure 4] FIG. 1 is a plan view showing an example of a planar layout of a memory device according to an embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout in a core region of a memory cell array included in the memory device according to the embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure in a memory region of a memory cell array included in the memory device according to the embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the embodiment. [Figure 8] FIG. 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to an embodiment. [Figure 9] FIG. 2 is a plan view showing an example of a planar layout of wiring layers in a memory device according to the embodiment. [Figure 10] FIG. 2 is a plan view showing an example of a planar layout of source lines, power supply lines, and shield lines in a memory device according to the embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of the cross-sectional structure of the shield wire SH and its vicinity included in the memory device according to the embodiment. [Figure 12] 12 is a cross-sectional view taken along line XII-XII in FIG. 10, showing an example of the cross-sectional structure of the shield wire SH and its vicinity included in the memory device according to the embodiment. [Figure 13] 1A to 1C are schematic diagrams illustrating an overview of a method for manufacturing a memory device according to an embodiment. [Figure 14] FIG. 1 is a plan view illustrating a method for testing a memory device according to an embodiment. [Figure 15] FIG. 1 is a cross-sectional view showing an example of a void defect that occurs in a memory device having a junction structure. [Figure 16]FIG. 10 is a plan view showing an example of a planar layout of wiring layers in a memory device according to a comparative example. [Figure 17] FIG. 10 is a plan view showing an example of a planar layout of source lines, power supply lines, and shield lines in a memory device according to a first modified example of the embodiment. [Figure 18] FIG. 10 is a plan view showing an example of a planar layout of source lines, power supply lines, and shield lines in a memory device according to a second modified example of the embodiment. [Figure 19] FIG. 2 is a cross-sectional view showing an example of a detailed cross-sectional structure of the vicinity of two bond pads arranged opposite to each other in a memory device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The embodiments illustrate devices and methods for embodying the technical ideas of the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. Illustrations of components are omitted as appropriate. Hatching added to plan views does not necessarily relate to the material or characteristics of the components. In this specification, components having substantially the same functions and configurations are assigned the same reference symbols. Numbers and letters added to reference symbols are used to refer to the same reference symbols and to distinguish between similar elements.

[0008] <1> composition First, the configuration of a memory device 1 according to the embodiment will be described.

[0009] <1-1> Overall configuration of memory device 1 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device 1 according to an embodiment. As shown in FIG. 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0010] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes a plurality of pages. A page corresponds to a unit in which data is read and written. Although not shown, the memory cell array 10 is provided with a plurality of bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and a plurality of word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0011] The input / output circuit 11 is an interface circuit that controls transmission and reception of input / output signals to and from the memory controller 2. The input / output signals include, for example, data DAT, status information, address information, commands, etc. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0012] The logic controller 12 controls each of the input / output circuit 11 and the sequencer 14 based on the control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command, address information, or the like. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signal.

[0013] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated under the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes a block address, a page address, a column address, etc. The commands include instructions for various operations of the memory device 1.

[0014] The sequencer 14 controls the overall operation of the memory device 1. Based on the command and address information stored in the register circuit 13, the sequencer 14 executes read operations, write operations, erase operations, and the like.

[0015] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, etc.

[0016] The row decoder module 16 is a circuit used to select a block BLK to be operated and to transfer a voltage to wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively, and are used to select the blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0017] The sense amplifier module 17 is a circuit used to transfer voltages to each bit line BL and to read data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding data, and the like.

[0018] The combination of the memory device 1 and the memory controller 2 may constitute one semiconductor device. TM Examples include memory cards and solid state drives (SSDs).

[0019] <1-2> Circuit configuration of memory cell array 10 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in a memory device 1 according to the embodiment. Fig. 2 shows two blocks BLK0 and BLK1 among a plurality of blocks BLK included in the memory cell array 10. As shown in Fig. 2, in the memory cell array 10, select gate lines SGD and SGS and word lines WL0 to WL(N-1) (N is an integer of 2 or more) are provided for each block BLK. Bit lines BL0 to BLm and source lines SL are shared by, for example, a plurality of blocks BLK.

[0020] Each block BLK includes multiple NAND strings NS. The multiple NAND strings NS are associated with bit lines BL0 to BLm, respectively. In other words, each bit line BL is shared among multiple blocks BLK by NAND strings NS assigned the same column address. Each NAND string NS is connected between the associated bit line BL and source line SL. Each NAND string NS includes, for example, N memory cell transistors MT0 to MT(N-1) and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and retains (stores) data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the block BLK.

[0021] In each NAND string NS, a select transistor ST1, memory cell transistors MT(N-1) to MT0, and a select transistor ST2 are connected in series in this order. Specifically, the drain and source terminals of the select transistor ST1 are connected to the associated bit line BL and the drain terminal of the memory cell transistor MT(N-1), respectively. The drain and source terminals of the select transistor ST2 are connected to the source terminal of the memory cell transistor MT0 and the source line SL, respectively. The memory cell transistors MT0 to MT(N-1) are connected in series between the select transistors ST1 and ST2.

[0022] Each select gate line SGD is connected to the gate terminal of each of the select transistors ST1 included in the associated block BLK. Each select gate line SGS is connected to the gate terminal of each of the select transistors ST2 included in the associated block BLK. Word lines WL0 to WL(N-1) are connected to the control gate terminals of each of the memory cell transistors MT0 to MT(N-1) included in the associated block BLK. A "page" corresponds to a set of memory cell transistors MT connected to a common word line WL within the same block BLK. A set of memory cell transistors MT connected to a common word line WL within the same block BLK can have a storage capacity of two or more pages of data depending on the number of bits stored in the memory cell transistors MT.

[0023] The memory cell array 10 may have other circuit configurations. For example, each block BLK may be provided with a plurality of independently controllable select gate lines SGD. In this case, each block BLK is configured to be selectable in units of a plurality of units each associated with a plurality of select gate lines SGD.

[0024] In the following, the memory device 1 according to the embodiment will be described taking as an example a case where each NAND string NS has eight memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7, respectively (that is, a case where N=8).

[0025] <1-3> Structure of memory device 1 The structure of the memory device 1 according to the embodiment will be described below.

[0026] In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the reference semiconductor substrate. "Up and down" are defined based on the direction along the Z direction. The positive direction (up) corresponds to the direction away from the reference semiconductor substrate. The XY plane (cross section) corresponds to a plane (cross section) parallel to each of the X and Y directions. The YZ cross section corresponds to a cross section parallel to each of the Y and Z directions. The XZ cross section corresponds to a cross section parallel to each of the X and Z directions.

[0027] (1: Appearance of memory device 1) First, the appearance of the memory device 1 according to the embodiment will be described. The memory device 1 according to the embodiment is formed by bonding two semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. That is, the memory device 1 according to the embodiment has a bonding surface formed by bonding semiconductor substrates W1 and W2. Each of the semiconductor substrates W1 and W2 is a silicon substrate. Below, a case will be described in which the semiconductor substrate W2 is removed during the manufacturing process of the memory device 1. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after bonding the semiconductor substrates W1 and W2 together.

[0028] 3 is a perspective view showing an example of the appearance of the memory device 1 according to the embodiment. As shown in FIG. 3, the memory device 1 includes, for example, a semiconductor substrate W1, a CMOS layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300.

[0029] The CMOS layer 100 is disposed on a semiconductor substrate W1. The CMOS layer 100 includes a CMOS circuit (control circuit) formed using the semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions and the like according to the design of the CMOS circuit. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17. The CMOS layer 100 may also be referred to as a circuit layer.

[0030] The bonding layer B1 is disposed on the CMOS layer 100. The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to a CMOS circuit provided in the CMOS layer 100 and form part of the semiconductor circuit.

[0031] The bonding layer B2 is disposed on the bonding layer B1. The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 provided in the memory layer 200 and form part of a semiconductor circuit. The plurality of bonding pads included in the bonding layer B2 are respectively connected to the plurality of bonding pads included in the bonding layer B1. The space between the bonding layers B1 and B2 corresponds to the boundary, i.e., the bonding surface, between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2.

[0032] The memory layer 200 is disposed on the bonding layer B2. The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2. The memory layer 200 may also be called a circuit layer.

[0033] The wiring layer 300 is disposed on the memory layer 200. The wiring layer 300 is formed after bonding the semiconductor substrates W1 and W2 together. The wiring layer 300 includes wiring connected to a semiconductor circuit provided in the memory layer 200 and a plurality of pads PD. The plurality of pads PD are exposed on the surface of the memory device 1. The plurality of pads PD are used to connect the memory device 1 to the memory controller 2 and the like, to supply power, and the like.

[0034] (2: Planar layout of memory device 1) 4 is a plan view showing an example of the planar layout of the memory device 1 according to the embodiment. As shown in Fig. 4, the memory device 1 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a kerf region KR.

[0035] The core region CR is, for example, a rectangular region provided near the center of the semiconductor substrate W1. In the core region CR, for example, a memory cell array 10, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17 are arranged.

[0036] The peripheral region PR is a quadrangular ring-shaped region provided so as to surround the outer periphery of the core region CR. In the peripheral region PR, for example, an input / output circuit 11, a logic controller 12, etc. are arranged. In addition, in the peripheral region PR, for example, contacts for connecting wiring provided in the wiring layer 300 with circuits provided in the CMOS layer 100 and the memory layer 200, etc. are arranged.

[0037] The wall region WR is a quadrangular ring-shaped region provided so as to surround the outer periphery of the peripheral region PR. At least one sealing portion ES (not shown) is arranged in the wall region WR so as to surround the outer periphery of the peripheral region PR. Details of the sealing portion ES will be described later. The kerf region KR is a quadrangular ring-shaped region provided to surround the outer periphery of the wall region WR. The kerf region KR is in contact with the outermost periphery of the memory device 1. For example, alignment marks used in manufacturing the memory device 1 are arranged in the kerf region KR. The structure of the kerf region KR may be removed by a dicing process described later.

[0038] (3: Planar layout of memory cell array 10) 5 is a plan view showing an example of a planar layout of a core region CR of a memory cell array 10 included in a memory device 1 according to the embodiment. As shown in FIG. 5, the memory cell array 10 includes a plurality of slits SLT, a plurality of memory pillars MP, and a plurality of contacts CV and CC. The memory cell array 10 also includes, for example, memory regions MA and contact regions CA aligned in the X direction.

[0039] Each slit SLT is a plate-like member extending along the X direction. Each slit SLT has a portion extending along the X direction and crosses the memory area MA and the contact area CA along the X direction. Multiple slits SLT are aligned in the Y direction. Each slit SLT separates adjacent wirings (e.g., word lines WL0 to WL7 and select gate lines SGD and SGS) through the slit SLT. In each slit SLT, a conductor with an insulating spacer on its sidewall may be arranged insulated from the wirings, or an insulator may be embedded. In the memory cell array 10, each of the regions partitioned along the Y direction by the slits SLT corresponds to one block BLK.

[0040] The memory area MA is an area used for storing data. A plurality of memory pillars MP are arranged in the memory area MA. Each memory pillar MP is, for example, a pillar-shaped component that functions as one NAND string NS. The plurality of memory pillars MP are arranged in a grid pattern for each block BLK. At least one bit line BL is arranged to overlap each memory pillar MP. Each of the plurality of bit lines BL has a portion extending in the Y direction and is aligned in the X direction. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The associated memory pillar MP and bit line BL are electrically connected via contacts CV.

[0041] The contact area CA is an area used for connecting stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) included in the memory cell array 10 to the row decoder module 16. In the contact area CA, a plurality of contacts CC are arranged for each block BLK. For each block BLK, each of the plurality of contacts CC is electrically connected to an associated one of the stacked wirings. In each block BLK, at least one contact CC is electrically connected to each of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. Note that in the contact area CA, the plurality of contacts CC in each block BLK are not limited to being arranged in a line in the X direction as shown in FIG. 5, but may be arranged in a grid pattern for each block BLK.

[0042] (4: Cross-sectional structure of memory area MA of memory cell array 10) Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure in a memory region MA of the memory cell array 10 included in the memory device 1 according to the embodiment. Fig. 6 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and shows coordinate axes based on the semiconductor substrate W2. As shown in Fig. 6, the memory cell array 10 includes, in the memory region MA, for example, conductor layers 21-25, insulator layers 31-35, an insulating member 36, and contacts CV, V1, and V2.

[0043] A conductor layer 21 is provided on a semiconductor substrate W2. An insulator layer 31 is provided on the conductor layer 21. Conductor layers 22 and insulator layers 32 are alternately provided on the insulator layer 31. That is, a plurality of conductor layers 22 are arranged side by side in the Z direction. The number of conductor layers 22 corresponds to the number of layers of stacked wiring (select gate lines SGS, word lines WL, and select gate lines SGD). An insulator layer 33, a conductor layer 23, an insulator layer 34, and an insulator layer 35 are provided in this order on the uppermost conductor layer 22. Each of the conductor layers 21 and 22 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 23 has, for example, a portion formed in a line shape extending in the Y direction. The conductor layer 21 is used as a source line SL. In this example, ten conductor layers 22 arranged in the Z direction are used as, in order from the source line SL side, select gate lines SGS, word lines WL0 to WL7, and select gate lines SGD. Conductor layer 23 is used as bit lines BL. Conductor layer 21 contains, for example, polysilicon (Si). Conductor layer 22 contains, for example, tungsten (W). Conductor layer 23 contains, for example, copper (Cu).

[0044] A conductive layer 24 is provided above the conductive layer 23. The conductive layer 24 is a wiring that relays the connection between the bit line BL and the sense amplifier module 17. The conductive layer 23 and the conductive layer 24 are connected via a contact V1. A conductive layer 25 is provided above the conductive layer 24. The conductive layer 25 corresponds to a bonding pad. The conductive layer 24 and the conductive layer 25 are connected via a contact V2. Side surfaces of the conductive layer 24 and the contacts V1 and V2 are covered with an insulator layer 34. The insulator layer 34 may be composed of multiple insulating films. Side surfaces of the conductive layer 25 are covered with the insulator layer 35. The insulator layer 35 and the conductive layer 25 are included in the junction layer B2. The memory cell array 10 may include multiple conductive layers 24 and multiple conductive layers 25. The conductive layer 25 includes, for example, copper.

[0045] The insulating member 36 has a plate-like portion extending along the XZ plane. The insulating member 36 separates the insulating layer 31 from the alternately arranged conductor layers 22 and 32. In this example, the insulating member 36 is embedded in the slit SLT. A conductor having an insulating spacer on its side wall may be arranged in the slit SLT so as to be insulated from each of the conductor layers 21 and 22.

[0046] Each memory pillar MP extends along the Z direction, penetrates the insulator layer 31, and the alternately arranged conductor layers 22 and insulator layers 32, and is connected to the conductor layer 21. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is an insulator extending along the Z direction. The semiconductor layer 41 covers the core member 40. A portion of the side surface of the semiconductor layer 41 contacts the conductor layer 21. That is, the semiconductor layer 41 and the conductor layer 21 (source line SL) in the memory pillar MP are connected via the side surface of the memory pillar MP. The stacked film 42 covers the side surface and bottom surface of the semiconductor layer 41, except for the contact portion between the semiconductor layer 41 and the conductor layer 21. The associated semiconductor layer 41 (memory pillar MP) and the conductor layer 23 (bit line BL) are connected via a contact CV.

[0047] The portion where the conductive layer 22 used as the select gate line SGS intersects with the memory pillar MP functions as a select transistor ST2. The portion where the conductive layer 22 used as the word line WL intersects with the memory pillar MP functions as a memory cell transistor MT. The portion where the conductive layer 22 used as the select gate line SGD intersects with the memory pillar MP functions as a select transistor ST1. In each memory pillar MP, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 included in the NAND string NS.

[0048] (5: Cross-sectional structure of memory pillar MP) FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 , showing an example of the cross-sectional structure of a memory pillar MP included in the memory device 1 according to the embodiment. FIG. 6 illustrates a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2. As shown in FIG. 6 , the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 contains, for example, silicon oxide (SiO2). The insulating film 44 is used as a charge storage layer of the memory cell transistor MT. The insulating film 44 contains, for example, silicon nitride (SiN).

[0049] (6: Cross-sectional structure of memory device 1) FIG. 8 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the embodiment. FIG. 8 shows a portion of the core region CR, the peripheral region PR, and the wall region WR after the semiconductor substrates W1 and W2 are bonded, and indicates coordinate axes based on the semiconductor substrate W1. In this example, the semiconductor substrate W2 is removed after the bonding process of the semiconductor substrates W1 and W2. The memory layer 200 and the bonding layer B2 have a structure in the core region CR in which the structure related to the memory cell array 10 shown in FIG. 6 is vertically inverted. As shown in FIG. 8, the CMOS layer 100 includes an insulator layer 110. The bonding layer B1 includes an insulator layer 111. The memory layer 200 includes an insulator layer 210, a conductor layer 211, a sacrificial member 212, and a conductor layer 213. The wiring layer 300 includes an insulator layer 301 , an insulator layer 302 , a conductor layer 303 , an insulator layer 304 , an insulator layer 305 , and an insulator layer 306 .

[0050] The insulator layer 110 is provided on the semiconductor substrate W1. The insulator layer 110 covers at least a portion of the wiring, contacts, elements, etc. provided in the CMOS layer 100. The insulator layer 110 may be composed of multiple types of insulating films. The insulator layer 111 is provided on the insulator layer 110. The insulator layer 111 covers the side surfaces of the bonding pads provided on the bonding layer B1. The insulator layer 35 of the bonding layer B2 is provided on the insulator layer 111. The insulator layer 210 is provided on the insulator layer 35. The insulator layer 210 covers at least a portion of the wiring, contacts, elements, etc. provided in the memory layer 200. The insulator layer 210 may be composed of multiple types of insulating films and may include insulator layers 33 and 34. A conductor layer 211, a sacrificial member 212, and a conductor layer 213 are sequentially stacked on the insulator layer 210. The set of the conductor layer 211, the sacrificial member 212, and the conductor layer 213 is provided at the same height as the conductor layer 21. Specifically, the height of the lower surface of the conductor layer 211 is aligned with the height of the lower surface of the conductor layer 21 (source line SL). The height of the upper surface of the conductor layer 213 is aligned with the height of the upper surface of the conductor layer 21 (source line SL). The conductor layer 21 in the core region CR corresponds to a structure in which the conductor layer 211, the sacrificial member 212, and the conductor layer 213 are stacked, and then the sacrificial member 212 is replaced with a conductor. In other words, the height of the sacrificial member 212 is the same as the height at which the conductor layer 21 and the semiconductor layer 41 in each memory pillar MP are connected. Each of the conductor layers 211 and 213 contains, for example, polysilicon (Si). The sacrificial member 212 contains, for example, silicon nitride (SiN).

[0051] The insulator layer 301, the insulator layer 302, the conductor layer 303, the insulator layer 304, the insulator layer 305, and the insulator layer 306 are provided in this order on the conductor layer 213 and the conductor layer 21. The conductor layer 303 is divided (insulated) between the peripheral region PR and the wall region WR. The conductor layer 303 may be divided (insulated) between the core region CR and the peripheral region PR, or may be provided continuously. Each of the insulator layers 301, 302, and 304 includes, for example, a silicon oxide film (SiO2). The insulator layer 305 includes, for example, silicon nitride (SiN). The insulator layer 306 includes, for example, polyimide.

[0052] The wiring layer 300 includes a via VA in the core region CR, a via VB in the peripheral region PR, and a via VC in the wall region WR. The via VA penetrates the insulator layers 301 and 302. The conductive layer 303 in the core region CR may have a portion in contact with the conductive layer 21 through the via VA. The via VB penetrates the conductive layer 211, the sacrificial member 212, the conductive layer 213, and the insulator layers 301 and 302. The conductive layer 303 in the peripheral region PR may have a portion in contact with the contact C3 (described later) through the via VB. The portion of the conductive layer 303 provided in the via VB is insulated from the conductive layers 211 and 213 by the insulator layer 302. The via VC penetrates the conductive layer 211, the sacrificial member 212, the conductive layer 213, and the insulator layers 301 and 302. The conductive layer 303 in the wall region WR has a portion that contacts sealing portions ES1 and ES2 (described later) through the via VC. The portion of the conductive layer 303 provided in the via VC is insulated from the conductive layers 211 and 213 by the insulator layer 302.

[0053] In the core region CR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, and the junction layer B1 includes a conductive layer 105. The gate insulating film 101 is provided on a semiconductor substrate W1. The gate electrode 102 in the core region CR is provided on the gate insulating film 101 and is used as the gate electrode of the transistor TR1. The transistor TR1 is included in, for example, a sense amplifier module 17. The conductive layer 103 is a wiring layer above the gate electrode 102. The contact C0 connects the gate electrode 102 and the conductive layer 103. The contact C0 connects the impurity diffusion region of the transistor TR1 provided in the semiconductor substrate W1 to the conductive layer 103. The conductive layer 104 is a wiring layer provided at a height between the conductive layer 103 and the junction layer B1. The contact C2 is provided at a height between the conductive layer 103 and the junction layer B1. At least one conductor layer 103 is connected to a conductor layer 105 via at least one contact C2 and at least one conductor layer 104. The conductor layer 105 corresponds to a bonding pad disposed on the bonding layer B1. The conductor layer 105 is in contact with a conductor layer 25 disposed opposite the conductor layer 105 on the bonding layer B2. As a result, the semiconductor layer 41 in the core region CR is electrically connected to the transistor TR1 via the contact CV, the conductor layers 23 to 25 and 103 to 105, and the contacts CV, V1, V2, C1, and C2.

[0054] In the peripheral region PR, the CMOS layer 100, like the core region CR, includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, and the junction layer B1 includes a conductive layer 105. The gate electrode 102 in the peripheral region PR is used as the gate electrode of the transistor TR2. The transistor TR2 may be, for example, a transistor connected to a power supply line or a transistor included in the input / output circuit 11. In the peripheral region PR, the junction layer B2 includes a conductive layer 25, and the memory layer 200 includes conductive layers 24 and 26 and contacts V1, V2, and C3. The conductive layer 26 is a wiring provided in the same layer as the conductive layer 23. At least one contact C3 is provided on the conductive layer 26. The upper portion of each contact C3 reaches at least the height of the conductive layer 211. The upper portion of each contact C3 is covered with the conductive layer 303 and is electrically connected to the conductive layer 303. As a result, the conductive layer 303 in the peripheral region PR is electrically connected to the transistor TR2 via at least one contact C3, the conductive layers 24 to 26 and 103 to 105, and the contacts V1, V2, C1, and C2.

[0055] In the wall region WR, the memory device 1 includes contacts C1W, C2W, C3W, V1W, and V2W and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W for each of the sealing portions ES1 and ES2. The contacts C1W, C2W, C3W, V1W, and V2W are provided in the same layer as the contacts C1, C2, C3, V1, and V2, respectively. The conductive layers 103W, 104W, 105W, 24W, 25W, and 26W are provided in the same layer as the conductive layers 103, 104, 105, 24, 25, and 26, respectively. Although not shown, the sets of contacts C1W, C2W, C3W, V1W, and V2W and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W are arranged in an annular shape in a plan view. That is, each of sealing portions ES1 and ES2 is arranged in a quadrangular annular shape in the wall region WR so as to surround the outer periphery of the core region CR and surround the peripheral region PR. The sealing portion ES2 is arranged outside the sealing portion ES1.

[0056] In the wall region WR, the semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is a diffusion region of P-type impurities (p + The N-type well region NW is a diffusion region of N-type impurities provided in the vicinity of the upper surface of the semiconductor substrate W1 (n + The P-type well region PW and the N-type well region NW correspond to the sealing portions ES1 and ES2, respectively. The conductive layer 303 in the wall region WR is connected to the P-type well region PW via contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing portion ES1 and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W. The conductive layer 303 in the wall region WR is connected to the N-type well region NW via contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing portion ES2 and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W.

[0057] The sealing portions ES1 and ES2 described above are structures that can release positive and negative charges generated inside and outside the wall region WR to the semiconductor substrate W1. Furthermore, each of the sealing portions ES1 and ES2 can prevent moisture and the like from penetrating from the outside of the wall region WR into the core region CR. Each of the sealing portions ES1 and ES2 can suppress stress generated in an interlayer insulating film (e.g., tetraethoxysilane (TEOS)) of the memory device 1. Furthermore, each of the sealing portions ES1 and ES2 can also be used as a crack stopper.

[0058] (7: Planar layout of wiring layer 300) 9 is a plan view showing an example of a planar layout of the wiring layer 300 in the memory device 1 according to the embodiment. FIG. 9 shows the core region CR, the peripheral region PR, the wall region WR, and some of the wiring and pads PD. As shown in FIG. 9, in the wall region WR, the sealing portion ES1 is provided so as to surround the outer periphery of the core region CR and the peripheral region PR. The sealing portion ES2 is provided so as to surround the outer periphery of the sealing portion ES1.

[0059] The peripheral region PR includes sub-regions SPR1 and SPR2. Each of the sub-regions SPR1 and SPR2 extends along the X direction. The sub-regions SPR1 and SPR2 sandwich the core region CR in the Y direction. A plurality of conductor layers 303 are arranged inside the wall region WR. Each of the plurality of conductor layers 303 has a portion extending in the Y direction. The plurality of conductor layers 303 are aligned in the X direction.

[0060] The multiple conductive layers 303 include a conductive layer 303A used as part of the source line SL, a conductive layer 303B used as part of the power line PL, and a conductive layer 303C used as part of the shield line SH. The conductive layer 303A overlaps the core region CR and the sub-region SPR1. The conductive layer 303B overlaps the core region CR and the sub-regions SPR1 and SPR2. The conductive layer 303C overlaps the core region CR and the sub-regions SPR1 and SPR2.

[0061] The conductor layers 303C are arranged every other one of the plurality of conductor layers 303 arranged in the X direction. The conductor layer 303A is arranged between two conductor layers 303C adjacent to each other in the X direction. The conductor layer 303B is arranged between two conductor layers 303C adjacent to each other in the X direction. The conductor layer 303A and the conductor layer 303B are arranged so as not to be adjacent to each other between two conductor layers 303C adjacent to each other in the X direction. In other words, the conductor layer 303A is arranged at the (4×k)th position of the plurality of conductor layers 303 arranged in the X direction. The conductor layer 303B is arranged at the (4×k-2)th position of the plurality of conductor layers 303 arranged in the X direction. The conductor layer 303C is arranged at the (2×k-1)th position (k is an integer greater than or equal to 1) of the plurality of conductor layers 303 arranged in the X direction. The type of the conductive layers 303 disposed on both ends in the X direction may be any of the conductive layers 303A, 303B, and 303C.

[0062] The pads PD are arranged, for example, between the core region CR and the sub-region SPR2. One pad PD is connected to each conductive layer 303B. A power supply voltage, a ground voltage, etc. are applied to the pads PD connected to the conductive layers 303B. One pad PD is connected to at least one conductive layer 303C. Pads PDs not shown may be connected to the input / output circuit 11, the logic controller 12, etc. Alternatively, a pad PD may be connected to the conductive layer 303A.

[0063] (8: Planar layout of source line SL, power line PL, and shield line SH) 10 is a plan view showing an example of the planar layout of source lines SL, power lines PL, and shield lines SH in a memory device 1 according to the embodiment. As shown in FIG. 10, each conductor layer 303A is connected to a via VB in the sub-region SPR1 and to a via VA in the core region CR. Each conductor layer 303B is connected to a via VB in each of the sub-regions SPR1 and SPR2. Multiple conductor layers 303C are electrically connected using multiple conductor layers 213 provided separately from each other in the same layer. Specifically, two conductor layers 303C (shield lines SH) adjacent in the X direction are electrically connected via the conductor layer 213.

[0064] More specifically, among the multiple conductor layers 303C aligned in the X direction, the conductor layer 303C arranged at the (2×i-1)th position (i is an integer equal to or greater than 1) from the end and the conductor layer 303C arranged at the (2×i)th position from the end are connected via the conductor layer 213 arranged between the core region CR and the subregion SPR2. The conductor layer 303C arranged at the (2×i)th position from the end and the conductor layer 303C arranged at the (2×i+1)th position from the end are connected via the conductor layer 213 arranged between the core region CR and the subregion SPR1.

[0065] In other words, the conductor layer 303C arranged at the (2×i-1)th position from the end in the X direction and the conductor layer 303C arranged at the (2×i)th position are electrically connected via the conductor layer 213 in the region on the sub-region SPR2 side outside the core region CR, and the conductor layer 303C arranged at the (2×i+1)th position are electrically connected via the conductor layer 213 in the region on the sub-region SPR1 side outside the core region CR.

[0066] Note that in the memory device 1, the arrangement of the sub-regions SPR1 and SPR2 may be interchanged. The associated conductor layer 213 and conductor layer 303C are connected through vias VA. In this way, the multiple conductor layers 303C aligned in the X direction are electrically connected by alternately using the conductor layer 213 provided on one side in the Y direction and the conductor layer 213 provided on the other side in the Y direction. In other words, the multiple conductor layers 303C are short-circuited to each other through the conductor layer 213 provided in a layer different from the wiring layer 300.

[0067] (9: Cross-sectional structure of the shielded wire SH and its surrounding area) FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 , showing an example of the cross-sectional structure of the shield line SH and its vicinity included in the memory device 1 according to the embodiment. As shown in FIG. 11 , the conductor layer 303C is disposed above the conductor layer 21 in the core region CR and is connected to the conductor layer 213 through a via VA in the peripheral region PR. The conductor layer 213 is divided into the shape shown in FIG. 10 by a dividing portion DP. The dividing portion DP divides the conductor layer 211, the sacrificial member 212, and the conductor layer 213. The dividing portion DP electrically separates the conductor layer 21 (source line SL) provided in the core region CR from the conductor layers 213 and 211 provided in the peripheral region PR. The dividing portion DP is formed, for example, after the formation of the insulating layer 301. An insulating layer 302 is embedded in the dividing portion DP. Note that the dividing portion DP may include a void.

[0068] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 10 , showing an example of the cross-sectional structure of the shield line SH and its vicinity included in the memory device 1 according to the embodiment. As shown in FIG. 12 , the conductor layer 213 connected to the shield line SH has two different conductor layers 303C connected to one end and the other end in the X direction via vias VA. A conductor layer 303A used as part of a source line SL or a conductor layer 303B used as part of a power line PL may be disposed above the conductor layer 213 connected to the shield line SH. In this way, depending on the layout of the multiple conductor layers 303, either the conductor layers 303A or 303B may overlap in the Z direction on the conductor layer 213 connected to the shield line SH (conductor layer 303C), and may be disposed so as to intersect with each other in the planar layout shown in FIG. 10 , for example.

[0069] <2> Manufacturing method Next, a method for manufacturing the memory device 1 according to the embodiment will be described.

[0070] <2-1> Overview of the manufacturing method of memory device 1 13 is a schematic diagram showing an overview of a manufacturing method for the memory device 1 according to the embodiment. Below, a rough processing flow in the manufacturing method for the memory device 1 will be described with reference to FIG.

[0071] First, semiconductor substrates W1 and W2 are prepared. Then, an exposure process, an etching process, etc. are performed on the semiconductor substrate W1, and a CMOS layer 100 and a bonding layer B1 are formed on the semiconductor substrate W1. Similarly, an exposure process, an etching process, etc. are performed on the semiconductor substrate W2, and a memory layer 200 and a bonding layer B2 are formed on the semiconductor substrate W2. The exposure process is a process of transferring a pattern of a mask (reticle) to a resist material on a wafer in shot units. A "shot" corresponds to a partitioned area of ​​exposure in the exposure process. In the exposure process, one shot of exposure is repeatedly performed with the position shifted. The shot arrangement of the semiconductor substrate W1 and the shot arrangement of the semiconductor substrate W2 are set to be the same.

[0072] Thereafter, a bonding process for bonding the semiconductor substrates W1 and W2 is performed. As a result, the front surface (bonding layer B1) of the semiconductor substrate W1 and the front surface (bonding layer B2) of the semiconductor substrate W2 are bonded together. Then, for example, after the semiconductor substrate W2 is removed, a wiring process is performed. In the wiring process, wiring (e.g., the conductor layer 303) and pads PD used for external connection with the circuit formed using the semiconductor substrates W1 and W2 are formed. The series of processes described above corresponds to the pre-process.

[0073] The semiconductor substrate W1 after the pre-processing has multiple memory devices 1. A test process is performed on these memory devices 1 to determine whether or not any defects have occurred in the memory devices 1 of the semiconductor substrate W1. After that, a dicing process is performed. The dicing process is a process of separating the semiconductor substrate W1 (wafer) into memory device 1 chip units by cutting the semiconductor substrate W1 (wafer) based on the shots and the arrangement of the memory devices 1 within the shots. This results in the formation of one memory device 1 chip. The memory device 1 chips are classified as non-defective or not based on the results of the test process.

[0074] <2-2> Overview of the test method FIG. 14 is a plan view for explaining an outline of a test method for a memory device 1 according to an embodiment. FIG. 14 illustrates a case where a defect occurs in a conductor layer 303 in the planar layout of the memory device 1 shown in FIG. 10. As shown in FIG. 14, a short defect can occur between adjacent conductor layers 303A (source line SL) and 303C (shield line SH), or between adjacent conductor layers 303B (power line PL) and 303C (shield line SH). An open defect can occur in each of the conductor layers 303A, 303B, and 303C, straddling the multiple conductor layers 303 aligned in the X direction.

[0075] In this example, the conductive layers 303A are electrically connected via the conductive layer 21 (not shown). The conductive layers 303C are also electrically connected. Therefore, a short defect between adjacent conductive layers 303A and 303C can be detected by checking the continuity between the source line SL and the shield line SH in the test process.

[0076] On the other hand, each conductor layer 303B is independent of the other. Therefore, a short defect between adjacent conductor layers 303B and 303C can be detected by checking the continuity between each power line PL and shield line SH in the test process.

[0077] Furthermore, if an open defect occurs in any of the conductive layers 303A, 303B, or 303C, the current-voltage characteristics of the shielding wire SH change. Therefore, an open defect in each conductive layer 303 can be detected, for example, by charging the shielding wire SH during a test process and then detecting the discharge rate of the charged shielding wire SH.

[0078] <3> Effects of the embodiment According to the embodiment, it is possible to improve the accuracy of detecting void defects on the bonding surface of the memory device 1 having a bonding structure. The effects of the embodiment will be described in detail below.

[0079] When a dicing process is performed on a semiconductor substrate with void defects at the bonding surface, there is a risk of contamination of the equipment. For this reason, ultrasonic and optical inspections are performed on all wafers in advance to detect void defects at the bonding surface and screen out wafers with voids. However, inspecting all wafers places a heavy load on the inspection equipment. To reduce the load on the inspection equipment, it is desirable to also perform detection using a die sort (D / S) test, but voids may occur in places that cannot be detected by die sort.

[0080] FIG. 15 is a cross-sectional view showing an example of a void defect that occurs in a memory device having a junction structure. FIG. 15 illustrates a case where a void (film floating void) occurs between the junction layer B1 and the junction layer B2 corresponding to the junction surface. In such a case, a convex portion that conforms to the shape of the void may be formed in the junction layer B2, the memory layer 200, and the wiring layer 300. Such a convex portion may cause defocusing in the lithography process when forming the wiring layer 300. Therefore, when a defect caused by defocusing (e.g., a short defect and an open defect) in the wiring layer 300 is detected in the inspection process, it can be assumed that a void defect has occurred in the junction surface.

[0081] FIG. 16 is a plan view showing an example of the planar layout of the wiring layer 300 in a memory device 1Z according to a comparative example. As shown in FIG. 16, the memory device 1Z has a configuration in which the conductor layer 303C (shield line SH) is omitted from the layout of the memory device 1 shown in FIG. 9. In the layout of the conductor layer 303 in the memory device 1Z, the power supply lines PL and the source lines SL are alternately arranged. Therefore, a short defect between adjacent power supply lines PL and source lines SL can be detected by checking whether the source lines SL and the power supply lines PL are electrically connected. On the other hand, in the comparative example, it is difficult to detect an open defect occurring in either the power supply line PL or the source line SL. As such, even if defocusing occurs due to voids at the junction surface, it may be difficult to detect the voids at the junction surface by die sorting.

[0082] In contrast, in the memory device 1 according to the embodiment, shield lines SH (conductor layer 303C) for detecting open defects / short defects caused by voids are added to the wiring layer 300. The shield lines SH are arranged alternately with the source lines SL or power supply lines PL. The multiple shield lines SH aligned in the X direction are electrically connected to each other.

[0083] As a result, a short defect between the source line SL and the shield line SH can be detected by checking whether adjacent source lines SL and shield lines SH are conductive. Also, a short defect between the power line PL and the shield line SH can be detected by checking whether adjacent power line PL and shield line SH are conductive. Furthermore, by checking the electrical characteristics of the shield line SH after charging using the pad PD provided in association with the shield line SH (the conductive layer 303C), it can be confirmed whether an open defect has occurred in the multiple conductive layers 303.

[0084] As a result, in the memory device 1 according to the embodiment, it is possible to detect whether or not a short defect and / or an open defect has occurred in the wiring layer 300 through a test process using the plurality of conductive layers 303. In this way, the memory device 1 according to the embodiment can improve the detection accuracy of void defects on the bonding surface of the memory device 1 having a bonding structure. Therefore, the memory device 1 according to the embodiment can detect void defects on the bonding surface that pose a risk in the dicing process, and can reduce the load (capacity, etc.) of in-line inspection.

[0085] <4> Variations, etc. The memory device 1 described above can be modified in various ways.

[0086] (First Modification) 17 is a plan view showing an example of the planar layout of the source lines SL, power supply lines PL, and shield lines SH in a memory device 1A according to a first modified example of the embodiment. FIG. 17 shows an extracted configuration similar to that of FIG. 10. As shown in FIG. 17, the memory device 1A differs from the memory device 1 in the arrangement of the subregions SPR1 and SPR2. Specifically, in the memory device 1A, the subregion SPR1 is arranged between the core region CR and a plurality of conductor layers 213 arranged on one end side in the Y direction (the upper side of the paper). Furthermore, in the memory device 1A, the subregion SPR2 is arranged between the core region CR and a plurality of conductor layers 213 arranged on the other end side in the Y direction (the lower side of the paper). In this way, the arrangements of the subregions SPR1 and SPR2 may be changed.

[0087] (Second Modification) 18 is a plan view showing an example of a planar layout of source lines, power supply lines, and shield lines in a memory device 1B according to a second modified example of the embodiment. FIG. 18 shows an extracted configuration similar to that in FIG. 9. As shown in FIG. 18, the memory device 1B has a different shape of the conductor layer 303C from the memory device 1. Specifically, the conductor layer 303C in the memory device 1B has a structure in which the multiple conductor layers 303C shown in FIG. 9 are continuously provided in the same layer with the peripheral region PR interposed therebetween.

[0088] Specifically, in the memory device 1B, the portion of the conductive layer 303C arranged at the (2×i−1)th position (i is an integer greater than or equal to 1) from the end in the X direction and the portion of the conductive layer 303C arranged at the (2×i)th position are continuously provided along the end of the conductive layer 303B (the lower side of the drawing). In addition, in the memory device 1B, the portion of the conductive layer 303C arranged at the (2×i)th position from the end in the X direction and the portion of the conductive layer 303C arranged at the (2×i+1)th position are continuously provided along the end of the conductive layer 303A (the upper side of the drawing). That is, in this example, the multiple portions of the conductive layer 303C extending in the Y direction and aligned in the X direction are continuously provided with alternating first portions provided along one end of either the conductive layers 303A or 303B and second portions provided along the other end of either the conductive layers 303A or 303B interposed therebetween. In this way, the conductive layer 303C may be provided integrally without using the conductive layer 213.

[0089] (others) FIG. 19 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bond pads in a memory device 1 according to the embodiment. FIG. 19 shows a conductive layer 105 (bond pad) formed using a semiconductor substrate W1 (not shown), a conductive layer 25 (bond pad) formed using a semiconductor substrate W2 (not shown), some contacts C2 and V2 connected thereto, and conductive layers 104 and 24. As shown in FIG. 19, the two opposing bond pads may have different tapered shapes based on the etching direction during formation. Specifically, the conductive layer 105 formed using the semiconductor substrate W1 has, for example, an inverse tapered shape. The conductive layer 25 formed using the semiconductor substrate W2 has, for example, a tapered shape. Therefore, the cross-sectional shape along the Z direction at the bonded portion of the conductive layer 105 and the conductive layer 25 may have a non-rectangular shape rather than a linear sidewall. Furthermore, the pair of opposing bond pads may be misaligned during bonding depending on the alignment during the bonding process. Therefore, a step may be formed between the side of the conductive layer 105 and the side of the conductive layer 25. The pair of two bond pads arranged opposite each other may have a boundary or may be integrated. The bond pads and the contacts C2, V2 connected to the bond pads may be formed integrally. A plurality of corresponding contacts C2, V2 may be connected to the bond pads. For example, the conductive layer 105 may be connected to the conductive layer 104 via a plurality of contacts C2. Similarly, the conductive layer 25 may be connected to the conductive layer 24 via a plurality of contacts V2.

[0090] In the embodiment, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 may be modified as appropriate. Other contacts may be inserted between the memory pillar MP and the conductive layer 23. Other contacts may be inserted between the contact C3 and the conductive layer 26. A conductive layer may be inserted at the connection portion between multiple contacts. The number of wiring layers and contacts included in the memory device 1 may be modified as appropriate depending on the circuit design. The memory pillar MP and each contact may have a tapered shape, an inverted tapered shape, or a bowing shape. The XY cross-sectional structure of the memory pillar MP may be circular or elliptical. Each wiring in the stacked wiring may include a metal oxide film around a conductor such as tungsten. The conductive layers alternately stacked with insulator layers in the stacked wiring may be considered to have such a metal oxide film.

[0091] In this specification, "connection" refers to electrical connection and does not exclude, for example, the presence of another element therebetween. "Electrically connected" may also refer to an insulator as long as it operates similarly to an electrically connected element. A "semiconductor substrate" may simply be referred to as a "substrate." A "semiconductor layer" may also be referred to as a "conductor layer." A "region" may be considered a structure contained in a substrate. For example, if a semiconductor substrate W1 is defined to include a memory region MA and a contact region CA, the memory region MA and the contact region CA are respectively associated with different regions above the semiconductor substrate W1. "Height" corresponds, for example, to the distance in the Z direction between the structure to be measured and the semiconductor substrate W1. A structure other than the semiconductor substrate W1 may also be used as the basis for "height." A "top (planar) view" corresponds, for example, to viewing the surface of the semiconductor substrate W1 from the vertical direction of the semiconductor substrate W1.

[0092] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0093] 1, 1A, 1B, 1Z... memory device, 2... memory controller, 10... memory cell array, 11... input / output circuit, 12... logic controller, 13... register circuit, 14... sequencer, 15... driver circuit, 16... row decoder module, 17... sense amplifier module, 21 to 26, 24W, 25W, 26W, 103 to 105, 103W, 104W, 105W, 211, 213, 303, 303A, 303B, 303C... conductive layer, 31 to 35, 110, 111, 210, 301, 302, 304 to 306... insulating layer, 36... insulating member, 40... core member, 41... semiconductor layer, 42... stacked film, 43... tunnel insulating film, 4 4...insulating film, 45...block insulating film, 100...CMOS layer, 101...gate insulating film, 102...gate electrode, 200...memory layer, 212...sacrificial member, 300...wiring layer, V1, V2, C0 to C3, C1W, C2W, C3W...contacts, ES1, ES2...sealing portion, B1, B2...bonding layer, CR...core region, PR...peripheral region, WR...wall region, KR...kerf region, SPR1, SPR2...sub-region, W1, W2...semiconductor substrate, BLK...block, BL...bit line, WL...word line, MT...memory cell transistor, ST1, ST2...select transistor, RD...row decoder, SAU...sense amplifier unit, TR1, TR2...transistor

Claims

1. 1. A memory device having a bonding surface, comprising: A substrate; a first circuit layer provided between the substrate and the bonding surface and including a first circuit; a second circuit layer provided above the bonding surface and including a second circuit; a wiring layer provided above the second circuit layer, the wiring layer including a plurality of first wirings and a plurality of second wirings each extending in a first direction; Equipped with the plurality of first wirings are electrically connected to at least one of the first circuit and the second circuit, and the plurality of second wirings are electrically connected to each other; the first wirings and the second wirings are alternately arranged in a second direction that intersects the first direction and runs along the surface of the substrate; Memory device.

2. the second circuit layer includes a plurality of first conductor layers provided separately from each other in the same layer; two second wirings adjacent to each other in the second direction are electrically connected via the first conductor layer; The memory device of claim 1 .

3. the plurality of second wirings are included in the wiring layer together with the plurality of second wirings, and are provided continuously with a plurality of first portions provided along one ends of the plurality of first wirings and a plurality of second portions provided along the other ends of the plurality of first wirings alternately interposed therebetween; The memory device of claim 1 .

4. the wiring layer further includes a pad having an exposed top surface, the pad being associated with one of the plurality of second wirings; The memory device of claim 1 .

5. a first pad provided adjacent to the bonding surface and electrically connected to the first circuit; a second pad provided adjacent to the bonding surface and electrically connected between the first pad and the second circuit; The direction of the taper of the first pad is different from the direction of the taper of the second pad. The memory device of claim 1 .

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