Core substrate and method for manufacturing core substrate

Abstract

To provide a through hole land for releasing gas generated from a hole filling resin of a through hole.SOLUTION: A core substrate of the present disclosure is a core substrate including a through hole that electrically connects both surfaces of the core substrate, wherein the through hole has a first conductive layer formed on an inner wall thereof, a second conductive layer formed inside the first conductive layer, and a resin filled inside the second conductive layer. A through hole land is formed in a portion where the through hole is exposed on the surface of the core substrate, and the through hole land includes a gas permeable region in a part of a region where the resin is exposed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a core substrate and a method for manufacturing the core substrate. [Background technology]

[0002] The semiconductor integrated circuit element is an area array type semiconductor integrated circuit element having a large number of electrode terminals arranged in a grid pattern over substantially the entire surface of one of its main surfaces, and flip-chip connection is used as a method for mounting such a semiconductor integrated circuit element on a wiring substrate. Furthermore, with the progress in the high integration of semiconductor integrated circuit elements, the density of area arrays is also becoming higher, and accordingly, wiring substrates for performing flip-chip connections are also required to have higher densities of electrodes for connecting to semiconductor integrated circuits. For this reason, SAP (Semi-Additive Process) is widely used as a method for forming wiring on wiring boards, particularly core boards using core materials, and there is a particular demand for miniaturization of through-holes and their surroundings.

[0003] Patent Document 1 discloses the following content as a printed wiring board and a method for manufacturing the same, in order to enable finer and denser wiring patterns on the board. "It comprises a substrate, insulating layers formed on both sides of the substrate, holes penetrating the substrate and the insulating layers, conductive layers formed to cover the inner surfaces of the holes, a filler material filling the holes except for the end faces of the conductive layers, and wiring layers connected to the end faces of the conductive layers and formed on the filler material and each of the insulating layers, the end faces of the conductive layers being formed at approximately the same position as the surface of the insulating layers or at a position closer to the substrate than the surface of the insulating layers." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123471 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, when forming a wiring layer above the through hole, a method is adopted in which a first plating layer formed on the substrate is removed to reduce the difference in elevation between the area above the through hole and the rest of the substrate. However, no consideration is given to the possibility that the filler material is then sealed by a second plating layer formed again above the through hole, and that gas generated from the filler material may cause problems with the wiring on the substrate. As a result, the effect is limited to reducing the difference in elevation between the area above the through hole and the rest of the substrate. Therefore, an object of the present invention is to provide a technique for suppressing problems caused by gas generated from the resin filling the through holes. [Means for solving the problem]

[0006] In order to solve the above problems, one of the representative core substrates of the present invention is: It has through holes that electrically connect both sides of the core board. the through hole has a first conductive layer formed on its inner wall, a second conductive layer formed inside the first conductive layer, and a resin filled inside the second conductive layer; A through-hole land is formed in the portion where the through-hole is exposed on the surface of the core substrate, and the through-hole land has a gas-permeable region in a part of the region where the resin is exposed. [Effects of the Invention]

[0007] According to the present invention, problems caused by gas generated from the resin filling the through holes can be suppressed. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments of the invention. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a diagram showing a schematic cross section of a core substrate of the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a through-hole land in a core substrate. [Figure 3] FIG. 3 is a diagram for explaining a comparison between a conventional through-hole land and the through-hole land of the first embodiment. [Figure 4] FIG. 4 is an explanatory diagram of the manufacturing flow of the core substrate of the first embodiment. [Figure 5] FIG. 5 is an explanatory diagram of the manufacturing flow of the core substrate of the first embodiment. [Figure 6] FIG. 6 is a diagram for explaining in detail the state of copper etching in the through-hole portion. [Figure 7] FIG. 7 is a diagram illustrating a core substrate that is the premise of the second embodiment. [Figure 8] FIG. 8 is a diagram for explaining the core substrate of the second embodiment. [Figure 9] FIG. 9 is a diagram illustrating a modified example of the through-hole land of the second embodiment. [Figure 10] FIG. 10 is a diagram showing the relationship between through-hole pitches among a plurality of adjacent through-holes. [Figure 11] FIG. 11 is a diagram showing an example in which through holes are arranged two-dimensionally. [Figure 12] FIG. 12 is an explanatory diagram of the manufacturing flow of the core substrate of the second embodiment that includes partially circular through-hole lands. [Figure 13] FIG. 13 is a cross-sectional view of a multilayer wiring board according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a multilayer wiring board according to the fourth embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor package according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are designated by the same reference numerals. When there are multiple components with the same or similar functions, they may be described using the same reference numeral with different subscripts. When there is no need to distinguish between these multiple components, the subscripts may be omitted. Furthermore, although terms such as "first," "second," and "third" may be used to describe various elements or components in this disclosure, it will be understood that these elements or components should not be limited by these terms. These terms are used only to distinguish one element or component from another. Thus, a first element or component discussed below could also be referred to as a second element or component without departing from the teachings of the inventive concept. In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member. The "upper surface" and "lower surface" may also be referred to as the "first surface" and "second surface."

[0011] The term "side surface" refers to a surface or thickness of a layer included in a plate-like member or a layer included in a plate-like member. Furthermore, a part of a surface and a side surface may be collectively referred to as an "edge portion." "Up" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "up" and its opposite, "down," are sometimes referred to as the "positive z-axis direction" and the "negative z-axis direction," and the horizontal direction is sometimes referred to as the "x-axis direction" and the "y-axis direction."

[0012] A "partial circle" refers to a shape in which a portion of a circular or donut-shaped ring shape has been removed, but an arc portion remains. The removed portion is called a "cutout portion." "Minimum safety distance" refers to the conductor gap (space) in the L / S (line and space rule) that is determined for each product and circuit to ensure insulation between conductors in fine electrical circuits.

[0013] First Embodiment (Core board structure) First, a cross-sectional configuration of a core substrate according to an embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a diagram showing an outline of a cross section of a core substrate according to an embodiment. The insulating material 10 that constitutes the core substrate 1 is made of glass epoxy, bismaleimide triazine resin (hereinafter referred to as "BT resin"), or the like, and has a thickness of 400 to 2000 micrometers. Core substrate 1 has through holes 30 formed therein for electrical conduction from first surface 100 to second surface 200 of core substrate 1. Through holes 30 have first electroless copper plating layer 21, which is a first conductive layer, and first electrolytic copper plating layer 22, which is a second conductive layer, on the side walls of the through holes provided in core substrate 1, and the through holes are further filled with hole-filling resin 40. The through-holes 30 have substantially circular through-hole lands 31 on each of the first surface 100 to the second surface 200 of the core substrate 1 . Through-hole land 31 is made of first electroless copper plating layer 21 and first electrolytic copper plating layer 22, and has a shape in which, in top view, a circular portion has a substantially circular opening 60 at the center where the conductor is removed. The bottom of opening 60 is filled with hole-filling resin 40.

[0014] Next, the configuration of the through-hole land 31 according to the embodiment of the present disclosure will be described with reference to FIG. Fig. 2 is a diagram showing an example of the configuration of a through-hole land 31 on a core substrate. Fig. 2(a) is a diagram (top view) of a portion of a through-hole land 31 formed on the core substrate as viewed from the positive direction of the z-axis of the core substrate, and Fig. 2(b) is a diagram showing the cross-sectional structure of a through-hole 30 including the through-hole land 31 formed on the core substrate. Note that the bottom of Fig. 2(a) shows the top view of the cross-sectional structure taken along line LL in Fig. 2(b).

[0015] 2(a), the through-hole 30 is a through-hole DL formed in the core substrate 1, extending from the first surface 100 to the second surface 200, with a first electroless copper-plated layer 21 formed on its inner surface and a first electrolytic copper-plated layer 22 formed substantially concentrically inside that. A hole-filling resin 40 is embedded in the center. First electroless copper plated layer 21 is formed on the sidewall of through hole DL using an electroless plating process, and has a thickness of approximately 2 micrometers or less. After first electroless copper plated layer 21 is formed, first electroless copper plated layer 22 is formed on the surface of first electroless copper plated layer 21 using an electrolytic copper plating process. The thickness of this layer is 12 to 40 micrometers. The hole filling resin 40 is an epoxy-based liquid resist material that is filled into the holes left after forming the first electrolytic copper plating layer 22 using a screen printing device in a reduced pressure environment, and is then cured in a high-temperature environment such as an oven.

[0016] Next, through-hole lands 31 are formed on the first surface 100 and the second surface 200. The through-hole lands 31 have an outer diameter larger than that of the through-holes DL and are formed to cover the through-holes DL. The through-hole lands 31 have an opening 60 in the center of their approximately circular shape, which is a circular hole cut out above the hole-filling resin 40. The opening 60 serves as a hole for allowing gas generated from the hole-filling resin 40 to escape.

[0017] The opening 60 may be formed on either the first surface 100 or the second surface 200 of the core substrate 1, or may be formed on both. The shape of the opening 60 is not limited to a substantially circular shape, but may be various shapes such as a polygon. The center of the opening does not have to coincide with the center of the through hole 30. The opening 60 may be composed of multiple openings, not just one opening. A large number of tiny openings, such as pinholes, may also be formed. The opening does not necessarily have to be hollow, but may be filled with a gas-permeable material. In other words, the through-hole land 31 only needs to have a gas-permeable opening (region) in the area in contact with the hole-filling resin 40.

[0018] When the diameter of through-hole 30 is 150 μm, the radius (r1) of opening 60 is preferably in the range of 15 μm to 45 μm, that is, 10% to 30% of the diameter of through-hole 30. If the radius of opening 60 exceeds 45 μm, there is a risk of incomplete conduction between through-hole land 31 and first electroless copper plating layer 21 and first electrolytic copper plating layer 22 on the inner wall of through-hole 30. If the radius is less than 15 μm, it may be impossible to form a dry film resist (DFR) on the filling resin. When the diameter of through hole 30 is 200 μm, it is preferable that the radius (r1) of opening 60 is in the range of 40 μm to 70 μm, that is, 20% to 35% of the diameter of through hole 30. When the radius (r1) of opening 60 is 70 μm, there is a risk that the electrical continuity between through hole land 31 and first electroless copper plating layer 21 and first electrolytic copper plating layer 22 on the inner wall of through hole 30 may be incomplete. In other words, it is most preferable that the radius (r1) be 20% to 30% of the diameter of through hole 30.

[0019] Furthermore, through-hole land 31 is connected to wiring portion 61 formed on the surface of core substrate 1, allowing electrical conduction. Through-hole land 31 is connected to first electrolytic copper plating layer 22 inside through-hole 30, and is also connected to wiring portion 61 on the surface of core substrate 1. This allows it to function as a connection between the wiring layers on first surface 100 and second surface 200 of core substrate 1. In the embodiment of the present disclosure, the through-hole land 31 has a gas-permeable region in the region in contact with the filling resin 40, so that gas generated from the filling resin 40 is not trapped in the through-hole land 31 but can escape to the outside via the gas-permeable region (opening 60). This prevents problems such as peeling of the through-hole land 31 and the wiring portion 61 caused by the gas generated from the filling resin 40, and stabilizes the connection between the first surface 100 side and the second surface 200 side of the core substrate 1 via the through hole 30.

[0020] The cross-sectional structure taken along line LL in Fig. 2(b) is shown at the bottom of Fig. 2(a). In this figure, a first electroless copper plating layer 21 and a first electrolytic copper plating layer 22 are formed in this order on the inner surface of the through hole, and a hole-filling resin 40 is further disposed in the center.

[0021] 2(b) shows in detail the cross-sectional structure of through hole 30 including through-hole land 31. Through-hole land 31 has a T-shaped cross section with protrusion 53 toward the center in the thickness direction of core substrate 1, and second electrolytic copper-plated layer 52 is formed on second electroless copper-plated layer 51. The lower end of protrusion 53 contacts first electroless copper-plated layer 21 and first electrolytic copper-plated layer 22. Furthermore, opening 60 is formed in a portion of the region of filling resin 40 above the z-axis where the filling resin 40 is exposed on the surface of core substrate 1, so that gas generated from filling resin 40 is not sealed by the metal film, as described above. The method for manufacturing through-hole land 31 will be described later.

[0022] Next, with reference to FIG. 3, the difference between a through-hole land on a conventional through-hole and a through-hole land in the embodiment of the present disclosure will be described. 3(a) is a cross-sectional view of a through-hole land with no opening over the through-hole. In a conventional example, a wiring layer is formed over the through-hole, so a through-hole land 31 is formed as a lid by covering the through-hole with filling resin 40. As mentioned above, filling resin 40 is an epoxy-based material cured in a high-temperature environment, and gas may be generated after the through-hole land 31 is formed. If such resin is sealed with metal and there is no way for the gas to escape, it may cause problems such as destruction of the through-hole land 31 or peeling of the through-hole land 31 from the substrate. In response to this, as shown in FIG. 3(b), an opening 60 is provided in the through-hole land 31 to avoid a sealed state with metal, thereby making it possible to avoid problems caused by gas being sealed in.

[0023] (Manufacturing method) Next, a method for manufacturing a through hole according to the first embodiment will be described with reference to Figures 4 and 5. Figures 4 and 5 are explanatory diagrams of the manufacturing flow of the core substrate according to the first embodiment. Below, the manufacturing method according to the embodiment will be described step by step.

[0024] (Step 1) Preparation of the resin plate 4(a), first, a plate-shaped core substrate 1 is prepared to form the core substrate 1. If the core substrate 1 is made of insulating resin, the surface may be subjected to an appropriate cleaning process. In addition, the surface of the core substrate 1 may be inspected for foreign matter, cracks, or bends using appropriate inspection methods and equipment.

[0025] (Step 2) Through-hole formation process Next, as shown in Figure 4(b), through holes DL are drilled at predetermined positions in the plate-shaped insulating resin using a drilling device. After that, cutting waste from the drill may be removed and the surface may be cleaned. Note that the method for forming the through holes DL is not limited to drilling, and other techniques such as laser processing and etching may also be used.

[0026] (Step 3) First electroless plating process Next, as shown in FIG. 4(c), a first electroless copper plating layer 21, which is a first conductive layer, is formed by an electroless plating process. Known techniques can be used for electroless plating. For example, a primer treatment may be performed before the electroless plating process. The primer treatment can improve the adhesion of the electroless copper plating layer. Next, the core substrate 1 is immersed in an electroless plating solution for a predetermined time to perform the electroless plating process. A known plating solution suitable for through-hole plating can be used as the electroless plating solution. After the plating process, the substrate is washed with water and then dried.

[0027] (Step 4) First electrolytic plating process Next, as shown in FIG. 4(d), a first electrolytic copper plating layer 22, which is a second conductive layer, is formed by an electrolytic plating process. This process can also be performed using a known electrolytic plating process. First, a power supply jig is attached to the core substrate 1 that has been subjected to electroless processing, and then electrolytic plating is performed in an electrolytic copper plating bath. A known plating solution suitable for through-hole plating can be used as the plating solution. In this electrolytic plating process, the plating process is terminated to the extent that the through holes DL are not blocked. Therefore, the diameter of the through holes DL becomes smaller, but voids remain as through holes. After the plating process, processing is performed and then drying is performed.

[0028] (Step 5) Hole filling process Next, as shown in FIG. 4(e), the voids remaining after the electrolytic plating process are filled with a hole-filling resin 40. That is, the hole-filling resin is filled into the inner region of the through-hole surrounded by the second conductive layer. Various methods can be used for filling, but for example, a paste-like hole-filling resin can be filled into the through-hole from the surface of the core substrate 1 that has been subjected to electrolytic processing using a screen printer. After filling, the process proceeds to a step of hardening the hole-filling resin. The resin can be hardened by heat treatment, and if processing in a reduced pressure atmosphere is required, a vacuum oven or the like can be used.

[0029] (Step 6) Polishing process Next, as shown in Figure 4(f), the core substrate filled with the hole-filling resin is polished, and the hole-filling resin protruding from the surface and the copper plating on the surface are removed using a known polishing method. Polishing is not performed until the insulating material 10 of the core substrate 1 is exposed, and is stopped when a copper plating thickness of about several micrometers remains (the copper plating layer remaining on the core substrate 1 is not shown in Figure 4(f)). The end 41 of the through hole, which has been electrolytically copper-plated inside, and the copper plating on the core substrate 1 are finished so that they are flush and approximately flat. This is also done on the second surface 200. After polishing, the substrate is washed with water and dried.

[0030] (Step 7) Copper etching process for through-holes 5(g), the copper plating on core substrate 1 remaining after the polishing process in step 6 and portions of first electroless copper plating layer 21 and first electrolytic copper plating layer 22 formed on the ends of the through holes are removed (for example, by etching using an etching solution mainly containing iron chloride and copper chloride). As a result, the insulating material of core substrate 1 is exposed on both surfaces of core substrate 1, and portions of first electroless copper plating layer 21 and first electrolytic copper plating layer 22 formed along the inner wall side surfaces of through holes 30 are removed, forming recesses 70. In other words, the first electroless copper plating layer 21, which is the first conductive layer formed along the inner wall side of the through hole 30, and the first electrolytic copper plating layer 22, which is the second conductive layer, are partially etched away toward the center in the thickness direction of the core substrate 1. The etching may be a wet process using a dedicated etching solution or acid, or a dry etching process using plasma. After the etching process, a water washing process and a drying process are performed.

[0031] (Step 8) Second electroless plating process 5(h), a second electroless copper plating layer 51, which is a third conductive layer, is formed on both surfaces of the core substrate using the same process as in step 3. The electroless plating solution used in the plating process is an electroless plating solution suitable for forming a copper layer by a semi-additive method.

[0032] (Step 9) Plating resist pattern formation process Next, as shown in FIG. 5(i), areas other than those that will become the through-hole lands and conductor patterns are masked with plating resist 54. Since the plating resist pattern is formed by photolithography, it is desirable to use a photosensitive resist, and dry film resist (DFR) can also be used as the plating resist. After the plating resist pattern is formed over the entire surface of the substrate, it is exposed in an exposure device using a photomask with the plating resist pattern formed on it. After exposure, the plating resist in areas that are not required as part of the pattern is removed in a developing device, thereby forming the desired plating resist pattern.

[0033] (Step 10) Surface copper plating (SAP, pattern formation) process 5(j), using a process similar to step 4, a second electrolytic copper plating layer 52, which is a fourth conductive layer, is formed in the areas where plating resist 54 is not formed, thereby forming through-hole lands 31. This process is a pattern formation process using the well-known SAP (Semi-Additive Process), and by using SAP, it is possible to form through-hole lands 31 with finer shapes than before. A solution that can be used for electrolytic copper plating by the semi-additive method can be used.

[0034] (Step 11) Plating resist stripping and seed layer removal process 5(k), the pattern of the plating resist 54 is removed using a removal device. After that, the entire surface is immersed in an etching solution to remove the second electroless copper plating layer 51 exposed by the removal of the plating resist.

[0035] Next, a method for removing the seed layer for forming the protrusion 53 described with reference to Fig. 2(b) will be described with reference to Fig. 6. Figs. 6(a) to 6(d) are all diagrams for explaining in more detail the copper etching process for the through-hole portion in step 7, which was described with reference to Fig. 5(g). Figure 6(b) is an enlarged view of end A of first electroless copper plating layer 21 and first electrolytic copper plating layer 22 in Figure 6(a). In Figures 6(a) and (b), recessed portion 70 is formed using a copper etching solution, and in this case, the ends of first electroless copper plating layer 21 and first electrolytic copper plating layer 22 are etched to the same extent, and the ends are approximately the same height. Specifically, the depth h of the recess 70, i.e., the length of the protrusion toward the center in the thickness direction of the core substrate, is preferably in the range of 10 μm to 50 μm, and more preferably in the range of 35 μm to 45 μm. If the depth exceeds 50 μm, there is a risk of air bubbles being generated by the electrolytic copper plating. On the other hand, if the depth h is less than 10 μm, there is a risk of areas where the recess 70 is not formed due to manufacturing variations. In this way, by providing the through-hole land 31 with a protrusion 53 directed toward the center of the core substrate 1, the through-hole land 31 can be firmly connected to the core substrate 1, and electrical conductivity can be reliably maintained even when the through-hole land 31 is formed finely. In addition, in FIG. 6(c) and FIG. 6(d), which is an enlarged view of the end A of the first electroless copper plating layer 21 and the first electrolytic copper plating layer 22 in FIG. 6(c), a step is provided in the recess by using an appropriate additive in the etching solution. That is, the position in the thickness direction of the core substrate where the first electroless copper plating layer (first conductive layer) is connected to the protrusion 53 is different from the position in the thickness direction of the core substrate where the first electrolytic copper plating layer 22 (second conductive layer) is connected to the protrusion.

[0036] In the etching process, it is possible to differentiate the etching rate depending on the type of copper to be etched, i.e., electroless copper plating or electrolytic copper plating, thereby enabling the first electroless copper plating layer 21 to be etched deeper than the first electrolytic copper plating layer 22. As a result, multiple steps can be formed in the recess 70. By providing such steps at the end of the plating layer, the contact area with the second electroless copper plating layer, i.e., the protrusion 53, which will be formed later, is increased, thereby improving the reliability of electrical continuity and the robustness of the physical connection. For this etching, an etchant (flash etchant) for electroless copper plating used in a semi-additive process is preferably used. This flash etchant is a mixture of sulfuric acid and hydrogen peroxide (sulfuric acid / hydrogen peroxide), and it is known that the etching rate of electroless copper plating is higher than that of electrolytic copper plating. Furthermore, when forming fine wiring using a semi-additive process, an etchant in which an appropriate additive is added to sulfuric acid / hydrogen peroxide is also known to reduce the difference in etching rate between electrolytic copper plating and electroless copper plating. Therefore, by selecting a flash etchant, the desired shape can be obtained.

[0037] Second Embodiment Next, a core substrate 1 according to a second embodiment will be described with reference to FIGS. 7 is a diagram illustrating core substrate technology that is the basis for explaining the core substrate of the second embodiment. In the following explanation, components that are the same as or equivalent to those in the first embodiment described above are given the same reference numerals, and their explanations will be simplified or omitted. Fig. 7 shows an example in which two through holes 30 are formed in core substrate 1, Fig. 7(b) is a top view of core substrate 1, and Fig. 7(a) shows the cross-sectional structure taken along line AA in Fig. 7(b). Each through hole 30 is formed, in this order from the wall surface of the hole that passes vertically through core substrate 1, with first electroless copper plating layer 21, first electrolytic copper plating layer 22, and hole-filling resin 40. Furthermore, through-hole land 31 at the top of through hole 30 is formed, in this order, with second electroless copper plating layer 51 and second electrolytic copper plating layer 52.

[0038] The core substrate 1 in which the through holes 30 are formed is made of a single layer or multiple layers (for example, four layers) of insulating resin, and the insulating resin material used is glass-cloth epoxy resin, BT (bismaleimide triazine) resin, etc. The core substrate is generally 0.4 mm to 1.6 mm thick and 500 x 600 mm in size. The core substrate 1 in which the through holes 30 are formed can be a copper clad laminate (CCL), which is an insulating substrate with copper foil formed on both sides, and the through holes can be formed in this CCL using a drill. The through holes can also be formed by laser processing. When multiple through holes are adjacent to each other, the distance between these through holes, i.e., the space width (S) from the edge of the through-hole land of one through hole to the edge of the through-hole land of the other through hole, must be equal to or greater than the minimum safety distance determined by the "line and space" rule. For this reason, even if attempts were made to shorten the through-hole pitch (THP) and place the through holes 30 closer together and at a higher density, it was not possible to shorten the through-hole pitch (THP) because the through-hole lands 31 are spread out concentrically.

[0039] For this reason, in the second embodiment, the through-hole lands 31 are formed in a partially circular shape. That is, they are formed in a shape having a notch. The core substrate of the second embodiment will be described below with reference to FIG. 8. 8 is a diagram illustrating the core substrate of the second embodiment. In the following description, the same or equivalent components as those in the first embodiment described above are denoted by the same reference numerals, and their description will be simplified or omitted. Fig. 8 shows an example in which through-hole lands 31 having a partially circular shape are formed on core substrate 1. Fig. 8(b) is a top view of core substrate 1, and Fig. 8(a) shows the cross-sectional structure taken along line AA in Fig. 8(b). The general shape of through-hole 30 is the same as in Fig. 7, but Fig. 8 differs from Fig. 7 in that through-hole lands 31 have a partially circular shape. 8, the through-hole land 31 has the opening 60 as in the first embodiment, but may not have the opening 60. The shape of the cutout portion is not limited to the shape shown in FIG.

[0040] (Modification of partial circle) Next, modified shapes of the through-hole land 31 of the second embodiment and the effect on shortening the through-hole pitch (THP) will be described with reference to Fig. 9. Fig. 9 is a diagram illustrating modified shapes of the through-hole land 31 of the second embodiment. In Fig. 9, (b) to (e) show the relationship between the modified shapes of the through-hole land 31 (hatched areas in the left column) and the through-hole pitch (THP) when multiple through-holes 30 are arranged symmetrically opposite each other and the space width (S) is set as the minimum safe distance.

[0041] Figure 9(a) shows the case of the underlying technology explained in Figure 7. In contrast, in the case of the through-hole land 31 having a partially circular shape shown in Figures 9(b) to 9(e), the through-hole land 31 has a notch 90, and it can be seen that in all cases, the through-hole pitch (THP) can be reduced compared to the case of (a). 9(b) shows a partial circle with a notch 90 formed by cutting a circular through-hole land with a straight line. When such a notch 90 is arranged opposite the notch 90 of another adjacent through hole 30, the through-hole pitch (THP) is reduced. Also, FIG. 9(c) shows a modified example in which the through-hole land 31 has the opening 60 shown in the first embodiment, and the effect of reducing the through-hole pitch (THP) is the same as in the case of FIG. 9(b).

[0042] Next, Fig. 9(d) shows an example in which a partial circle is cut out from a circular through-hole land to form a cutout portion 90, and the remaining partial circle is used as the through-hole land 31. Fig. 9(e) shows a modified example in which the original through-hole land 31 has an opening 60. In either case, by arranging the respective cutout portions 90 opposite each other, the through-hole pitch (THP) can be shortened.

[0043] Next, referring to Figure 10, the positional relationship of the partial circular cutout portion 90 with the adjacent through hole and the effect of shortening the through hole pitch (THP) will be described. Figure 10 is a diagram showing the relationship between the through hole pitch (THP) of multiple adjacent through holes. Figure 10(a) shows the case of the underlying technology described in Figure 7. In contrast, Figure 10(b) shows a case where the through hole land of at least one of the multiple through holes is arranged so that the partial circular cutout portion faces the adjacent through hole, thereby achieving the effect of shortening the through hole pitch (THP). Furthermore, Figure 10(c) shows a case where the through-hole lands of at least one pair of adjacent through-holes among multiple through-holes are arranged so that the cutout portions of the partial circles face each other, thereby achieving a further reduction in the through-hole pitch (THP).

[0044] Next, an example of the shape and arrangement of the partially circular cutout portion 90 in the case where the through holes are arranged two-dimensionally will be described with reference to Fig. 11. Fig. 11 is a diagram showing an example in which the through holes are arranged two-dimensionally. 11(a), through-hole land 31 is a partial circle of a roughly semicircular shape, and among the multiple through holes arranged in a lattice pattern, the cutout portion of at least one through-hole land 31 is disposed diagonally toward an adjacent through hole. For example, the cutout portion of through-hole A is disposed toward through-hole E, and the cutout portion of through-hole G is disposed toward through-hole E. As a result, in the example of through-hole A, line segment L formed by the cutout portion of the partial circle is disposed in a shape that is inclined at approximately 45 degrees relative to the multiple through holes arranged in a lattice pattern. By adopting this shape and layout, it is possible to significantly reduce the through-hole pitch (THP) of multiple through-holes arranged two-dimensionally. The through-hole layout shown in Figure 11(b) is an example of a layout without partial circular through-hole lands, and since it is possible to reduce the through-hole pitch (THP) in both the vertical and horizontal directions, by using partial circular through-hole lands and setting the shortest distance between the through-hole lands of adjacent through-holes as the minimum safe distance for the core board, it is possible to significantly improve the through-hole filling rate per unit area.

[0045] (Manufacturing method) Next, a method for manufacturing a core substrate according to a second embodiment having partially circular through-hole lands will be described with reference to Fig. 12. The first half of the method for manufacturing through-holes according to the second embodiment is the same as the method for manufacturing through-holes according to the first embodiment. Therefore, the steps shown in Figs. 4 and 5(g) of the manufacturing method according to the first embodiment will be omitted, and the steps shown in Figs. 5(h) to 5(k) of the first embodiment will be replaced with Fig. 12 for the case of two through-holes. 12, in addition to the cross-sectional view of the core substrate, a top view of the core substrate viewed from above the z-axis is also shown. The method for manufacturing the core substrate of the second embodiment will be explained step by step below. In the following explanation, components that are the same as or equivalent to those in the first embodiment will be given the same reference numerals, and their explanation will be simplified or omitted.

[0046] (Step of FIG. 12(h)) Second electroless plating process 12(h), a second electroless copper plating layer 51, which is a third conductive layer, is formed on both sides of the core substrate. The processing method in this step is the same as the step described in step 8 of the first embodiment, so a detailed description thereof will be omitted.

[0047] (Step of FIG. 12(i)) Plating resist pattern formation process 12(i), the area other than the through-hole lands and conductive pattern is masked with plating resist 54. In this process, the plating resist pattern is formed so that the through-holes become partial circles, and the partial circular through-hole land shapes are plated in a later process, as shown in the top view on the right. The processing method in this process is the same as that described in step 9 of the first embodiment, so a detailed description will be omitted.

[0048] (Step in Figure 12(j)) Surface copper plating (SAP, pattern formation) process 12(j), a second electrolytic copper plating layer 52, which is a fourth conductive layer, is formed in the area where the plating resist 54 is not formed, to form the through-hole land 31. The processing method in this step is the same as the step described in step 10 of the first embodiment, and therefore a detailed description thereof will be omitted.

[0049] (Step in Figure 12(k)) Plating resist stripping and seed layer removal process 12(k), the pattern of plating resist 54 is removed using a removal device. After that, the entire surface is immersed in an etching solution to remove the second electroless copper plating layer 51 exposed by the removal of the plating resist. In the above, an example was given in which the cutout portions of the through-hole lands are arranged opposite each other in two through holes, but it goes without saying that the desired through-hole land can be formed using the same process even if the shape or orientation of the cutout portions is changed in various ways, thereby making it possible to make the shortest distance between the through-hole lands the minimum safe distance for the core board.

[0050] <Third embodiment> Next, a multilayer wiring board using the core substrate of the first embodiment will be described with reference to Fig. 13. Fig. 13 is a cross-sectional view of a multilayer wiring board of a third embodiment. 13 can be used as an FCBGA substrate, and has a plurality of insulating resin buildup layers 71 laminated on the first surface 100 and the second surface 200 of the core substrate 1 of the first embodiment. Like the buildup layers of a general multilayer wiring substrate, each buildup layer is composed of an insulating resin layer, with interlayer conductive vias 72 formed therein and conductor patterns 75 extending from these interlayer conductive vias 72. Of the buildup layers 71, a solder resist layer 73 is formed on the outside of the buildup resin layer that is outermost from the core substrate 1, and solder balls 74 are formed on the outside for electrical connection with semiconductor chips or other substrates.

[0051] 13, through-hole lands 31 each having a gas permeable region near the center are formed of a metal material at the upper and / or lower ends of through-holes 30. In other words, interlayer conductive vias 72 are formed directly above or below the peripheral region of through-hole land 31. The hole filling resin 40 in the through-holes is configured to communicate with the insulating resin of the build-up layer 71.

[0052] Therefore, in the multilayer wiring board of the third embodiment, even if gas is generated from the hole filling resin 40 in the through hole 30, the gas can escape to the buildup layer 71, preventing problems such as peeling of the through hole land due to the gas. Furthermore, because the through hole lands 31 themselves are formed at high density using SAP, it is possible to significantly increase the wiring density in the buildup resin layer compared to conventional methods. Furthermore, by arranging interlayer conductive vias 72 in the buildup layer directly above or directly below the peripheral area of ​​the through hole lands 31, a high-density wiring board can be realized. Furthermore, because the through hole lands 31 have the protrusions 53, the through hole lands 31 are firmly connected to the through holes 30, making it possible to arrange the interlayer conductive vias 72 directly above or directly below the peripheral area of ​​the through hole lands 31. That is, even if interlayer conductive vias 72 are formed in the peripheral region of through-hole land 31, i.e., in a region other than the center, and through-hole land 31 is subjected to uneven stress in the xy plane, through-hole land 31 has protrusions 53 that protrude in the depth direction of through-hole 30, and thus protrusions 53 function as anchors for through-hole land 31. With this structure, through-hole land 31 absorbs distortion caused by uneven stress and prevents peeling or deformation of through-hole land 31.

[0053] <Fourth embodiment> Next, a multilayer wiring board using the core substrate of the second embodiment will be described with reference to Fig. 14. Fig. 14 is a cross-sectional view of a multilayer wiring board of the fourth embodiment. In the following description, components that are the same as or equivalent to those in the multilayer wiring board described in the third embodiment above will be given the same reference numerals, and their description will be simplified or omitted. The multilayer wiring board of the fourth embodiment has a configuration in which a plurality of insulating resin buildup layers 71 are laminated on the first surface 100 and the second surface 200 of the core substrate 1 of the second embodiment, similar to the third embodiment. In this buildup layer, each layer is composed of an insulating resin layer, similar to the buildup layers of a general multilayer wiring board, and interlayer conductive vias 72 are formed therein. As in the third embodiment, a conductor pattern 75 may be extended from this interlayer conductive via 72, or a solder resist layer 73 may be formed on the outside of the buildup resin layer that is outermost from the core substrate 1 among the buildup layers 71, and solder balls 74 may be formed thereon to establish electrical connection with a semiconductor chip or another substrate.

[0054] Fifth Embodiment Next, with reference to Fig. 15, a semiconductor package in which a semiconductor chip 76 is mounted on the multilayer wiring board of the third embodiment described in Fig. 13 and the multilayer wiring board of the fourth embodiment described in Fig. 14 will be described. Fig. 15 is a cross-sectional view of a semiconductor package of the fifth embodiment. In the following description, components that are the same as or equivalent to those in the multilayer wiring board described in Fig. 13 above will be assigned the same reference numerals, and their description will be simplified or omitted. 15, a semiconductor package is constructed by bonding a semiconductor chip 76 to solder balls 74. In a later process, underfill can be inserted into the gap between the semiconductor chip 76 and the solder balls 74 to reliably bond the semiconductor chip 76 to the multilayer wiring board. Such a semiconductor package can also be connected to other wiring boards or semiconductor chips using the solder balls 74 on the opposite side of the core substrate 1.

[0055] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. For example, in the above-described embodiment, electroless plating and electrolytic plating are used to form the conductive layer on the side surface of the through-hole and the through-hole land, but the method of forming the conductive layer and the through-hole land is not limited to electroless plating and electrolytic plating, and various other techniques such as sputtering, vapor deposition, chemical vapor deposition, etc. Also, while an example has been described in which copper is used as the material for the conductive layer, it goes without saying that the material for the conductive layer is not limited to copper, and various conductive metal materials and alloys can also be used. Furthermore, various dimensions and shapes may be adopted for the through holes, through hole lands, core substrates, build-up layers, etc., without departing from the spirit of the present disclosure. The present disclosure includes the following aspects.

[0056] (Aspect 1) In a core substrate having through holes that electrically connect both sides of the core substrate, a through-hole land is formed at a portion where the through-hole is exposed on the surface of the core substrate, The through-hole land is partially circular in shape. A core substrate characterized by:

[0057] (Aspect 2) In the core substrate according to aspect 1, A plurality of through holes are formed in the core substrate, The through-hole land of at least one of the plurality of through-holes is arranged such that the notched portion of the partial circle faces the adjacent through-hole. A core substrate characterized by:

[0058] (Aspect 3) In the core substrate according to the first or second aspect, A plurality of through holes are formed in the core substrate, Among the plurality of through holes, at least one pair of adjacent through holes has through hole lands in which the notched portions of the partial circles are arranged opposite to each other. A core substrate characterized by:

[0059] (Aspect 4) In the core substrate according to any one of aspects 1 to 3, The shortest distance between the through-hole lands of at least one pair of adjacent through-holes among the plurality of through-holes is the minimum safety distance of the core board. A core substrate characterized by:

[0060] (Aspect 5) In the core substrate according to any one of aspects 1 to 4, the through hole has a first conductive layer formed on its inner wall, a second conductive layer formed inside the first conductive layer, and a resin filled inside the second conductive layer; The through-hole land has a gas permeable area in a part of the area where the resin is exposed. A core substrate characterized by:

[0061] (Aspect 6) In the core substrate according to any one of aspects 1 to 5, The through-hole land has a protrusion that connects to the first conductive layer and / or the second conductive layer toward the center in the thickness direction of the core substrate. A core substrate characterized by:

[0062] (Aspect 7) In the core substrate according to any one of aspects 1 to 6, The position in the thickness direction of the core substrate where the first conductive layer is connected to the protruding portion is different from the position in the thickness direction of the core substrate where the second conductive layer is connected to the protruding portion. A core substrate characterized by:

[0063] (Aspect 8) In the core substrate according to any one of aspects 1 to 7, the through-hole land has a substantially circular opening as a gas permeable region in a part of the region where the resin is exposed, the radius of the opening is 20% to 30% of the diameter of the through-hole; The length of the protrusion toward the center of the core substrate in the thickness direction is 10 μm to 50 μm. A core substrate characterized by:

[0064] (Aspect 9) In the core substrate according to any one of aspects 1 to 8, the first conductive layer is an electroless copper plating layer, the second conductive layer is an electrolytic copper plating layer, The protrusion is composed of an electroless copper plating layer and an electrolytic copper plating layer. A core substrate characterized by:

[0065] (Aspect 10) a first step of forming a first conductive layer by electroless plating on a core substrate made of an insulating material in which through holes are formed; a second step of forming a second conductive layer on the upper surface of the first conductive layer by electroplating; a third step of filling a region of the through hole surrounded by the second conductive layer with a hole-filling resin; a fourth step of polishing both surfaces of the core substrate to make the both surfaces of the core substrate substantially flat; a fifth step of etching the core substrate to expose insulating resin on both surfaces of the core substrate, and partially etching away the first conductive layer and the second conductive layer on the inner walls of the through holes toward the center in the thickness direction of the core substrate; a sixth step of forming a third conductive layer on the core substrate by electroless plating; a seventh step of forming a resist pattern on the third conductive layer in an area including at least the gas permeable area in the through-hole land, and forming a fourth conductive layer; A method for manufacturing a core substrate comprising:

[0066] (Aspect 11) In the method for producing a core substrate according to aspect 10, the etching process used in the fifth step is an etching process having different etching rates for the first conductive layer and the second conductive layer; The depths to which the first conductive layer and the second conductive layer are removed toward the center of the core substrate in the thickness direction are different. A method for manufacturing a core substrate, comprising:

[0067] (Aspect 12) A build-up layer is provided on at least one surface of the core substrate according to any one of aspects 1 to 9; at least one interlayer conductive via in the buildup layer connected to the through-hole land of the core substrate is disposed directly above or directly below the peripheral region of the through-hole land; the resin on the inner side of the second conductive layer of the core substrate communicates with the insulating resin layer of the build-up layer; Among the build-up layers, a solder resist layer and solder balls are arranged on the outer side of the outermost build-up layer from the core substrate. A multilayer wiring board characterized by:

[0068] (Aspect 13) A semiconductor chip is connected to the solder balls of the multilayer wiring board according to the twelfth embodiment. Semiconductor package. [Explanation of symbols]

[0069] 1: Core board 10: Insulating material 21: First electroless copper plating layer 22: First electrolytic copper plating layer 30:Through hole 31:Through-hole land 40: Hole-filling resin 51: Second electroless copper plating layer 52: Second electrolytic copper plating layer 53:Protrusion 54: Plating resist 60: Opening 70: Recessed part 71: Build-up layer 72: Interlayer conductive via 73: Solder resist layer 74: Solder ball 90: Notch 100: 1st page 200: 2nd side DH:Through hole S: Space THP: Through-hole pitch

Claims

1. In a core substrate having through holes that electrically connect both sides of the core substrate, a through-hole land is formed at a portion where the through-hole is exposed on the surface of the core substrate, The through-hole land is partially circular in shape. A core substrate characterized by:

2. 2. The core substrate according to claim 1, A plurality of through holes are formed in the core substrate, The through-hole land of at least one of the plurality of through-holes is arranged such that the notched portion of the partial circle faces the adjacent through-hole. A core substrate characterized by:

3. 2. The core substrate according to claim 1, A plurality of through holes are formed in the core substrate, Among the plurality of through holes, at least one pair of adjacent through holes has through hole lands in which the notched portions of the partial circles are arranged opposite to each other. A core substrate characterized by:

4. 4. The core substrate according to claim 2, The shortest distance between through-hole lands of at least one pair of adjacent through-holes among the plurality of through-holes is the minimum safety distance of the core board. A core substrate characterized by:

5. The core substrate according to any one of claims 1 to 3, the through hole has a first conductive layer formed on its inner wall, a second conductive layer formed inside the first conductive layer, and a resin filled inside the second conductive layer; The through-hole land has a gas permeable area in a part of the area where the resin is exposed. A core substrate characterized by:

6. The core substrate according to claim 5, The through-hole land has a protrusion that is connected to the first conductive layer and / or the second conductive layer toward the center in the thickness direction of the core substrate. A core substrate characterized by:

7. 7. The core substrate according to claim 6, The position in the thickness direction of the core substrate where the first conductive layer is connected to the protruding portion is different from the position in the thickness direction of the core substrate where the second conductive layer is connected to the protruding portion. A core substrate characterized by:

8. 7. The core substrate according to claim 6, the through-hole land has a substantially circular opening as a gas permeable region in a part of the region where the resin is exposed, the radius of the opening is 20% to 30% of the diameter of the through-hole; The length of the protrusion toward the center of the core substrate in the thickness direction is 10 μm to 50 μm. A core substrate characterized by:

9. 7. The core substrate according to claim 6, the first conductive layer is an electroless copper plating layer, the second conductive layer is an electrolytic copper plating layer, The protrusion is composed of an electroless copper plating layer and an electrolytic copper plating layer. A core substrate characterized by:

10. a first step of forming a first conductive layer by electroless plating on a core substrate made of an insulating material in which through holes are formed; a second step of forming a second conductive layer on the upper surface of the first conductive layer by electroplating; a third step of filling a region of the through hole surrounded by the second conductive layer with a hole-filling resin; a fourth step of polishing both surfaces of the core substrate to make the both surfaces of the core substrate substantially flat; a fifth step of etching the core substrate to expose insulating resin on both surfaces of the core substrate, and partially etching away the first conductive layer and the second conductive layer on the inner walls of the through holes toward the center in the thickness direction of the core substrate; a sixth step of forming a third conductive layer on the core substrate by electroless plating; a seventh step of forming a resist pattern on the third conductive layer in an area including at least the gas permeable area in the through-hole land, and forming a fourth conductive layer; A method for manufacturing a core substrate comprising:

11. The method for manufacturing a core substrate according to claim 10, the etching process used in the fifth step is an etching process having different etching rates for the first conductive layer and the second conductive layer; The depths to which the first conductive layer and the second conductive layer are removed toward the center of the core substrate in the thickness direction are different. A method for manufacturing a core substrate, comprising:

12. A build-up layer is provided on at least one surface of the core substrate according to claim 5, at least one interlayer conductive via in the buildup layer connected to the through-hole land of the core substrate is disposed directly above or directly below the peripheral region of the through-hole land; the resin on the inner side of the second conductive layer of the core substrate communicates with the insulating resin layer of the build-up layer; Among the build-up layers, a solder resist layer and solder balls are arranged on the outer side of the outermost build-up layer from the core substrate. A multilayer wiring board characterized by:

13. A semiconductor chip is connected to the solder balls of the multilayer wiring board according to claim 12. Semiconductor package.

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