Protection circuit and display device including the same

Abstract

To provide a protection circuit capable of suppressing an increase in a time constant of an input signal, and a display device including the protection circuit.SOLUTION: The display device includes a plurality of pixels, a driver circuit for controlling the plurality of pixels, a plurality of first protection circuits connected in parallel to each other, a first terminal electrically connected to the driver circuit through the plurality of first protection circuits, a first power supply line and a second power supply line to which a high potential and a low potential are supplied, respectively, and a first control signal wiring. Each of the plurality of first protection circuits includes a resistor, a first diode, and a second diode. A first end and a second end of the resistance element are electrically coupled to the first terminal and the first control signal wiring, respectively. An input terminal and an output terminal of the first diode are electrically connected to a second terminal of the resistor and the first power supply line, respectively. An input terminal and an output terminal of the second diode are electrically connected to the second power supply line and a second terminal of the resistor, respectively.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a protection circuit and a display device including the protection circuit. [Background technology]

[0002] In display devices such as liquid crystal display devices, a plurality of pixels for reproducing an image and a drive circuit for driving the plurality of pixels are provided on a substrate. The plurality of pixels and the drive circuit are composed of numerous semiconductor elements, such as thin-film transistors, and are formed using photolithography, which requires many processes. For this reason, a protection circuit may be provided to prevent damage to the pixels and the drive circuit not only from surge currents but also from electrostatic breakdown due to static electricity generated during manufacturing. For example, Patent Documents 1 and 2 disclose display devices provided with a protection circuit for protecting the drive circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-49149 [Patent Document 2] Japanese Patent Publication No. 2020-154250 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a protection circuit having a novel structure and a display device including the protection circuit, or to provide a protection circuit capable of suppressing deterioration (increase) of the time constant of an input signal and a display device including the protection circuit. [Means for solving the problem]

[0005] One embodiment of the present invention is a display device. The display device includes a plurality of pixels, a drive circuit, a plurality of first protection circuits, a first terminal, a first power supply line, a second power supply line, and a first control signal wiring. The drive circuit is configured to control the plurality of pixels. The plurality of first protection circuits are connected in parallel to each other. The first terminal is electrically connected to the drive circuit via the plurality of first protection circuits. The first power supply line and the second power supply line are configured to receive a first potential and a second potential lower than the first potential, respectively. Each of the plurality of first protection circuits includes a resistive element, a first diode, and a second diode. The first end and second end of the resistive element are electrically connected to the first terminal and the first control signal wiring, respectively. The input terminal and output terminal of the first diode are electrically connected to the second end of the resistive element and the first power supply line, respectively. The input terminal and output terminal of the second diode are electrically connected to the second power supply line and the second end of the resistive element, respectively.

[0006] One embodiment of the present invention is a protection circuit. The protection circuit includes a first resistive element, a second resistive element, and a first diode, a second diode, a third diode, and a fourth diode. A first end of the first resistive element and a first end of the second resistive element are electrically connected to each other. A second end of the first resistive element and a second end of the second resistive element are electrically connected to each other. A second end of the first resistive element is electrically connected to an input terminal of the first diode and an output terminal of the second diode. A second end of the second resistive element is electrically connected to an input terminal of the third diode and an output terminal of the fourth diode. The output terminals of the first diode and the third diode are electrically connected to each other. The input terminals of the second diode and the fourth diode are electrically connected to each other. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 2] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 3]1 is an equivalent circuit diagram including a protection circuit according to an embodiment of the present invention; [Figure 4] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 5] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 6] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 7] FIG. 2 is an equivalent circuit diagram showing an example of a protection circuit. [Figure 8] 1 is an equivalent circuit diagram including a protection circuit according to an embodiment of the present invention; [Figure 9] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 10] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 11] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 12] 1 is an equivalent circuit diagram including a protection circuit according to an embodiment of the present invention; [Figure 13] 1 is an equivalent circuit diagram including a protection circuit according to an embodiment of the present invention; [Figure 14] 1 is an equivalent circuit diagram including a protection circuit according to an embodiment of the present invention; [Figure 15] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 16] 1 is an equivalent circuit diagram including a protection circuit according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0009] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in the previous drawings may be given the same reference numerals, and duplicated explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures, and when these are individually represented, a hyphen and a natural number are added after the reference numeral.

[0010] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0011] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0012] 1. Overall configuration of the display device FIG. 1 shows a schematic top view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a substrate 102 and an opposing substrate (not shown) facing the substrate 102. Various conductive films, semiconductor films, insulating films, and the like are patterned using a photolithography process and disposed between the substrate 102 and the opposing substrate. Appropriate combinations of these conductive films, semiconductor films, insulating films, and the like form a plurality of pixels 104, each including a display element, as well as drive circuits (gate line drive circuit 120, signal line drive circuit 122) for driving the pixels, a protection circuit unit 124 composed of a plurality of protection circuits (described later), and a plurality of terminals 108 electrically connected to the drive circuits. The region where the plurality of pixels 104 are formed (the region surrounded by a dashed line in FIG. 1 ) is a display region 106, and the region surrounding the display region 106 and where the drive circuits, protection circuit unit 124, terminals 108, and the like are provided is a frame region. Although not shown in Figure 1, one or more patterned conductive films are used to form on the substrate 102 a plurality of gate lines extending from the gate line driving circuit 120 to the pixels 104, a plurality of video signal lines extending from the signal line driving circuit 122 to the pixels 104, control signal wiring connecting the protection circuit unit 124 and the signal line driving circuit 122, power supply lines for supplying a constant potential, and the like.

[0013] As shown in Fig. 1, a plurality of pixels 104 are arranged in a matrix having a plurality of rows and a plurality of columns. The signal line driving circuit 122 is arranged so that its longitudinal direction is parallel to the row direction or the column direction (the row direction in the example shown in Fig. 1), while the gate line driving circuit 120 is arranged so that its longitudinal direction is parallel to the column direction or the row direction (the column direction in the example shown in Fig. 1). A display element is provided in each pixel 104, and each pixel functions as a minimum unit for providing color information. The display element may be a liquid crystal element or an electroluminescent element.

[0014] The plurality of terminals 108 are arranged in a row or column direction. The plurality of terminals 108 are electrically connected to a flexible printed circuit board (hereinafter referred to as FPC) 180, and the FPC 180 is connected to an external circuit 182 via a connector 184. A high voltage potential (V DD ) and V DD A low voltage potential (V SS ) is supplied via FPC 180 and terminal 108. V DD and V SS is supplied to the pixels 104 and the driving circuit. More specifically, as shown in FIG. DD and V SS are supplied to one or more terminals 108 selected from the plurality of terminals 108 via a plurality of wirings 130-1 provided on the FPC 180. DD and V SS are supplied to power supply lines 132 extending from the terminals 108, and are then supplied to the pixels 104 and the signal line driving circuit 122 by the power supply lines 132. The power supply lines 132 may cross the protection circuit units 124, but may not be connected to the protection circuits that make up the protection circuit units 124. Although not shown, a portion of the power supply lines 132 is connected to the gate line driving circuit 120, and thereby the gate line driving circuit 120 receives V DD and V SS is supplied.

[0015] The external circuit 182 further generates various signals, such as a high-frequency clock signal, a video signal for controlling the pixels 104, an initialization signal, and a reset signal, and these signals are input to the signal line driver circuit 122 via the FPC 180, the terminals 108, and the protection circuit unit 124. Specifically, as shown in FIG. 2 , the clock signal is input to one or more terminals 108 via one or more wirings 130-3 provided on the FPC 180. The clock signal input from each wiring 130-3 is input to one terminal 108, then input to a protection circuit included in the protection circuit unit 124, and further input to the signal line driver circuit 122 via one control signal wiring 136 that electrically connects the protection circuit and the signal line driver circuit 122. More specifically, the control signal wiring 136 branches into wiring 138, and the clock signal is input via wiring 138 to a plurality of buffers, scanners, and the like (not shown) that constitute the signal line driver circuit 122.

[0016] On the other hand, signals with lower frequencies than the clock signal, such as a video signal, an initialization signal, and a reset signal, are input via one or more wirings 130-2 provided on the FPC 180. Each wiring 130-2 is connected to one terminal 108. Each terminal 108 to which a video signal, an initialization signal, a reset signal, or the like is supplied is connected to one signal wiring 134 via a protection circuit included in the protection circuit unit 124. These signals are input to the signal line driving circuit 122 via the signal wiring 134, and signals for controlling the pixels 104 are supplied to each pixel 104 via the signal signal lines 126 by the signal line driving circuit 122.

[0017] 2.Protection circuit The protection circuit unit 124 includes a protection circuit according to one embodiment of the present invention. As shown in the equivalent circuit of Fig. 3, the protection circuit unit 124 of the display device 100 according to one embodiment of the present invention is provided with a plurality of protection circuits 140 that are electrically connected to each control signal wiring 136 and connected in parallel with each other. In the equivalent circuit of Fig. 3, two protection circuits 140 electrically connect one control signal wiring 136 and one terminal 108.

[0018] Each protection circuit 140 includes a resistive element 142 and two diodes (a first diode 144-1 and a second diode 144-2). A first end of the resistive element 142 of one protection circuit 140 is electrically connected to a first end of the resistive element 142 of another protection circuit 140, and these first ends are connected to a terminal 108 to which a clock signal is input. Therefore, one terminal 108 is shared by multiple protection circuits 140. A second end of the resistive element 142 of one protection circuit 140 and a second end of the resistive element 142 of another protection circuit 140 are also electrically connected to each other, and these second ends are electrically connected to one control signal wiring 136. Therefore, one control signal wiring 136 is shared by multiple protection circuits 140.

[0019] In each protection circuit 140, the second end of the resistive element 142 is connected to the input terminal of the first diode 144-1 and the output terminal of the second diode 144-2. DD The input terminal of the second diode 144-2 is electrically connected to the high potential power supply line 132-1, which is supplied with V SS The input terminals of the first diodes 144-1 of the protection circuits 140 are electrically connected to the low-potential power supply line 132-2 to which the input terminals of the second diodes 144-2 of the protection circuits 140 are electrically connected to each other.

[0020] The resistance of the resistive elements 142 is the same among the multiple protection circuits 140, for example, between 0.5 kΩ and 5.0 kΩ. By providing resistive elements 142 with a relatively large resistance, the current input to the signal line driving circuit 122 can be reduced even when a large current is input from the terminal 108 due to a surge current or static electricity. Even if the resistance of the resistive elements 142 among the multiple protection circuits 140 differs due to inevitable manufacturing variations in the manufacturing process, the resistance of the control signal wiring 136 between the connection node N1 connecting the multiple protection circuits 140 and each resistive element 142 is smaller than the resistance of the control signal wiring 136 from the connection node N1 to the signal line driving circuit 122. This allows a portion of the current flowing through the resistive elements 142, which has the above-mentioned resistance value, to be diverted to the second diodes 144-2 of other protection circuits 140 via the connection node N1. This allows the display device 100 to have high resistance to electrostatic discharge damage caused by static electricity or a surge current.

[0021] It is also possible to recognize a plurality of protection circuits 140 connected to one terminal 108 and its corresponding control signal wiring 136 as one protection circuit. In this case, each protection circuit is recognized as including a first resistance element (resistance element 142 of the protection circuit 140 on the left side in FIG. 3) and a second resistance element (resistance element 142 of the protection circuit 140 on the right side in FIG. 3) connected in parallel with each other, as well as a first diode (first diode 144-1 of the protection circuit 140 on the left side in FIG. 3), a second diode (second diode 144-2 of the protection circuit 140 on the left side in FIG. 3), a third diode (first diode 144-1 of the protection circuit 140 on the right side in FIG. 3), and a fourth diode (second diode 144-2 of the protection circuit 140 on the right side in FIG. 3).

[0022] FIG. 4 shows a schematic top view of two protection circuits 140, and FIGS. 5 and 6 show schematic end views along the dashed lines AA′ and BB′ in FIG. 4, respectively. As can be seen from FIGS. 4 and 5, each diode 144 in the protection circuit 140 is formed from multiple transistors 150 electrically connected to each other. The structure of the transistors 150 is not limited and may be a bottom-gate transistor or a top-gate transistor. Alternatively, the transistor 150 may have multiple gate electrodes sandwiching a semiconductor film from above and below. In the example shown in FIG. 5, the transistor 150 is a bottom-gate transistor and is provided directly on the substrate 102 or on an undercoat 110 of any configuration. In this example, the transistor 150 includes a gate electrode 152, a gate insulating film 154 on the gate electrode 152, a semiconductor film 156 located on the gate insulating film 154 and overlapping the gate electrode 152, an interlayer insulating film 158 on the semiconductor film 156, and a pair of source / drain terminals 160 located on the interlayer insulating film 158 and electrically connected to the semiconductor film 156. Adjacent transistors 150 share a source / drain terminal 160, thereby electrically connecting the adjacent transistors 150. As shown in Fig. 4, one of the pair of source / drain terminals 160 of each transistor 150 is electrically connected to the terminal 108 via a resistive element 142, and the other source / drain terminal 160 is electrically connected to the high-potential power supply line 132-1 or the low-potential power supply line 132-2 via a connection wiring 146 present in the same layer as the gate electrode 152, and is also electrically connected to the corresponding gate electrode 152. A planarization film 112 is provided on the transistor 150 (Fig. 5), which absorbs irregularities caused by the transistor 150 and forms a flat surface.

[0023] The transistor 150, the planarization film 112, and other components described above can be formed using known materials and methods, and therefore detailed description thereof will be omitted. Briefly, the undercoat 110, the gate insulating film 154, the interlayer insulating film 158, and other components may be formed of one or more films containing silicon-containing inorganic compounds such as silicon nitride and silicon oxide. The planarization film 112 may be configured to contain a polymer such as an acrylic resin, an epoxy resin, a silicone resin, or a polyimide resin. The gate electrode 152, the source / drain terminals 160, the power supply line 132, and the connection wiring 146 may be configured to contain a metal such as molybdenum, tantalum, titanium, copper, or aluminum, or an alloy containing one or more of these metals. Preferably, the metal is selected so that the resistance of the source / drain terminals 160 is lower than that of the gate electrode 152. The control signal wiring 136 and the power supply line 132 are formed in the same layer as the source / drain terminals 160. The gate electrode 152 and the connection wiring 146 are formed in the same layer, but are arranged in a different layer from the source / drain terminals 160. The semiconductor film 156 may contain silicon or an oxide of a group 13 transition metal such as gallium or indium. There are no restrictions on the crystallinity of the semiconductor film 156, and it may be single crystalline, polycrystalline, or amorphous. Although not shown, the planarization film 112 extends to the display region 106, and a display element is provided in each pixel 104 using the flat upper surface of the planarization film 112.

[0024] 3, the connection node N1 is preferably provided on the protection circuit 140 side of the power supply line 132. In other words, the connection node N1 is preferably located between the multiple protection circuits 140 and the high-potential power supply line 132-1, and between the multiple protection circuits 140 and the low-potential power supply line 132-2. In this case, the control signal wiring 136 does not intersect with the power supply line 132 between the resistance element 142 and the connection node N1, but intersects with the power supply line 132 between the connection node N1 and the signal line drive circuit 122. As shown in FIGS. 4 and 6, the multiple protection circuits 140 and the control signal wiring 136 are electrically connected via a connection wiring 136a that constitutes a part of the control signal wiring 136. The connection wiring 136a is in the same layer as the gate electrode 152 and intersects with the power supply line 132. The control signal wiring 136 including the connection wiring 136a and the plurality of protection circuits 140 are electrically connected through openings provided in the gate insulating film 154 and the interlayer insulating film 158 and arranged between the plurality of protection circuits 140 and the power supply line 132. Therefore, between the plurality of protection circuits 140 and the signal line driving circuit 122, there is only one wiring that is not connected to two power supply lines 132 and that intersects with the single connection wiring 136a. This configuration makes it possible to suppress an increase in parasitic capacitance caused by the power supply line 132.

[0025] As described above, a plurality of protection circuits 140 are provided between the terminal 108 to which a clock signal is input and the corresponding control signal wiring 136. However, signals other than the clock signal do not necessarily need to be input to the terminal 108 to which a plurality of protection circuits 140 are connected. For example, as shown in FIG. 7 , a single protection circuit 140 may be provided between the terminal 108 and the signal wiring 134. That is, the total number of protection circuits 140 connected to one terminal 108 and its corresponding signal wiring 134 may be one. The configuration of the protection circuit 140 connected to the signal wiring 134 is the same as the configuration of the protection circuit 140 connected to the control signal wiring 136. Therefore, the resistance of the former resistive element 142 is also the same as the resistance of the latter resistive element 142.

[0026] Conventionally, increasing the resistance of resistive elements in the protection circuit has been used to improve the signal line driver circuit 122's resistance to surge currents and static electricity. However, increasing the resistance of resistive elements increases the time constant of signals supplied through the protection circuit. In particular, an increase in the time constant of high-frequency clock signals narrows the driving margin of the signal line driver circuit and is a major cause of abnormal operation. The increase in time constant due to increased resistance of resistive elements can be suppressed by increasing the number of wirings supplying the signals. However, as the number of signal wirings 134 and power supply lines 132 increases with the trend toward higher resolution display devices, the parasitic capacitance between the control signal wiring 136 supplying the clock signal and the signal wiring 134, and between the control signal wiring 136 and the power supply line 132 in the frame area, increases. Because this increase in parasitic capacitance actually increases the time constant, increasing the number of wirings is not necessarily an effective way to reduce the time constant. Furthermore, increasing the number of control signal wirings 136 increases the number of terminals 108 and the size of the connector 184.

[0027] Meanwhile, in the display device 100, a plurality of protection circuits 140 connected in parallel are provided on the control signal wiring 136, which electrically connects the terminal to which the clock signal is input and the signal line driving circuit 122. Therefore, if the number of protection circuits connected to the terminal 108 to which the clock signal is input is n (n is an integer greater than or equal to 2), the combined resistance of the resistive elements 142 of the plurality of protection circuits 140 is 1 / n of that of a single protection circuit 140. Because the resistance of a resistive element is one of the parameters that determine the time constant, reducing the combined resistance can reduce the time constant. Therefore, by applying the embodiment of the present invention, it is possible to reduce the time constant of the clock signal and widen the driving margin of the signal line driving circuit without increasing the number of terminals or the size of the connector 184. Furthermore, as described above, providing a plurality of protection circuits 140 on the terminal 108 to which the clock signal is input can significantly improve resistance to static electricity-induced currents and surge currents.

[0028] Furthermore, as described above, the electrical connection between the protection circuit 140 and the control signal wiring 136 is made between the protection circuit 140 and the power supply line 132, which suppresses an increase in parasitic capacitance caused by intersection with the power supply line 132. This structure can also be said to contribute to reducing the time constant of the clock signal. Therefore, by applying one of the embodiments of the present invention, it is possible to reliably ensure the drive margin of the signal line drive circuit even in an ultra-high definition display device.

[0029] 3. Protection circuit layout As described above, in the display device 100, multiple protection circuits 140 are connected to the terminals 108 to which a clock signal is input. Therefore, the area of ​​the protection circuits for the terminals 108 to which the clock signal is input is larger than the area of ​​the protection circuits 140 for the terminals 108 to which other signals are input. However, by adopting the layout described below, it is possible to arrange the protection circuits 140 without increasing the area required to arrange all of the terminals 108. Below, this layout will be described using an area in which a first terminal 108-1 to which a clock signal is input, and second and third terminals 108-2 and 108-3 to which signals other than the clock signal are input, as shown in the equivalent circuit of FIG. 8 , are arranged. In FIG. 8 , the second terminal 108-2 and the third terminal 108-3 are arranged in this order on either side of one first terminal 108-1. The second terminal 108-2 is sandwiched between the first terminal 108-1 and the third terminal 108-3. A plurality of (here, two) first protection circuits 140-1 are connected to the first terminal 108-1, and a single second protection circuit 140-2 and a single third protection circuit 140-3 are connected to the second terminal 108-2 and the third terminal 108-3, respectively.

[0030] A schematic top view corresponding to the equivalent circuit of FIG. 8 is shown in FIG. 9. A portion of the terminal 108 and the resistive element 142 are shown here. As shown in FIG. 9, the multiple terminals 108 are arranged so that the interval S3 between adjacent terminals 108 is constant. In other words, the pitch between the multiple terminals 108 is the same. The interval S3 may be set appropriately within the range of, for example, 40 μm to 1.0 mm.

[0031] In contrast, the protection circuit 140 is provided so that the spacing between adjacent resistive elements 142 varies in the arrangement direction (row direction or column direction) of the terminals 108. Specifically, the protection circuit 140 is arranged so that the spacing S1 between the resistive element 142 of the first protection circuit 140-1 closest to the second protection circuit 140-2 and the resistive element 142 of the second protection circuit 140-2 is smaller than the spacing S2 between the resistive elements 142 of the second protection circuit 140-2 and the third protection circuit 140-3. Therefore, the resistive element 142 of the second protection circuit 140-2 is shifted relatively to the opposite side of the first protection circuit 140-1 with respect to the corresponding second terminal 108-2. In the example shown in FIG. 9, the resistive element 142 of the third protection circuit 140-3 is also shifted relatively to the opposite side of the first protection circuit 140-1 with respect to the corresponding third terminal 108-3. Although not shown, when a fourth protection circuit is placed on the opposite side of the second protection circuit 140-2 with respect to the third protection circuit 140-3, the distance between the resistive elements 142 of the third protection circuit 140-3 and the fourth protection circuit may be the same as distance S2 or may be larger than distance S2. The distance between the resistive elements 142 of adjacent protection circuits 140 may increase stepwise or continuously across the entire terminals 108 as the distance increases from the first protection circuit 140-1 in the arrangement direction of the terminals 108, or the distance between the resistive elements 142 may be constant in protection circuits 140 that are a certain distance or more away from the first protection circuit 140-1. By adopting such a layout, even if the length of the area occupied by the multiple first protection circuits 140-1 connected to the first terminal 108-1 (the length in the arrangement direction of the terminals 108) is greater than the width of each terminal 108 (the length in the arrangement direction of the terminals 108), the protection circuits 140 can be arranged without increasing the spacing S3 between the terminals 108.

[0032] 10, the length of the resistive element 142 (the length in the direction perpendicular to the arrangement direction of the terminals 108) may be changed. That is, the length L1 of the resistive element 142 of the first protection circuit 140-1 is set to be equal to the length L in the column direction of the resistive element 142 of the second protection circuit 140-2 and the third protection circuit 140-3. 2、The protection circuits 140 may be arranged so that the length is longer than L3. By adopting this layout, the width of the area occupied by each protection circuit 140 (the length in the arrangement direction of the terminals 108) can be made equal to or less than the pitch of the terminals 108, so that the protection circuits 140 can be arranged without shifting the resistive elements 142 with respect to the terminals 108 or increasing the spacing S3 between the terminals 108. Note that, because the resistance of the resistive elements 142 is set to be the same between the protection circuits 140, the width W1 of the resistive element 142 of the first protection circuit 140-1 is smaller than the widths W2 and W3 of the resistive elements 142 of the second protection circuit 140-2 and the third protection circuit 140-3.

[0033] By adopting the layout shown in FIG. 10 , a space 128 can be created between the protection circuits 140 other than the first protection circuit 140-1 and the signal line driver circuit 122 ( FIG. 11 ). Therefore, various configurations (such as wiring and pads) can be provided in this space 128. For example, as shown in FIG. 11 , the power supply line 132 is bent so that the distance (first distance) between the power supply line 132 and the signal line driver circuit 122 in the region sandwiched between the protection circuit 140 connected to the terminal 108 to which a clock signal is input and the signal line driver circuit 122 is shorter than the distance (second distance) in the region sandwiched between the protection circuit 140 connected to the terminal 108 to which a signal other than the clock signal is input and the signal line driver circuit 122. Therefore, as shown in FIG. 11 , a wiring 186 for supplying power to the gate line driver circuit 120 can be arranged in the space 128. Therefore, the width of the wiring 186 can be increased, thereby reducing the effect of the resistance of the wiring 186. Although not shown, if the power supply line 132 is not bent in this manner, a space 128 can be formed between the power supply line 132 and the protection circuit 140 .

[0034] 4. Variations The structures of the protection circuit 140 and the display device 100 including the protection circuit 140 are not limited to the above-described structures. Modified examples of the protection circuit 140 and the display device 100 will be described below.

[0035] 4-1. Variation 1 There is no restriction on the number of protection circuits 140 connected to a terminal 108 to which a clock signal is input. As shown in the equivalent circuit of FIG. 12, three or more protection circuits 140 may be connected to the terminal 108. Even in this case, multiple protection circuits 140 connected to one terminal 108 and its corresponding control signal wiring 136 can be recognized as a single protection circuit. In this case, each protection circuit is recognized as including a third resistance element (resistance element 142 of the protection circuit 140 on the right side in FIG. 11), a fifth diode (first diode 144-1 of the protection circuit 140), and a sixth diode (second diode 144-2 of the protection circuit 140) in addition to a first resistance element, a second resistance element, and first to fourth diodes. The first and second ends of the third resistance element are electrically connected to the terminal 108 and the second end of the first resistance element, respectively. The second end of the third resistor element is further electrically connected to the input terminal of the fifth diode and the output terminal of the sixth diode. The output terminal of the fifth diode and the input terminal of the sixth diode are electrically connected to the output terminal of the first diode and the input terminal of the second diode, respectively. Although not shown, an auxiliary resistor element (described below) may also be connected between the third resistor element and the connection node N1. By providing three or more protection circuits 140, the electrostatic breakdown voltage of the display device can be more effectively improved.

[0036] 4-2. Variation 2 To further improve electrostatic breakdown voltage resistance, a resistive element may be further provided in each protection circuit 140. Specifically, as shown in the equivalent circuit of FIG. 13, an auxiliary resistive element 148 may be provided between the resistive element 142 and the connection node N1 in each protection circuit 140. A first terminal and a second terminal of the auxiliary resistive element 148 are electrically connected to the second terminal of the resistive element 142 and the control signal wiring 136, respectively. Second terminals of the plurality of protection circuits 140 are electrically connected to each other. In other words, the resistive element 142 is electrically connected to the control signal wiring 136 via the auxiliary resistive element 148.

[0037] Similar to the example shown in FIG. 3 etc., the connection node N1 between the protection circuit 140 and the control signal wiring 136 can be established between the power supply line 132 and the protection circuit 140 (FIG. 13). More specifically, the connection node N1 can be established between the power supply line 132 and the auxiliary resistance element 148. This makes it possible to prevent an increase in parasitic capacitance caused by the power supply line 132. However, taking into consideration the layout and depending on the size of the auxiliary resistance element 148, the power supply line 132 may be arranged to intersect with the protection circuit 140, and the connection node N1 between the protection circuit 140 and the control signal wiring 136 may be arranged between the signal line drive circuit 122 and the power supply line 132, as shown in FIGS. 14 and 15.

[0038] As shown in FIG. 15 , the auxiliary resistor 148 is preferably formed using a metal film present in the same layer as the gate electrode 152 constituting the transistor 150. The auxiliary resistor 148 is formed to have a narrower width than other wiring (e.g., the control signal wiring 136, the connection wiring 146, etc.). To obtain resistance, the auxiliary resistor 148 is configured to have a bent or curved structure to lengthen the current path. The resistance value of the auxiliary resistor 148 may be the same as or different from that of the resistor 142, and may be set to, for example, 0.5 kΩ to 5.0 kΩ, preferably 0.1 kΩ to 1.0 kΩ. By providing the auxiliary resistor 148, electrostatic breakdown of the drive circuit and electrostatic breakdown due to surge current can be more effectively prevented.

[0039] 4-3. Variation 3 In the above example, the multiple protection circuits 140 connected in parallel to each other are connected to the terminal 108 to which a clock signal, which is a high-frequency signal, is input and the control signal wiring 136, and the total number of protection circuits 140 connected to the terminals 108 to which signals with lower frequencies than the clock signal, such as a video signal, a reset signal, and an initialization signal, is one. However, the configuration of the display device 100 is not limited to this, and multiple protection circuits 140 connected in parallel to each other may also be connected to the terminal 108 to which a signal with a lower frequency than the clock signal is input. For example, as shown in the equivalent circuit of FIG. 16 , multiple protection circuits 140 connected in parallel to each other may be connected to a first terminal 108-1 to which a clock signal is input and a second terminal 108-2 adjacent to the first terminal 108-1 to which a video signal, a reset signal, or an initialization signal is input. All of these multiple protection circuits 140 are connected to the signal wiring 134, thereby inputting the video signal, the reset signal, or the initialization signal to the signal line drive circuit 122. Although not shown, a plurality of protection circuits 140 connected in parallel to each other may be provided for terminals 108 for inputting signals (e.g., enable signals) to be input to the gate line driving circuit 120 and signals (sensor signals) to be input to a touch panel provided on the display device 100. Alternatively, a plurality of protection circuits 140 connected in parallel to each other may be provided for terminals 108 for supplying power to the gate line driving circuit 120.

[0040] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0041] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0042] 100: display device, 102: substrate, 104: pixel, 106: display region, 108: terminal, 108-1: first terminal, 108-2: second terminal, 108-3: third terminal, 110: undercoat, 112: planarization film, 120: gate line driving circuit, 122: signal line driving circuit, 124: protection circuit unit, 126: video signal line, 128: space, 130-1: wiring, 130-2: wiring, 130-3: wiring, 132: power supply line, 132-1: high potential power supply line, 132-2: low potential power supply line, 134: signal wiring, 136: control signal wiring wire, 136a: connecting wiring, 138: wiring, 140: protection circuit, 140-1: first protection circuit, 140-2: second protection circuit, 140-3: third protection circuit, 142: resistance element, 144: diode, 144-1: first diode, 144-2: second diode, 146: connecting wiring, 148: auxiliary resistance element, 150: transistor, 152: gate electrode, 154: gate insulating film, 156: semiconductor film, 158: interlayer insulating film, 160: drain terminal, 180: FPC, 182: external circuit, 184: connector, 186: wiring

Claims

1. A plurality of pixels, a drive circuit configured to control the plurality of pixels; a plurality of first protection circuits connected in parallel with each other; a first terminal electrically connected to the drive circuit via the plurality of first protection circuits; a first power supply line configured to receive a first potential; a second power supply line configured to receive a second potential lower than the first potential; and a first control signal wiring that electrically connects the plurality of first protection circuits to the drive circuit; Each of the plurality of first protection circuits includes: a resistive element having a first end and a second end electrically connected to the first terminal and the first control signal wiring, respectively; a first diode having an input terminal and an output terminal electrically connected to the second end of the resistor element and the first power supply line, respectively; a second diode whose input terminal and output terminal are electrically connected to the second power supply line and the second end of the resistor element, respectively;

2. 2. The display device according to claim 1, wherein a node to which the first control signal wiring and the plurality of protection circuits are connected is located on the side of the plurality of protection circuits with respect to the first power supply line and the second power supply line.

3. The display device according to claim 1 , wherein the first terminal is configured to receive a clock signal.

4. a second protection circuit; a second terminal electrically connected to the drive circuit via the second protection circuit; and a first signal wiring that electrically connects the second protection circuit to the drive circuit; the second protection circuit has the same configuration as the first protection circuit, The display device according to claim 1 , wherein the first terminal and the second terminal are configured to receive a first signal and a second signal having a frequency lower than that of the first signal, respectively.

5. The display device according to claim 4 , wherein the total number of protection circuits connected to the first signal wiring is one.

6. The display device according to claim 1 , wherein the total number of the first protection circuits is two or three.

7. the first protection circuit further includes an auxiliary resistance element; a first end of the auxiliary resistor element electrically connected to the second end of the resistor element; The display device according to claim 1 , wherein a second end of the auxiliary resistor element is electrically connected to the first control signal wiring.

8. 8. The display device according to claim 7, wherein a connection node between said first control signal wiring and said plurality of protection circuits is located on said drive circuit side with respect to said first power supply line and said second power supply line.

9. a third protection circuit; a third terminal electrically connected to the drive circuit via the third protection circuit; and a second signal wiring that connects the third protection circuit to the drive circuit; the third protection circuit has the same configuration as the first protection circuit, the third terminal is configured to receive a third signal having a lower frequency than the first signal; the second terminal is adjacent to the first terminal and the third terminal and is sandwiched between the first terminal and the third terminal; The display device according to claim 4 , wherein the first terminals, the second terminals, and the third terminals are arranged at the same pitch.

10. The display device according to claim 9 , wherein the total number of protection circuits connected to the second signal wiring is one.

11. 10. The display device of claim 9, wherein a first distance between a resistive element of the second protection circuit and a resistive element of the first protection circuit closest to the second protection circuit is smaller than a second distance between the resistive element of the second protection circuit and a resistive element of the third protection circuit.

12. the plurality of pixels are arranged in a matrix having a plurality of rows and a plurality of columns, 10. The display device according to claim 9, wherein the length of the resistive element of the first protection circuit in the column direction is longer than those of the second protection circuit and the third protection circuit.

13. the plurality of pixels are arranged in a matrix having a plurality of rows and a plurality of columns, 10. The display device according to claim 9, wherein the length in the row direction of the resistive element of the first protection circuit is shorter than those of the second protection circuit and the third protection circuit.

14. 10. The display device according to claim 9, wherein a distance from the first power supply line to the drive circuit in a region between the first protection circuit and the drive circuit is shorter than a distance from the first power supply line to the drive circuit in a region between the second protection circuit and the drive circuit.

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