Signal processing apparatus and method

Abstract

To provide a signal processing apparatus and method capable of applying normalization processing of a floating point to data of an expression form other than two's complement expression.SOLUTION: In a storage processing unit 11 of a signal processing device, a normalization circuit 20 that normalizes, for each block, a plurality of pieces of data represented in a second representation form that is the same as two's complement representation when a value of the data is positive or 0 and in which (D-N-1) bits between a most significant bit and lower N bits including a least significant bit are inverted from two's complement representation of D bits (D is a positive integer satisfying D ≥ 3) when the value is negative performs, for a bit string of (D-1) bits excluding the most significant bit of the plurality of pieces of data of the block, A maximum exponent is calculated from a logical operation result for each bit of the plurality of pieces of data, and a bit string of the (D-1) bits excluding the most significant bit of the plurality of pieces of data is shifted corresponding to the maximum exponent.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to signal processing devices and methods. [Background technology]

[0002] One of the important processes in digital signal processing is FFT (Fast Fourier Transform). For example, Frequency Domain Equalization (FDE) is a well-known technique for compensating for waveform distortion during signal transmission in wireless and wired communications. In Frequency Domain Equalization (FDE), first, signal data in the time domain is converted to data in the frequency domain using FFT. Next, filtering for equalization is performed in the frequency domain. The filtered data in the frequency domain is then reconverted to signal data in the time domain using IFFT (Inverse Fast Fourier Transform). This compensates for waveform distortion in the original time domain signal. When there is no need to distinguish between FFT and IFFT, they are sometimes referred to as "FFT / IFFT."

[0003] Generally, "butterfly operations" are used in FFT / IFFT processing. For example, Reference 1 discloses an FFT device using butterfly operations. Reference 1 also discloses "twiddle multiplication," which will be described later, i.e., multiplication using a twiddle coefficient or twiddle factor. Furthermore, Reference 4 discloses Cooley-Tukey butterfly operations as an efficient FFT / IFFT process. However, Cooley-Tukey FFT / IFFTs with a large number of points require complex circuits. Therefore, FFT / IFFT processing is performed by decomposing the data into two smaller FFTs / IFFTs based on the Prime Factor method described in Reference 5, for example.

[0004] 21 shows a data flow 500 of a 64-point FFT decomposed into two stages of radix-8 butterfly processing using the Prime Factor method. The data flow 500 includes a data rearrangement unit 501, butterfly calculation units 502 and 503, and a total of 16 radix-8 butterfly calculation processes, and a twiddle coefficient {W k}(W=exp(-2πj / N), j 2 In FIG. 21, the twiddle coefficient is (W 0 , W 1 ,…,W 7 ),…,(W 0 , W 7 ,…,W 49 )). In FIG. 21, data flow 500 converts input time domain data x(n) (n=0, 1, . . . , 63) into frequency domain signal X(k) (k=0, 1, . . . , 63) by FFT processing. Note that part of the data flow is not shown in FIG. 21. In FIG. 21, data flow 500 has the same basic configuration even when IFFT processing is performed. Input frequency domain signal X(k) (k=0, 1, . . . , 63) is converted (IFFT) into time domain data x(n) (n=0, 1, . . . , 63) by processing of data flow 500 and output.

[0005] When the number of FFT points is large, implementing all of the data flow 500 shown in Fig. 21 using a circuit would result in an enormous scale. Therefore, when the number of FFT points is large, a method is generally adopted in which the entire FFT process is implemented by repeatedly using circuits that implement processing of a portion of the data flow, depending on the required processing performance.

[0006] For example, in the data flow of Fig. 21, if an FFT device that performs FFT processing on eight pieces of data in parallel (hereinafter simply referred to as "8 data in parallel") is configured as a physical circuit, 64-point FFT processing can be realized by a total of eight repeated processes. The eight repeated processes are performed in order by performing the processes corresponding to the partial data flows 505a to 505h that are performed on the eight pieces of data, and specifically, are performed as follows. That is, The first time, the process corresponding to the partial data flow 505a is performed. The second time, the process corresponding to the partial data flow 505b is performed. The third time, processing corresponding to partial data flow 505c (not shown) is performed. Similarly, processing corresponding to partial data flow 505h is performed in order up to the eighth time. By performing the above processing, 64-point FFT processing is realized.

[0007] In butterfly operations, data arranged in sequential order is read out and processed in an order that follows a predetermined rule. Therefore, data rearrangement is required for butterfly operations. For this purpose, a RAM (Random Access Memory) circuit is mainly used. For example, Reference 2 describes an FFT device that rearranges data using a RAM circuit for butterfly operations. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] WO 2019 / 131754 (page 7, Figure 1) Summary of the Invention [Problem to be solved by the invention]

[0009] Two's complement representation is widely used as a binary representation method for signal data in digital signal processing. Two's complement representation has the advantage that it can represent subtraction processing as addition processing, allowing addition / subtraction processing circuits to be implemented on a small circuit scale.

[0010] On the other hand, in two's complement representation, there is a large difference in bit-wise values ​​between small positive values ​​and small negative values ​​near 0. For this reason, when a signal whose value frequently changes between positive and negative near 0 is represented in two's complement, it has the characteristic of having a high bit-wise operation rate (toggle rate). The dynamic power consumption P of a digital signal processing circuit realized using a CMOS (Complementary Metal Oxide Semiconductor) circuit can be expressed by the following equation (1). P=(1 / 2)*a*C*V2*f … (1) where: a:Circuit activity (percentage-activity), C: Load capacity, V: voltage, f: operating frequency The percentage activity of a circuit is given by the ratio of an estimate of the number of switching times in a certain time period to the number of clock cycles in that period.

[0011] Since the bit-by-bit operation rate (toggle rate) of signal data determines the circuit operation rate a, reducing the bit-by-bit operation rate is effective in reducing power consumption. Meanwhile, signal data for communication signal processing often changes frequently between positive and negative values ​​near the value 0.

[0012] Furthermore, in fast Fourier transform (FFT) processing, which is one of the important processes in digital signal processing, the internal data often takes small values ​​close to 0. When two's complement representation is used in these processes, the bit-by-bit operation rate increases, which results in a problem of increased power consumption.

[0013] In contrast, sign-magnitude representation is a method of representing digital data that has a small bit-by-bit activity rate near the value 0.

[0014] FIG. 22 shows an example of two's complement representation and sign-magnitude representation, where a binary representation of signal values ​​from +15 to -16 for 5-bit signal data is shown. In two's complement representation, it can be seen that the bit values ​​on the higher-order side differ greatly between positive and negative values, with the value 0 as the boundary. Therefore, when a signal that frequently changes between positive and negative values ​​near the value 0 is represented, the bit-by-bit operation rate increases. For example, when a value changes from +1 to -1, all 7 bits except the least significant bit (LSB) transition.

[0015] On the other hand, sign-magnitude representation uses the most significant bit (MSB) to represent the sign and the remaining bits to represent the absolute value of the value. This means that the difference in bit values ​​between positive and negative values ​​is small around the value 0. Therefore, even when representing a signal that frequently changes between positive and negative values ​​near the value 0, the bit-wise operation rate is low. For example, when a signal value changes from +1 to -1, only the most significant bit transitions. However, sign-magnitude representation cannot represent subtraction as an addition operation, so separate addition and subtraction circuits are required. As a result, the circuit size required to perform addition and subtraction operations increases. Since circuit size determines the load capacitance C in the dynamic power consumption P shown in equation (1), an increase in circuit size increases power consumption. In other words, while sign-magnitude representation can reduce the circuit operation rate a compared to two's complement representation, it also increases the load capacitance C of the addition and subtraction circuit. This results in higher power consumption, especially in signal processing involving many additions and subtractions.

[0016] It is also possible to use two's complement representation for addition and subtraction operations, which allows for efficient circuit implementation, and sign-magnitude representation for operations other than addition and subtraction, which can reduce the operating rate. However, converting between two's complement representation and sign-magnitude representation requires bit inversion and adding one (increment). Therefore, if a circuit requires many conversion operations, the power consumption will increase by the amount of the conversion circuitry.

[0017] FIG. 23 shows an example of the configuration of a conversion circuit 600 between two's complement representation and sign-magnitude representation. Referring to FIG. 23, the conversion circuit 600 has a configuration in which a bit inversion circuit 601 and a 1-increment circuit 602 are connected. The bit inversion circuit 601 includes (D-1) XOR circuits 607 that perform an exclusive OR (XOR) operation between the most significant bit representing the code from the input terminal IN[D-1] and each bit from the input terminal IN[i] (i = 0 to D-2). The 1-increment circuit 602 outputs the most significant bit representing the code from the input terminal IN[D-1] as is from the output terminal OUT[D-1], and outputs values ​​obtained by adding 1 to the outputs of the (D-1) XOR circuits 607 to the output terminals OUT[0] to OUT[D-2]. In the conversion circuit 600, the circuit size of the 1-increment circuit 602 in particular is not negligible compared to other logic processing circuits and arithmetic processing circuits. Therefore, when a large number of conversion processes are required, the circuit size and power consumption of the entire circuit increase by the amount of the conversion circuits.

[0018] In addition, block floating-point is sometimes used in FFTs to improve calculation accuracy. In block floating-point systems, it is desirable that the floating-point normalization process be applicable to data in formats other than two's complement representation.

[0019] Therefore, an object of the present disclosure is to provide an apparatus and a method that solves at least one of the above problems. Below, a signal processing apparatus and a method are disclosed that, for example, can suppress or reduce the increase in the circuit size and power consumption of the entire circuit, and also enable the application of normalization processing to data in representation formats other than two's complement representation in block floating point.

[0020] According to some embodiments of the present disclosure, a signal processing device includes an arithmetic processing unit that performs arithmetic processing on data expressed in two's complement representation, and a storage processing unit that performs storage processing on data expressed in a second representation format as a data representation format. The second representation format is the same as the two's complement representation when the value of D-bit data is positive or 0, and is a representation format in which (DN-1) bits between the most significant bit indicating the sign and the lowest N bits (N is a positive integer N≦D-2) on the least significant bit side are inverted from the two's complement representation of D bits (D is a positive integer D≧3) when the value of the data is negative. The storage processing unit includes a normalization circuit that normalizes a block consisting of multiple data represented in the second representation format. The normalization circuit includes a maximum exponent calculation circuit that calculates a maximum exponent from a calculation result corresponding to a bitwise OR between the plurality of data for a bit string of (D-1) bits excluding the most significant bit of the plurality of data in the block, and a shift circuit that shifts the bit string of (D-1) bits excluding the most significant bit of the plurality of data in accordance with the maximum exponent.

[0021] According to one of some embodiments of the present disclosure, a signal processing method performs arithmetic processing on data expressed in a two's complement representation and performs storage processing on data expressed in a second representation format as a data representation format, wherein the second representation format is the same as the two's complement representation when the data value is positive or 0, and when the data value is negative, is a representation format in which (D-1) bits between a most significant bit indicating a sign and the lowest N bits (N is a positive integer N≦D-2) on the least significant bit side of a D-bit (D is a positive integer N≦D-2) two's complement representation are inverted, and the storage processing includes a normalization process for a block consisting of multiple data represented in the second representation format, in which a maximum exponent is found from a calculation result corresponding to a bit-by-bit logical sum between the multiple data for a (D-1)-bit bit string excluding the most significant bit of the multiple data, and the bit string excluding the most significant bit of the multiple data is shifted by the maximum exponent. [Effects of the Invention]

[0022] According to the present disclosure, it is possible to realize a signal processing device that can suppress or reduce the increase in the circuit size and power consumption of the entire circuit, and that can apply normalization processing to data in representation formats other than two's complement representation in block floating point. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a diagram schematically illustrating one of several examples of a signal processing device according to the present disclosure. [Figure 2] FIG. 2 is a diagram schematically illustrating an example of a configuration of a storage processing unit in the present disclosure. [Figure 3] FIG. 1 is a diagram illustrating an example of a data representation format in the present disclosure in a table format. [Figure 4] FIG. 2 is a diagram schematically illustrating an example of the configuration of a conversion circuit according to the present disclosure. [Figure 5] FIG. 2 is a diagram illustrating an example of the configuration of a block floating-point normalization circuit according to the present disclosure. [Figure 6] FIG. 2 is a diagram schematically illustrating an example of the configuration of a maximum exponent calculation circuit according to the present disclosure. [Figure 7] 1A and 1B are diagrams illustrating a non-limiting example of a register configuration and timing according to the present disclosure. [Figure 8] FIG. 2 is a diagram schematically illustrating an example of the configuration of a correction circuit according to the present disclosure. [Figure 9] FIG. 2 is a diagram schematically illustrating an example of the configuration of a selection conversion circuit according to the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating an example of the operation of the present disclosure. [Figure 11] FIG. 10 is a diagram illustrating an example of the operation of the present disclosure. [Figure 12] FIG. 10 is a graph showing an example of the effect of the present disclosure. [Figure 13] FIG. 2 is a diagram schematically illustrating an example of the configuration of a storage processing unit in the present disclosure. [Figure 14] FIG. 2 is a block diagram illustrating an example of the configuration of a conversion circuit according to the present disclosure. [Figure 15] FIG. 10 is a diagram illustrating an example of the operation of the present disclosure. [Figure 16] FIG. 1 is a diagram schematically illustrating one of several examples of a signal processing device according to the present disclosure. [Figure 17] FIG. 10 is a diagram illustrating an example of rearrangement in the present disclosure. [Figure 18] FIG. 10 is a diagram illustrating an example of rearrangement in the present disclosure. [Figure 19] FIG. 2 is a diagram schematically illustrating an example of the configuration of a sorting processing unit in the present disclosure. [Figure 20] FIG. 10 is a diagram illustrating an example of the operation of a sorting processing unit in the present disclosure. [Figure 21] FIG. 10 is a diagram illustrating an example of a data flow of 64-point FFT processing. [Figure 22] FIG. 10 is a diagram showing an example of a data representation format in a table format. [Figure 23] FIG. 2 is a diagram schematically illustrating an example of the configuration of a conversion circuit. [Figure 24] FIG. 2 is a diagram schematically illustrating an example of the configuration of a conversion circuit. [Figure 25] FIG. 10 is a diagram illustrating an example of the configuration of a block floating-point normalization circuit. DETAILED DESCRIPTION OF THE INVENTION

[0024] Several embodiments of the present disclosure will be described. First, as a premise of the present disclosure, the "sign magnitude--representation" disclosed in Patent Document 1 and the like will be described as a data representation format that aims to reduce the circuit size and power consumption of the conversion circuit of FIG. 21. According to Patent Document 1, the "sign magnitude--representation" is the same as the two's complement representation when the data value is positive or 0, and is a representation format in which all bits lower than the most significant bit indicating the sign are inverted from the two's complement representation when the data value is negative. According to Patent Document 1, arithmetic processing is performed on data represented in the two's complement representation, and storage processing is performed on data represented in the "sign magnitude--representation," which is a second representation format as a data representation format.

[0025] 22 shows binary representation of signal values ​​of +15 to -16 for 5-bit signal data as an example of the sign magnitude representation, in addition to the two's complement representation and the sign magnitude representation. The sign magnitude representation is the same as the two's complement representation when the data value is positive or 0, and when the data value is negative, it is a representation in which bits other than the most significant bit indicating the sign are inverted from the two's complement representation.

[0026] 24 schematically shows an example of the configuration of a conversion circuit 610 between two's complement representation and sign-magnitude representation. Conversion between two's complement representation and sign-magnitude representation can be achieved only by bit inversion processing by a bit inversion circuit 601, and does not require the one-increment processing by a one-increment circuit 602 that is required for two's complement representation and sign-magnitude representation, thereby making it possible to reduce the circuit size and power consumption of the conversion circuit.

[0027] However, even when the sign-magnitude representation is applied, if the number of conversion circuits is large, the overall circuit size and power consumption still increase.

[0028] Another problem with the sign-magnitude-- representation is that it is difficult to use it in conjunction with low-order bit masking, a low-power technology. Low-order bit masking suppresses bit transitions by fixing the values ​​of some of the lowest-order bits in the signal data. Although this reduces calculation accuracy, it is expected to reduce power consumption by reducing bit transitions. However, when performing conversion processing related to the sign-magnitude-- representation after low-order bit masking, the fixed low-order bit values ​​will undergo bit transitions again, thereby invalidating the suppression of bit transitions achieved by the low-order bit masking, resulting in an increase in power consumption.

[0029] In digital signal processing, floating-point arithmetic has the advantage of being able to perform calculations with high precision even when the range of values ​​of the signal data being handled is wide. However, it requires complex circuits, which results in problems of large circuit size and power consumption. On the other hand, fixed-point arithmetic has the advantage of simple circuits, small circuit size and power consumption, but it also has problems of low calculation precision. Block floating-point arithmetic is an arithmetic method that combines the advantages of both floating-point and fixed-point arithmetic.

[0030] In block floating-point calculations, multiple signal data are grouped together as a single block, and normalized across the entire block so that each block has a common exponent. Note that floating-point normalization involves shifting (right-shifting) the mantissa and making the most significant digit a value other than 0. In block floating-point normalization, the mantissa is shifted by an exponent common to the block.

[0031] In block floating-point processing, for example, the following steps perform block floating-point normalization (Reference 3). (1) Find the maximum exponent of all data in the block. (2) The entire block is shifted (normalized) by the maximum exponent. Here, the maximum exponent is the maximum exponent that does not cause overflow of all data in the block. The maximum exponent is equal to the exponent value of the data with the largest absolute value among all data in the block.

[0032] FIG. 25 shows a schematic diagram of an example of the configuration of a block floating-point normalization circuit (hereinafter referred to as a "normalization circuit") (Reference 3). The normalization circuit 700 performs block floating-point normalization processing on each piece of input data that constitutes a block. The normalization circuit 700 normalizes the input data and outputs the normalized data.

[0033] 25, the normalization circuit 700 includes a memory circuit 720, a maximum exponent calculation circuit 710, and a shift circuit 730.

[0034] The maximum exponent calculation circuit 710 calculates the maximum exponent for the input data that has been input, and outputs the calculated maximum exponent to the shift circuit 730 as the maximum exponent 708.

[0035] The memory circuit 720 holds the input data while the maximum exponent calculation circuit 710 calculates the maximum exponent of the input data. The input data is sequentially input to the memory circuit 720 and the maximum exponent calculation circuit 710 from, for example, an external device (not shown). The memory circuit 720 sequentially holds the input data input from the external device. After the maximum exponent calculation circuit 710 completes the calculation of the maximum exponent, the memory circuit 720 sequentially outputs the held input data to the shift circuit 730 as input data 721.

[0036] The shift circuit 730 performs normalization processing by shifting the input data output by the memory circuit 720 based on the maximum exponent 708 calculated by the maximum exponent calculation circuit 710 .

[0037] Normalization circuit 700 is based on the premise that at least the mantissa of input data in block floating-point notation is expressed using two's complement notation. Block floating-point normalization processing in normalization circuit 700 is performed on the portion using two's complement notation. Input data in a representation format other than two's complement notation must be converted to two's complement notation before normalization processing.

[0038] 25, the normalization process is performed only on the parts that use two's complement representation. Therefore, for input data in a representation format other than two's complement representation, the data is converted into two's complement representation before normalization. For this reason, a conversion circuit to two's complement representation is required.

[0039] The problems analyzed above are merely examples, and the present disclosure discloses, for example, several forms of signal processing devices that solve the above problems.

[0040] FIG. 1 is a diagram illustrating a schematic diagram of an example of some embodiments of a signal processing device 10 according to the present disclosure. Referring to FIG. 1, the signal processing device 10 includes storage processing units 11a, 11b, and 11c that perform storage processing such as buffering, retiming, and rearrangement of signal data, and arithmetic processing units 12a and 12b that perform arithmetic processing such as addition, subtraction, multiplication, and division. In FIG. 1, arrows illustrate an example of the flow of data in processing. In the following description, the storage processing units 11a, 11b, 11c, etc. will be referred to as the storage processing unit 11, with the symbols a, b, c, etc. omitted, unless it is necessary to specifically describe each unit. The same applies to other elements.

[0041] The storage processing unit 11a receives signal data in which at least the mantissa part of the block floating-point data is expressed in two's complement representation from outside (not shown) of the signal processing device 10, performs storage processing, and outputs the data to the arithmetic processing unit 12a. In the present disclosure, "signal data in which at least the mantissa part of the block floating-point data is expressed in two's complement representation" is also referred to as "signal data expressed in two's complement representation."

[0042] The arithmetic processing unit 12a receives signal data expressed in two's complement notation from the storage processing unit 11a, performs arithmetic processing on the data, and outputs the result to the storage processing unit 11b.

[0043] The storage processing unit 11b receives signal data expressed in two's complement notation from the arithmetic processing unit 12a, performs storage processing on the data, and outputs the data to the arithmetic processing unit 12b.

[0044] The arithmetic processing unit 12b receives the signal data expressed in two's complement notation from the storage processing unit 11b, performs arithmetic processing on the data, and outputs the result to the storage processing unit 11c.

[0045] The storage processing unit 11c receives signal data expressed in two's complement notation from the arithmetic processing unit 12b, performs storage processing, and outputs the data to the outside of the signal processing device .

[0046] The memory processing units 11a, 11b, and 11c have a common circuit configuration and can be realized, for example, by the memory processing unit 11 shown in Fig. 2. Referring to Fig. 2, the memory processing unit 11 includes a first conversion circuit 13a, a memory circuit 14, a normalization circuit 20, a correction circuit 21, and a second conversion circuit 13b.

[0047] In the storage processing unit 11, the first conversion circuit 13a receives signal data expressed in two's complement representation, converts it into signal data expressed in "partial code absolute value representation", and outputs it. Note that "partial code absolute value representation" is a new term coined by the inventor (it is a term used only in this specification and is not a general technical term). "Partial code absolute value representation" corresponds to the "second representation format" in the claims of this patent application.

[0048] The partial sign magnitude-- representation is the same as the two's complement representation when a D-bit (D is a positive integer such that D≧3) data value is positive or 0. When the D-bit data value is negative, the partial sign magnitude-- representation is a representation in which (DN-1) bits excluding the most significant bit (MSB) and the most significant N bits (N is a positive integer such that N≦D-2) from the most significant bit (MSB) and least significant bit (LSB) indicating the sign are inverted from the two's complement representation (the most significant N bits from the LSB are the least significant N bits (including the LSB) on the LSB side). In other words, in the "partial sign magnitude-- representation," the least significant N bits on the least significant bit (LSB) side of D-bit data are the same as the two's complement representation, and the (DN-1) bits between the most significant bit (MSB) and the least significant bit (LSB) are the same representation format as the "sign magnitude-- representation." Hereinafter, this value of N is referred to as the "number of unconverted bits" and is treated as one of the parameters that define the "partial code absolute value--representation."

[0049] Fig. 3 shows the "partial sign absolute value representation" when the number of non-conversion bits N=2 for signal data with the number of data bits D=6, and for comparison, the binary representations of signal values ​​from +15 to -16 using the two's complement representation, the sign absolute value representation, and the "sign absolute value representation". In Fig. 3, when the data value is positive, the "partial sign absolute value representation", the two's complement representation, the sign absolute value representation, and the "sign absolute value representation" are all the same bit representation.

[0050] If the data value is 0, the partial sign-magnitude representation and the two's complement representation are identical bit representations.

[0051] If the data value is negative, the partial sign magnitude--representation is a representation in which three bits ((DN-1) bits between the MSB and the two least significant bits on the LSB side, which indicate the sign) are inverted from the two's complement representation ((DN-1) bits = (6-2-1) bits between the MSB and the two least significant bits on the LSB side).

[0052] Similarly, when the data value is negative, the two's complement representation is a representation in which the three bits ((DN-1) bits between the MSB and the two least significant bits on the LSB side = (6-2-1) bits) excluding the most significant bit (MSB) and the two least significant bits (LSB) that indicate the sign are inverted from the partial sign magnitude representation. Therefore, when the data value is negative, the partial sign magnitude representation differs from the sign magnitude representation in the two least significant bits on the LSB side.

[0053] As shown in Figure 3, the partial sign-magnitude-- representation, like the sign-magnitude-- representation and the sign-magnitude--- representation, has a small difference in bit values ​​between positive and negative values ​​with the value 0 as the boundary. Therefore, even when expressing a signal that frequently changes between positive and negative values ​​near the value 0, it has the characteristic of having a small bit-wise operation rate.

[0054] For example, if the signal value changes from +1 to -1, the partial code absolute value -- representation changes from +1 ("000001") to -1 ("100011"), so a total of two bits transition: the most significant bit and the second bit from the least significant bit.

[0055] On the other hand, in two's complement representation, the change is from +1 ("000001") to -1 ("111111"), so a total of five bits other than the least significant bit transition.

[0056] In the sign-magnitude representation, the change is from +1 ("000001") to -1 ("100000"), so a total of two bits, the most significant bit and the least significant bit, transition.

[0057] Referring again to FIG. 2, the memory circuit 14 receives the signal data expressed in the partial code absolute value representation output by the first conversion circuit 13a, stores the signal data in the partial code absolute value representation, and outputs the signal data in the partial code absolute value representation to the normalization circuit 20.

[0058] The normalization circuit 20 performs block floating point normalization processing on the signal data expressed in the partial sign magnitude representation.

[0059] The normalization circuit 20 inputs the signal data 23 after storage processing output by the memory circuit 14 and the signal data 24 before storage processing output by the first conversion circuit 13a, performs normalization processing, and outputs normalized data 25 after normalization and a maximum exponent 22 indicating the amount of shift in the normalization processing to the correction circuit 21.

[0060] The correction circuit 21 refers to the maximum exponent 22 and performs a process of correcting the bit positions that are the same as those in the two's complement representation and the bit positions that are the same as those in the sign-magnitude representation of the normalized data 25 of the partial sign-magnitude representation normalized by the normalization circuit 20 to the same as those before the normalization process. The correction circuit 21 outputs corrected data 26, which is the signal data after the correction process, to the second conversion circuit 13b.

[0061] The second conversion circuit 13b converts the correction data 26 expressed in the partial sign absolute value representation output by the correction circuit 21 into signal data expressed in two's complement representation and outputs the signal data.

[0062] The first and second conversion circuits 13a and 13b have the same configuration and can be realized, for example, by the conversion circuit 13 shown in Figure 4. When there is no need to distinguish between the first and second conversion circuits 13a and 13b, they will be referred to as the conversion circuit 13. Referring to Figure 4, the conversion circuit 13 receives D-bit (D is a positive integer D≧3) signal data (IN[0] to IN[D-1]) in two's complement representation in parallel, converts it from two's complement representation to partial sign absolute value representation, and outputs D-bit (OUT[0] to OUT[D-1]) in parallel.

[0063] In addition, the conversion circuit 13 inputs D-bit signal data (IN[0] to IN[D-1]) in partial code absolute value representation in parallel, converts the partial code absolute value representation to two's complement representation, and outputs D bits (OUT[0] to OUT[D-1]) in parallel.

[0064] The conversion circuit 13 outputs the most significant bit (MSB) indicating the code input from the input IN[D-1] as it is as a code bit to OUT[D-1].

[0065] The least significant bit (LSB) through N bits input from inputs IN[0] to IN[N-1] are output as is to outputs OUT[0] to OUT[N-1], respectively.

[0066] The bits input from the inputs IN[N] to IN[D-2] are respectively input to an XOR (exclusive OR) circuit 17 i (i=N to D-2) and outputs the exclusive OR (XOR) with the most significant bit (MSB) indicating the code input from input IN[D-1] to outputs OUT[N] to OUT[D-2], respectively.

[0067] If the input data value is positive or 0, the most significant bit (MSB) indicating the sign input from input IN[D-1] is 0, and the bit values ​​input to inputs IN[0] to IN[D-2] are output as is to outputs OUT[0] to OUT[D-2], respectively.

[0068] On the other hand, if the input data value is negative, the most significant bit (MSB) indicating the sign input from input IN[D-1] is 1, and the bit values ​​input to inputs IN[0] to IN[N-1] are output as they are to outputs OUT[0] to OUT[N-1]. Also, the bit values ​​input to inputs IN[N] to IN[D-2] are output to outputs OUT[N] to OUT[D-2] by XOR circuits 17. N ~17 D-2 The inverted value is output.

[0069] Through the above process, the conversion circuit 13 realizes conversion from the two's complement representation to the partial sign-magnitude representation, or conversion from the partial sign-magnitude representation to the two's complement representation.

[0070] As described above, in the conversion circuit 13, conversion between two's complement representation and partial sign-magnitude-value representation can be realized only by bit inversion processing. The process of adding 1, which was required for conversion between two's complement representation and sign-magnitude-value representation, is not required. The bit inversion processing can be realized only by an exclusive OR (XOR circuit). In other words, it can be realized with a circuit scale that is overwhelmingly smaller than other logic processing circuits and arithmetic processing circuits.

[0071] In the conversion circuit 13, the XOR circuit 17 N ~17 D-2 The number of digits is DN-1, which is smaller than that required for conversion between two's complement representation and sign-magnitude representation. This allows the circuit scale of the conversion circuit 13 to be reduced.

[0072] Next, a block floating-point normalization circuit will be described with reference to Fig. 5. Fig. 5 is a diagram schematically illustrating an example of the configuration of a block floating-point normalization circuit (hereinafter referred to as a normalization circuit) according to an embodiment of the present disclosure. In Fig. 5, a normalization circuit 20 performs block floating-point normalization processing on each piece of signal data 23 constituting a block. The normalization circuit normalizes input data and outputs the normalized data 25.

[0073] 5, the normalization circuit 20 includes a maximum exponent calculation circuit 30 and a shift circuit 29. The maximum exponent calculation circuit 30 calculates a maximum exponent 22 for the input signal data 24 and outputs it to the shift circuit 29. The shift circuit 29 performs normalization processing by arithmetically shifting the signal data 23 based on the maximum exponent 22 calculated by the maximum exponent calculation circuit 30. The arithmetic shift shifts the bit string excluding the sign bit (most significant bit), but does not shift the sign bit. As a result of the shift, excess bits are discarded and zeros are inserted into the vacant spaces. The shift circuit 29, which is a floating-point hardware circuit, is configured, for example, with a barrel shifter. The barrel shifter arithmetically shifts the signal data 23 by the number of bits corresponding to the maximum exponent 22 in one clock cycle (where n is an integer greater than or equal to 2, and an n-bit shift does not require n clocks).

[0074] 6 is a diagram schematically illustrating the configuration of the maximum exponent calculation circuit 30. Referring to FIG. 6, the maximum exponent calculation circuit 30 calculates the maximum exponent of all data in a block made up of a plurality of signal data 24. At this time, the maximum exponent calculation circuit 30 identifies the end of the block by referring to the input block end signal BE. The block end signal is input to the maximum exponent calculation circuit 30 from, for example, an external circuit (not shown). Then, the external circuit outputs an asserted block end signal BE to the maximum exponent calculation circuit 30 in the cycle in which the last input data in the block is output to the maximum exponent calculation circuit 30.

[0075] The maximum exponent calculation circuit 30 includes, as main circuits, a logical OR circuit 32, a register 33, and an MSB side bit position detection circuit .

[0076] The logical sum circuit 32 calculates a bit-wise logical sum (OR) of the lower D-1 bits excluding the sign bit of the D-bit signal data 24 input thereto and a D-1-bit register value 37 output by the register 33, and outputs the calculated logical sum as a logical sum value 36 to the register 33. For example, for signal data 24 (a[D-1:0]) with a bit width of D, the logical sum circuit 32 receives the lower D-1 bits a[D-1:0] of the signal data 24 and data q[D-1:0] with a bit width of D-1 output from the register 33. The logical sum circuit 32 includes, for example, (D-1) 2-bit input OR circuits (not shown), and the i-th (i=0, ..., D-2) OR circuit performs the operation d[i]=OR(a[i], q[i]) (i=0, ..., D-2) and outputs a D-1-bit logical sum value 36 (d[D-2:0]) in parallel.

[0077] The register 33 may be configured as a circuit that holds and outputs the logical sum 36 (d[D-2:0]) output by the logical sum circuit 32 for each operation cycle based on a clock signal clk generated by a clock generator (not shown). In this case, the register 33 may be configured as a register that captures the logical sum 36 (d[D-2:0]) output by the logical sum circuit 32, for example, in response to the clock signal clk, and holds and outputs the captured value. The register 33 outputs the held logical sum as a register value 37 to the logical sum circuit 32 and the MSB-side bit position detection circuit 34 for each clock cycle. A block end signal BE generated by a control circuit (not shown) is also input to the register 33. When the block end signal BE becomes active (e.g., high level), the register 33 recognizes the last operation cycle in which the final logical sum 36 based on the last input data of the block is input from the logical sum circuit 32 to the register 33. The register 33 may be configured to reset the register value 37 (logical sum value) held for each block to an initial value of 0 in the cycle following the final operation cycle of each block. In this case, the register 33 outputs the final register value 37 (final logical sum value of the block) to the MSB side bit position detection circuit 34, and then resets the held value to 0.

[0078] 7A is a diagram schematically illustrating a non-limiting example of the configuration of register 33, illustrating a case where input data (logical sum value 36 output from logical sum circuit 32) is 8 bits (D=8). In the nth cycle (clock cycle), register 33 receives, holds, and outputs logical sum value 36, which is the result of the logical sum operation just before by logical sum circuit 32. Logical sum circuit 32 performs a logical sum operation on signal data 24 in the nth cycle and register value 37 output from register 33, and outputs the operation result as new logical sum value 36. As shown in FIG. 7A, the register 33 includes a flip-flop 331 (FF) that receives a block end signal BE at a data terminal D, takes in the value of the data terminal D based on a clock signal clk, and outputs the value from an output terminal Q, and (D-1) selectors 332 (Sel0 to Sel1) that receive the output of the flip-flop 331 as a selection signal s, select input data d0 to dD-2 when the selection signal s is 0, and output a fixed value 0 (low level: ground (GND) level) when the selection signal s is 1. D-2 ), and (D-1) selectors 332 (Sel0 to Sel D-2 ) output signals ds0 to dsD-2 are input to the data terminals D, and the values ​​of the data terminals D are taken in based on the clock signal clk, and output from the output terminals Q. D-2 ) is provided.

[0079] Figure 7(B) is a diagram explaining a non-limiting example of the operation of Figure 7(A) when eight consecutive data pieces form one block, and schematically shows an example of timing waveforms of the block end signal BE, clock signal clk, selection signal s, least significant bit a0 of signal data 24, least significant bit d0 of logical sum value 36 output from logical sum circuit 32, output ds0 of selector 332 (Sel0), and output q0 of flip-flop 333 (FF0). For simplicity of explanation, each of the flip-flops 331 and 333 is illustrated as a master-slave flip-flop in which the value of the data terminal D is taken into the master flip-flop (not shown) when the clock signal clk is high (or at the time of rising from low to high), and the output of the master flip-flop (not shown) is taken into the slave flip-flop (not shown) when the clock signal clk is low (or at the time of falling from high to low) and is output from the output terminal Q (the value of the output terminal Q is held and output until the clock signal clk next goes low). However, it goes without saying that the flip-flops 331 and 333 are not limited to the master-slave flip-flops described above.

[0080] The logical sum value 36 output from the logical sum circuit 32 in a certain cycle is the logical sum of the value of the signal data 24 in that cycle and the register value 37 held and output by the register 33 (the logical sum value 36 output from the logical sum circuit 32 in the cycle immediately preceding that cycle). Therefore, in FIG. 7(B), the least significant bit (LSB) a0 of the signal data 24 is shown as 0 in cycles 5 to 7 and 1 in cycle 8. This is to clarify the explanation of the operation when the block end signal BE is asserted in cycle 8. Note that the high level of the waveform is 1 and the low level is 0.

[0081] In cycle 8, the block end signal BE becomes 1. Also, the least significant bit a0 of the signal data 24 becomes 1. When the block end signal BE transitions from 0 to 1 in cycle 8, the flip-flop 331 sets the output Q (=selection signal s) to 1 at the falling edge of the clock signal clk (dashed arrow (1)). However, the selection signal s is 0 until just before the falling edge of the clock signal clk in cycle 8, and the selector 332 (Sel0) selects and outputs the least significant bit d0 of the logical sum value 36 output from the logical sum circuit 32. The terminal q0 connected to the output terminal Q of the flip-flop 333 (FF0) is 0 until cycle 8, and since the least significant bit a0 of the signal data 24 becomes 1 in cycle 8, the least significant bit d0 of the logical sum value 36 output from the logical sum circuit 32 transitions from 0 to 1. Furthermore, the selection signal s is 0 until just before the falling edge of the clock signal clk in cycle 8, the selector 332 (Sel0) selects d0, and its output ds0 transitions from 0 to 1 in cycle 8. The flip-flop 333 (FF0) captures ds0=1 when the clock signal clk is high in cycle 8, and at the falling edge of the clock signal clk in cycle 8, the terminal q0 connected to the output terminal Q of the flip-flop 333 (FF0) is set to 1 (dashed arrow (2)).

[0082] When the selection signal s becomes 1 at the falling edge of the clock signal clk in cycle 8, the selector 332 (Sel0) selects the low level (fixed value 0) and its output ds0 becomes 0 (dashed arrow (3)).

[0083] The output ds0=0 of the selector 332 (Sel0) is captured by the flip-flop 333 (FF0) when the clock signal clk transitions to high level in cycle 9, and the flip-flop 333 (FF0) sets the terminal q0 connected to the output terminal Q to 0 at the falling edge of the clock signal clk in cycle 9 (dashed arrow (5)). That is, the output (register value 37) of the flip-flop 333 (FF0) of the register 33 is reset to 0 at the falling edge of the clock signal clk in cycle 9. Note that the least significant bit a0 of the signal data 24 is 0 in cycle 9, and the least significant bit q0 of the register value 37 becomes 0 at the falling edge of the clock signal clk in cycle 9. As a result, d0, which is the logical sum of the least significant bit a0 of the signal data 24 and the least significant bit q0 of the register value 37, changes from 1 to 0 (dashed arrow (6)).

[0084] In cycle 9, the least significant bit a0 of the signal data 24 is 0, but in the first half of cycle 9, the terminal q0 connected to the output terminal Q of the flip-flop 333 (FF0) of the register 33 is 1, so the least significant bit d0 of the logical sum value 36 output from the logical sum circuit 32 is 1. At the falling edge of the clock signal clk in cycle 9, the selection signal s, which is the output of the flip-flop 331, changes from 1 to 0 (broken arrow (4)). D-2 ) takes in the outputs d0 to dD-2 of the OR circuit 32 generated in the second half of cycle 8 (the period when the clock signal clk is at low level), and holds and outputs the register value 37 as the final OR value of the block until the falling edge of the clock signal clk in cycle 9, and transmits it to the MSB side bit position detection circuit 34.

[0085] In cycle 9, the MSB-side bit position detection circuit 34 receives and holds the register value 37 (the final logical sum value 36 of the block) output by the register 33. The MSB-side bit position detection circuit 34 detects the first bit position at which a transition from 0 to 1 occurs on the MSB side of the bit string constituting the register value 37. The MSB-side bit position detection circuit 34 calculates and outputs the maximum exponent 22 from the detected bit position. Specifically, when the position at which the bit value of the register value 37 output by the register 33 is 1 is the Mth bit counting from the MSB side (M is an integer equal to or greater than 0), the MSB-side bit position detection circuit 34 outputs -1×M as the maximum exponent. For example, if the position at which the bit value of the register value 37 is 1 is the first bit counting from the MSB side, then the value of the 0th bit from the MSB side will be 0 for all of the remaining D-1 bits excluding the sign bit (MSB) in the input data. Conversely, in this case, the value of the first bit from the MSB side of the remaining bit string excluding the sign bit (MSB) of any of the input data is 1. Therefore, according to the above-mentioned calculation formula (-1 x M), it is possible to calculate -1 x 1 = -1 as the maximum exponent corresponding to the shift amount that does not change the sign of any of the input data and correctly expresses the normalized value.

[0086] Here, the register 33 outputs a register value 37 for each operation cycle, and the MSB side bit position detection circuit 34 calculates the maximum exponent 22 based on the register value 37 indicating the final logical sum value of the block. The MSB side bit position detection circuit 34 references the block end signal BE to identify the cycle in which the register value 37 indicating the final logical sum value of the block is output from the register 33. The MSB side bit position detection circuit 34 may include a register (not shown) that captures, holds, and outputs the register value 37 based on a signal obtained by sampling the block end signal BE with the clock signal clk, and detects the MSB side bit position from the held register value 37. As described above, after the register value 37 indicating the final logical sum value of the block is captured by the MSB side bit position detection circuit 34 in cycle 8, the register 33 is reset in cycle 9, and the register value 37 (q[D-2:0]) is set to 0.

[0087] 2 again, the correction circuit 21 can be realized, for example, by the configuration shown in Fig. 8. Referring to Fig. 8, the correction circuit 21 is composed of a plurality of selection conversion circuits 40 and a decoder circuit 42. This circuit corrects the value of the number of unconverted bits N in the signal data of the partial code absolute value representation normalized by the normalization circuit 20 to the same value as before the normalization process.

[0088] Specifically, the correction circuit 21 outputs the most significant bit indicating the code input from input IN[D-1] as is to OUT[D-1] as the code bit. The least significant bit (LSB) through N bits input from inputs IN[0] to IN[N-1] are output as is to outputs OUT[0] to OUT[N-1], respectively. The selection conversion circuit 40 selects either the input as is or after bit inversion by exclusive OR processing with the most significant bit (MSB) indicating the code input from input IN[D-1] based on the selection signal 41, and then outputs the selected bit to outputs OUT[N] to OUT[D-2], respectively.

[0089] The decoder circuit 42 references the maximum exponent 22 output by the normalization circuit 20 and controls each of the multiple selection conversion circuits 40 to output either the input data as is or bit-inverted data by exclusive ORing with the most significant bit indicating the code input from the input IN[D-1]. It outputs a selection signal 41 that corrects the number N of unconverted bits in the input signal data to the same as before normalization. (DN-1) selection conversion circuits 40 are connected to (DN-1) bits between the most significant bit (MSB) and the lower N bits including the least significant bit (LSB). N ~40 D-2 The decoder circuit 42 decodes the maximum exponent 22 and outputs the (DN-1) selection conversion circuits 40 N ~40 D-2 , and outputs the decoded result to (DN-1) selection signals 41. For example, if the maximum exponent 22 is -M (M-bit right shift: M≦(DN-1)), the decoder circuit 42 decodes M and outputs the decoded result to the selection conversion circuit 40 that connects the lower M bits IN[N] to IN[N+M-1] of the (DN-1) selection signals 41 to the lower M bits IN[N] to IN[N+M-1]. N ~40 N+M-1 Alternatively, the selection signal 41 may be output to select the other selection conversion circuits 40 and deselect the other selection conversion circuits 40.

[0090] The selection conversion circuit 40 can be realized, for example, by the configuration shown in Fig. 9. Referring to Fig. 9, the selection conversion circuit 40 is composed of an AND circuit 43 and an XOR circuit 44. When the value of the selection signal 41 is 0, the output of the AND circuit 43 is always 0, so the selection conversion circuit 40 outputs the input data as is. When the value of the selection signal 41 is 1, the output of the AND circuit 43 is the value of the sign bit input from the input IN[D-1], so the selection conversion circuit 40 outputs a value obtained by performing an exclusive OR operation with the sign bit (IN[D-1]) by the XOR circuit 44.

[0091] Through the above process, the correction circuit 21 performs a correction process on the signal data 24 of the partial code absolute value representation, whose number of unconverted bits N has been changed by the normalization circuit 20, to make the number of unconverted bits N the same as that of the partial code absolute value representation before the normalization process. The number of unconverted bits N of the signal data 24 of the partial code absolute value representation has been changed by the normalization circuit 20. Therefore, the signal data 24 of the partial code absolute value representation from the normalization circuit 20 cannot be correctly converted back to a two's complement representation by the conversion circuit 13b as it is. Therefore, by correcting the data obtained by normalizing the signal data of the partial code absolute value representation converted from a two's complement representation by the conversion circuit 13a in Figure 2 using the correction circuit 21, it can be converted back to a two's complement representation by the conversion circuit 13b in Figure 2.

[0092] Next, an example of the operation of the storage processing unit 11 will be described with reference to Fig. 10 and Fig. 11. Fig. 10 and Fig. 11 are timing charts showing an example of the operation of the storage processing unit 11. The storage processing unit 11 operates based on an input clock signal.

[0093] As an example of a block floating-point signal data block consisting of multiple signal data to be processed, we will explain a block whose mantissa consists of eight pieces of data, input data 1 to input data 8, as shown below. Each piece of input data is 8 bits (In[D-1,0], D=8). Below, the value of each piece of data is expressed in two's complement notation. Note that in the bit strings of the data shown below, the leftmost most significant bit is the MSB and the rightmost bit is the LSB. The MSB is the sign bit.

[0094] Input data 1: 00000111 Input data 2: 00010001 Input data 3: 00000110 Input data 4: 11110011 Input data 5: 11111000 Input data 6: 00000110 Input data 7: 11101011 Input data 8: 00011011

[0095] 10, the storage processing unit 11 sequentially inputs input data 1 to input data 8 in the first cycle (cycle 1) to the eighth cycle (cycle 8) of the operation cycle. Note that X represents Don't Care in the cycle immediately preceding cycle 1. In cycles 1 to 8, the conversion circuit 13a converts input data 1 to input data 8, which are expressed in two's complement notation, into partial code absolute value-- notation and outputs them as signal data 24(1) to signal data 24(8). Here, in the partial code absolute value-- notation, the number of data bits D=8 bits and the number of non-converted bits N=3 bits.

[0096] Conversion circuits 13a and 13b perform conversion processing corresponding to the number of non-conversion bits N=3. Therefore, when the MSB of signal data 24(1) to 24(8) is 1 among 8-bit data, the upper 3 bits from the least significant bit (LSB) are the same as the 2's complement representation, and the other lower 5 bits from the most significant bit (MSB) are the same as the sign-magnitude-- representation. Specifically, the values ​​are as follows:

[0097] Signal Data 24(1): 00000111 Signal Data 24(2): 00010001 Signal Data 24(3): 00000110 Signal Data 24(4): 10001011 Signal Data 24(5): 10000000 Signal Data 24(6): 00000110 Signal Data 24(7): 10010011 Signal Data 24(8): 00011011

[0098] In the signal data 24(4), (5), and (7), the lower N (=3) bits including the LSB of the input data are left unconverted, and the upper DN-1 (=4) bits are inverted from the input data.

[0099] In cycles 1 to 8, the memory circuit 14 receives and stores signal data 24(1) to 24(8).

[0100] Next, with reference to FIG. 10, the operations of the normalization circuit 20 and the correction circuit 21 will be described for each cycle.

[0101] (Cycle 1) In the first cycle (cycle 1) of the operation cycle, maximum exponent calculation circuit 30 in normalization circuit 20 receives signal data (1). Logical OR circuit 32 constituting maximum exponent calculation circuit 30 calculates the logical OR of the remaining 7 bits of signal data (1), excluding the sign bit (MSB), and register value 37(1) output by register 33. Logical OR circuit 32 outputs the calculated logical OR to register 33 as logical OR value (1). Here, the value of register value 37(1) in cycle 1 is the initial value of 0. Logical OR value 36(1): 0000111

[0102] Register 33 holds logical sum value 36(1) output by logical sum circuit 32 in cycle 1. Register 33 may be configured to capture and hold logical sum value 36(1) output by logical sum circuit 32 in cycle 1 at the rising edge of the clock signal in cycle 2. Register 33 outputs the held logical sum value 36(1) as register value 37(2) in cycle 2, which is the next operating cycle.

[0103] (Cycle 2) Next, in the second cycle (cycle 2) of the operation cycle, maximum exponent calculation circuit 30 receives signal data (2). Logical OR circuit 32 constituting maximum exponent calculation circuit 30 calculates a logical OR between the remaining 7 bits of signal data (2), excluding the sign bit (MSB), and register value 37(2) output by register 33 (logical OR value 36(1) output by logical OR circuit 32 in cycle 1), and outputs the calculated logical OR to register 33 as logical OR value 36(2). Here, the value of register value 37(2) in cycle 1 is logical OR value 36(1) held in cycle 1. Logical OR value 36(2): 0010111

[0104] Register 33 holds logical sum value 36(2) output by logical sum circuit 32 in cycle 2. Register 33 may be configured to capture and hold logical sum value 36(1) output by logical sum circuit 32 in cycle 2 at the rising edge of the clock signal in cycle 3. Register 33 outputs the held logical sum value 36(2) as register value 37(3) in cycle 3, which is the next operating cycle.

[0105] OR circuit 32 is a combinational circuit (asynchronous circuit) that outputs the logical OR of the remaining 7 bits of signal data (2), excluding the sign bit (MSB), and register value 37(1)(0), until the falling edge of the clock signal in cycle 2. When register value 37(2) (logical OR value 36(1)) is output from register 33 at the falling edge of the clock signal in cycle 2, OR circuit 32 outputs the logical OR of the remaining 7 bits of signal data (2), excluding the sign bit (MSB), and register value 37(2) (logical OR value 36(1)) to register 33 as logical OR value 36(2).

[0106] (Cycles 3 to 8) Similarly, in cycles 3 to 8, signal data (3) to signal data (8) are input. Logical OR circuit 32 constituting maximum exponent calculation circuit 30 calculates the logical OR of the remaining 7 bits excluding the sign bit of each of signal data (3) to signal data (8) with register value 37(3) to register value 37(8) output by register 33. Logical OR circuit 32 outputs the calculated logical OR to register 33 as logical OR value 36(3) to logical OR value 36(8). Here, the values ​​of register value 37(3) to register value 37(8) in cycles 3 to 8 are logical OR value 36(2) to logical OR value 36(7) held in cycles 2 to 7, respectively.

[0107] Logical OR value 36(3): 0010111 Logical OR value 36(4): 0011111 Logical OR value 36(5): 0011111 Logical OR value 36(6): 0011111 Logical OR value 36(7): 0011111 Logical OR value 36(8): 0011111

[0108] In cycle 8, the block end signal BE is made active (high level). The maximum exponent calculation circuit 30 receives signal data (8), and the logical sum circuit 32 calculates the logical sum of the remaining seven bits of the signal data (8), excluding the sign bit (MSB), and the register value 37(8) output by the register 33. In cycle 8, until the falling edge of the clock signal, the logical sum circuit 32 outputs the logical sum of the remaining seven bits of the signal data (8), excluding the sign bit (MSB), and the register value 37(7). When the register 33 outputs the register value 37(8) (logical sum value 36(7)) at the falling edge of the clock signal in cycle 8, the logical sum circuit 32 outputs the logical sum of the remaining seven bits of the signal data (8), excluding the sign bit (MSB), and the register value 37(8) (logical sum value 36(7)) to the register 33 as the logical sum value 36(8).

[0109] (Cycle 9) The register 33 takes in the logical sum value 36(8) output by the logical sum circuit 32 in cycle 8 at the rising edge of the clock signal in cycle 9, and outputs the logical sum value 36(8) as a register value 37(9) to the MSB side bit position detection circuit 34 at the falling edge of the clock signal in cycle 9. Cycle 9 is the cycle following the last operation cycle of the block.

[0110] In cycle 9, the MSB-side bit position detection circuit 34 detects the bit position of the transition value on the MSB side of the bit string that constitutes the final logical sum value (8) as a block. The MSB-side bit position detection circuit 34 calculates the maximum exponent from the detected bit position and outputs the calculated value to the maximum exponent 22. Specifically, if the MSB is the 0th bit, the bit position where the bit value of the logical sum value (8) is 1 is the 2nd bit counting from the MSB side. Therefore, according to the above-mentioned calculation formula (-1 × M), the maximum exponent is -1 × 2 = -2. Therefore, the MSB-side bit position detection circuit 34 outputs -2 as the maximum exponent 22.

[0111] In cycle 9, which is the cycle following the last operation cycle of the block, register 33 resets the logical sum value held for the block to the initial value of 0. As a result, register 33 outputs the initial value of 0 in the next cycle.

[0112] Here, the MSB side bit position detection circuit 34 and the register 33 identify the last operation cycle of each block as the cycle in which the value of the input block end signal becomes 1.

[0113] In FIG. 10, the value of the block end signal is 1 in cycle 8, which indicates that cycle 8 is the last operation cycle of the block.

[0114] Next, the operation of the normalization process in cycles 9 to 16 will be described with reference to FIG.

[0115] In cycles 1 to 8, the memory circuit 14 holds the signal data (1) to (8) while the maximum exponent calculation circuit 30 constituting the normalization circuit 20 is calculating the maximum exponent.

[0116] Next, in cycles 9 to 16 after the maximum exponent calculation circuit 30 has completed the calculation of the maximum exponent in cycle 9, the memory circuit 14 outputs the held input data to the signal data 23. Here, the memory circuit 14 may implement a data rearrangement process required in the signal processing device 10. For example, as the data rearrangement process, the signal data input in the order of signal data (1) to signal data (8) may be rearranged in the order of signal data (1), signal data (5), signal data (2), signal data (6), signal data (3), signal data (7), signal data (4), signal data (8), and output to the signal data 23.

[0117] In the following, a case will be described in which data is not rearranged and is output in the order in which it was input.

[0118] In the normalization circuit 20, the maximum exponent calculation circuit 30 calculates the maximum exponent in cycles 1 to 8. Next, in cycle 9, the maximum exponent calculation circuit 30 outputs −2, which is the calculated maximum exponent, to the shift circuit 29 as the maximum exponent 22. The maximum exponent calculation circuit 30 continues to output −2, which is the maximum exponent, until cycle 16, when the output of the input data held by the storage circuit 14 is completed.

[0119] Here, the maximum exponent calculation circuit 30 identifies the timing to end the output of the maximum exponent by referring to the block end signal. Specifically, the maximum exponent calculation circuit 30 ends the output of the maximum exponent in cycle 16 when the value of the block end signal becomes 1 again.

[0120] In cycles 9 to 16, shift circuit 29 performs normalization processing by sequentially arithmetically shifting signal data 23(1) to signal data 23(8) output by memory circuit 14 based on the maximum exponent −2 calculated and output by maximum exponent calculation circuit 30. Then, shift circuit 29 outputs the data obtained by shifting signal data 23(1) to signal data 23(8) as normalized data 25(1) to normalized data 25(8). Shift circuit 29 may be configured as a barrel shifter that shifts (arithmetically shifts) an arbitrary bit length at a time. In a barrel shifter, a shift (arithmetic shift) of multiple bits is performed within one clock cycle.

[0121] Here, when the maximum exponent output from the maximum exponent calculation circuit 30 is −m (m is an integer equal to or greater than 0), the shift circuit 29 performs normalization by arithmetically shifting the signal data 23(1) to 23(8) to the left by m bits.

[0122] As a result, the normalized data 25(1) to normalized data 25(8) output by the shift circuit 29 become the values ​​shown below, and the normalization process is completed correctly. The data after normalization of the signal data 23(k) is shown as normalized data 25(k) (k is a positive integer between 1 and 8).

[0123] Normalized Data 25(1): 00011100 Normalized Data 25(2): 01000100 Normalized Data 25(3): 00011000 Normalized Data 25(4): 10101100 Normalized Data 25(5): 10000000 Normalized Data 25(6): 00011000 Normalized Data 25(7): 11001100 Normalized Data 25(8): 01101100

[0124] The correction circuit 21 refers to the maximum exponent 22 and performs a process of correcting the number of unconverted bits N for the normalized data 25 of the partial code absolute value representation normalized by the normalization circuit 20 to the same value as before the normalization process.

[0125] The number of unconverted bits of the signal data 24 before normalization is N = 3. In contrast, the number of unconverted bits N of the normalized data 25 after normalization is changed to N = 5 as a result of being shifted 2 bits to the left by the normalization.

[0126] The correction circuit 21 converts only the fourth and fifth bits from the least significant bit (LSB) back into sign-magnitude--representation, thereby correcting N to N=3 before normalization.

[0127] In the correction circuit 21, the decoder circuit 42 references the value of the maximum exponent -2 output by the normalization circuit 20 to the maximum exponent 22, and outputs the value 0011 (expressed in binary) to the selection signal 41 so as to select and convert only the fourth and fifth bits from the most significant bit (MSB). Here, the value 0011 is a control signal value that controls the selection conversion circuit 40 not to convert the second and third bits from the most significant bit (MSB), and controls the selection conversion circuit 40 to convert the fourth and fifth bits from the most significant bit (MSB).

[0128] Specifically, in cycles 9 to 16, the correction circuit 21 performs correction processing on the normalized data 25(1) to normalized data 25(8) output by the normalization circuit 20, and outputs the corrected data 26(1) to corrected data 26(8).

[0129] Correction Data 26(1): 00011100 Correction Data 26(2): 01000100 Correction Data 26(3): 00011000 Correction Data 26(4): 10110100 Correction Data 26(5): 10011000 Correction Data 26(6): 00011000 Correction Data 26(7): 11010100 Correction Data 26(8): 01101100

[0130] In the normalized data 25(4), (5), and (7), the selection signal 41 inverts the fourth and fifth bits from the MSB.

[0131] Next, the conversion circuit 13b performs a conversion process corresponding to the number of non-conversion bits N = 3. Specifically, in cycles 9 to 16, the conversion circuit 13b converts the correction data 26(1) to the correction data 26(8) expressed in the partial code absolute value -- representation into two's complement representation and outputs them as output data (1) to output data (8).

[0132] Output data(1): 00011100 Output data(2): 01000100 Output data(3): 00011000 Output data(4): 11001100 Output data(5): 11100000 Output data(6): 00011000 Output data(7): 10101100 Output data(8): 01101100

[0133] In the output data (4), (5), and (7), the lower N (=3) bits including the LSB of the correction data are left unconverted, and each of the upper DN-1 (=4) bits is inverted from the correction data.

[0134] As described above, according to an example of the signal processing device 10 of the present disclosure, the storage processing units 11a, 11b, and 11c convert data expressed in two's complement representation into the partial sign-magnitude-value representation, perform storage processing, and then convert it back to two's complement representation. As shown in FIG. 3 , the partial sign-magnitude-value representation, like the sign-magnitude-value representation, has a small difference in bit values ​​between positive and negative values ​​with the value 0 as the boundary. Therefore, even when a signal that frequently changes between positive and negative values ​​near the value 0 is represented, the bit-wise operation rate is small. As a result, the circuit operation rate of the storage processing units 11a, 11b, and 11c can be reduced compared to when the signal is stored in the two's complement representation. Furthermore, the conversion process between the two's complement representation and the partial sign-magnitude-value representation by the conversion circuit 13 can be achieved only by bit inversion processing, eliminating the need for the increment process (increment) required for the sign-magnitude-value representation. The bit inversion process can be achieved using only an XOR circuit. This allows for a significantly smaller circuit scale than other logic processing circuits or arithmetic processing circuits. Furthermore, since fewer XOR circuits 17 are required than in the conversion between two's complement representation and sign-magnitude representation, the circuit scale of the conversion circuit 13 can be reduced accordingly.

[0135] FIG. 12 is a diagram that schematically illustrates the effects of the present disclosure using graphs. FIG. 12 shows a graph illustrating the effect of applying the partial sign-magnitude-value-- representation to two exemplary circuits, Circuit A and Circuit B, in a storage processing unit in an FFT processing circuit, each having a signal data bit width of 8 bits (D=8). The horizontal axis of FIG. 12 represents the number of bits (DN-1) to be inverted in the conversion process between the two's complement representation and the partial sign-magnitude-value-- representation. When there are 0 bits, no bits are inverted, and the conversion process is equivalent to the two's complement representation. When there are 7 bits, all bits except the sign bit are inverted, and the conversion process is equivalent to the sign-magnitude-value-- representation. When there are 1 to 6 bits, the conversion process corresponds to the partial sign-magnitude-value-- representation. The left vertical axis represents the reduction rate of the operation rate per bit, and is a relative value based on the operation rate in the two's complement representation. The right vertical axis represents the circuit size of the conversion circuit, and is a relative value based on the circuit size of the conversion circuit in the sign-magnitude-value-- representation.

[0136] Referring to FIG. 12, when the number of bits to be inverted in the partial sign-magnitude-value-- representation is, for example, 4, the bitwise operation rate of circuits A and B is reduced to approximately 20 to 30% of the case where the two's complement representation is applied, which is equivalent to the case where the sign-magnitude-value-- representation is applied. Meanwhile, the circuit scale is reduced to approximately 40% of the case where the sign-magnitude-value-- representation is applied. That is, according to this embodiment, a conversion circuit smaller than that of the sign-magnitude-value-- representation can reduce the bitwise operation rate to the same level as the sign-magnitude-value-- representation. In some embodiments of the present disclosure, even when processing signals that frequently change between positive and negative values ​​near the value 0, the circuit operation rate of the storage processing units 11a, 11b, and 11c can be reduced. This reduces the power consumption of the storage processing units 11a, 11b, and 11c.

[0137] The arithmetic processing is performed in the arithmetic processing units 12a and 12b using the two's complement representation. Therefore, the operation rate of the circuits involved in the arithmetic processing is not reduced. However, unlike when the sign-magnitude representation is used, since a conversion circuit (including a circuit for adding one) for converting data representation formats to and from the two's complement representation is not included, the circuit size does not increase. Therefore, the power consumption of the entire signal processing device can be reduced by the amount that the power consumption of the storage processing units 11a, 11b, and 11c is reduced.

[0138] In the above-described present disclosure, storage processing such as buffering processing, retiming processing, and rearrangement processing of signal data is performed in the storage processing units 11a, 11b, and 11c using the partial code absolute value representation, and arithmetic processing such as addition, subtraction, multiplication, and division is performed in the arithmetic processing units 12a and 12b using the two's complement representation. However, if a desired result can be obtained by processing using the partial code absolute value representation, the storage processing units 11a, 11b, and 11c may perform arithmetic processing such as addition, subtraction, multiplication, and division based on the partial code absolute value representation in addition to the storage processing.

[0139] Furthermore, the correction circuit 21 performs a correction process on the signal data 24 in the partial code absolute value-- representation in which the number of non-conversion bits N has been changed by the normalization circuit 20, thereby making the number of non-conversion bits N the same as that in the partial code absolute value-- representation before the normalization process. Therefore, even if the number of non-conversion bits N has been changed by the normalization process performed by the normalization circuit 20, it is possible to convert the partial code absolute value-- representation back to the two's complement representation. As a result, according to this embodiment, it is possible to perform a normalization process on signal data expressed in the partial code absolute value-- representation.

[0140] Normalization processing must be performed in the portion using two's complement representation, or if another representation format is used, it must be performed after converting to two's complement representation. This means that normalization processing cannot be performed in the appropriate portion, or multiple circuits for conversion to two's complement representation are required. This results in problems such as increased circuit size and power consumption. In contrast, according to this embodiment, normalization processing can be performed in the appropriate portion without converting to two's complement representation, thereby reducing circuit size and power consumption.

[0141] Other examples of some embodiments of the present disclosure will be described. Fig. 13 is a diagram showing an example of the configuration of a storage processing unit 51. The storage processing unit 51 includes a conversion circuit 13, a storage circuit 14, a normalization circuit 20, and a conversion circuit 53. The conversion circuit 13, the storage circuit 14, and the normalization circuit 20 have the same configuration as the circuits constituting the storage processing unit 11 in Fig. 2, and are assigned the same reference numerals. The conversion circuit 53 has a different configuration from the conversion circuit 13 in Fig. 4, and performs conversion processing by referring to the maximum exponent 22.

[0142] Fig. 14 is a diagram showing an example of the configuration of the conversion circuit 53. Referring to Fig. 14, the conversion circuit 53 outputs the most significant bit indicating the code input from input IN[D-1] as is to OUT[D-1] as a code bit. The least significant bit to N bits input from inputs IN[0] to IN[N-1] are output as is to outputs OUT[0] to OUT[N-1], respectively.

[0143] The other (DN-1) bits input from the inputs IN[N] to IN[D-2] are respectively input to the selection conversion circuit 40 N ~40 D-2 Based on the selection signal 55, either the input is left as is, or the input is bit-inverted by exclusive ORing with the most significant bit indicating the code input from input IN[D-1], and then output to outputs OUT[N] to OUT[D-2], respectively.

[0144] The decoder circuit 54 refers to the maximum exponent 22 output by the normalization circuit 20 and controls each of the multiple selection conversion circuits 40 to output either the input as is, or the data after bit inversion and conversion by exclusive OR processing with the most significant bit indicating the code input from input IN[D-1], thereby outputting a selection signal 55 that corrects the representation bit position in the input signal data to be the same as before the normalization processing.

[0145] Specifically, the decoder circuit 54 controls the selection conversion circuit 40 so that the least significant bit (LSB) to N bits are not converted. The (DN-1) bits between the most significant bit (MSB) which is the sign bit and the lower N bits are converted by the selection conversion circuit 40. N ~40 D-2 As a result, the conversion circuit 53 can directly convert signal data expressed in the partial sign magnitude representation, in which the number of non-converted bits N has been changed by normalization processing, into two's complement representation.

[0146] Next, an example of the operation of the storage processing unit 51 will be described. In the storage processing unit 51, the conversion circuit 13, the memory circuit 14, and the normalization circuit 20 have the same configuration as the circuits constituting the storage processing unit 11 according to the first embodiment, and perform the same operations. Specifically, the operations performed are the same as those of the storage processing unit 11 in cycles 1 to 9 described in Fig. 10, and therefore the operations of the storage processing unit 51 in cycles 1 to 9 will not be described.

[0147] The operation of the conversion circuit 53 in cycles 9 to 16 will be described with reference to FIG. The normalization circuit 20 operates in the same manner as the normalization circuit 20 of the storage processing unit 11 according to the first embodiment in cycles 9 to 16. Specifically, in cycles 9 to 16, the normalization data 25(1) to 25(8) output by the normalization circuit 20 have the following values:

[0148] Normalized Data 25(1): 00011100 Normalized Data 25(2): 01000100 Normalized Data 25(3): 00011000 Normalized Data 25(4): 10101100 Normalized Data 25(5): 10000000 Normalized Data 25(6): 00011000 Normalized Data 25(7): 11001100 Normalized Data 25(8): 01101100

[0149] The conversion circuit 53 refers to the maximum exponent 22 and converts the normalized data 25 of the partial sign absolute value representation normalized by the normalization circuit 20 into output data expressed in two's complement representation. The number of unconverted bits N of the normalized data 25 after normalization is changed to N=5 as a result of being shifted two bits to the left by the normalization process. The conversion circuit 53 performs bit inversion on only the second and third bits from the most significant bit by exclusive ORing with the most significant bit, thereby correctly converting the data into two's complement representation.

[0150] In the conversion circuit 53, the decoder circuit 54 references the maximum exponent, −2, output to the maximum exponent 22 by the normalization circuit 20, and outputs the value 1100 (expressed in binary) to the selection signal 55 so as to select and convert only the second and third bits from the most significant bit (MSB). Here, the value 1100 is output by the selection conversion circuits 406, 405 (40 in FIG. 14) of the second and third bits from the most significant bit. D-2 , 40 D-3, D=8), and the selection conversion circuits 404 and 403 (40 in FIG. 14) for the fourth and fifth bits from the most significant bit are controlled to convert the D―4 , 40 D-5 , D=8) is a control signal value that controls so that no conversion is performed. Specifically, in cycles 9 to 16, the conversion circuit 53 converts normalized data 25(1) to normalized data 25(8) output by the normalization circuit 20 into two's complement representation and outputs them as output data (1) to output data (8).

[0151] Output data(1): 00011100 Output data(2): 01000100 Output data(3): 00011000 Output data(4): 11001100 Output data(5): 11100000 Output data(6): 00011000 Output data(7): 10101100 Output data(8): 01101100

[0152] In the configuration of FIG. 2, for example, for normalized data (7) 11001100 with 8 bits (D=8) and the number of unconverted bits N=3, when the maximum exponent 22 is -2, in the correction circuit 21 (FIG. 8), the 4-bit selection signal 41 (0011) from the decoder circuit 42 is used to invert the bits from IN[3] and IN[4] in the selection conversion circuits 40(3) and 40(4), and the selection conversion circuits 40(5) and 40(6) output correction data (7) 11010100 with the bits from IN[5] and IN[6] left unchanged, and the conversion circuit 13b (FIG. 4) inverts the bits from IN[3] to IN[6] to output output data 10101100 from OUT[7:0]. In response to this, in conversion circuit 53, the bits from IN[5] and IN[6] are inverted in selection conversion circuits 40(5) and 40(6) in response to a 4-bit selection signal 55(1100) from decoder circuit 54, and the bits from IN[3] and IN[4] are left unchanged in selection conversion circuits 40(3) and 40(4), and output data (7) 10101100 is output from OUT[7:0].

[0153] As described above, in this example as well, the partial sign absolute value -- representation can reduce the operating rate of the circuit in the storage processing unit 51 even when processing a signal that frequently changes between positive and negative values ​​near the value 0. This makes it possible to reduce power consumption in the storage processing unit 51.

[0154] Furthermore, the conversion circuit 53 can directly convert the signal data 24 in the partial sign absolute value representation, in which the number of unconverted bits N has been changed by the normalization circuit 20, into a two's complement representation by referring to the maximum exponent 22. As a result, normalization processing can be performed even on signal data expressed in the partial sign absolute value representation. Therefore, normalization processing can be performed at an appropriate point without converting to a two's complement representation. As a result, the circuit size and power consumption can be reduced. Furthermore, the correction circuit 21 in FIG. 2 is not required, and the circuit size and power consumption can be reduced accordingly.

[0155] FIG. 16 is a diagram schematically illustrating an example of an FFT device 130 according to an embodiment of the present disclosure. The FFT device 130 processes a 64-point FFT decomposed into two stages of radix-8 butterfly processing using a pipeline circuit according to the data flow 500 shown in FIG. 21. The FFT device 130 receives time-domain data x(n) (n=0, 1, . . . , N-1) and performs a Fourier transform on x(n) using FFT processing to generate and output a frequency-domain signal X(k) (k=0, 1, . . . , N-1). Here, N is a positive integer representing the FFT block size. Although not particularly limited, it is assumed that the FFT device 130 performs 64-point FFT processing with eight data in parallel (N=64). In this case, the FFT device 130 receives time-domain data x(n) and performs a Fourier transform on the x(n) using FFT processing to generate and output a frequency-domain signal X(k). At this time, a total of 64 pieces of data are input as input data x(n), 8 pieces of data at a time, over a period of 8 cycles, in the order shown in Fig. 17. Note that the numbers 0 to 63 shown as the contents of the table (elements of 8 rows and 8 columns) in Fig. 17 represent the subscript n of x(n).

[0156] Specifically, in the first cycle, eight pieces of data x(0), x(1), . . . , x(7) that make up the data set P1 are input.

[0157] Then, in the second cycle, eight pieces of data x(8), x(9), ..., x(15) that make up data set P2 are input. Similarly, from the third to eighth cycles, data that make up data sets P3 to P8 are input.

[0158] Similarly, 64 pieces of data are output as output data X(k), eight pieces of data at a time over a period of eight cycles, in the order shown in Fig. 10. Note that the numbers 0 to 63 shown as the contents of the table in Fig. 10 represent the subscript k of X(k).

[0159] Specifically, in the first cycle, eight pieces of data x(0), x(1), . . . , x(7) that make up the data set P1 are output.

[0160] In the second cycle, eight pieces of data x(8), x(9), . . . , x(15) that make up data set P2 are output. Similarly, from the third to eighth cycles, data that make up data sets P3 to P8 are output.

[0161] As shown in FIG. 16, the FFT device 130 includes a first data rearrangement unit 200a, a first butterfly calculation unit 301a, a second data rearrangement unit 200b, a twiddle multiplication unit 302, a second butterfly calculation unit 301b, and a third data rearrangement unit 200c.

[0162] The FFT device 130 performs pipeline processing of the first data rearrangement process, the first butterfly operation process, the second data rearrangement process, the twiddle multiplication process, the second butterfly operation process, and the third data rearrangement process.

[0163] The first data rearrangement unit 200a and the second data rearrangement unit 200b are buffer circuits for rearranging data. The first data rearrangement unit 200a and the second data rearrangement unit 200b rearrange the data sequence before and after the first butterfly calculation unit 301a, respectively, based on the data dependency in the FFT processing algorithm.

[0164] Similarly, the third data rearrangement unit 200c is a buffer circuit for rearranging data, and rearranges the data sequence after the second butterfly computation unit 301b based on the data dependency in the FFT processing algorithm.

[0165] Specifically, the first data rearrangement unit 200a rearranges the input order of the input data x(n) from the "sequential order" shown in FIG. 17 to the "bit reverse order" shown in FIG. 18, which is the order in which the data is input to the first butterfly calculation unit 301a.

[0166] The bit reverse order shown in FIG. 18 corresponds to the input data set to the radix-8 butterfly calculation processing unit 502 in the first stage in the data flow diagram shown in FIG.

[0167] Specifically, in the first cycle, eight pieces of data x(0), x(8), . . . , x(56) that make up data set Q1 are input. Then, in the second cycle, eight pieces of data x(1), x(9), . . . , x(57) that make up data set Q2 are input. Thereafter, in the third to eighth cycles, data that make up data sets Q3 to Q8 are input in the same manner.

[0168] The sequential order refers to the order of the eight data sets P1, P2, P3, P4, P5, P6, P7, and P8 shown in Fig. 17. Each data set Ps (s is a value indicating the order of the processing cycle, s = 1, 2, ..., 8) consists of eight data items arranged in order from ps(0) to ps(7).

[0169] Assuming that a total of 64 pieces of data x(0) to x(63) are input in the order shown in FIG. 17, with 8 pieces of data each over a period of 8 cycles, ps(i) (i=0, . . . , 7) is given by the following: ps(i)=x[8×(s-1)+i]

[0170] The data sets are arranged in the order of P1, P2, P3, P4, P5, P6, P7, and P8 in accordance with the progress of the processing cycle. "Sequential order" means that s sets of data sets are created by arranging is data items in order of i items from the beginning, and then arranging each data set in cycle order.

[0171] The bit reverse order refers to the order of the eight data sets Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 shown in Figure 18. Each data set Qs (where s is a value representing the order of the processing cycle, and s = 1, 2, ..., 8) consists of eight data items arranged in order from qs(0) to qs(7). For 64 data items x(0) to x(63) input in sequential order, qs(i) (i = 0, ..., 7) is given by: qs(i)=x[(s-1)+8×i]

[0172] The data sets are arranged in the order of Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8, corresponding to the progress of the processing cycle. The bit-reverse order is where is data items input in sequential order are arranged in cycle order, starting from the beginning, with s items at a time, and i data items in the same cycle are grouped together and arranged in data order.

[0173] Each data set in bit reverse order is uniquely determined once each set in sequential order is set. Among the data constituting each data set Qs (s=1,...,8) in bit reverse order, the i-th data Qs(i) (i=0,...,7) is the s-1-th data Pi+1(s-1) in the i+1-th cycle in sequential order. That is, Qs(i)=Pi+1(s-1)

[0174] Here, if the i-th data of Ps and Qs (s=1,...,8) is expressed as Ps(i) and Qs(i) (i=1,...,8), the above formula becomes Qs(i)=Pi(s) This becomes:

[0175] That is, for the data in each data set, Qs(i) and Pi(s) have a relationship in which the order of the cycle progression and the order of the data positions are interchanged. Therefore, if data input in bit reverse order is rearranged according to the bit reverse order, it will be in sequential order.

[0176] Each row ps(i) in Fig. 17 and each of the eight rows qs(i) in Fig. 18 indicate the data to be input at the i-th stage in the next stage. The eight numbers included in each data set are identification information that specifies one of the FFT points, specifically the value of the subscript n in x(n).

[0177] The sequential order and bit-reverse order are not limited to those exemplified in Figures 17 and 18. That is, each data set in the sequential order may be created by arranging data in order according to the number of FFT points, the number of cycles, and the number of data to be processed in parallel, as described above. And each data set in the bit-reverse order may be created by swapping the order of the data input in the sequential order with respect to the progression of cycles and the order with respect to the data positions, as described above.

[0178] The first butterfly computation unit 301a is a butterfly computation unit that processes the first butterfly computation (first butterfly computation) of the radix-8 butterfly computations that are performed twice in the data flow 500 of FIG.

[0179] The first butterfly computation unit 301a outputs the results of the butterfly computation as data y(n) (n=0, 1, . . . , 63) in the sequential order shown in FIG.

[0180] The second data rearrangement unit 200b rearranges the data y(n) output in sequential order by the first butterfly calculation unit 301a into the bit-reverse order shown in FIG. 18 for input to the second butterfly calculation unit 301b.

[0181] The twiddle multiplication unit 302 is a circuit that processes complex rotation on the complex plane in the FFT calculation after the first butterfly calculation process, and corresponds to the twiddle multiplication unit 504 in the data flow 500 in Fig. 21. Note that in the twiddle multiplication process, data rearrangement is not performed.

[0182] The second butterfly operation unit 301b corresponds to the butterfly operation processing circuit that performs the second processing in the radix-8 butterfly operation unit 503 in the data flow diagram of Fig. 21. The second butterfly operation unit 301b performs butterfly operation on the post-twiddle multiplication data y'(n) (n=0, 1,..., 63) that is input in bit-reverse order, and outputs the result X(k) (n=0, 1,..., 63), also in bit-reverse order.

[0183] The third data rearrangement unit 200c rearranges the data X(k) output in bit reverse order by the second butterfly computation unit 301b into the sequential order shown in FIG.

[0184] The data rearrangement unit 200 temporarily stores input data and controls the selection and output of the stored data, thereby realizing data rearrangement processing in accordance with either the sequential order shown in Fig. 17 or the bit-reverse order shown in Fig. 18. A specific example of the data rearrangement unit 200 is shown below.

[0185] Referring to FIG. 19, the data rearrangement processing unit 200 includes a first conversion circuit 231, a first data distribution unit 202, eight RAM circuits 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h, a second data distribution unit 203, a write address control unit 212, a read address control unit 213, a normalization circuit 220, and a second conversion circuit 232.

[0186] The first conversion circuit 231 simultaneously (in parallel) inputs eight data (D-bit data in two's complement representation) from eight inputs in0 to in7 input in the sequential order shown in FIG. 17, and converts the data expressed in two's complement representation into partial code absolute value -- representation.

[0187] The first conversion circuit 231 is composed of eight conversion circuits 13a to 13h corresponding to eight inputs in0 to in7. Each of the conversion circuits 13a to 13h is identical to the conversion circuit 13 in Fig. 4. The conversion circuits 13a to 13h convert the data input in parallel, expressed in two's complement notation, into a partial code absolute value-- notation. Specifically, when the most significant bit indicating the sign in the input D-bit data is 1, (DN-1) bits excluding the most significant bit and the most significant N bits from the least significant bit are inverted and converted into a partial code absolute value-- notation.

[0188] The first data distribution unit 202 performs distribution processing on the eight pieces of data converted into the partial code absolute value -- representation by the first conversion circuit 231, and outputs the data to eight outputs (data lines) 205a to 205h.

[0189] Each of the eight RAM circuits 210a-210h can store eight pieces of data. Therefore, the RAM circuits 210a-210h can store a total of 64 pieces of data (8 x 8: 8 in parallel, 8 deep), which is equal to the number of points in a 64-point FFT. The RAM circuits 210a-210h are dual-port RAM circuits with independent write and read ports. When write and read operations occur at the same time for the same address, read operations take priority. That is, data stored at the addresses targeted for write and read operations is read first, followed by the data targeted for write operations. The RAM circuits 210a-210h may be configured as dual-port static random access memory (SRAM) or dynamic random access memory (DRAM). Control terminals such as chip enable (CE), output enable (OE), and write enable (WE), as well as the control signals input to these control terminals, are omitted from the RAM circuits 210a-210h.

[0190] The RAM circuit 210a stores the data output by the first data distribution unit 202 to the data line (D bit) 205a at the address output by the write address control unit 212 to the address line 207a, and reads out the stored data from the address output by the read address control unit 213 to the address line 208a and outputs it to the data line 206a.

[0191] Similarly, the RAM circuit 210b stores the data output by the first data distribution unit 202 to the data line 205b at the address output by the write address control unit 212 to the address line 207b, and reads out the stored data from the address output by the read address control unit 213 to the address line 208b and outputs it to the data line 206b.

[0192] The RAM circuit 210c stores the data output by the first data distribution unit 202 to the data line 205c at the address output by the write address control unit 212 to the address line 207c, and reads out the stored data from the address output by the read address control unit 213 to the address line 208c and outputs it to the data line 206c.

[0193] The RAM circuit 210d stores the data output by the first data distribution unit 202 to the data line 205d at the address output by the write address control unit 212 to the address line 207d, and reads out the stored data from the address output by the read address control unit 213 to the address line 208d and outputs it to the data line 206d.

[0194] The RAM circuit 210e stores the data output by the first data distribution unit 202 to the data line 205e at the address output by the write address control unit 212 to the address line 207e, and reads out the stored data from the address output by the read address control unit 213 to the address line 208e and outputs it to the data line 206e.

[0195] The RAM circuit 210f stores the data output by the first data distribution unit 202 to the data line 205f at the address output by the write address control unit 212 to the address line 207f, and reads out the stored data from the address output by the read address control unit 213 to the address line 208f and outputs it to the data line 206f.

[0196] The RAM circuit 210g stores the data output by the first data distribution unit 202 to the data line 205g at the address output by the write address control unit 212 to the address line 207g, and reads out the stored data from the address output by the read address control unit 213 to the address line 208g and outputs it to the data line 206g.

[0197] The RAM circuit 210h stores the data output by the first data distribution unit 202 to the data line 205h at the address output by the write address control unit 212 to the address line 207h, and reads out the stored data from the address output by the read address control unit 213 to the address line 208h and outputs it to the data line 206h.

[0198] The second data distribution unit 203 simultaneously receives eight pieces of data from eight inputs (data lines) 206a to 206h, performs data distribution processing, and simultaneously outputs eight pieces of data from eight output data lines 209a to 209h to the normalization circuit 220. The normalization circuit 220 includes eight normalization circuits 20a to 20h (FIG. 5) corresponding to the eight output data lines 209a to 209h.

[0199] The eight normalization circuits 20a to 20h of the normalization circuit 220 each normalize a block consisting of eight consecutive data, and output normalized data 25a to 25h and maximum exponents 22a to 22h to the eight conversion circuits 53a to 53h of the second conversion circuit 232, respectively.

[0200] Each of the conversion circuits 53a to 53h of the second conversion circuit 232 has the configuration shown in Fig. 14. When the most significant bit of the input normalized data (D bits) expressed in two's complement notation is 1 (negative data), the conversion circuits 53 (53a to 53h) invert the bits of the selection signal 55 that are 1 for (DN-1) bits between the most significant bit of the normalized data and the lowest N bits on the least significant bit (LSB) side based on the selection signal 55 that is the result of decoding the maximum exponent 22 (22a to 22h) by the decoder circuit 54 and output the result.

[0201] The write address control section 212 refers to the input operation mode 201 and outputs addresses to which the RAM circuits 210a to 210h write data to the address lines 207a to 207h, respectively.

[0202] The read address control section 213 refers to the input operation mode 201 and outputs addresses from which the RAM circuits 210a to 210h read data to the address lines 208a to 208h, respectively.

[0203] Next, a specific operation of the data rearrangement unit 200 will be described.

[0204] The data rearrangement unit 200 During the eight cycles from t0 to t7, 64 pieces of data from 0a to 63a are input in sequential order from inputs in0 to in7 in eight parallel inputs. In the eight cycles from t8 to t15, 64 pieces of data 0a to 63a are output in bit reverse order to eight outputs out0 to out7 in parallel.

[0205] The data rearrangement unit 200 similarly During the eight cycles from t8 to t15, 64 pieces of data from 0b to 63b are input in sequential order from input in0 to in7 in eight parallel inputs. During the eight cycles from t16 to t23, 64 pieces of data from 0b to 63b are output in bit reverse order to eight outputs out0 to out7 in parallel.

[0206] The data rearrangement unit 200 further During the eight cycles from t16 to t23, 64 pieces of data from 0c to 63c are input in sequential order from input in0 to in7 in eight parallel inputs. In the eight cycles from t24 to t31, 64 pieces of data 0c to 63c are output in bit reverse order to the outputs out0 to out7 in eight parallel arrangements (not shown).

[0207] First, the input operation of data 0a to 63a in the eight cycles from t0 to t7 in the data rearrangement processing unit 200 will be described in detail.

[0208] The first data distribution unit 202 In cycle t0, Data 0a is input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a), and output to the data line 205a. The data 1a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205b, The data 2a input from in2 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205c, The data 3a input from in3 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205d, The data 4a input from in4 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205e, The data 5a input from in5 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205f, The data 6a input from in6 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205g, The data 7a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205h.

[0209] The first data distribution unit 202 In cycle t1, The data 8a input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205b, The data 9a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205c, The data 10a input from in2 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205d, The data 11a input from in3 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205e, The data 12a input from in4 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205f, The data 13a input from in5 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205g, The data 14a input from in6 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205h, The data 15a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205a.

[0210] The first data distribution unit 202 In cycle t2, The data 16a input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205c, The data 17a input from in1 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205d, The data 18a input from in2 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205e, The data 19a input from in3 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205f, The data 20a input from in4 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205g, The data 21a input from in5 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205h, The data 22a input from in6 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205a, The data 23a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205b.

[0211] The first data distribution unit 202 In cycle t3, The data 24a input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205d, The data 25a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205e, The data 26a input from in2 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205f, The data 27a input from in3 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205g, The data 28a input from in4 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205h, The data 29a input from in5 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205a, The data 30a input from in6 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205b, The data 31a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205c.

[0212] The first data distribution unit 202 In cycle t4, The data 32a input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205e, The data 33a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205f, The data 34a input from in2 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205g, The data 35a input from in3 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205h, The data 36a input from in4 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205a, The data 37a input from in5 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205b, The data 38a input from in6 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205c, The data 39a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205d.

[0213] The first data distribution unit 202 In cycle t5, The data 40a input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205f, The data 41a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205g, The data 42a input from in2 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205h, The data 43a input from in3 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205a, The data 44a input from in4 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205b, The data 45a input from in5 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205c, The data 46a input from in6 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205d, The data 47a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205e.

[0214] The first data distribution unit 202 In cycle t6, The data 48a input from in0 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205g, The data 49a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205h, The data 50a input from in2 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205a, The data 51a input from in3 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205b, The data 52a input from in4 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205c, The data 53a input from in5 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205d, The data 54a input from in6 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205e, The data 55a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205f.

[0215] The first data distribution unit 202 In cycle t7, The data 56a input from in0 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13a) is output to the data line 205h, The data 57a input from in1 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13b) is output to the data line 205a, The data 58a input from in2 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13c) is output to the data line 205b, The data 59a input from in3 and converted from a two's complement representation to a partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13d) is output to the data line 205c, The data 60a input from in4 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13e) is output to the data line 205d, The data 61a input from in5 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13f) is output to the data line 205e, The data 62a input from in6 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13g) is output to the data line 205f, The data 63a input from in7 and converted from two's complement representation to partial sign absolute value representation by the first conversion circuit 231 (conversion circuit 13h) is output to the data line 205g.

[0216] As described above, the first data distribution unit 202 rotates and outputs eight pieces of data that are input simultaneously in parallel, and can be easily realized by, for example, a shift circuit.

[0217] Similarly, the first data distribution unit 202 In cycles t9 to t15, data 0b to 63b are sorted. In the cycles from t16 to t23, the allocation operation is performed on data 0c to 63c.

[0218] Next, the write and read operations of the write address control unit 212, the read address control unit 213, and the RAM circuits 210a to 210h controlled by them will be described.

[0219] The write address control unit 212 and the read address control unit 213 operate by referring to the input operation mode 201. Here, the operation mode 201 is a control signal given from a higher-level control circuit (not shown) such as a CPU (Central Processing Unit), and is either a first or second operation mode.

[0220] The operation mode 201 indicates the same operation mode for eight consecutive cycles in which data corresponding to the number of points of the 64-point FFT is input, and indicates a different operation mode every eight cycles.

[0221] Specifically, in FIG. 20, the operation mode 201 indicates the operation mode 0, which is the first operation mode, during the eight cycles from t0 to t7 in which data 0a to 63a are input.

[0222] The eight cycles from t8 to t15 in which data 0b to 63b are input indicate the second operation mode, operation mode 1. In the eight cycles from t8 to t15, data is read in operation mode 1, which is the second operation mode, from the RAM circuits 210a to 210h to which data was written in operation mode 0, which is the first operation mode, in the eight cycles from t0 to t7.

[0223] In the eight cycles from t16 to t23 in which data 0c to 63c are input, the first operation mode, operation mode 0, is again indicated. In the eight cycles from t16 to t23 in which data 0c to 63c are input, data is read in operation mode 0, the first operation mode, from the RAM circuits 210a to 210h in which data was written in operation mode 1, the second operation mode, in the eight cycles from cycles t8 to t15.

[0224] Similarly, the operation mode 201 is a signal that alternately indicates operation mode 0 or operation mode 1 every eight cycles.

[0225] When the input operation mode 201 is operation mode 0, which is the first operation mode, the write address control section 212 generates write addresses in accordance with the first address order.

[0226] When the input operation mode 201 is operation mode 1, which is the second operation mode, the write address control section 212 generates write addresses in accordance with the second address order.

[0227] The first address sequence is an address sequence that always specifies different addresses for each of the RAM circuits 210a to 210h. That is, in the first operation mode, different addresses are always output to the address lines 207a to 207h.

[0228] On the other hand, the second address order is an address order that always specifies the same address for each of the RAM circuits 210a to 210h. That is, in the second operation mode, the same addresses are always output to the address lines 207a to 207h.

[0229] The read address control unit 213 also performs the same operation as the write address control unit 212. That is, when the input operation mode 201 is operation mode 0, which is the first operation mode, the read address control unit 213 generates read addresses (mutually different addresses) for each of the RAM circuits 210a to 210h in accordance with the first address order. When the input operation mode 201 is operation mode 1, which is the second operation mode, the read address control unit 213 generates read addresses (mutually identical addresses) for each of the RAM circuits 210a to 210h in accordance with the second address order.

[0230] A specific example of the write and read operations of the write address control unit 212, the read address control unit 213, and the RAM circuits 210a to 210h will be described with reference to FIG.

[0231] first, In the eight cycles from t0 to t7, data 0a to 63a are written to the RAM circuits 210a to 210h.

[0232] In the eight cycles from t8 to t15, the data 0a to 63a written to the RAM circuits 210a to 210h are read out, and the data 0b to 63b are written to the RAM circuits 210a to 210h.

[0233] In eight cycles from t16 to t23, data 0b to 63b written to the RAM circuits 210a to 210h are read, and data 0c to 63c are written to the RAM circuits 210a to 210h. Note that in the eight cycles from t0 to t7, a read operation of the data written in the previous eight cycles from t0 to t7 is also performed, but this is not shown in the figure.

[0234] 20, writing and reading in the RAM circuits 210a to 210h are always performed to the same address in the same cycle. When writing and reading occur at the same timing to the same address, the RAM circuits 210a to 210h prioritize reading. Therefore, in the RAM circuits 210a to 210h, data 0a to 63a are read and then data 0b to 63b are written in each of the cycles t8 to t15.

[0235] Similarly, in each of the cycles t16 to t23, data 0b to 63b are read, and then data 0c to 63c are written.

[0236] Next, details of the write operations of the write address control unit 212 and the RAM circuits 210a to 210h controlled by it in cycles t0 to t7 will be shown.

[0237] Referring to Figure 20, In the eight cycles from t0 to t7, the operation mode 201 indicates the operation mode 0, which is the first operation mode, and the write address control unit 212 generates write addresses in accordance with the first address order.

[0238] The RAM circuits 210a to 210h write the data output by the first data distribution unit 202 to 207a to 207h to the write addresses generated by the write address control unit 212.

[0239] in particular, In cycle t0, The RAM circuit 210a writes data 0a to the address 0 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes data 1a to address 1 output by the write address control unit 212 onto the address line 207b. The RAM circuit 210c writes data 2a to address 2 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes data 3a to address 3 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes data 4a to address 4 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes data 5a to address 5 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes data 6a to the address 6 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes data 7a to the address 7 output by the write address control unit 212 to the address line 207h.

[0240] In cycle t1, The RAM circuit 210a writes data 15a to address 7 output by the write address control unit 212 onto the address line 207a. The RAM circuit 210b writes the data 8a to the address 0 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 9a to the address 1 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 10a to the address 2 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 11a to the address 3 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 12a to the address 4 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 13a to the address 5 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 14a to the address 6 output by the write address control unit 212 to the address line 207h.

[0241] In cycle t2, The RAM circuit 210a writes the data 22a to the address 6 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 23a to the address 7 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 16a to the address 0 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 17a to the address 1 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 18a to the address 2 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 19a to the address 3 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 20a to the address 4 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 21a to the address 5 output by the write address control unit 212 to the address line 207h.

[0242] In cycle t3, The RAM circuit 210a writes the data 29a to the address 5 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 30a to the address 6 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 31a to the address 7 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 24a to the address 0 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 25a to the address 1 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 26a to the address 2 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 27a to the address 3 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 28a to the address 4 output by the write address control unit 212 to the address line 207h.

[0243] In cycle t4, The RAM circuit 210a writes the data 36a to the address 4 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 37a to the address 5 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 38a to the address 6 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 39a to the address 7 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 32a to the address 0 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 33a to the address 1 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 34a to the address 2 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 35a to the address 3 output by the write address control unit 212 to the address line 207h.

[0244] In cycle t5, The RAM circuit 210a writes the data 43a to the address 3 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 44a to the address 4 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 45a to the address 5 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 46a to the address 6 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 47a to the address 7 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 40a to the address 0 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 41a to the address 1 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 42a to the address 2 output by the write address control unit 212 to the address line 207h.

[0245] In cycle t6, The RAM circuit 210a writes the data 50a to the address 2 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 51a to the address 3 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 52a to the address 4 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes data 53a to address 5 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 54a to the address 6 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 55a to the address 7 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 48a to the address 0 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 49a to the address 1 output by the write address control unit 212 to the address line 207h.

[0246] In cycle t7, The RAM circuit 210a writes the data 57a to the address 1 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 58a to the address 2 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 59a to the address 3 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 60a to the address 4 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 61a to the address 5 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 62a to the address 6 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 63a to the address 7 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 56a to the address 0 output by the write address control unit 212 to the address line 207h.

[0247] As described above, in the first address order, different addresses are output to the address lines 207a to 207h that indicate the write addresses of the RAM circuits 210a to 210h.

[0248] Also, different addresses are output to the address lines 207a to 207h in each of the cycles t0 to t7. For example, different addresses 0 to 7 are output to the address line 207a in the cycles t0 to t7.

[0249] Next, a specific example of the read operation of the read address control unit 213 and the RAM circuits 210a to 210h controlled by it in the cycles t8 to t15 will be shown.

[0250] As a result of the write operations in cycles t0 to t7, at the time of cycle t8, data 0a to 63a are stored in the RAM circuits 210a to 210h, respectively, as shown in FIG.

[0251] In eight cycles from t8 to t15, the operation mode 201 indicates the second operation mode, operation mode 1, and the read address control unit 213 generates read addresses in accordance with the second address order. The RAM circuits 210a to 210h output the stored data from the read addresses generated by the read address control unit 213 to the data lines 206a to 206h.

[0252] in particular, In cycle t8, The read address control unit 213 outputs an address 0 to all of the address lines 208a to 208h. The RAM circuit 210a reads data 0a from address 0. The RAM circuit 210b reads data 8a from address 0. The RAM circuit 210c reads the data 16a from address 0. The RAM circuit 210d reads the data 24a from address 0. The RAM circuit 210e reads the data 32a from address 0. The RAM circuit 210f reads the data 40a from address 0. The RAM circuit 210g reads the data 48a from address 0. The RAM circuit 210h reads the data 56a from address 0.

[0253] In cycle t9, The read address control unit 213 outputs the address 1 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 57a from address 1. The RAM circuit 210b reads data 1a from address 1. The RAM circuit 210c reads data 9a from address 1. The RAM circuit 210d reads the data 17a from address 1. The RAM circuit 210e reads the data 25a from address 1. The RAM circuit 210f reads the data 33a from address 1. The RAM circuit 210g reads the data 41a from address 1. The RAM circuit 210h reads the data 49a from address 1.

[0254] In cycle t10, The read address control unit 213 outputs the address 2 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 50a from address 2. The RAM circuit 210b reads the data 58a from address 2. The RAM circuit 210c reads data 2a from address 2. The RAM circuit 210d reads the data 10a from address 2. The RAM circuit 210e reads the data 18a from address 2. The RAM circuit 210f reads the data 26a from the address 2. The RAM circuit 210g reads the data 34a from address 2. The RAM circuit 210h reads the data 42a from address 2.

[0255] In cycle t11, The read address control unit 213 outputs the address 3 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 43a from address 3. The RAM circuit 210b reads the data 51a from address 3. The RAM circuit 210c reads the data 59a from address 3. The RAM circuit 210d reads data 3a from address 3. The RAM circuit 210e reads the data 11a from the address 3. The RAM circuit 210f reads the data 19a from address 3. The RAM circuit 210g reads the data 27a from address 3. The RAM circuit 210h reads the data 35a from address 3.

[0256] In cycle t12, The read address control unit 213 outputs the address 4 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 36a from address 4. The RAM circuit 210b reads the data 44a from address 4. The RAM circuit 210c reads the data 52a from address 4. The RAM circuit 210d reads the data 60a from address 4. The RAM circuit 210e reads data 4a from address 4. The RAM circuit 210f reads the data 12a from the address 4. The RAM circuit 210g reads the data 20a from address 4. The RAM circuit 210h reads the data 28a from address 4.

[0257] In cycle t13, The read address control unit 213 outputs the address 5 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 29a from address 5. The RAM circuit 210b reads the data 37a from address 5. The RAM circuit 210c reads the data 45a from address 5. The RAM circuit 210d reads data 53a from address 5. The RAM circuit 210e reads the data 61a from address 5. The RAM circuit 210f reads data 5a from address 5. The RAM circuit 210g reads the data 13a from the address 5. The RAM circuit 210h reads the data 21a from address 5.

[0258] In cycle t14, The read address control unit 213 outputs the address 6 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 22a from address 6. The RAM circuit 210b reads the data 30a from address 6. The RAM circuit 210c reads the data 38a from address 6. The RAM circuit 210d reads the data 46a from address 6. The RAM circuit 210e reads the data 54a from address 6. The RAM circuit 210f reads the data 62a from the address 6. The RAM circuit 210g reads data 6a from address 6. The RAM circuit 210h reads the data 14a from the address 6.

[0259] In cycle t15, The read address control unit 213 outputs the address 7 to all of the address lines 208a to 208h. The RAM circuit 210a reads data 15a from address 7. The RAM circuit 210b reads the data 23a from the address 7. The RAM circuit 210c reads the data 31a from address 7. The RAM circuit 210d reads the data 39a from address 7. The RAM circuit 210e reads the data 47a from the address 7. The RAM circuit 210f reads the data 55a from the address 7. The RAM circuit 210g reads the data 63a from the address 7. The RAM circuit 210h reads data 7a from address 7.

[0260] As described above, in the second address order, the same address is output to all of the address lines 208a-208h, which indicate the read addresses of the RAM circuits 210a-210h. Also, different addresses are output to the address lines 208a-208h in the cycles t8-t15. For example, different addresses, addresses 0-7, are output to the address line 208a in the cycles t8-t15.

[0261] Next, a specific example of the write operation of the write address control unit 212 and the RAM circuits 210a to 210h controlled by it in the cycles t8 to t15 will be shown.

[0262] In the eight cycles from t8 to t15, the operation mode 201 indicates the operation mode 1, which is the second operation mode, and the write address control unit 212 generates write addresses in accordance with the second address order.

[0263] The RAM circuits 210a to 210h write the data that the first data distribution unit 202 has output to the data lines 205a to 205h to the write addresses generated by the write address control unit 212.

[0264] in particular, In cycle t8, The write address control unit 212 outputs an address 0 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 0b to address 0. The RAM circuit 210b writes data 1b to address 0. The RAM circuit 210c writes data 2b to address 0. The RAM circuit 210d writes data 3b to address 0. The RAM circuit 210e writes data 4b to address 0. The RAM circuit 210f writes data 5b to address 0. The RAM circuit 210g writes data 6b to address 0. The RAM circuit 210h writes data 7b to address 0.

[0265] In cycle t9, The write address control unit 212 outputs the address 1 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 15b to address 1. The RAM circuit 210b writes data 8b to address 1. The RAM circuit 210c writes data 9b to address 1. The RAM circuit 210d writes data 10b to address 1. The RAM circuit 210e writes the data 11b to the address 1. The RAM circuit 210f writes data 12b to address 1. The RAM circuit 210g writes data 13b to address 1. The RAM circuit 210h writes data 14b to address 1.

[0266] In cycle t10, The write address control unit 212 outputs address 2 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 22b to address 2. The RAM circuit 210b writes data 23b to address 2. The RAM circuit 210c writes data 16b to address 2. The RAM circuit 210d writes the data 17b to the address 2. The RAM circuit 210e writes the data 18b to the address 2. The RAM circuit 210f writes the data 19b to the address 2. The RAM circuit 210g writes the data 20b to the address 2. The RAM circuit 210h writes the data 21b to the address 2.

[0267] In cycle t11, The write address control unit 212 outputs the address 3 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 29b to address 3. The RAM circuit 210b writes data 30b to address 3. The RAM circuit 210c writes data 31b to address 3. The RAM circuit 210d writes data 24b to address 3. The RAM circuit 210e writes data 25b to address 3. The RAM circuit 210f writes the data 26b to the address 3. The RAM circuit 210g writes the data 27b to the address 3. The RAM circuit 210h writes the data 28b to the address 3.

[0268] In cycle t12, The write address control unit 212 outputs the address 4 to all of the address lines 207a to 207h. The RAM circuit 210a writes the data 36b to address 4. The RAM circuit 210b writes data 37b to address 4. The RAM circuit 210c writes the data 38b to address 4. The RAM circuit 210d writes data 39b to address 4. The RAM circuit 210e writes data 32b to address 4. The RAM circuit 210f writes the data 33b to the address 4. The RAM circuit 210g writes the data 34b to the address 4. The RAM circuit 210h writes the data 35b to the address 4.

[0269] In cycle t13, The write address control unit 212 outputs the address 5 to all of the address lines 207a to 207h. The RAM circuit 210a writes the data 43b to the address 5. The RAM circuit 210b writes the data 44b to the address 5. The RAM circuit 210c writes data 45b to address 5. The RAM circuit 210d writes the data 46b to the address 5. The RAM circuit 210e writes the data 47b to the address 5. The RAM circuit 210f writes the data 40b to the address 5. The RAM circuit 210g writes the data 41b to the address 5. The RAM circuit 210h writes the data 42b to the address 5.

[0270] In cycle t14, The write address control unit 212 outputs the address 6 to all of the address lines 207a to 207h. The RAM circuit 210a writes the data 50b to the address 6. The RAM circuit 210b writes data 51b to address 6. The RAM circuit 210c writes data 52b to address 6. The RAM circuit 210d writes data 53b to address 6. The RAM circuit 210e writes the data 54b to the address 6. The RAM circuit 210f writes data 55b to address 6. The RAM circuit 210g writes the data 48b to the address 6. The RAM circuit 210h writes data 49b to address 6.

[0271] In cycle t15, The write address control unit 212 outputs the address 7 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 57b to address 7. The RAM circuit 210b writes data 58b to address 7. The RAM circuit 210c writes data 59b to address 7. The RAM circuit 210d writes the data 60b to the address 7. The RAM circuit 210e writes the data 61b to the address 7. The RAM circuit 210f writes the data 62b to the address 7. The RAM circuit 210g writes the data 63b to the address 7. The RAM circuit 210h writes data 56b to address 7.

[0272] As described above, in the second address order, the same address is output to all of the address lines 207a to 207h that indicate the write addresses of the RAM circuits 210a to 210h.

[0273] Also, different addresses are output to address lines 207a to 207h in cycles t8 to t15, respectively. For example, different addresses 0 to 7 are output to address line 207a in cycles t0 to t7.

[0274] Next, a specific example of the read operation of the read address control unit 213 and the RAM circuits 210a to 210h controlled by it in the cycles t16 to t23 will be shown.

[0275] As a result of the write operation in cycles t8 to t15, at the time of cycle t16, data 0b to 63b are stored in the RAM circuits 210a to 210h as shown in FIG.

[0276] In the eight cycles from t16 to t23, the operation mode 201 indicates the first operation mode, operation mode 0, and the read address control unit 213 generates read addresses according to the first address order. The RAM circuits 210a to 210h output the stored data from the read addresses generated by the read address control unit 213 to the data lines 206a to 206h.

[0277] Specifically, in cycle t16, The RAM circuit 210a reads data 0b from the address 0 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 8b from address 1 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads out data 16b from address 2 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads the data 24b from the address 3 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 32b from address 4 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads the data 40b from the address 5 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 48b from the address 6 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads data 56b from address 7 output by the read address control unit 213 to the address line 208h.

[0278] In cycle t17, The RAM circuit 210a reads data 57b from address 7 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 1b from address 0 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 9b from address 1 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads out data 17b from address 2 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 25b from address 3 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads the data 33b from the address 4 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 41b from the address 5 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads out data 49b from address 6 output by the read address control unit 213 to the address line 208h.

[0279] In cycle t18, The RAM circuit 210a reads out data 50b from address 6 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 58b from address 7 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 2b from address 0 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads out data 10b from address 1 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out the data 18b from the address 2 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads the data 26b from the address 3 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 34b from the address 4 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads the data 42b from the address 5 output by the read address control unit 213 to the address line 208h.

[0280] In cycle t19, The RAM circuit 210a reads out the data 43b from the address 5 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads out data 51b from address 6 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 59b from address 7 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 3b from address 0 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 11b from address 1 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads out the data 19b from the address 2 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 27b from the address 3 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads out the data 35b from the address 4 output by the read address control unit 213 to the address line 208h.

[0281] In cycle t20, The RAM circuit 210a reads out the data 36b from the address 4 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 44b from address 5 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 52b from address 6 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 60b from address 7 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 4b from address 0 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads data 12b from the address 1 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 20b from the address 2 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads the data 28b from the address 3 output by the read address control unit 213 to the address line 208h.

[0282] In cycle t21, The RAM circuit 210a reads data 29b from address 3 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 37b from address 4 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 45b from address 5 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads out data 53b from address 6 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out the data 61b from the address 7 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads data 5b from address 0 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out data 13b from address 1 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads the data 21b from the address 2 output by the read address control unit 213 to the address line 208h.

[0283] In cycle t22, The RAM circuit 210a reads out data 22b from address 2 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 30b from address 3 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads the data 38b from the address 4 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 46b from address 5 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out the data 54b from the address 6 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads out the data 62b from the address 7 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads data 6b from address 0 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads out data 14b from address 1 output by the read address control unit 213 to the address line 208h.

[0284] In cycle t23, The RAM circuit 210a reads data 15b from address 1 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 23b from address 2 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 31b from address 3 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 39b from address 4 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 47b from address 5 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads out data 55b from address 6 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 63b from the address 7 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads data 7b from address 0 output by the read address control unit 213 to the address line 208h.

[0285] As described above, in the first address order, different addresses are output to the address lines 208a to 208h that indicate the read addresses of the RAM circuits 210a to 210h.

[0286] Also, different addresses are output to the address lines 208a to 208h in each of the cycles t16 to t23. For example, different addresses 0 to 7 are output to the address line 208a in the cycles t16 to t23.

[0287] Next, the operation of the second data distribution unit 203 in the cycle from t8 to t15 will be described.

[0288] Specifically, in cycle t8, Data 0a, 8a, 16a, 24a, 32a, 40a, 48a, and 56a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209a, 209b, 209c, 209d, 209e, 209f, 209g, and 209h.

[0289] In cycle t9, Data 57a, 1a, 9a, 17a, 25a, 33a, 41a, and 49a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209h, 209a, 209b, 209c, 209d, 209e, 209f, and 209g.

[0290] In cycle t10, Data 50a, 58a, 2a, 10a, 18a, 26a, 34a, and 42a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209g, 209h, 209a, 209b, 209c, 209d, 209e, and 209f.

[0291] In cycle t11, Data 43a, 51a, 59a, 3a, 11a, 19a, 27a, and 35a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209f, 209g, 209h, 209a, 209b, 209c, 209d, and 209e.

[0292] In cycle t12, Data 36a, 44a, 52a, 60a, 4a, 12a, 20a, and 28a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209e, 209f, 209g, 209h, 209a, 209b, 209c, and 209d.

[0293] In cycle t13, Data 29a, 37a, 45a, 53a, 61a, 5a, 13a, and 21a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209d, 209e, 209f, 209g, 209h, 209a, 209b, and 209c.

[0294] In cycle t14, Data 22a, 30a, 38a, 46a, 54a, 62a, 6a, and 14a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209c, 209d, 209e, 209f, 209g, 209h, 209a, and 209b.

[0295] In cycle t15, Data 15a, 23a, 31a, 49a, 47a, 55a, 63a, and 7a input from data lines 206a, 206b, 206c, 206d, 206e, 206f, 206g, and 206h are output from data lines 209b, 209c, 209d, 209e, 209f, 209g, 209h, and 209a.

[0296] As described above, as a result of the data distribution process by the second data distribution unit 203, data 0a to 63a are output to the data lines 209a to 209h in bit reverse order in the cycles t8 to t15.

[0297] The second data distribution unit 203, like the first data distribution unit 202, rotates and outputs eight pieces of data that are input in parallel at the same time, and can be easily realized by, for example, a shift circuit.

[0298] The second data distribution unit 203 also performs a similar distribution operation on data 0b to 63b in the cycles t16 to t23, and outputs data 0b to 63b to out0 to out7 in bit reverse order.

[0299] The normalization circuit 20a performs normalization processing on the block of eight data 0a, 1a, 2a, 3a, 4a, 5a, 6a, and 7a output from the second data distribution unit 203 to the data line 209a in cycles t8 to t15, respectively, and outputs normalized data 25a and maximum exponent 22a to the conversion circuit 53a. The conversion circuit 53a generates a selection signal in the decoder circuit 54 based on the maximum exponent 22a, converts the D-bit normalized data 25a into two's complement representation, and outputs it from the output terminal out0. The normalization circuit 20a may be provided with a memory for holding data for a period (e.g., 8 cycles) during which the maximum exponent calculation circuit 30 of FIG. 5 calculates the maximum exponent for one block of data. The memory may store data 0a, 1a, 2a, 3a, 4a, 5a, 6a, and 7a output from the second data sorting unit 203 in cycles t8 to t15, calculate a maximum exponent 22a in a maximum exponent calculation circuit (20 of FIG. 5) not shown, and output data obtained by shifting the data 0a, 1a, 2a, 3a, 4a, 5a, 6a, and 7a by the maximum exponent 22a as normalized data 25a together with the maximum exponent 22a in cycles t16 to 24. Data 0b, 1b, 2b, 3b, 4b, 5b, 6b, and 7b of the next block are sequentially stored in the memory (not shown) of the normalization circuit 20a, and calculate the maximum exponent.

[0300] Similarly, the normalization circuit 20b performs normalization processing on the block of eight data 8a, 9a, 10a, 11a, 12a, 13a, 14a, and 15a output from the second data distribution unit 203 to the data line 209b in cycles t8 to t15, and outputs normalized data 25b and maximum exponent 22b to the conversion circuit 53b. The conversion circuit 53b generates a selection signal based on the maximum exponent 22b, converts the D-bit normalized data 25b into two's complement representation, and outputs it from the output terminal out1. Like the normalization circuit 20a, the normalization circuit 20b includes a memory (not shown) of a length (e.g., 8) corresponding to the number of data in one block, and the memory stores the data 8a-15a output from the second data sorter 203 in cycles t8-t15, calculates the maximum exponent 22b in a maximum exponent calculation circuit (20 in FIG. 5), and outputs the data 8a-15a shifted by the maximum exponent 22b as normalized data 25b together with the converted exponent 22b in cycles t16-t23, and stores the data 8b-15b of the next block in the memory (not shown) of the normalization circuit 20b, and calculates the maximum exponent. The pairs of the normalization circuit 20c and conversion circuit 53c to the normalization circuit 20h and conversion circuit 53h operate in the same manner.

[0301] The data rearrangement process has been described above using an example of rearrangement from sequential order to bit-reverse order, but rearrangement from bit-reverse order to sequential order can also be similarly realized.

[0302] As described above, the data rearrangement unit 200 provided in the FFT device 130 realizes the data rearrangement process required for the butterfly computation, such as rearrangement from "sequential order" to "bit-reverse order" and rearrangement from "bit-reverse order" to "sequential order", by controlling the write and read operations of the RAM circuits 210a to 210h using two types of address orders, first and second.

[0303] For example, data written to a RAM circuit in a first address order is read out in a second address order, and data written in the second address order is read out in the first address order.

[0304] As a result, even when performing FFT processing on continuously input signals, data rearrangement can be achieved using a RAM circuit with a storage capacity equal to the number of FFT points.

[0305] Therefore, compared to double-buffer technology, which requires a storage capacity of at least twice the number of FFT points for data rearrangement, this disclosure can reduce the storage capacity of the RAM circuit by half, thereby reducing the circuit size and power consumption of the RAM circuit. As a result, the circuit size and power consumption of the entire FFT device 130, including the data rearrangement processing unit, can be reduced.

[0306] Furthermore, the FFT device 130 of the present disclosure performs the data rearrangement required for butterfly computation, from "sequential order" to "bit-reverse order" or from "bit-reverse order" to "sequential order," after converting to the partial code absolute value -- representation. Therefore, compared to performing the rearrangement process while keeping the two's complement representation, it is possible to reduce the operation rate of circuits such as flip-flop circuits and selector circuits that constitute the RAM circuits 210a to 210h and the first data distribution unit 202 and second data distribution unit 203.

[0307] Furthermore, in the present disclosure, the conversion process between two's complement representation and partial sign-magnitude-value representation can be realized only by bit inversion processing, and does not require the 1 addition process (increment process) required for sign-magnitude-value representation. Since the bit inversion processing circuit can be realized using only XOR circuits, it can be realized with an overwhelmingly smaller circuit scale than other logic processing circuits or arithmetic processing circuits. Furthermore, since fewer XOR circuits are required compared to the conversion process between two's complement representation and partial sign-magnitude-value representation, it can be realized with an even smaller circuit scale.

[0308] Therefore, according to the present disclosure, even when processing a signal that frequently changes between positive and negative values ​​near the value 0, the operation rate of the circuit in the data rearrangement process can be reduced, thereby reducing power consumption in the data rearrangement processing unit.

[0309] The butterfly operation processing and twiddle multiplication processing are performed in the butterfly operation processing unit and the twiddle multiplication processing unit using the two's complement representation. Therefore, the operation rate of the circuits related to these operations is not reduced, but the circuit scale does not increase due to conversion between data representation formats, as occurs when the sign-magnitude representation is applied.

[0310] Therefore, according to the present disclosure, the power consumption of the entire FFT device can be reduced by the amount of power consumed by the data rearrangement process. Furthermore, since the circuit scale of the transform circuit is smaller than that of the sign-magnitude representation, more transform processing can be performed at more optimal locations. Therefore, the power consumption of the entire FFT device can be further reduced.

[0311] The above-described embodiments are, for example, as follows (but are not limited to):

[0312] (Appendix 1) The signal processing device is The digital multiplier comprises an arithmetic processing unit that performs arithmetic processing on data expressed in two's complement representation, and a storage processing unit that performs storage processing on data expressed in a second representation format as a data representation format. The second representation format, with respect to the D-bit data, is If the value of the data is positive or 0, it is the same as the two's complement representation, If the value of the data is negative, the representation format is one in which the (DN-1) bits between the most significant bit indicating the sign and the lowest N bits (N is a positive integer N≦D-2) on the least significant bit side of the D-bit (D is a positive integer D≧3) two's complement representation are inverted. The storage processing unit includes a normalization circuit that normalizes a block made up of a plurality of data represented in the second representation format. The normalization circuit includes a maximum exponent calculation circuit that calculates a maximum exponent from a logical operation result corresponding to a bit-by-bit logical sum between the plurality of data of the block for (D-1) bits excluding the most significant bit of the plurality of data of the block, and a shift circuit that arithmetically shifts the plurality of data of the block by the maximum exponent.

[0313] (Supplementary Note 2) In the signal processing device of Supplementary Note 1, the maximum exponent calculation circuit comprises a logical OR circuit; The register includes a detection circuit for detecting the maximum exponent. The OR circuit outputs the result of a bit-by-bit OR operation between (D-1) bits excluding the most significant bit of the input data and the (D-1) bit register value output from the register. the register receives the (D-1)-bit logical sum operation result output from the logical sum circuit in parallel in response to a clock signal, holds and outputs the result as the register value; When the data input to the OR circuit is the first data of the block, the register supplies the register value in which the (D-1) bits are all 0 to the OR circuit. When the final logical sum operation result of the block by the logical sum circuit is output from the register as the register value, the detection circuit receives the register value and detects, as the maximum exponent, the first bit position of the final logical sum operation result of the block that transitions from 0 to 1, counting from the most significant bit side.

[0314] (Appendix 3) In the signal processing device of appendix 1 or 2, the register receives a block end signal, and in a cycle in which the block end signal indicates that the data is the last of the plurality of data in the block, the OR circuit outputs a result of an OR operation between the last data of the block and the register value from the register as a final OR operation result for the block; In response to the clock signal, the register takes in the final logical sum of the blocks, holds and outputs the result as the register value, transmits the register value to the detection circuit, and then resets the register value to 0.

[0315] (Supplementary Note 4) In the signal processing device according to any one of Supplementary Notes 1 to 3, the storage processing unit includes a correction circuit that corrects the data expressed in the second representation format normalized by the normalization circuit; the correction circuit includes a decoding circuit that decodes the maximum exponent calculated by the normalization circuit and outputs a selection signal; and a selection correction circuit that outputs the value of each of the (DN-1) bits between the most significant bit and the lowest N bits (N is a positive integer such that N≦D-2) on the least significant bit side of the data expressed in the second representation format normalized by the normalization circuit either as is or inverted based on the most significant bit of the data normalized by the normalization circuit and the selection signal.

[0316] (Appendix 5) In the signal processing device of Appendix 4, the storage processing unit includes a first conversion circuit that converts the data expressed in the two's complement representation into data expressed in the second representation format; a second conversion circuit that converts the data expressed in the second representation format output from the correction circuit into data expressed in the two's complement representation.

[0317] (Supplementary Note 6) In the signal processing device according to any one of Supplementary Notes 1 to 3, the storage processing unit includes a first conversion circuit that converts the data expressed in the two's complement representation into data expressed in the second representation format; and a second conversion circuit that converts the data expressed in the second representation format output from the normalization circuit into data expressed in the two's complement representation. The second conversion circuit includes a decoding circuit that decodes the maximum exponent calculated by the normalization circuit and outputs a selection signal, and a selection correction circuit that outputs, for the data expressed in the second representation format normalized by the normalization circuit, the value of each of the (DN-1) bits between the most significant bit and the lowest N bits (N is a positive integer such that N≦D-2) on the least significant bit side, either as is or an inverted value, based on the most significant bit of the data normalized by the normalization circuit and the selection signal.

[0318] (Appendix 7) In the signal processing device of Appendix 6, The data rearrangement processing unit rearranges a plurality of data input in a first order into a second order. The data rearrangement processing unit includes: a first conversion circuit that receives the plurality of data in the two's complement representation and converts the received plurality of data from the two's complement representation to the second representation format and outputs the converted data; a first data allocation unit that receives the plurality of data in the second representation format output from the first conversion circuit and performs allocation processing; a memory circuit having a plurality of memory elements that store the plurality of data for a plurality of cycles; a first control unit that writes the plurality of data in the second representation format to the memory circuit according to one of a first address order and a second address order; and a second control unit that reads the plurality of data in the second representation format, which have been written to the memory circuit according to one of the first address order and the second address order, from the memory circuit according to the other of the first address order and the second address order. The plurality of data in the second representation format sorted by the first data sorting unit are written into the plurality of memory elements of the memory circuit using addresses from the first control unit. The data rearrangement processing unit further includes: a second data sorting unit that receives the plurality of data in the second representation format read from the plurality of memory elements of the memory circuit according to addresses from the second control unit and performs sorting processing; a plurality of normalization circuits that receive the plurality of data in the second representation format output from the second data sorting unit, respectively; and a plurality of second conversion circuits that receive the plurality of normalized data in the second representation format and the maximum exponent output from the plurality of normalization circuits, correct the (DN-1) bits between the lowest N bits (N is a positive integer such that N≦D-2) on the least significant bit side of the input plurality of data in the second representation format by correcting a bit selected based on the maximum exponent, converting the data into the plurality of data in the two's complement representation, and outputting the converted data.

[0319] (Supplementary Note 8) In the signal processing device of Supplementary Note 7, in the memory processing unit, the first address order is such that the addresses simultaneously supplied to the memory elements are different from one another; In the second address order, the addresses simultaneously supplied to the storage elements are the same.

[0320] (Supplementary Note 9) The signal processing device of Supplementary Note 7 is a signal processing device that performs an n×n point fast Fourier transform or an inverse fast Fourier transform, and the storage processing unit includes first to third data rearrangement processing units that are composed of the data rearrangement processing unit. The arithmetic processing unit includes first and second butterfly arithmetic processing units, and a twiddle multiplication processing unit that performs processing to multiply data by a twiddle coefficient. the first data rearrangement processing unit receives n pieces of data input in parallel in sequential order for n cycles, rearranges the data in bit reverse order, and outputs n pieces of the data rearranged in bit reverse order in parallel for n cycles; the first butterfly operation unit performs a butterfly operation on the n pieces of data output in parallel from the first data rearrangement unit, and outputs the n pieces of data resulting from the butterfly operation in parallel; the second data rearrangement unit receives n pieces of data output in parallel in sequential order from the first butterfly operation unit for n cycles, rearranges the pieces of data in the bit reverse order, and outputs n pieces of data rearranged in the bit reverse order in parallel for n cycles; the twiddle multiplication processing unit multiplies the data output from the second data rearrangement processing unit by a corresponding twiddle coefficient; the second butterfly calculation unit performs butterfly calculations on the n pieces of data output from the twiddle multiplication unit, and outputs the n pieces of data resulting from the butterfly calculations in parallel; the third data rearrangement unit receives n cycles of n pieces of data output in parallel in the bit reverse order from the second butterfly operation unit, rearranges the data into the sequential order, and outputs n pieces of the data rearranged in the sequential order in parallel for n cycles; The first and second butterfly calculation processing units and the twiddle multiplication processing unit perform calculation processing on the data expressed in the two's complement representation.

[0321] (Supplementary Note 10) A signal processing method for performing arithmetic processing on data expressed in two's complement representation and storing data expressed in a second representation format as a data representation format, the second representation format is identical to two's complement representation when the data value is positive or 0; If the data value is negative, it is a representation format in which the (DN-1) bits between the most significant bit indicating the sign and the lower N bits (N is a positive integer N≦D-2) including the least significant bit are inverted from the two's complement representation of D bits (D is a positive integer D≧3), The storage process includes: a normalization process for a block consisting of a plurality of data represented in the second representation format, for lower (D-1) bits excluding the most significant bit of the plurality of data, to find a maximum exponent from a calculation result corresponding to a bit-by-bit logical sum between the plurality of data, and normalizing the plurality of data of the block by the maximum exponent; The normalization process is determining a maximum exponent from a result of a bit-by-bit logical operation between a plurality of data for lower (D-1) bits excluding the most significant bit of the plurality of data in the block; The bit string excluding the most significant bit of the plurality of data is shifted by the maximum exponent.

[0322] (Supplementary Note 11) The signal processing method of Supplementary Note 10, The process of obtaining the maximum exponent is a logical sum circuit outputs a result of a bit-by-bit logical sum operation between the (D-1) bits excluding the most significant bit of the input data and the (D-1) bit register value output from the register; a register that receives the (D-1)-bit logical sum operation result output from the logical sum circuit in parallel in response to a clock signal, holds and outputs the result as the register value; When the data input to the OR circuit is the first data of the block, the register supplies the register value in which the (D-1) bits are all 0 to the OR circuit, and when the final OR operation result of the block by the OR circuit is output from the register as the register value, the register detects the first bit position that transitions from 0 to 1, counting from the most significant bit side of the final OR operation result of the block, as the maximum exponent.

[0323] (Supplementary Note 12) The signal processing method of Supplementary Note 11, the register receives a block end signal, and in a cycle in which the block end signal indicates that the data is the last of the plurality of data in the block, the OR circuit outputs a result of an OR operation between the last data of the block and the register value from the register as a final OR operation result for the block; In response to the clock signal, the register takes in the final logical sum of the blocks, holds and outputs the result as the register value, transmits the register value to the detection circuit, and then resets the register value to 0.

[0324] (Supplementary Note 13) The signal processing method according to any one of Supplementary Notes 10 to 12, the storage process includes a correction process of correcting the data expressed in the second representation format normalized in the normalization process, The correction process decodes the maximum exponent and outputs a selection signal, and outputs the value of each of the (DN-1) bits between the most significant bit and the lowest N bits (N is a positive integer satisfying N≦D-2) on the least significant bit side of the data normalized by the normalization circuit, either as is or inverted, based on the most significant bit of the data normalized by the normalization circuit and the selection signal.

[0325] (Supplementary Note 14) The signal processing method of Supplementary Note 13, In the storage process, a first conversion process converts the data expressed in the two's complement representation from the first arithmetic process into data expressed in the second representation format; A second conversion process converts the data expressed in the second representation format into data expressed in the two's complement representation and outputs the converted data to a second arithmetic process.

[0326] (Supplementary Note 15) The signal processing method according to any one of Supplementary Notes 10 to 13, In the storage process, a first conversion process converts the data expressed in the two's complement representation from the first arithmetic process into data expressed in the second representation format; When converting the data expressed in the second representation format into data expressed in the two's complement representation and outputting it to a second arithmetic process, the second conversion process decodes the maximum exponent and outputs a selection signal, and outputs the value of each of the (DN-1) bits between the most significant bit and the lowest N bits (N is a positive integer such that N≦D-2) on the least significant bit side of the data expressed in the normalized second representation format either as is or with an inverted value, based on the most significant bit of the data normalized by the normalization circuit and the selection signal.

[0327] (Supplementary Note 16) The signal processing method of Supplementary Note 14, The storage process includes a data rearrangement process for rearranging a plurality of data items input in a first order into a second order. the data rearrangement process includes a first conversion process of inputting the plurality of data represented in two's complement representation, converting the input plurality of data from the two's complement representation to the second representation format, and outputting the converted data; a first data sorting process for inputting the plurality of data in the second representation format output from the first conversion circuit and performing sorting; a process of writing the plurality of data in the second representation format to a storage circuit including a plurality of storage elements for storing the plurality of data for a plurality of cycles, in accordance with one of a first address sequence and a second address sequence; and a process of reading the plurality of data in the second representation format, which have been written to the storage circuit in accordance with one of the first address sequence and the second address sequence, from the storage circuit in accordance with the other of the first address sequence and the second address sequence. The plurality of data in the second representation format, which have been sorted by the first data sorting process, are written to the plurality of memory elements of the storage circuit. a second data sorting process for inputting and sorting the plurality of data in the second representation format read from the plurality of memory elements of the memory circuit; The method includes a plurality of normalization processes that respectively input the plurality of data in the second representation format output from the second data allocation process, and the plurality of second conversion processes input the plurality of normalized data in the second representation format and the maximum exponent, correct the (DN-1) bits between the lowest N bits (N is a positive integer such that N≦D-2) on the least significant bit side of the plurality of data in the second representation format that have been input, and convert the data into the plurality of data in the two's complement representation and output the corrected data.

[0328] [Reference document 1] Japanese Patent Application Laid-Open No. 8-137832 [Reference 2] JP 2001-56806 A [Reference 3] Patent No. 4883251 [Reference 4] JWCooley, JWTukey, "An Algorithm for the Machine Calculation of Complex Fourier Series," Mathematics of Computation, US, American Mathematical Society, Apr. 1965, Vol.19, No. 90, pp. 297-301 [Reference 5] DPKolba, "A Prime Factor FFT Algorithm Using High-Speed ​​Convolution," IEEE Trans. on Acoustics, US, IEEE Signal Processing Society, Aug. 1977, Vol.29, No.4, pp. 281-294

[0329] The disclosures of the above patent documents and references are incorporated herein by reference. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure (including the claims) and based on the basic technical concepts. Furthermore, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each example, each element of each drawing, etc.) are possible within the scope of the claims. In other words, it goes without saying that the present invention includes various modifications and alterations that would be possible for a person skilled in the art based on the entire disclosure and technical concepts. [Explanation of symbols]

[0330] 10. Signal Processing Device 11, 11a, 11b, 11c Memory Processing Unit 12a, 12b Processing unit 13, 13a~13h conversion circuit 14 Memory circuit 17, 17 N ~17 D-2 XOR circuit 20 Normalization circuit 21 Correction circuit 22 maximum index 23, 24 Signal Data 25 Normalized Data 26 Correction Data 29 Shift Circuit 30 Maximum index calculation circuit 32 OR circuit 33 Registers 34 MSB side bit position detection circuit 36 Logical OR 37 Register Values 40, 40 N ~40 D-2 Selection conversion circuit 41 Selection signal 42 Decoder circuit 43 AND circuit 44 XOR circuit 51 Memory Processing Unit 53, 53a~53h conversion circuit 54 Decoder circuit 55 Selection signal 130 FFT equipment 200 Data sorting processing unit 200a First data rearrangement processing unit 200b Second data sorting unit 200c Third data sorting processing unit 201 Operation Mode 202 First Data Distribution Unit 203 Second Data Distribution Unit 205a~205h data line 206a~206h data line 207a~207h Address lines 208a~208h Address lines 209a~209h data line 210a~210h RAM circuit 212 Write address control section 213 Read address control unit 220, 220a~220h normalization circuit 231 first conversion circuit 232 Second conversion circuit 301a First butterfly calculation processing unit 301b Second butterfly calculation processing unit 302 Twist multiplication processing unit 331 Flip-Flop 332 Selector 333 Flip-Flop 500 Data Flow 501 Data sorting processing unit 502, 503 butterfly calculation processing unit 504 Twist multiplication processing unit 505a~505h Partial data flow 600 conversion circuit 601 Bit Inversion Circuit 602 1 Addition Circuit 607 XOR circuit 610 Conversion Circuit 700 Normalization circuit 710 Maximum index calculation circuit 720 Memory Circuit 730 Shift Circuit

Claims

1. a processing unit that performs arithmetic processing on data expressed in two's complement notation; a storage processing unit that performs storage processing on data expressed in a second representation format as a data representation format; Equipped with The second representation format, with respect to the D-bit data, is If the value of the data is positive or 0, it is the same as the two's complement representation, If the value of the data is negative, the representation is a representation in which (D-N-1) bits between the most significant bit indicating the sign and the lowest N bits (N is a positive integer N≦D-2) on the least significant bit side of the D-bit (D is a positive integer satisfying D≧3) two's complement representation are inverted, The storage processing unit a normalization circuit for normalizing a block of data represented in the second representation format; The normalization circuit a maximum exponent calculation circuit that calculates a maximum exponent from a logical operation result corresponding to a bit-by-bit logical sum between the plurality of data of the block for (D-1) bits excluding the most significant bit of the plurality of data of the block; a shift circuit for arithmetically shifting the plurality of data of the block by the maximum exponent; A signal processing device comprising:

2. The maximum exponent calculation circuit a logical sum circuit; A register and a detection circuit for detecting the maximum exponent; Equipped with the logical sum circuit outputs a bit-by-bit logical sum operation result between (D-1) bits excluding the most significant bit of the input data and a (D-1)-bit register value output from the register; the register receives the (D-1)-bit logical sum result output from the logical sum circuit in response to a clock signal, holds it as the register value, and outputs it; When the data input to the OR circuit is the first data of the block, the register supplies the register value in which the (D-1) bits are all 0 to the OR circuit; 2. The signal processing device according to claim 1, wherein when a final logical sum operation result of the block by the logical sum circuit is output from the register as the register value, the detection circuit receives the register value and detects, as the maximum exponent, a first bit position at which a transition from 0 to 1 occurs, counting from the most significant bit side of the final logical sum operation result of the block.

3. the register receives a block end signal, and in a cycle in which the block end signal indicates that the data is the last of the plurality of data in the block, the OR circuit outputs a result of an OR operation between the last data of the block and the register value from the register as a final OR operation result for the block; 3. The signal processing device according to claim 2, wherein the register receives the final logical sum of the blocks, holds and outputs the result as the register value in response to the clock signal, transmits the register value to the detection circuit, and then resets the register value to 0.

4. the storage processing unit includes a correction circuit that corrects the data expressed in the second representation format normalized by the normalization circuit; the correction circuit includes a decoding circuit that decodes the maximum exponent calculated by the normalization circuit and outputs a selection signal; a selection correction circuit that outputs, based on the most significant bit of the data normalized by the normalization circuit and the selection signal, a value of each of the (D-N-1) bits between the most significant bit and the lowest N bits (N is a positive integer satisfying N≦D-2) on the least significant bit side of the data expressed in the second representation format normalized by the normalization circuit, either as is or an inverted value; The signal processing device according to claim 1 , comprising:

5. the storage processing unit includes a first conversion circuit that converts the data expressed in the two's complement representation into data expressed in the second representation format; a second conversion circuit that converts the data expressed in the second representation format output from the correction circuit into data expressed in the two's complement representation; The signal processing device according to claim 4, comprising:

6. the storage processing unit includes a first conversion circuit that converts the data expressed in the two's complement representation into data expressed in the second representation format; a second conversion circuit that converts the data expressed in the second representation format output from the normalization circuit into data expressed in the two's complement representation; Equipped with the second conversion circuit includes a decoding circuit that decodes the maximum exponent calculated by the normalization circuit and outputs a selection signal; a selection correction circuit that outputs, based on the most significant bit of the data normalized by the normalization circuit and the selection signal, a value of each of the (D-N-1) bits between the most significant bit and the lowest N bits (N is a positive integer satisfying N≦D-2) on the least significant bit side of the data expressed in the second representation format normalized by the normalization circuit, either as is or an inverted value; The signal processing device according to claim 1 , comprising:

7. The storage processing unit a data rearrangement processing unit that rearranges a plurality of data input in a first order into a second order; The data rearrangement processing unit a first conversion circuit that receives the plurality of data in the two's complement representation, converts the received plurality of data from the two's complement representation to the second representation format, and outputs the converted data; a first data sorting unit that receives the plurality of data in the second representation format output from the first conversion circuit and performs sorting processing; a memory circuit including a plurality of memory elements for storing the plurality of data allocated by the first data allocation unit for a plurality of cycles; a first control unit that writes the plurality of data in the second representation format into the memory circuit in accordance with one of a first address order and a second address order; a second control unit that reads the plurality of data in the second representation format, which have been written to the storage circuit in accordance with one of the first address sequence and the second address sequence, from the storage circuit in accordance with the other of the first address sequence and the second address sequence; Equipped with the plurality of data in the second representation format allocated by the first data allocation unit are written into the plurality of memory elements of the memory circuit in accordance with addresses from the first control unit; a second data sorting unit that inputs the plurality of data in the second representation format read from the plurality of memory elements of the memory circuit in accordance with addresses from the second control unit and performs sorting processing; a plurality of the normalization circuits each receiving the plurality of data in the second representation format output from the second data sorting unit; a plurality of second conversion circuits that receive the plurality of normalized data in the second representation format output from the plurality of normalization circuits and the maximum exponent, correct the (D-N-1) bits between the lowest N bits (N is a positive integer satisfying N≦D-2) on the least significant bit side of the plurality of data in the second representation format that have been received, by selecting a bit based on the maximum exponent, convert the plurality of data into the plurality of data in the two's complement representation, and output the result; 7. The signal processing device according to claim 6, comprising:

8. In the storage processing unit, the first address order is such that a plurality of addresses simultaneously supplied to the plurality of storage elements of the storage circuit are different from one another; 8. The signal processing device according to claim 7, wherein the second address order is such that the addresses simultaneously supplied to the storage elements of the storage circuit are the same.

9. A signal processing device for performing an n×n point fast Fourier transform or an inverse fast Fourier transform, The storage processing unit a data rearrangement unit configured of first to third data rearrangement units, The arithmetic processing unit first and second butterfly calculation processing units; a twiddle multiplication processing unit that performs processing to multiply the data by a twiddle coefficient; Equipped with The first data rearrangement processing unit n pieces of data input in parallel in sequential order are input for n cycles, rearranged in bit reverse order, and the n pieces of data rearranged in bit reverse order are output in parallel for n cycles; The first butterfly calculation processing unit performing a butterfly operation on the n pieces of data output in parallel from the first data rearrangement unit, and outputting the n pieces of data resulting from the butterfly operation in parallel; the second data rearrangement unit receives n pieces of data output in parallel in sequential order from the first butterfly operation unit for n cycles, rearranges the pieces of data in the bit reverse order, and outputs n pieces of data rearranged in the bit reverse order in parallel for n cycles; the twiddle multiplication processing unit multiplies the data output from the second data rearrangement processing unit by a corresponding twiddle coefficient; the second butterfly calculation unit performs butterfly calculations on the n pieces of data output from the twiddle multiplication unit, and outputs the n pieces of data resulting from the butterfly calculations in parallel; the third data rearrangement unit receives n cycles of n pieces of data output in parallel in the bit reverse order from the second butterfly operation unit, rearranges the n pieces of data into the sequential order, and outputs n pieces of the data rearranged in the sequential order in parallel for n cycles; 8. The signal processing device according to claim 7, wherein the first and second butterfly operation processing units and the twiddle multiplication processing unit perform operation processing on the data expressed in two's complement notation.

10. Performing arithmetic processing on data expressed in two's complement notation; performing a storage process on the data expressed in the second representation format as the data representation format; the second representation format is identical to two's complement representation when the data value is positive or 0; If the data value is negative, the representation is a D-bit (D is a positive integer satisfying D≧3) two's complement representation in which the D-N-1) bits between the most significant bit indicating the sign and the lower N bits (N is a positive integer satisfying N≦D-2) including the least significant bit are inverted. The storage process includes: A signal processing method including a normalization process for a block consisting of a plurality of data represented in the second representation format, in which a maximum exponent is calculated from a result of an operation corresponding to a bit-by-bit logical sum between the plurality of data for a bit string of (D-1) bits excluding the most significant bit of the plurality of data, and the bit string excluding the most significant bit of the plurality of data is shifted by the maximum exponent.

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