Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device capable of suitably coping with high-speed driving, and an electronic apparatus.SOLUTION: An electro-optical device including a first substrate, a second substrate, and an electro-optical layer disposed between the first substrate and the second substrate, the electro-optical device including a display region having a plurality of pixels and a peripheral region provided outside the display region, the first substrate includes a transmission gate including an N-channel type transistor and a P-channel type transistor, a conductive portion closer to the electro-optical layer than the transmission gate, and a light shielding film closer to the electro-optical layer than the conductive portion, and the light shielding film overlaps one of the N-channel type transistor and the P-channel type transistor and the conductive portion in plan view, and does not overlap the other of the N-channel type transistor and the P-channel type transistor in plan view.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Electronic devices such as projectors use electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel.

[0003] Patent Document 1 discloses a device including a plurality of pixel circuits and a peripheral circuit that drives and controls the plurality of pixel circuits. The peripheral circuit includes a transistor, wiring arranged above the transistor, and a light-shielding film arranged above the wiring to block light from entering the transistor. The light-shielding film is arranged to cover the entire area of ​​the transistor in a plan view. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-63318 Summary of the Invention [Problem to be solved by the invention]

[0005] Consider a case where a transmission gate is used that includes an N-channel transistor and a P-channel transistor. In this case, if a light-shielding film covers the entire transmission gate in plan view, the capacitive coupling formed between the light-shielding film and the wiring for each of the N-channel transistor and the P-channel transistor will be equivalent. Therefore, if there is a difference in performance between the N-channel transistor and the P-channel transistor, this difference cannot be eliminated. If this difference in performance is large, it becomes difficult to make the electro-optical device compatible with high-speed operation. [Means for solving the problem]

[0006] One embodiment of the electro-optical device of the present invention comprises a first substrate, a second substrate, and an electro-optical layer disposed between the first substrate and the second substrate, a display area having a plurality of pixels, and a peripheral area provided outside the display area, the first substrate having a transmission gate including an N-channel transistor and a P-channel transistor, a conductive portion closer to the electro-optical layer than the transmission gate, and a light-shielding film closer to the electro-optical layer than the conductive portion, the light-shielding film overlapping one of the N-channel transistor and the P-channel transistor in a planar view and not overlapping the other of the N-channel transistor and the P-channel transistor in a planar view.

[0007] One embodiment of the electro-optical device of the present invention comprises a first substrate, a second substrate, and an electro-optical layer disposed between the first substrate and the second substrate, a display region having a plurality of pixels, and a peripheral region provided outside the display region, the first substrate having a transmission gate including an N-channel transistor and a P-channel transistor, a conductive portion closer to the electro-optical layer than the transmission gate, a first light-shielding film closer to the electro-optical layer than the wiring, and a second light-shielding film closer to the electro-optical layer than the conductive portion, the first light-shielding film overlapping the N-channel transistor in a planar view, and the second light-shielding film overlapping the P-channel transistor in a planar view, and the light-shielding property of either the first light-shielding film or the second light-shielding film being lower than the light-shielding property of the other.

[0008] An electronic device according to an aspect of the present invention includes the electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to a first embodiment. [Figure 2] 2 is a cross-sectional view of the electro-optical device shown in FIG. 1 taken along the line AA. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the pixel in FIG. [Figure 4] FIG. 2 is a diagram showing an electrical configuration of the peripheral circuit shown in FIG. [Figure 5] FIG. 5 is a plan view showing the configuration of the transmission gate shown in FIG. [Figure 6] 5 is a cross-sectional view taken along line B1-B1 in FIG. 4. [Figure 7] This is a cross section corresponding to the line B2-B2 in Figure 4. [Figure 8] FIG. 8 is a diagram showing the light-shielding film shown in FIGS. 6 and 7. [Figure 9] FIG. 10 is a diagram showing a light-shielding film of a comparative example. [Figure 10] FIG. 3 is a plan view showing the arrangement of a plurality of light-shielding parts relative to a plurality of transmission gates in the first embodiment. [Figure 11] FIG. 10 is a plan view showing the arrangement of a plurality of light-shielding parts relative to a plurality of transmission gates in a first modified example. [Figure 12] FIG. 10 is a plan view of a light-shielding film in a second modified example. [Figure 13] FIG. 13 is a cross-sectional view of the light-shielding film shown in FIG. [Figure 14] FIG. 10 is a diagram showing a light-shielding film of a comparative example. [Figure 15] FIG. 10 is a plan view showing a first light-shielding film and a second light-shielding film in a second embodiment. [Figure 16] 17 is a cross-sectional view showing the first light-shielding film and the second light-shielding film shown in FIG. 16. FIG. [Figure 17] FIG. 11 is a plan view showing a first light-shielding film and a second light-shielding film in a third modified example. [Figure 18] 18 is a cross-sectional view showing the first light-shielding film and the second light-shielding film shown in FIG. 17. FIG. [Figure 19] FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. [Figure 20] FIG. 1 is a plan view showing a smartphone as an example of an electronic device. [Figure 21] FIG. 1 is a schematic diagram illustrating a projector as an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual dimensions and some parts are shown schematically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0011] 1. Electro-optical devices A. First embodiment A1.Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to a first embodiment. FIG. 2 is a cross-sectional view of the electro-optical device 100 shown in FIG. 1 taken along line AA. For ease of explanation, the following description will appropriately use the mutually perpendicular X-axis, Y-axis, and Z-axis. A direction along the X-axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y-axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z-axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction.

[0012] Furthermore, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are spaced apart. Furthermore, "electrical connection" between element α and element β includes not only a configuration in which element α and element β are electrically connected by direct bonding, but also a configuration in which element α and element β are indirectly electrically connected via another conductor. Furthermore, "equal" includes not only cases in which they are strictly equal, but also cases in which there is a difference on the order of manufacturing error and measurement error.

[0013] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device that employs an active matrix driving method. The electro-optical device 100 includes a first substrate 2, a second substrate 3, a frame-shaped sealing member 4, and a liquid crystal layer 5. As shown in FIG. 2, the first substrate 2, the liquid crystal layer 5, and the second substrate 3 are arranged in this order in the Z1 direction. Note that a view from the Z1 direction or the Z2 direction in which these elements overlap is referred to as a "plan view." Furthermore, although the shape of the electro-optical device 100 shown in FIG. 1 is rectangular in plan view, it may also be a polygon other than a rectangle or a circle.

[0014] 2, the first substrate 2 has a substrate 21, a laminate 22, a plurality of pixel electrodes 25, a plurality of dummy pixel electrodes 25d, a peripheral electrode 26, and an alignment film 29. The substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the alignment film 29 are laminated in this order in the Z1 direction. Note that "translucency" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more.

[0015] 2 is a flat plate having light-transmitting and insulating properties, and is made of, for example, a glass substrate or a quartz substrate. The laminate 22 has light-transmitting properties and includes a plurality of insulating films. Various wirings and the like are also provided on the laminate 22.

[0016] The pixel electrodes 25, the dummy pixel electrodes 25d, and the peripheral electrode 26 are disposed on the laminate 22. The pixel electrodes 25 apply an electric field to the liquid crystal layer 5. Although the dummy pixel electrodes 25d do not contribute to display, they have the same configuration as the pixel electrodes 25 and are driven and controlled in the same manner as the pixel electrodes 25. For example, the dummy pixel electrodes 25d are used to reduce noise in image signals written to the pixel electrodes 25. The peripheral electrode 26 is an ion trap electrode that traps ionic impurities in the liquid crystal layer 5. Each of the pixel electrodes 25, the dummy pixel electrodes 25d, and the peripheral electrode 26 includes a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and fluorine-doped tin oxide (FTO).

[0017] The alignment film 29 is light-transmitting and insulating. The alignment film 29 aligns the liquid crystal molecules in the liquid crystal layer 5. The alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The alignment film 29 is made of a material such as polyimide or silicon oxide.

[0018] The second substrate 3 is disposed opposite the first substrate 2. The second substrate 3 has a substrate 31, an inorganic insulating layer 32, a common electrode 33, and an alignment film 34. Although not shown, the second substrate 3 also has a light-shielding partition that surrounds the plurality of pixel electrodes 25 in a planar view. Note that "light-shielding" refers to light-shielding properties against visible light, and preferably refers to a visible light transmittance of less than 50%, more preferably 10% or less.

[0019] The substrate 31, inorganic insulating layer 32, common electrode 33, and alignment film 34 are stacked in this order in the Z2 direction. The substrate 31 is a flat plate having translucent and insulating properties, such as a glass substrate or a quartz substrate. The inorganic insulating layer 32 is also translucent and insulating, and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode disposed across the liquid crystal layer 5 from the plurality of pixel electrodes 25. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes a transparent conductive material, such as ITO, IZO, or FTO. The alignment film 34 is translucent and insulating. The alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The alignment film 34 is made of a material such as polyimide or silicon oxide.

[0020] The sealing member 4 is disposed between the first substrate 2 and the second substrate 3 to seal the space therebetween. The sealing member 4 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 4 may also contain a gap material made of an inorganic material such as glass.

[0021] The liquid crystal layer 5 is disposed within the region surrounded by the first substrate 2, the second substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0022] As shown in Fig. 3, a plurality of scanning line driving circuits 11, peripheral circuits 12, and a plurality of external terminals 13 are arranged on the first substrate 2. Some of the plurality of external terminals 13 are connected to wiring (not shown) drawn from the scanning line driving circuits 11 or the peripheral circuits 12. The plurality of external terminals 13 also includes a terminal to which a constant potential Vcom is applied. This terminal is electrically connected to a common electrode 33 on the second substrate 3 via wiring and conductive materials (not shown). Therefore, the constant potential Vcom is supplied to the common electrode 33.

[0023] The electro-optical device 100 has a display area A10 that displays an image and a peripheral area A20 located outside the display area A10 in a planar view. A plurality of pixels P are arranged in a matrix in the display area A10. A plurality of pixel electrodes 25 are arranged in a one-to-one correspondence with the plurality of pixels P. The aforementioned common electrode 33 is provided in common to the plurality of pixels P. The peripheral area A20 surrounds the display area A10 in a planar view. A scanning line driving circuit 11 and a peripheral circuit 12 are arranged in the peripheral area A20.

[0024] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Fig. 2, an image is displayed by modulating light LL after it enters the second substrate 3 and before it is emitted from the first substrate 2. Note that an image may also be displayed by modulating light that has entered the first substrate 2 and before it is emitted from the second substrate 3.

[0025] The electro-optical device 100 is also applied to display devices that perform color display, such as personal computers and smartphones, which will be described later. When applied to such display devices, a color filter is appropriately used for the electro-optical device 100. The electro-optical device 100 is also applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. In this case, the color filter is omitted from the electro-optical device 100.

[0026] A2. Electrical configuration of pixel P 3 is an equivalent circuit diagram showing the electrical configuration of the pixel P in FIG. 1. As shown in FIG. 3, the first substrate 2 has a plurality of transistors 23, n scanning lines 241, m data lines 242, and n constant potential lines 243. n and m are each an integer of 2 or greater. A transistor 23 is disposed at each intersection of the n scanning lines 241 and the m data lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

[0027] Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y2 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding plurality of transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1. Scanning signals G1, G2, ..., and Gn are supplied line-sequentially to the 1st to nth scanning lines 241 from the scanning line driving circuit 11.

[0028] 3 extend in the Y1 direction, and the m data lines 242 are arranged at equal intervals in the X1 direction. Each of the m data lines 242 is electrically connected to the sources of the corresponding transistors 23. The m data lines 242 are electrically connected to the peripheral circuit 12 shown in FIG. 1. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m data lines 242 from the peripheral circuit 12.

[0029] 3 are electrically insulated from one another and arranged in a grid pattern in plan view. An area surrounded by two adjacent scan lines 241 and two adjacent data lines 242 corresponds to a pixel P. A transistor 23, a pixel electrode 25, and a capacitance element 24 are provided for each pixel P. The pixel electrodes 25 are provided in a one-to-one correspondence with the transistors 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0030] Each of the n constant potential lines 243 extends in the X1 direction and is arranged at equal intervals in the Y2 direction. The n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m data lines 242 and are spaced apart from them. A constant potential Vcom is applied to each of the n constant potential lines 243. Each of the n constant potential lines 243 is electrically connected to one of two electrodes of a corresponding capacitance element 24. Each capacitance element 24 is a storage capacitor for storing the potential of a pixel electrode 25. The capacitance elements 24 are provided in a one-to-one correspondence with the transistors 23. The other of the two electrodes of each capacitance element 24 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitance element 24, and the other electrode is electrically connected to the drain of the transistor 23.

[0031] When the scan signals G1, G2, ..., and Gn become active in sequence and n scan lines 241 are selected in sequence, the transistor 23 connected to the selected scan line 241 is turned on. Then, image signals S1, S2, ..., and Sm having a magnitude corresponding to the gradation to be displayed are received by the pixel P corresponding to the selected scan line 241 via m data lines 242 and applied to the pixel electrode 25. A voltage corresponding to the gradation to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the orientation of the liquid crystal molecules changes in response to the applied voltage. The applied voltage is maintained by the capacitive element 24. This change in the orientation of the liquid crystal molecules modulates light, enabling gradation display.

[0032] A3. Electrical configuration of peripheral circuit 12 Fig. 4 is a diagram showing the electrical configuration of the peripheral circuit 12 shown in Fig. 1. The peripheral circuit 12 shown in Fig. 4 is a circuit that distributes data signals to data lines 242 in accordance with a selection signal. The peripheral circuit 12 has a transmission gate 15, NOT circuits 16 and 17, and a NOT circuit 18 for each data line 242.

[0033] The transmission gate 15 is an analog switch in which a P-channel transistor P1 and an N-channel transistor N1 are connected in parallel, and each of the P-channel transistor P1 and the N-channel transistor N1 is a thin-film transistor.

[0034] An input terminal of the transmission gate 15 is connected to a data signal line 244. An output terminal of the transmission gate 15 is connected to a data line 242. For example, one data line 242 is commonly connected to two transmission gates 15 corresponding to three data signal lines 244. Note that one data line 242 may be commonly connected to three or more transmission gates 15.

[0035] The transmission gate 15 is an element that writes the data signal Vid supplied to the data signal line 244 to the data line 242. The data signal Vid supplied from the data signal line 244 is horizontally scanned onto the three data lines 242 corresponding to the data signal line 244, and is a signal for supplying potentials according to the gradations of the corresponding three pixels in a time-division manner during the horizontal scanning period.

[0036] The gate of the N-channel transistor N1 of the transmission gate 15 is electrically connected to NOT circuits 16 and 17 via wiring 248. The NOT circuit 16 inverts the logic level of the selection signal Sela or Selb and outputs it. The NOT circuit 17 re-inverts the logic level of the inverted signal from the NOT circuit 16 and outputs it. In other words, the NOT circuits 16 and 17 are buffer circuits that buffer the logic level of the selection signal Sela or Selb. The NOT circuit 17 supplies the buffered selection signal Sela or Selb to the gate of the N-channel transistor N1 in the transmission gate 15.

[0037] A NOT circuit 18 is electrically connected to the gate of the P-channel transistor P1 of the transmission gate 15 via a wiring 247. The NOT circuit 18 inverts the logic level of the selection signal Selb and supplies it to the gate of the P-channel transistor P1 of the transmission gate 15.

[0038] The selection signals Sela and Selb are signals for selecting the data line 242. The selection signals Sela and Selb are supplied via a selection signal line 245 or 246.

[0039] As described above, the transmission gate 15 has a P-channel transistor P1 and an N-channel transistor N1 connected in parallel. In this transmission gate 15, the P-channel transistor P1 and the N-channel transistor N1 are simultaneously turned on. This reduces the on-resistance by approximately half compared to a configuration consisting of only one of the P-channel transistor P1 and the N-channel transistor N1. Furthermore, in the transmission gate 15, when the data signal Vid is positive, the P-channel transistor P1 compensates for the insufficient writing of the N-channel transistor N1. Conversely, when the data signal Vid is negative, the N-channel transistor N1 compensates for the insufficient writing of the P-channel transistor P1. Therefore, using the transmission gate 15 can suppress display unevenness caused by polarity differences. For these reasons, for high resolution, it is preferable to use the transmission gate 15 as an element that writes the data signal Vid supplied to the data signal line 244 to the data line 242.

[0040] A4.Configuration of Transmission Gate 15 Fig. 5 is a plan view showing the configuration of the transmission gate 15 shown in Fig. 4. As shown in Fig. 15, the P-channel transistor P1 and the N-channel transistor N1 of each transmission gate 15 are arranged along the Y1 direction, which is the extension direction of the data signal line 244 and the data line 242. In the example of Fig. 5, two transmission gates 15 share a portion with each other.

[0041] The P-channel transistor P1 has a semiconductor layer 151, a gate electrode 152, and a gate insulating film. The gate insulating film is disposed between the semiconductor layer 151 and the gate electrode 152 and is not shown in FIG. 5. The semiconductor layer 151 has at least a source-drain region 151a, a channel region 151c, and a source-drain region 151e. The source-drain region 151a is electrically connected to the data signal line 244. The source-drain region 151e is electrically connected to the data line 242. The semiconductor layer 151 may have an LDD (Lightly Doped Drain) structure, in which case it may further have a lightly doped drain region and a lightly doped source region.

[0042] Similarly, the N-channel transistor N1 has a semiconductor layer 155, a gate electrode 156, and a gate insulating film. The gate insulating film is disposed between the semiconductor layer 155 and the gate electrode 156 and is not shown in FIG. 5. The semiconductor layer 155 has a source-drain region 155a, a channel region 155c, and a source-drain region 155e. The source-drain region 155a is electrically connected to the data signal line 244. The source-drain region 155e is electrically connected to the data line 242. The semiconductor layer 151 may have an LDD (Lightly Doped Drain) structure, in which case it may further have a lightly doped drain region and a lightly doped source region.

[0043] 5, two transmission gates 15 share a portion with each other. Specifically, the source-drain region 151a of the P-channel transistor P1 of the two transmission gates 15 is shared, but the source-drain region 151e is independent. Similarly, the source-drain region 155a of the N-channel transistor N1 of the two transmission gates 15 is shared, but the source-drain region 155e is independent.

[0044] In this specification, the term "source / drain region" refers to a region that includes either a source or a drain. For example, if the source / drain region 155a is the source region, the source / drain region 155e is the drain region.

[0045] Fig. 6 is a view corresponding to the cross section taken along line B1-B1 in Fig. 4. Fig. 7 is a view corresponding to the cross section taken along line B2-B2 in Fig. 4. As shown in Fig. 6 and Fig. 7, laminate 22 of first substrate 2 has a plurality of light-transmitting insulating layers 221-227. Insulating layers 221-227 are formed of an inorganic material containing silicon, such as silicon oxide or silicon oxynitride.

[0046] A plurality of lower light-shielding portions 51 are provided on the substrate 21. Each lower light-shielding portion 51 is located below the N-channel transistor N1 and the P-channel transistor P1 and overlaps them in a plan view. Each lower light-shielding portion 51 has light-shielding properties and is provided to prevent light from entering the N-channel transistor N1 and the P-channel transistor P1 from below. Each lower light-shielding portion 51 is formed of, for example, a metal such as tungsten, aluminum, or titanium, an oxide of the metal, or a nitride of the metal.

[0047] An N-channel transistor N1 and a P-channel transistor P1 are arranged on the insulating layer 221. Relay electrodes 52 and 56 are arranged on the insulating layer 222. The relay electrode 52 is connected to the source-drain region 155e via a contact 591 that penetrates the insulating layer 222. The relay electrode 56 is connected to the source-drain region 155a via a contact 594 that penetrates the insulating layer 222. Furthermore, relay electrodes 53 and 57 are arranged on the insulating layer 223. The relay electrode 53 is connected to the relay electrode 52 via a contact 592 that penetrates the insulating layer 223. The relay electrode 57 is connected to the relay electrode 56 via a contact 595 that penetrates the insulating layer 223.

[0048] Relay electrodes 54 and 58 are disposed on the insulating layer 224. The relay electrode 54 is connected to the relay electrode 53 via a contact 593 that penetrates the insulating layer 224. The relay electrode 54 is electrically connected to the data line 242 shown in FIG. 4. The relay electrode 57 is connected to the relay electrode 56 via a contact 595 that penetrates the insulating layer 223. The relay electrode 57 is electrically connected to the data signal line 244 shown in FIG. 4.

[0049] Furthermore, relay electrodes 55 and 59 are disposed on insulating layer 225. Relay electrode 55 is electrically connected to wiring 247 via various relay electrodes and contacts not shown in Figures 6 and 7. Relay electrode 59 is electrically connected to wiring 248 via various relay electrodes and contacts not shown in Figures 6 and 7.

[0050] In addition, a light-shielding film 60 is disposed on the insulating layer 226 .

[0051] A5. Light shielding film 60 Fig. 8 is a diagram showing the light-shielding film 60 shown in Fig. 6 and Fig. 7. As shown in Fig. 6 and Fig. 7, the light-shielding film 60 having light-shielding properties is disposed on the insulating layer 226. As shown in Figs. 6, 7, and 8, the light-shielding film 60 is disposed on the N-channel transistor N1. The light-shielding film 60 covers the N-channel transistor N1 in plan view, but does not cover the P-channel transistor P1 in plan view.

[0052] The light-shielding film 60 is made of a metal such as aluminum or titanium, an oxide of the metal, or a nitride of the metal. The light-shielding film 60 is configured as a single layer or a multilayer. The light-shielding film 60 is provided to block light from entering the transmission gate 15.

[0053] Here, there may be a difference in performance between the N-channel transistor N1 and the P-channel transistor P1 in the transmission gate 15. The lower performance transistor may cause a delay in the rise time of the selection signal, including the digital signal waveform, compared to the higher performance transistor, i.e., the waveform may become rounded.

[0054] Fig. 9 is a diagram showing a light-shielding film 60Z of a comparative example. In the comparative example shown in Fig. 9, the light-shielding film 60Z is disposed on an N-channel transistor N1 and a P-channel transistor P1. The light-shielding film 60Z covers the N-channel transistor N1 and the P-channel transistor P1 in a plan view.

[0055] As shown in the comparative example in FIG. 9 , when the light-shielding film 60Z is provided to cover both the N-channel transistor N1 and the P-channel transistor P1, the capacitive coupling K1 between the relay electrode 54 and the light-shielding film 60Z increases. The relay electrode 54 corresponds to a "conductive portion." Although the relay electrode 54 and the light-shielding film 60 have different potentials, their proximity results in capacitive coupling between them. In other words, the light-shielding film 60 and the relay electrode 54 have a potential difference that generates the capacitive coupling K1. The light-shielding film 60 is closer to the liquid crystal layer 5 than the relay electrode 54 along the Z axis, and the relay electrode 54 is closer to the liquid crystal layer 5 than the transmission gate 15. Therefore, the transmission gate 15, the relay electrode 54, and the light-shielding film 60 are aligned in this order toward the liquid crystal layer 5 along the Z axis.

[0056] When the capacitive coupling K1 increases, the waveform of either the N-channel transistor N1 or the P-channel transistor P1 becomes more rounded than the other, which increases the difference in rise time of the select signal between the N-channel transistor N1 and the P-channel transistor P1.

[0057] For this reason, in this embodiment, the light-shielding film 60 is not provided on the lower-performance one of the N-channel transistor N1 and the P-channel transistor P1. As a result, the effect of the capacitive coupling K1 occurring between the relay electrode 54 as a conductive part and the light-shielding film 60 can be reduced for the lower-performance one. This reduces the waveform rounding described above for the lower-performance one. This reduces the performance difference between the N-channel transistor N1 and the P-channel transistor P1. By reducing the performance difference, insufficient writing of the data signal to the data line 242 can be prevented even during high-speed driving. This makes it possible to provide an electro-optical device 100 suitable for high-speed driving.

[0058] In particular, in this embodiment, the light-shielding film 60 overlaps the N-channel transistor N1 in a planar view, but does not overlap the P-channel transistor P1 in a planar view. The light-shielding film 60 is provided at a position different from the P-channel transistor P1 in a planar view. Generally, the P-channel transistor P1 has lower performance than the N-channel transistor N1. Therefore, by having the light-shielding film 60 overlap the N-channel transistor N1 in a planar view but not overlap the P-channel transistor P1, the difference in performance between the N-channel transistor N1 and the P-channel transistor P1 can be reduced.

[0059] The light-shielding film 60 is at a constant potential Vcom, for example. When the light-shielding film 60 is at a constant potential Vcom, noise generation can be suppressed compared to when the light-shielding film 60 is not at the constant potential Vcom. The light-shielding film 60 may be at a GND potential or a power supply potential, for example.

[0060] 10 is a plan view showing the arrangement of a plurality of light-shielding films 60 relative to a plurality of transmission gates 15 in the first embodiment. As shown in FIG. 10, in this embodiment, in each transmission gate 15, the P-channel transistor P1 and the N-channel transistor N1 are arranged along the Y1 direction. Furthermore, the plurality of P-channel transistors P1 are arranged along the X1 direction, and the plurality of N-channel transistors N1 are arranged along the X1 direction. Therefore, the plurality of light-shielding films 60 are arranged along the X1 direction.

[0061] 10, the plurality of light-shielding films 60 are provided individually, but they may be integrally connected. By providing the plurality of light-shielding films 60 integrally, manufacturing is easier than when the films are provided individually.

[0062] B. Modification of the First Embodiment The first embodiment may be modified in various ways. Specific examples of modifications that may be applied to the first embodiment are given below. Two or more of the following examples may be combined as long as they are not mutually contradictory.

[0063] B-1. First modified example 11 is a plan view showing the arrangement of a plurality of light-shielding films 60 relative to a plurality of transmission gates 15 in the first modified example. As shown in FIG. 11, in the first modified example, a plurality of P-channel transistors P1 and a plurality of N-channel transistors N1 are arranged in a staggered manner in a planar view. Therefore, the plurality of light-shielding films 60 are arranged in a staggered manner in a planar view. In this way, the arrangement of the plurality of light-shielding films 60 is arranged according to the transistors, and therefore, the arrangement in a planar view is not particularly limited.

[0064] B-2. Second modified example Fig. 12 is a plan view of the light-shielding film 60 in the second modified example. Fig. 13 is a cross-sectional view of the light-shielding film 60 shown in Fig. 12. As shown in Figs. 12 and 13, in the second modified example, the light-shielding film 60 overlaps the P-channel transistor P1 in a plan view, but does not overlap the N-channel transistor N1 in a plan view.

[0065] 13, the gate electrode 152 of the P-channel transistor P1 is electrically connected to the relay electrode 53 via a plurality of contacts 597. The relay electrode 53 is electrically connected to the relay electrode 54 via a plurality of contacts 598. The relay electrode 54 is electrically connected to the relay electrode 55 as a conductive portion via a plurality of contacts 599.

[0066] 14 is a diagram showing a light-shielding film 60Z of a comparative example. In the comparative example of FIG. 14, the light-shielding film 60Z overlaps the P-channel transistor P1 and the N-channel transistor N1 in a plan view. In this case, the rise time of the selection signal supplied to the N-channel transistor N1 may be delayed due to the influence of the capacitive coupling K2 formed between the N-channel transistor N1 and the relay electrode 55 provided directly below it. This results in a large difference in the rise time of the selection signal between the N-channel transistor N1 and the P-channel transistor P1.

[0067] In this modification, the relay electrode 55 is not disposed directly below the P-channel transistor P1, so the influence of the capacitive coupling K2 is unlikely to occur.

[0068] In view of the above, in this modified example, the light-shielding film 60 overlaps the P-channel transistor P1 in a planar view, but does not overlap the N-channel transistor N1 in a planar view, thereby reducing the performance difference between the P-channel transistor P1 and the N-channel transistor N1.

[0069] C. Second embodiment In the second embodiment below, the elements having the same functions as those in the first embodiment will be designated by the same reference numerals used in the description of the first embodiment, and detailed description of each element will be omitted as appropriate.

[0070] Fig. 14 is a plan view showing the first light-shielding film 61 and the second light-shielding film 62 in the second embodiment. Fig. 15 is a cross-sectional view showing the first light-shielding film 61 and the second light-shielding film 62 shown in Fig. 14.

[0071] In this embodiment, a first light-shielding film 61 and a second light-shielding film 62 are provided instead of the light-shielding film 60 of the first embodiment. The first light-shielding film 61 and the second light-shielding film 62 are closer to the liquid crystal layer 5 than the relay electrode 54, and the relay electrode 54 is closer to the liquid crystal layer 5 than the transmission gate 15. The transmission gate 15, the relay electrode 54, and the first light-shielding film 61 are aligned in this order along the Z axis toward the liquid crystal layer 5. The transmission gate 15, the relay electrode 54, and the second light-shielding film 62 are aligned in this order along the Z axis toward the liquid crystal layer 5.

[0072] The first light-shielding film 61 overlaps the N-channel transistor N1 in a planar view. The second light-shielding film 62 overlaps the P-channel transistor P1 in a planar view. The light-shielding ability of the first light-shielding film 61 with respect to the N-channel transistor N1 is higher than the light-shielding ability of the second light-shielding film 62 with respect to the N-channel transistor N1. This allows the capacitive coupling K1 between the relay electrode 54 and the P-channel transistor P1 to be smaller than the capacitive coupling K1 between the relay electrode 54 and the N-channel transistor N1. The capacitive coupling K1 is formed because the first light-shielding film 61 and the relay electrode 54 have different potentials and the second light-shielding film 62 and the relay electrode 54 have different potentials. In other words, there is a potential difference between the first light-shielding film 61 and the relay electrode 54 that forms the capacitive coupling K1. There is a potential difference between the second light-shielding film 62 and the relay electrode 54 that forms the capacitive coupling K1.

[0073] In this way, by making the light-shielding property of the second light-shielding film 62 lower than that of the first light-shielding film 61, it is possible to prevent the waveform from becoming too rounded in the P-channel transistor P1, which generally has lower performance than the N-channel transistor N1. This reduces the performance difference between the N-channel transistor N1 and the P-channel transistor P1. By reducing the performance difference, it is possible to prevent insufficient writing of the data signal to the data line 242 even during high-speed driving. This makes it possible to provide an electro-optical device 100 that is suitable for high-speed driving.

[0074] As described above, the distance D2 between the second light-shielding film 62 and the relay electrode 54 is longer than the distance D1 between the first light-shielding film 61 and the relay electrode 54. Therefore, the light-shielding property of the second light-shielding film 62 can be made lower than the light-shielding property of the first light-shielding film 61.

[0075] D. Modification of the Second Embodiment The second embodiment may be modified in various ways. Specific examples of modifications that may be applied to the first embodiment are given below. Two or more of the following examples may be combined as long as they are not mutually contradictory.

[0076] The distance D1 between the first light-shielding film 61 and the relay electrode 54 may be longer than the distance D2 between the second light-shielding film 62 and the relay electrode 54. For example, from the viewpoint of reducing the influence of the capacitive coupling K2, similar to FIG. 13, the distance D1 may be longer than the distance D2.

[0077] D-1. Third modified example FIG. 17 is a plan view showing the first light-shielding film 61 and the second light-shielding film 62 in the third modified example. FIG. 18 is a cross-sectional view showing the first light-shielding film 61 and the second light-shielding film 62 shown in FIG. 17. As shown in FIG. 18, in this modified example, the first light-shielding film 61 and the second light-shielding film 62 are located in the same layer. As shown in FIG. 17, the degree of overlap of the first light-shielding film 61 with the N-channel transistor N1 in a plan view is lower than the degree of overlap of the second light-shielding film 62 with the P-channel transistor P1 in a plan view. Therefore, the light-shielding property of the second light-shielding film 62 can be made lower than the light-shielding property of the first light-shielding film 61.

[0078] In this modification, as in the second embodiment, the light-shielding ability of the first light-shielding film 61 for the N-channel transistor N1 is higher than the light-shielding ability of the second light-shielding film 62 for the N-channel transistor N1. This makes it possible to prevent the waveform from becoming too rounded in the P-channel transistor P1, which generally has lower performance than the N-channel transistor N1. This makes it possible to reduce the difference in performance between the N-channel transistor N1 and the P-channel transistor P1.

[0079] The overlapping degree of the second light-shielding film 62 with the P-channel transistor P1 in a plan view may be lower than the overlapping degree of the first light-shielding film 61 with the N-channel transistor N1 in a plan view. For example, from the viewpoint of reducing the influence of the capacitive coupling K2, similar to FIG. 13 , the overlapping degree of the second light-shielding film 62 may be lower than the overlapping degree of the first light-shielding film 61.

[0080] E. Variations The above-described exemplary embodiments may be modified in various ways. Specific modifications that may be applied to the above-described embodiments are exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined as appropriate to the extent that they are not mutually inconsistent.

[0081] In the above-described embodiments, the electro-optical device 100 is an active matrix type, but the driving method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix type.

[0082] The driving method of the "electro-optical device" is not limited to the vertical electric field method, but may be a horizontal electric field method. The horizontal electric field method may be, for example, an in-plane switching (IPS) mode. The vertical electric field method may be, for example, a twisted nematic (TN) mode, a vertical alignment (VA) mode, a PVA mode, or an optically compensated bend (OCB) mode.

[0083] 2.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0084] 19 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 has an electro-optical device 100 that displays various images, a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0085] 20 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to an operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0086] FIG. 21 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-plate projector. The electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. In other words, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0087] The illumination optical system 4001 supplies a red component r of light emitted from an illumination device 4002, which is a light source, to an electro-optical device 1r, a green component g to an electro-optical device 1g, and a blue component b to an electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 in accordance with a display image. The projection optical system 4003 combines the light emitted from the electro-optical devices 1r, 1g, and 1b and projects the combined light onto a projection surface 4004.

[0088] The above electronic devices include the electro-optical device 100 and the control unit 2003, 3002, or 4005. The electro-optical device 100 is suitable for high-speed driving. Therefore, by including the electro-optical device 100, the personal computer 2000, the smartphone 3000, or the projection display device 4000 can be driven at high speed.

[0089] Electronic devices to which the electro-optical device of the present invention can be applied are not limited to the devices exemplified above, and examples thereof include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals. Furthermore, examples of electronic devices to which the present invention can be applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0090] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the above-described embodiments. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added.

[0091] In the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to an image sensor, etc. [Explanation of symbols]

[0092] 12...peripheral circuit, 15...transmission gate, 61...first light-shielding film, 62...second light-shielding film, 100...electro-optical device, 151...semiconductor layer, 151a...drain region, 151c...channel region, 151e...drain region, 152...gate electrode, 155...semiconductor layer, 155a...drain region, 155c...channel region, 155e...drain region, 156...gate electrode, 241...scanning line, 242...data line, 243...constant potential line, 244...data signal line, A10...display area, A20...peripheral area, D1...distance, D2...distance, N1...N-channel transistor, P...pixel, P1...P-channel transistor, Vcom...constant potential.

Claims

1. a first substrate, a second substrate, and an electro-optic layer disposed between the first substrate and the second substrate; a display area having a plurality of pixels and a peripheral area provided outside the display area; The first substrate is a transmission gate including an N-channel transistor and a P-channel transistor; a conductive portion closer to the electro-optic layer than the transmission gate; a light-shielding film closer to the electro-optical layer than the conductive portion; the light-shielding film overlaps one of the N-channel transistor and the P-channel transistor in a plan view, and does not overlap the other of the N-channel transistor and the P-channel transistor in a plan view; Electro-optical device characterized by:

2. the light-shielding film and the conductive portion have different potentials. The electro-optical device according to claim 1 .

3. The light-shielding film has a constant potential. The electro-optical device according to claim 1 .

4. the N-channel transistor overlaps the light-shielding film and the conductive portion in a plan view, the P-channel transistor does not overlap the light-shielding film in a plan view; The electro-optical device according to claim 1 .

5. a first substrate, a second substrate, and an electro-optic layer disposed between the first substrate and the second substrate; a display area having a plurality of pixels and a peripheral area provided outside the display area; The first substrate is a transmission gate including an N-channel transistor and a P-channel transistor; a conductive portion closer to the electro-optic layer than the transmission gate; a first light-shielding film that is closer to the electro-optical layer than the conductive portion; a second light-shielding film that is closer to the electro-optical layer than the conductive portion; the first light-shielding film overlaps with the N-channel transistor in a plan view, the second light-shielding film overlaps with the P-channel transistor in a plan view, the light-shielding property of one of the first light-shielding film and the second light-shielding film is lower than the light-shielding property of the other one of the first light-shielding film and the second light-shielding film; Electro-optical device characterized by:

6. the first light-shielding film and the conductive portion have different potentials, the second light-shielding film and the conductive portion have different potentials. The electro-optical device according to claim 5 .

7. each of the first light-shielding film and the second light-shielding film is at a constant potential; The electro-optical device according to claim 5 .

8. The light-shielding property of the first light-shielding film is higher than the light-shielding property of the second light-shielding film. The electro-optical device according to claim 5 .

9. a distance between one of the first light-shielding film and the second light-shielding film and the conductive portion is longer than a distance between the other of the first light-shielding film and the conductive portion; The electro-optical device according to claim 5 .

10. the first light-shielding film and the second light-shielding film are located in the same layer; one of an overlapping degree of the first light-shielding film over the N-channel transistor in a plan view and an overlapping degree of the second light-shielding film over the P-channel transistor in a plan view is lower than the other; The electro-optical device according to claim 5 .

11. The electro-optical device according to claim 1 or 5; and a control unit that controls the operation of the electro-optical device.

Images