Multilayer printed wiring board

Abstract

To provide a multilayer printed board in which heat dissipation is ensured while enhancing insulation.SOLUTION: A multilayer printed wiring board (30) includes insulating layers (39) and wiring layers (32) alternately formed on both surface sides of an insulating substrate (44), wherein the wiring layers are electrically connected to external circuit elements, floating potential conductor layers (45) not electrically connected to the wiring layers are provided on the insulating substrate, and the floating potential conductor layers are formed on one surface side and the other surface side of the insulating substrate and are provided between the wiring layers to which at least different potentials are applied.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a multilayer printed wiring board. [Background technology]

[0002] Power conversion devices convert DC power to AC power by switching inverter circuits, which are configured with switching elements on upper and lower arms, but the switching elements generate heat when they are energized or switched, so high heat dissipation is required. In power conversion devices using multilayer printed circuit boards, heat is dissipated by forming thermal vias in the multilayer printed circuit board, but in a structure in which DC potential wiring and AC potential wiring are stacked, if the DC voltage to be converted is high, it is necessary to thicken the insulating layer inside the printed circuit board to improve insulation, but on the other hand, this creates the problem of reduced heat dissipation.

[0003] Regarding the structure of a multilayer printed circuit board, Patent Document 1 below discloses a configuration in which conductor layers are formed on both sides of an insulating base material, and Patent Document 2 below discloses a configuration in which a conductor with a floating potential is provided within an insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-042957 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-59147 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the configurations described in Patent Documents 1 and 2, an object of the present invention is to provide a multilayer printed wiring board that ensures heat dissipation and improves insulation. [Means for solving the problem]

[0006] A multilayer printed circuit board in which insulating layers and wiring layers are alternately formed on both sides of an insulating substrate, the wiring layers being electrically connected to external circuit elements, and floating potential conductor layers not electrically connected to the wiring layers being provided on the insulating substrate, the floating potential conductor layers being formed on one side and the other side of the insulating substrate, and being provided between the wiring layers to which at least different potentials are applied. [Effects of the Invention]

[0007] It is possible to provide a multilayer printed wiring board that ensures heat dissipation and improves insulation. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor package. [Figure 2] Cross section AA of Figure 1. [Figure 3] FIG. 3 is a plan view of the semiconductor package as viewed from direction B in FIG. 2. [Figure 4] FIG. 4 is a plan view of the semiconductor package of FIG. 3 excluding the molding resin. [Figure 5] FIG. 5 is a plan view of the semiconductor package of FIG. 4 excluding the source conductor. [Figure 6] 1 is a plan view showing a printed wiring board on which a plurality of semiconductor packages are mounted according to an embodiment of the present invention; [Figure 7] FIG. 7 is a plan view of the first layer of the printed wiring board of FIG. 6 excluding the semiconductor package. [Figure 8] FIG. 3 is a plan view of a second layer of a printed wiring board according to an embodiment of the present invention. [Figure 9] FIG. 4 is a plan view of the third and fourth layers of a printed wiring board according to an embodiment of the present invention. [Figure 10] 7 is a cross-sectional view taken along line CC of FIG. 6 according to one embodiment of the present invention. [Figure 11] 1 illustrates a floating potential conductor layer of a printed wiring board according to one embodiment of the present invention. [Figure 12] 1 is an electrical circuit diagram of a power conversion device according to an embodiment of the present invention. [Figure 13] Variant. [Figure 14] 14 is an electrical circuit diagram of the power conversion device of FIG. 13. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0010] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0011] (One embodiment and overall configuration) (Figs. 1 to 5) The semiconductor package 10 has a drain conductor 3, a source conductor 4, a drain terminal 11, a gate signal terminal 12, a temperature detection terminal 13, a source signal terminal 15, and a semiconductor element 20. Each component in the semiconductor package 10 is molded with a molding resin 6.

[0012] The semiconductor element 20 has a source electrode 21, a drain electrode, a gate signal electrode 23, and a source signal electrode 24. The drain electrode is provided on the surface of the semiconductor element 20 opposite to the source electrode 21, and is therefore not shown. The gate signal terminal 12 and the gate signal electrode 23 are connected by a bonding wire 5. The source signal terminal 15 and the source signal electrode 24 are also connected by a bonding wire 5.

[0013] On one surface of the semiconductor element 20, a drain electrode of the semiconductor element 20 is joined to a drain conductor 3 via solder 2. On the other surface of the semiconductor element 20, a source electrode 21 of the semiconductor element 20 is joined to a source conductor 4 via solder 2. A drain terminal 11 is connected to the drain conductor 3.

[0014] (Fig. 6, Fig. 7) The printed wiring board 30 is formed in four layers in the stacking direction. The printed wiring board 30 shown in FIGS. 6 and 7 is the first layer. A plurality of semiconductor packages 10 are mounted on the printed wiring board 30. In the power conversion device 50, an upper arm drain wiring pattern 31, which is a high-potential side wiring pattern, an output wiring pattern 32, and a lower arm source wiring pattern 33, which is a low-potential side wiring pattern, are formed on the first layer of the printed wiring board 30. The output wiring pattern 32 includes an upper arm source wiring pattern and a lower arm drain wiring pattern. The source conductors of the plurality of semiconductor packages 10 are electrically connected in parallel to the upper arm source wiring pattern 32 and the lower arm source wiring pattern 33, respectively.

[0015] The printed wiring board 30 and the upper arm drain wiring pattern 31 have capacitor connecting through-hole vias 35. The output wiring pattern 32 has output through-holes 40.

[0016] Additionally, an upper arm gate signal wiring pattern 36H and a lower arm gate signal wiring pattern 36L are formed on the first layer of the printed wiring board 30. The upper arm gate signal wiring pattern 36H has a through-hole via 41H for connecting gate signals to the upper arm gate drive circuit. The lower arm gate signal wiring pattern 36L has a through-hole via 41L for connecting gate signals to the lower arm gate drive circuit. The upper arm gate signal wiring pattern 36H and the lower arm gate signal wiring pattern 36L transmit gate drive signals to the semiconductor elements 20 (FIG. 1) of the semiconductor packages 10H and 10L via the gate signal terminals 12 (FIG. 1).

[0017] Furthermore, the printed wiring board 30 is formed with a through-hole via 42H for connecting source signals of the upper arm gate drive circuit and a through-hole via 42L for connecting source signals of the lower arm gate drive circuit.

[0018] The upper arm semiconductor packages 10H are connected to the upper arm drain wiring pattern 31, the output wiring pattern 32 (upper arm source wiring pattern), and the signal wiring pattern 36H. The lower arm semiconductor packages 10L are connected to the output wiring pattern 32 (lower arm drain wiring pattern), the lower arm source wiring pattern 33, and the signal wiring pattern 36L. The output wiring pattern 32 and the lower arm source wiring pattern 33 have a plurality of through holes 38.

[0019] (Fig. 8, Fig. 9) An upper arm source signal wiring pattern 37H is provided on the second layer, which is the lower layer of the multiple layers included in the printed wiring board 30. Similarly, a lower arm source signal wiring pattern 37L is provided on the second layer, which is the lower layer of the printed wiring board 30. A lower arm source wiring pattern 33 and an output wiring pattern 32 are formed on the third and fourth layers of the printed wiring board 30.

[0020] The upper arm source signal wiring pattern 37H is connected to a source signal connecting through-hole via 42H (FIG. 6) of the upper arm gate drive circuit, and the lower arm source signal wiring pattern 37L is connected to a source signal connecting through-hole via 42L (FIG. 6) of the lower arm gate drive circuit.

[0021] (Fig. 10 to 12) 10, source wiring patterns 32 and 33 are formed on multiple layers in the stacking direction on a printed wiring board 30. The drain wiring pattern and the source wiring pattern are electrically connected to external circuit elements, thereby constituting a power conversion circuit.

[0022] The source conductor 4 of the semiconductor package 10 is bonded to source wiring patterns 32 and 33 formed on the first layer of the printed wiring board 30 on the surface opposite to the surface connected to the semiconductor element 20 (FIG. 1). In the printed wiring board 30, the conductor layers are insulated from each other by insulating layers 39, which are prepregs, so that the printed wiring board 30 has a multilayer structure in which insulating layers 39 and conductor wiring layers are formed alternately.

[0023] In the printed wiring board 30, an insulating substrate 44 is provided in an inner layer between a conductor wiring layer at a DC potential and a conductor wiring layer at an AC potential. Furthermore, floating potential conductor layers 45 are formed on both sides of the insulating substrate 44. The floating potential conductor layers 45 are not electrically connected to the conductor wiring layers.

[0024] 10, the floating potential conductor layer 45 is formed at positions in the stacking direction between the upper arm drain wiring pattern 31 and the insulating substrate 44, between the output wiring pattern 32 and the insulating substrate 44, between the upper arm source signal wiring pattern 37H and the insulating substrate 44, and between the lower arm source signal wiring pattern 37L and the insulating substrate 44. In other words, the floating potential conductor layer 45 is provided at least between conductor wiring layers to which different potentials are applied.

[0025] The floating potential conductor layer 45 is provided between conductor wirings that are not electrically connected and to which a high potential is applied. Two floating potential conductor layers 45 are provided on the insulating substrate 44 in the stacking direction.

[0026] 12 , DC power output from a battery (not shown) is smoothed by a smoothing capacitor 80 and input to the power conversion device 50. The smoothed DC power is input to each upper arm semiconductor package 10H via a positive-side capacitor connecting through-hole via 35 and an upper arm drain wiring pattern 31, and is input to each lower arm semiconductor package 10L via a negative-side capacitor connecting through-hole via 35 and a lower arm source wiring pattern 33.

[0027] The upper arm gate signal wiring pattern 36H is connected to the gates of each upper arm semiconductor package 10H and is connected to the gate drive circuit 70 via a gate signal connecting through-hole via 41H. Similarly, the upper arm source signal wiring pattern 37H is connected to the source side of each upper arm semiconductor package 10H and is connected to the gate drive circuit 70 via a gate signal connecting through-hole via 41L.

[0028] The lower arm gate signal wiring pattern 36L is connected to the gate of each lower arm semiconductor package 10L and is connected to the gate drive circuit 70 via a source signal connecting through-hole via 42H. Similarly, the lower arm source signal wiring pattern 37L is connected to the source side of each lower arm semiconductor package 10L and is connected to the gate drive circuit 70 via a source signal connecting through-hole via 42L.

[0029] 10 and 12, a floating potential conductor layer 45 is provided on an insulating substrate 44, thereby forming a capacitance circuit between each conductor layer and the insulating substrate 44 to divide the voltage between a wiring layer at an AC potential and a wiring layer at a DC potential in the power conversion circuit. The formed capacitance circuit generates a parasitic capacitance C1 between the upper arm drain wiring pattern 31, which is a DC potential wiring, and the floating potential conductor layer 45. Furthermore, a parasitic capacitance C2 is generated between the floating potential conductor layers 45 on the insulating substrate 44. Furthermore, a parasitic capacitance C3 is generated between the output wiring pattern 32, which is an AC potential wiring, and the floating potential conductor layer 45.

[0030] In order to make these parasitic capacitances C1 to C3 the same, it is necessary to adjust the thickness of the insulating substrate 44 and the thickness of the insulating layer 39 formed between the floating potential conductor layer 45 and each wiring layer (wiring patterns 31, 32) to accommodate cases where the insulating substrate 44 and the insulating layer 39 are made of different materials and have different dielectric constants. Therefore, the thickness of the insulating substrate 44 and the thickness of the insulating layer 39 provided between the floating potential conductor layer 45 and the wiring layer 31 at a DC potential are different from each other. Note that the thickness of the insulating substrate 44 and the thickness of the insulating layer 39 provided between the floating potential conductor layer 45 and the wiring layer 32 at an AC potential may also be different from each other.

[0031] In this way, by making the parasitic capacitances C1 to C3 the same between conductor wiring layers with different potentials, the voltage applied to the insulating layer 39 can be divided equally and reduced. This eliminates the need to increase the thickness of the insulating layer 39 to ensure insulation, and insulation can be ensured with a thin insulating layer 39. Furthermore, even if voids occur in the insulating layer 39, the configuration of the present invention allows the thickness of the insulating substrate 44 required to prevent partial discharge caused by the voids to be smaller than in the past. Furthermore, thermal resistance can be reduced compared to the past, and the maximum voltage applied to the insulating substrate 44 is reduced.

[0032] As shown in Figure 11, no through-holes 38 are formed in the floating potential conductor layer 45 of the insulating substrate 44. If through-holes 38 were formed in the floating potential conductor layer 45, the floating potential conductor layer 45 would be electrically connected to a conductor wiring layer having any potential in the power conversion circuit, and the floating potential conductor layer 45 would no longer be at a floating potential. Therefore, in order to prevent the floating potential conductor layer 45 from being electrically connected to each conductor wiring layer, a predetermined distance is provided between the through-holes 38 that are not at a floating potential and the floating potential conductor layer 45. By electrically isolating them in this manner, the effect of the floating potential conductor layer 45 can be ensured.

[0033] (Variation) (Fig. 13, Fig. 14) In addition to the above-described embodiment, the floating potential conductor layer 45 may be formed between the lower arm source wiring pattern 33 and the insulating substrate 44. The floating potential conductor layer 45 is formed on both sides of the insulating substrate 44 at a position overlapping the lower arm source wiring pattern 33 in the stacking direction.

[0034] With this configuration, a capacitance circuit is similarly formed that divides the space between the lower arm source wiring pattern 33 and the output wiring pattern 32. By forming the capacitance circuit, a parasitic capacitance C4 is generated between the lower arm source wiring pattern 33, which is a DC potential wiring, and the floating potential conductor layer 45. A parasitic capacitance C5 is generated between the floating potential conductor layers 45. A parasitic capacitance C6 is generated between the output wiring pattern 32, which is an AC potential wiring, and the floating potential conductor layer 45. As described above, the same effect can be achieved by adjusting the thickness so that the parasitic capacitances C4 to C6 have the same capacitance.

[0035] The floating potential conductor layer 45 may be formed at least either between the upper arm drain wiring pattern 31 and the output wiring pattern 32 or between the output wiring pattern 32 and the lower arm source wiring pattern 33.

[0036] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0037] (1) A multilayer printed wiring board 30 in which insulating layers 39 and wiring layers are alternately formed on both sides of an insulating substrate 44, the wiring layers being electrically connected to external circuit elements, and floating potential conductor layers 45 not electrically connected to the wiring layers being provided on the insulating substrate 44, the floating potential conductor layers 45 being formed on one side and the other side of the insulating substrate 44, and being provided at least between the wiring layers to which different potentials are applied. In this way, a multilayer printed wiring board 30 can be provided that ensures heat dissipation and improves insulation.

[0038] (2) The floating potential conductor layer 45 is spaced a predetermined distance from the through-holes 38 that connect the wiring layers at the same potential. This ensures that the floating potential is maintained because the floating potential conductor layer 45 is not electrically connected to the power conversion circuit.

[0039] (3) The floating potential conductor layer 45 forms a capacitance circuit that divides the voltage between the wiring layer 32, which has an AC potential, and the wiring layer 31, which has a DC potential. This allows the applied voltage to be divided, thereby achieving a lower voltage.

[0040] (4) The thickness of the insulating substrate 44 is different from the thickness of the insulating layer 39 provided between the floating potential conductor layer 45 and the wiring layer 31 at a DC potential. By doing so, when the dielectric constants of the insulating substrate 44 and the insulating layer 39 are different, the voltage is evenly divided, and the insulating layer 39 can be made as thin as possible.

[0041] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0042] 2 Solder 3 Drain conductor 4 Source conductor 5 Bonding Wire 6 Molding resin 10 Semiconductor Package 10H Upper arm semiconductor package 10L Lower arm semiconductor package 11 Drain terminal 12 Gate signal terminal 13 Temperature detection terminal 15 Source signal terminal 20 Semiconductor elements 21 Source electrode 23 Gate signal electrode 24 source signal electrodes 30 Printed wiring board 31 Upper arm drain wiring pattern 32 Output wiring pattern (upper arm source wiring pattern, lower arm drain wiring pattern) 33 Lower arm source wiring pattern 35 Capacitor connection through-hole via 36H Upper arm gate signal wiring pattern 36L Lower arm gate signal wiring pattern 37H Upper arm source signal wiring pattern 37L Lower arm source signal wiring pattern 38 through holes 39 Insulating layer 40 Output through-hole via 41H Gate signal connection through-hole via (upper arm gate drive circuit) 41L Gate signal connection through-hole via (lower arm gate drive circuit) 42H Source signal connection through-hole via (upper arm gate drive circuit) 42L Source signal connection through-hole via (lower arm gate drive circuit) 44 Insulating substrate 45 Floating potential conductor layer 50 Power conversion device C1~C6 Parasitic capacitance

Claims

1. A multilayer printed wiring board in which insulating layers and wiring layers are alternately formed on both sides of an insulating substrate, the wiring layer is electrically connected to an external circuit element; a floating potential conductor layer that is not electrically connected to the wiring layer is provided on the insulating substrate; The floating potential conductor layers are formed on one surface side and the other surface side of the insulating substrate, and are provided at least between the wiring layers to which different potentials are applied. Multilayer printed wiring board.

2. 2. The multilayer printed wiring board according to claim 1, The floating potential conductor layer has a predetermined distance from the through hole that connects the wiring layers of the same potential. Multilayer printed wiring board.

3. 2. The multilayer printed wiring board according to claim 1, The floating potential conductor layer forms a capacitance circuit that divides the voltage between the wiring layer at an AC potential and the wiring layer at a DC potential. Multilayer printed wiring board.

4. 4. The multilayer printed wiring board according to claim 3, The thickness of the insulating substrate is different from the thickness of the insulating layer provided between the floating potential conductor layer and the wiring layer at the DC potential. Multilayer printed wiring board.

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