Semiconductor memory device

Abstract

To improve the operation speed of a semiconductor storage device and to reduce the area of the semiconductor storage device in the layout structure of an SRAM cell using a CFET.SOLUTION: Active regions PU1 and PU2 in which drive transistors P1 and P2, which are P-type transistors, are formed are formed in a lower portion of the cell. Active regions PD1 and PD2 in which load transistors N1 and N2, which are N-type transistors, are formed are formed in the upper portion of the cell. The nanosheet 25,26 overlaps with the nanosheet 23,22 in a plan view. The nanosheet 25,26 has a smaller width in the X direction than the nanosheet 22,23.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a layout structure of a static random access memory (SRAM) cell (hereinafter, also simply referred to as a cell, as appropriate) using a complementary field effect transistor (CFET). [Background technology]

[0002] SRAM is widely used in semiconductor integrated circuits. One type of SRAM is 1-port SRAM, which has one port for reading and writing data.

[0003] Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, reduced operating voltage, and improved operating speed through the reduction of gate length (scaling). However, in recent years, excessive scaling has caused problems with off-state current and the resulting significant increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional one. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses the layout of a one-port SRAM cell using a CFET in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate. In Patent Document 1, the six transistors that make up the one-port SRAM cell include a transistor that is made up of multiple nanowire transistors. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2020 / 255656 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, in a transistor made up of a plurality of nanowire transistors, the nanowire transistors must be spaced apart from one another, which increases the area of ​​the semiconductor memory device.

[0007] Furthermore, by providing the bit lines and power supply wiring separately in the buried wiring layer and the upper wiring layer, the width of the wiring provided in the upper wiring layer is increased, but the wiring in the buried wiring layer cannot be provided overlapping with the transistor (nanosheet).As a result, the wiring width of the wiring formed in the buried wiring layer cannot be increased, which increases the wiring resistance of the wiring and reduces the operating speed of the semiconductor memory device.

[0008] The present disclosure aims to improve the operating speed of a semiconductor memory device and reduce the area of ​​the semiconductor memory device in a layout structure of an SRAM cell using a CFET. [Means for solving the problem]

[0009] The present disclosure provides a semiconductor memory device including an SRAM cell, the SRAM cell comprising a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a drain connected to the second node and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the first, second, fifth, and sixth transistors are transistors of a first conductivity type, and the third and fourth transistors are transistors of a conductivity type different from the first conductivity type. a second conductive type transistor, the SRAM cell comprising: a first active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in a first direction; a second active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; a third active region formed higher than the first and second active regions in the depth direction, the channel, source, and drain of the third transistor, the channel being a third nanosheet extending in the first direction; and a fourth active region formed higher than the first and second active regions in the depth direction, the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction; the first and third nanosheets overlapping in a plan view; and the second and fourth nanosheets overlapping in a plan view, the third nanosheet being deeper than the first nanosheet.The width in a second direction perpendicular to the first direction and the depth direction is smaller, and the width in the second direction of the fourth nanosheet is smaller than that of the second nanosheet.

[0010] According to the present disclosure, the widths of the third and fourth nanosheets in the second direction are smaller than the widths of the first and second nanosheets in the second direction. That is, the drive capabilities of the first and second drive transistors are higher than the drive capabilities of the third and fourth transistors. This eliminates the need to include a transistor composed of multiple transistors among the six transistors that make up a one-port SRAM cell, thereby reducing the area of ​​the semiconductor memory device. Furthermore, by setting the drive capabilities of the first and second transistors higher than those of the third and fourth transistors, the operating speed, lower operating voltage limit, and operational stability of the semiconductor memory device can be improved. [Effects of the Invention]

[0011] According to the present disclosure, in a layout structure of an SRAM cell using a CFET, it is possible to improve the operating speed of a semiconductor memory device and reduce the area of ​​the semiconductor memory device. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. [Figure 3] FIG. 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. [Figure 4] FIG. 1 is a circuit diagram showing the configuration of an SRAM cell according to a first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 6] 4 shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. [Figure 7]FIG. 4 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. [Figure 8] FIG. 10 is a plan view showing an example of a layout structure of an SRAM cell according to the second embodiment. [Figure 9] FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells. At least some of the plurality of SRAM cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0014] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In addition, in this specification, expressions such as "same wiring width" that mean that the width, etc., are the same are used. is assumed to include the range of manufacturing variations.

[0015] (First embodiment) (SRAM cell configuration) 1 to 3 show examples of the layout structure of an SRAM cell according to the first embodiment, with FIGS. 1(a) and 1(b) being plan views, and FIGS. 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, FIG. 1(a) shows the upper part of the cell, i.e., the part including the nanosheet transistor formed on the side farther from the substrate, and FIG. 1(b) shows the lower part of the cell, i.e., the part including the nanosheet transistor formed on the side closer to the substrate. FIG. 2(a) shows the cross section along line X1-X1', FIG. 2(b) shows the cross section along line X2-X2', FIG. 2(c) shows the cross section along line X3-X3', FIG. 3(a) shows the cross section along line X4-X4', and FIG. 3(b) shows the cross section along line X5-X5'.

[0016] In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction (depth direction).

[0017] 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell includes an SRAM circuit made up of drive transistors PU1 and PU2, load transistors PD1 and PD2, and access transistors PG1 and PG2. The drive transistors PU1 and PU2 and the access transistors PG1 and PG2 are P-type FETs, and the load transistors PD1 and PD2 are N-type FETs.

[0018] The drive transistor PU1 is provided between a power supply VDD and a first node NA, and the load transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the drive transistor PU1 and the load transistor PD1 are connected to a second node NB, and they form an inverter INV1. The drive transistor PU2 is provided between the power supply VDD and the second node NB, and the load transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the drive transistor PU2 and the load transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0019] The access transistor PG1 is provided between the bit line BL and a first node NA, and its gate is connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and its gate is connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0020] In an SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a low level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a low level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a high level while data is written to the first and second nodes NA and NB, the latch state is established and the data written to the first and second nodes NA and NB is held.

[0021] Furthermore, if the bit lines BL and BLB are discharged to a low level in advance and the word line WL is driven to a low level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, allowing data to be read from the SRAM cell. Specifically, if the first node NA is at a high level and the second node NB is at a low level, the bit line BL is charged to a high level and the bit line BLB is maintained at a low level. On the other hand, if the first node NA is at a low level and the second node NB is at a high level, the bit line BL is maintained at a low level and the bit line BLB is charged to a high level.

[0022] As described above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0023] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 1 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0024] In addition, the dotted lines surrounding the cells in plan views such as Figure 1 indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of the adjacent cell in the X or Y direction.

[0025] 1, on both sides of the SRAM cell in the X direction, there are SRAM cells that are inverted in the X direction, and on both sides of the SRAM cell in the Y direction, there are SRAM cells that are inverted in the Y direction.

[0026] As shown in Figure 1(b), a wiring layer called BM0 (Backside Metal 0) is formed on the backside of the semiconductor chip where the transistors are formed. The BM0 wiring layer corresponds to the backside wiring layer.

[0027] The BM0 wiring layer is formed with a power supply wiring 11 extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0028] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in a plan view.

[0029] In the P-type transistor region, access transistors PG1 and PG2 and drive transistors PU1 and PU2 are formed. The access transistor PG1, the drive transistors PU1 and PU2, and the access transistor PG2 each have a channel made of two overlapping sheet structures in a plan view, and each have nanosheets 21 to 24 extending in the Y direction.

[0030] In the active region P1, the portion that becomes the source of the drive transistor PU1 is connected to the power supply wiring 11 through a via 91 that is provided at a position that overlaps with the power supply wiring 11 in a planar view. In the active region P2, the portion that becomes the source of the drive transistor PU2 is connected to the power supply wiring 11 through a via 92 that is provided at a position that overlaps with the power supply wiring 11 in a planar view.

[0031] As shown in FIG. 1(a), multiple active regions that form the channel, source, and drain of the N-type transistor are formed in the N-type transistor region. Specifically, active regions N1 and N2 are formed in the N-type transistor region. Active regions N1 and N2 are respectively disposed above active regions P1 and P2 in the Z direction. Active regions N1 and N2 overlap with active regions P1 and P2, respectively, in a plan view.

[0032] In the N-type transistor region, load transistors PD1 and PD2 are formed. The load transistors PD1 and PD2 have channels made of two overlapping sheet structures in a plan view, and have nanosheets 25 and 26 extending in the Y direction, respectively.

[0033] The width in the X direction of nanosheets 21 to 24 is twice the width in the X direction of nanosheets 25 and 26. In plan view, the right end of nanosheet 25 and the right end of nanosheet 22 are aligned in the X direction. In plan view, the left end of nanosheet 26 and the left end of nanosheet 23 are aligned in the X direction.

[0034] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0035] Gate wirings (Gate) 31 to 34 are formed extending in the X direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21 in the X and Z directions. The gate wiring 32 surrounds the outer periphery of the nanosheets 23 and 26 in the X and Z directions. The gate wiring 33 surrounds the outer periphery of the nanosheets 22 and 25 in the X and Z directions. The gate wiring 34 surrounds the outer periphery of the nanosheet 24 in the X and Z directions. The gate wiring 31 corresponds to the gate of the access transistor PG1. The gate wiring 32 corresponds to the gates of the drive transistor PU2 and the load transistor PD2. The gate wiring 33 corresponds to the gates of the drive transistor PU1 and the load transistor PD1. The gate wiring 34 corresponds to the gate of the access transistor PG2.

[0036] As shown in FIG. 1(b), local interconnects (LI) 41-44 extending in the X direction are formed below the cell. The local interconnect 41 is connected to a portion in the active region P1 that will become the source of the access transistor PG1. The local interconnect 42 is connected to a portion in the active region P1 that will become the drain of the access transistor PG1 and a portion in the active region P1 that will become the drain of the drive transistor PU1. The local interconnect 43 is connected to a portion in the active region P2 that will become the drain of the drive transistor PU2 and a portion in the active region P2 that will become the drain of the access transistor PG2. The local interconnect 44 is connected to a portion in the active region P2 that will become the source of the access transistor PG2.

[0037] As shown in FIG. 1(a), local wirings 45 to 48 extending in the X direction are formed above the cell. The local wiring 45 is connected to a portion in the active region N2 that will become the source of the load transistor PD2. The local wiring 46 is connected to a portion in the active region N1 that will become the drain of the load transistor PD1. The local wiring 47 is connected to a portion in the active region N2 that will become the drain of the load transistor PD2. The local wiring 48 is connected to a portion in the active region N1 that will become the source of the load transistor PD1.

[0038] The local wiring 46 is connected to the gate wiring 32 via a shared contact 51. The local wiring 46 is connected to the local wiring 42 via a via 52. The local wiring 47 is connected to the gate wiring 33 via a shared contact 53. The local wiring 47 is connected to the local wiring 43 via a via 54. The gate wiring 32, the local wirings 42 and 46, the shared contact 51, and the via 52 correspond to a first node NA. The gate wiring 33, the local wirings 43 and 47, the shared contact 53, and the via 54 correspond to a second node NB.

[0039] A power supply line 61 and lines 62 and 63 are formed in the M1 wiring layer, which is a metal wiring layer above the active regions N1 and N2, and extend in the Y direction from the top to the bottom of the cell in the drawing. Lines 64 and 65 are also formed. The power supply line 61 supplies a power supply voltage VSS. The lines 62 and 63 correspond to the bit lines BL and BLB, respectively.

[0040] In a plan view, the power supply wiring 61 overlaps with the power supply wiring 11. The power supply wiring 61 is connected to the local wiring 45 through a via 55, and is connected to the local wiring 48 through a via 56.

[0041] In a plan view, the wiring 62 overlaps with the active regions P1 and N1 and the power supply wiring 11. In a plan view, the wiring 63 overlaps with the active regions P2 and N2 and the power supply wiring 11. The wiring 62 is connected to the local wiring 41 through a via 57. The wiring 63 is connected to the local wiring 44 through a via 58.

[0042] In the M2 wiring layer, which is the layer above the M1 wiring layer, a wiring 71 is formed that extends in the X direction from both the left and right ends of the cell in the drawing. The wiring 71 corresponds to the word line WL. The wiring 71 is connected to the gate wiring 31 via a via 81, a wiring 64, and a via 59. The wiring 71 is connected to the gate wiring 34 via a via 82, a wiring 65, and a via 60.

[0043] With the above configuration, the width of nanosheets 25 and 26 in the X direction is half the width of nanosheets 22 and 23 in the X direction. In other words, the drive capability of drive transistors PU1 and PU2 is higher than that of load transistors PD1 and PD2. This eliminates the need to include a transistor composed of multiple transistors among the six transistors that make up a one-port SRAM cell, thereby reducing the area of ​​the semiconductor memory device. Furthermore, by setting the drive capability of drive transistors PU1 and PU2 and access transistors PG1 and PG2 higher than that of load transistors PD1 and PD2, the operating speed, lower operating voltage limit, and operational stability of the semiconductor memory device can be improved.

[0044] Furthermore, power supply wiring 11 that supplies power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. The power supply wiring 11 overlaps with the active regions P1 and P2 in a planar view, and is connected to each other by vias 91 and 92 provided in the overlapping region. Therefore, since the active regions (transistors) and the power supply wiring can be arranged to overlap, the wiring width of the power supply wiring 11 that supplies power supply voltage VDD can be increased, and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and stability of the semiconductor memory device.

[0045] Furthermore, a power supply wiring 11 that supplies a power supply voltage VDD is formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. As a result, the wiring formed in the BM0 wiring layer is only the power supply wiring that supplies the power supply voltage VDD, and the wiring width of the power supply wiring 11 can be increased. This reduces the wiring resistance of the power supply wiring and suppresses power supply voltage drops, thereby improving the operating speed and operational stability of the semiconductor memory device. Furthermore, increasing the wiring width of the power supply wiring 11 reduces the wiring resistance of the wiring that supplies the power supply voltage VDD, thereby improving operational stability, particularly the retention characteristics (static noise margin) of the SRAM cell.

[0046] Furthermore, a power supply line 61 that supplies a power supply voltage VSS and lines 62 and 63 corresponding to the bit lines BL and BLB, respectively, are formed in the M1 wiring layer, which is a metal wiring layer above the transistors. As a result, no lines that supply a power supply voltage VDD are formed in the M1 wiring layer, allowing the widths of the power supply line 61 and the lines 62 and 63 to be increased. Furthermore, by increasing the wiring width of the power supply line 61, the wiring resistance of the line that supplies the power supply voltage VSS can be reduced, thereby improving operational stability, particularly the retention characteristics (static noise margin) of the SRAM cell. By increasing the wiring width of the lines 62 and 63, the wiring resistance of the bit lines BL and BLB can be reduced, thereby improving the operating speed of the semiconductor memory device.

[0047] 5A to 5C are diagrams for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Specifically, FIGS. 5A to 5C are cross-sectional views taken along line X6-X6' in FIG.

[0048] In FIG. 1, the nanosheet 22 (23) of the drive transistor PU1 (PU2) and the nanosheet 25 (26) of the load transistor PD1 (PD2) are stacked in the Z direction. As described above, the width of the nanosheet 22 (23) in the X direction is half the width of the nanosheet 25 (26) in the X direction. That is, in FIG. 1, nanosheets with different widths in the X direction are stacked in the Z direction. In the following explanation, a method for manufacturing a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction will be described using FIGS. 5(a) to 5(c).

[0049] 5(a), a laminated semiconductor 210 is formed on a semiconductor substrate 200. The laminated semiconductor 210 is formed by alternately laminating semiconductor layers 220 and 230. Here, silicon (Si) is used as the material for the semiconductor layer 220, and a silicon germanium alloy (SiGe) is used as the material for the semiconductor layer 230.

[0050] 5, the laminated semiconductor 210 includes four semiconductor layers 220. Of the four semiconductor layers 220, the two semiconductor layers 220 (220a) at the top of the drawing correspond to the nanosheet 25 at the top of the cell, and the two semiconductor layers 220 (220b) at the bottom of the drawing correspond to the nanosheet 22 at the bottom of the cell.

[0051] After forming the laminated semiconductor 210 on the semiconductor substrate 200, a mask 241 is formed above the laminated semiconductor 210 in the figure. The width and position of the mask 241 in the X and Y directions are formed to match the width and position of the nanosheet 22 in the X and Y directions. Then, the laminated semiconductor 210 on both the left and right sides of the mask 241 in the X direction in the figure is removed by anisotropic etching. Thereafter, the mask 241 is removed.

[0052] Next, as shown in FIG. 5(b), a mask 242 is formed on the upper right portion of the laminated semiconductor 210 in the drawing. The width and position of the mask 242 in the X and Y directions are formed to match the width and position of the nanosheet 25 in the X and Y directions. Then, the laminated semiconductor 210 on the left side of the mask 242 in the drawing is removed by anisotropic etching. Specifically, the upper portion of the laminated semiconductor 210 arranged on the left side of the mask 242 in the drawing, i.e., the semiconductor layer 220a and the semiconductor layer 230, are removed. Then, after the mask 242 is removed, the load transistor PD1 and the drive transistor PU1 are formed.

[0053] By the manufacturing method described above, it is possible to manufacture a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction, as shown in FIG. 5(c).

[0054] In FIG. 1, no nanosheets are formed on the upper portions of the nanosheets 21 and 24 in the Z direction. That is, in this embodiment, no nanosheets are formed on the upper portions of the cells, and nanosheets are formed only on the lower portions of the cells. In this case, in FIG. 5(b), no mask 242 is formed on the upper portion of the laminated semiconductor 210, and the upper portions of the laminated semiconductor 210, i.e., the semiconductor layer 220a and the semiconductor layer 230, are all removed. This allows a nanosheet (transistor) to be formed only on the lower portions of the cells, and not on the upper portions of the cells.

[0055] (Other configuration examples) Fig. 6(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 6(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0056] 6(b) shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 6(b), a power supply wiring 11 that supplies VDD is formed in a wiring layer provided on the surface of chip B. The power supply wiring 11 is connected to active region P2 of chip A through via 92. Although not shown in the figure, the power supply wiring 11 is also connected to active region P1 of chip A through via 91.

[0057] (Variation) 7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 7A shows the upper part of the cell and Fig. 7B shows the lower part of the cell.

[0058] 7, compared to FIG. 1, the power supply wiring 61 in the M1 wiring layer is omitted, and power supply wirings 72 and 73 extending in the X direction to both the left and right ends of the cell in the drawing are formed in the M2 wiring layer.

[0059] Power supply wiring 72 and 73 supply a power supply voltage VSS. Power supply wiring 72 is connected to a portion of active region N2 that will become the source of load transistor PD2 via via 83, wiring 66, via 60a, and local wiring 45. Power supply wiring 73 is connected to a portion of active region N1 that will become the source of load transistor PD1 via via 84, wiring 67, via 60b, and local wiring 48. Note that wiring 66 and 67 are wirings formed in the M1 wiring layer.

[0060] In FIG. 7, power supply wirings 72 and 73 that supply a power supply voltage VSS are formed in the M2 wiring layer. As a result, the power supply wirings 72 and 73 that supply the power supply voltage VSS are formed to penetrate the SRAM cell in the X direction and are connected to the power supply wirings 72 and 73 of the SRAM cells arranged adjacent to the SRAM cell on both the left and right sides of the SRAM cell in the drawing, forming a continuous cell array in the X direction. Therefore, it is not necessary to form wiring that penetrates the SRAM cell in the Y direction and supplies the power supply voltage VSS in the M1 wiring layer. This allows the wiring width of the wirings 62 and 63 to be increased, thereby reducing the wiring resistance of the bit lines BL and BLB. Furthermore, the distance between the wirings 62 and 63 can be increased. This allows the operating speed of the semiconductor memory device to be improved.

[0061] (Second embodiment) 8A and 8B are plan views showing an example of the layout structure of an SRAM cell according to the second embodiment, in which (a) shows the upper part of the cell and (b) shows the lower part of the cell.

[0062] 8, compared to FIG. 1, wires 12 and 13 are arranged in the BM0 wiring layer instead of the power supply wire 11. Power supply wires 68 to 70 are arranged in the M1 wiring layer instead of the power supply wire 61 and the wires 62 and 63.

[0063] 8(b), the BM0 wiring layer is formed with wirings 12 and 13 that extend in the Y direction from the top to the bottom of the cell in the drawing. The wirings 12 and 13 correspond to the bit lines BL and BLB, respectively.

[0064] In the active region P1, the portion that becomes the source of the access transistor PG1 is connected to the wiring 12 through a via 93 that is provided at a position that overlaps with the wiring 12 in a plan view. In the active region P2, the portion that becomes the source of the access transistor PG2 is connected to the wiring 13 through a via 94 that is provided at a position that overlaps with the wiring 13 in a plan view.

[0065] 8(a), power supply wirings 68 to 70 are formed in the M1 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 68 supplies a power supply voltage VDD. The power supply wirings 69 and 70 supply a power supply voltage VSS.

[0066] The power supply wiring 68 is connected to the portion of the active region P2 that will become the source of the drive transistor PU2 through a via 60c and a local wiring 49. The power supply wiring 68 is connected to the portion of the active region P1 that will become the source of the drive transistor PU1 through a via 60d and a local wiring 50.

[0067] In a plan view, the power supply wiring 69 overlaps with the active regions P1 and N1 and the wiring 12. In a plan view, the power supply wiring 70 overlaps with the active regions P2 and N2 and the wiring 13. The power supply wiring 69 is connected to a portion of the active region N1 that will become the source of the load transistor PD1 through a via 56 and a local wiring 48. The power supply wiring 70 is connected to a portion of the active region N2 that will become the source of the load transistor PD2 through a via 55 and a local wiring 45.

[0068] In FIG. 8, similar to FIG. 1, the X-direction width of nanosheets 25 and 26 is half the X-direction width of nanosheets 22 and 23. That is, the drive capability of drive transistors PU1 and PU2 is higher than that of load transistors PD1 and PD2. This eliminates the need to include a transistor composed of multiple transistors among the six transistors that make up a one-port SRAM cell, thereby reducing the area of ​​the semiconductor memory device. Furthermore, by setting the drive capability of drive transistors PU1 and PU2 and access transistors PG1 and PG2 higher than that of load transistors PD1 and PD2, the operating speed, lower operating voltage limit, and operational stability of the semiconductor memory device can be improved.

[0069] Furthermore, wirings 12 and 13 corresponding to the bit lines BL and BLB, respectively, are formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. The wiring 12 overlaps the active region P1 in a planar view and is connected to each other by a via 93 provided in the overlapping region. The wiring 13 overlaps the active region P2 in a planar view and is connected to each other by a via 94 provided in the overlapping region. Therefore, since the active region (transistor) and the bit line can be arranged to overlap, the wiring width of the wirings 12 and 13 corresponding to the bit lines BL and BLB, respectively, can be increased, and the wiring resistance of the bit line can be reduced. This can improve the operating speed of the semiconductor memory device.

[0070] Furthermore, wirings 12 and 13 corresponding to the bit lines BL and BLB, respectively, are formed in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor. As a result, wirings for supplying power supply voltages VDD and VSS are not formed in the BM0 wiring layer, and therefore the wiring widths of the wirings 12 and 13 can be increased. By increasing the wiring widths of the wirings 12 and 13, the wiring resistance of the bit lines BL and BLB can be reduced, thereby improving the operating speed of the semiconductor memory device.

[0071] Furthermore, a power supply wiring 68 that supplies a power supply voltage VDD and power supply wirings 69 and 70 that supply a power supply voltage VSS are formed in the M1 wiring layer, which is a metal wiring layer above the transistors. Meanwhile, as described above, the bit lines BL and BLB are formed in the BM0 wiring layer. As a result, the wiring formed in the M1 wiring layer is limited to the power supply wiring that supplies the power supply voltages VDD and VSS, and the wiring width of the power supply wirings 68 to 70 can be increased. This reduces the wiring resistance of the power supply wiring and suppresses power supply voltage drops, thereby improving the operating speed and operational stability of the semiconductor memory device. Furthermore, increasing the wiring width of the power supply wirings 68 to 70 reduces the wiring resistance of the wiring that supplies the power supply voltages VDD and VSS, thereby improving operational stability, particularly the retention characteristics (static noise margin) of the SRAM cells.

[0072] (Variation) 9A and 9B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment, in which Fig. 9A shows the upper part of the cell and Fig. 9B shows the lower part of the cell.

[0073] 9, compared to FIG. 8, the power supply wirings 69 and 70 in the M1 wiring layer are omitted, and power supply wirings 72 and 73 extending in the X direction to both the left and right ends of the cell in the drawing are formed in the M2 wiring layer.

[0074] Power supply wiring 72 and 73 supply a power supply voltage VSS. Power supply wiring 72 is connected to a portion of active region N2 that will become the source of load transistor PD2 via via 83, wiring 66, via 60a, and local wiring 45. Power supply wiring 73 is connected to a portion of active region N1 that will become the source of load transistor PD1 via via 84, wiring 67, via 60b, and local wiring 48. Note that wiring 66 and 67 are wirings formed in the M1 wiring layer.

[0075] The power supply wiring 68 overlaps with the wirings 12 and 13 and the active regions P1, P2, N1, and N2 in plan view.

[0076] 9, power supply wirings 72 and 73 that supply power supply voltage VSS are formed in the M2 wiring layer. As a result, the power supply wirings 72 and 73 that supply power supply voltage VSS are formed to penetrate the SRAM cell in the X direction and are connected to the power supply wirings 72 and 73 of the SRAM cells that are arranged adjacent to the SRAM cell on both the left and right sides of the SRAM cell in the drawing, so that the cell array is continuous in the X direction. Therefore, it is not necessary to form wiring that penetrates the SRAM cell in the Y direction and supplies power supply voltage VSS in the M1 wiring layer, so the wiring width of the power supply wiring 68 can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and power supply voltage drops can be suppressed, thereby improving the operating speed and operating stability of the semiconductor memory device.

[0077] In the above-described embodiments and modifications, each transistor is provided with two nanosheets, but some or all of the transistors may be provided with one nanosheet or three or more nanosheets.

[0078] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0079] In addition, in each of the above-described embodiments and modifications, the shared contacts 51 and 53 may be manufactured in the same process as the contacts (gate-contacts) and local wiring, or may be manufactured in a separate process.

[0080] In addition, in the above-described embodiments and modifications, the width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26, but this is not limited to this. The width in the X direction of the nanosheets 21 to 26 may be determined depending on the drive capability of each transistor configured in the SRAM cell.

[0081] Furthermore, in each of the above-described embodiments and variations, the power supply that supplies the power supply voltage VDD to the sources of the drive transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device. [Industrial Applicability]

[0082] According to the present disclosure, in a layout structure of an SRAM cell using a CFET, it is possible to improve the operating speed of a semiconductor memory device and reduce the area of ​​the semiconductor memory device. [Explanation of symbols]

[0083] 11,61,68~70,72,73 Power wiring 91~94 Beer 21~26 Nanosheets 31~34 Gate wiring 12,13,62,63 Wiring PU1, PU2 drive transistor PD1, PD2 load transistors PG1, PG2 access transistors BL,BLB bit lines WL Word Line

Claims

1. A semiconductor memory device including an SRAM cell, The SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line; the first, second, fifth, and sixth transistors are transistors of a first conductivity type; the third and fourth transistors are transistors of a second conductivity type different from the first conductivity type, The SRAM cell comprises: a first active region that constitutes a channel, a source, and a drain of the first transistor, the first active region including a first nanosheet extending in a first direction as the channel; a second active region that constitutes a channel, a source, and a drain of the second transistor, the second active region including a second nanosheet extending in the first direction as the channel; a third active region formed above the first and second active regions in the depth direction, constituting a channel, a source, and a drain of the third transistor, the channel including a third nanosheet extending in the first direction; a fourth active region formed above the first and second active regions in the depth direction, constituting a channel, a source, and a drain of the fourth transistor, the channel including a fourth nanosheet extending in the first direction; the first and third nanosheets overlap in a planar view, the second and fourth nanosheets overlap in plan view, The third nanosheet has a smaller width in a second direction perpendicular to the first direction and the depth direction than the first nanosheet, A semiconductor memory device, wherein the fourth nanosheet has a smaller width in the second direction than the second nanosheet.

2. 2. The semiconductor memory device according to claim 1, the first active region constitutes a channel, a source, and a drain of the fifth transistor, and includes, as the channel, a fifth nanosheet extending in the first direction; The second active region constitutes the channel, source, and drain of the sixth transistor, and includes a sixth nanosheet extending in the first direction as the channel.

3. 2. The semiconductor memory device according to claim 1, The SRAM cell comprises: a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to sixth transistors, extending in the first direction, overlapping the first and second active regions in a plan view, and connected to the first power supply; a first via formed in a region where a region serving as a source of the first transistor in the first active region and the first power supply wiring overlap, the first via connecting the source of the first transistor in the first active region and the first power supply wiring; a second via formed in a region where a region serving as a source of the second transistor in the second active region overlaps with the first power supply wiring, the second via connecting the source of the second transistor in the second active region with the first power supply wiring.

4. 2. The semiconductor memory device according to claim 1, the SRAM cell is formed in a metal wiring layer above the first to sixth transistors, extends in the first direction, and includes a first power supply wiring connected to the first power supply; the first power supply wiring is connected to a region in the first active region that serves as a source of the first transistor, and to a region in the second active region that serves as a source of the second transistor.

5. 2. The semiconductor memory device according to claim 1, the SRAM cell is formed in a metal wiring layer above the first to sixth transistors, extends in the first direction, and includes a second power supply wiring connected to the second power supply; the second power supply wiring is connected to a region in the third active region that serves as a source of the third transistor, and to a region in the fourth active region that serves as a source of the fourth transistor.

6. 2. The semiconductor memory device according to claim 1, the SRAM cell is formed in a metal wiring layer above the first to sixth transistors, extends in the second direction, and includes third and fourth power supply wirings connected to the second power supply; the third power supply wiring is connected to a region in the third active region that serves as a source of the third transistor, the fourth power supply wiring is connected to a region in the fourth active region that serves as a source of the fourth transistor.

7. 2. The semiconductor memory device according to claim 1, the first bit line is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in the first direction; The second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction.

8. 2. The semiconductor memory device according to claim 1, the first bit line is formed in a back wiring layer that is a wiring layer on the back side of the first to sixth transistors, and includes a first wiring extending in the first direction; the second bit line is formed in the backside wiring layer and includes a second wiring extending in the first direction; The SRAM cell comprises: a first via formed in a region where a region serving as a source of the fifth transistor and the first wiring overlap, and connecting the source of the fifth transistor and the first wiring; a second via formed in a region where a region serving as a source of the sixth transistor and the second wiring overlap, the second via connecting the source of the sixth transistor and the second wiring.

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