Method of manufacturing semiconductor device and semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of efficiently manufacturing a plurality of kinds of trench structures, and the semiconductor device.SOLUTION: Forming a semiconductor layer located on a semiconductor substrate and having a first conductivity type, simultaneously forming a first trench having the semiconductor layer as a bottom surface and a second trench penetrating the semiconductor layer, simultaneously forming an insulator filling the first trench and an insulating layer covering the second trench, and removing a part of the insulator so as not to expose the bottom surface of the first trench; The method includes removing a part of the insulating layer so as to expose the semiconductor substrate in the second groove, and embedding a first conductor separated from the semiconductor layer in the first groove and embedding a second conductor in contact with the semiconductor substrate in the second groove, wherein a width of the second groove is larger than a width of the first groove.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a vertical trench MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-295778

[0004] [overview] An object according to one aspect of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can efficiently manufacture a plurality of types of trench structures.

[0005] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the steps of: forming a semiconductor layer located on a semiconductor substrate and having a first conductivity type; simultaneously forming a first trench having the semiconductor layer as a bottom surface and a second trench penetrating the semiconductor layer; simultaneously forming an insulator filling the first trench and an insulating layer covering the second trench; removing a portion of the insulator so as not to expose the bottom surface of the first trench and removing a portion of the insulating layer so as to expose the semiconductor substrate in the second trench; and embedding a first conductor spaced from the semiconductor layer in the first trench and a second conductor in contact with the semiconductor substrate in the second trench, wherein the width of the second trench is greater than the width of the first trench. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3]FIG. 3 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9A] FIG. 9A is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9B] FIG. 9B is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9C] FIG. 9C is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9D] FIG. 9D is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 9E] FIG. 9E is a schematic cross-sectional view for explaining an example of a manufacturing method for each trench structure. [Figure 10] FIG. 10 is a perspective cross-sectional view of a main part of a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, identical elements or elements having the same functions will be designated by the same reference numerals, and duplicate explanations will be omitted. In this specification, the term "same" and similar words are not limited to "completely identical." Furthermore, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of the components shown may differ from the actual dimensions.

[0008] Fig. 1 is a schematic plan view showing a semiconductor device according to this embodiment, and Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1.

[0009] 1, the semiconductor device 100 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 100 may be referred to as an SSI (Small Scale IC), an MSI (Middle Scale IC), an LSI (Large Scale IC), a VLSI (Very Large Scale IC), an ULSI (Ultra Large Scale IC), or the like based on the number of circuit elements integrated therein. The semiconductor device 100 is used, for example, as an LSI on which a reference voltage circuit (VREF circuit) is mounted. In this embodiment, the semiconductor device 100 includes a rectangular parallelepiped chip 101 (semiconductor chip).

[0010] The chip 101 has a first main surface 3, which is the main surface, and a second main surface 4, which is the back surface. The chip 101 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D, which connect the first main surface 3 and the second main surface 4. Hereinafter, the thickness direction of the chip 101 (the thickness direction of the semiconductor layer 2, which will be described later) corresponds to the Z-axis direction, the direction perpendicular to the thickness direction corresponds to the X-axis direction, and the direction perpendicular to the Z-axis direction and the X-axis direction corresponds to the Y-axis direction. Hereinafter, the view from the Z-axis direction will be referred to as a planar view, and the directions extending in the X-axis and Y-axis directions will be referred to as planar directions. The direction toward the first main surface 3 in the Z-axis direction will be referred to as the upward direction, and the direction toward the second main surface 4 in the Z-axis direction will be referred to as the downward direction. Hereinafter, the view from the Z-axis direction will also be simply referred to as a planar view.

[0011] The first main surface 3 and the second main surface 4 each extend perpendicular to the Z-axis direction. In plan view, the planar shape of the first main surface 3 and the planar shape of the second main surface 4 are each quadrilateral, but are not limited to this. The first side surface 5A and the second side surface 5B each extend along the X-axis direction in plan view. The third side surface 5C and the fourth side surface 5D each extend along the Y-axis direction in plan view.

[0012] The semiconductor device 100 includes multiple device regions 10. A gap is provided between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the chip 101. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape. Various devices are formed in each device region 10. As shown in FIG. 2 , at least one device region 10 includes an element region ER surrounded by a trench structure 50 in a plan view. Each element region ER may include at least one of a semiconductor switching device, a semiconductor rectifier device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0013] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used as the MISFET. The MOSFET may be an enhancement type or a depletion type. The MOSFET may have a planar structure or a vertical structure. The element region ER can also be a power transistor. MISFETs with drain-source voltages of high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V) are also known. In addition, optical devices such as light-emitting elements and light-receiving elements can be used as the element region ER formed in the device region 10.

[0014] In this embodiment, the semiconductor material constituting the chip 101 is silicon (Si), but is not limited to this. Compound semiconductors can also be used as the semiconductor material constituting the chip 101. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. III-V compound semiconductors are, for example, Ga-containing semiconductors such as GaAs and GaN. IV-IV compound semiconductors are, for example, Si-containing semiconductors such as SiC and SiGe.

[0015] As shown in FIGS. 1 and 2 , a device region 10 constituting a semiconductor device includes a semiconductor substrate 1 and a semiconductor layer 2 located on the semiconductor substrate 1. The semiconductor substrate 1 functions as a base substrate for forming the semiconductor layer 2 and is, for example, a single-crystal Si substrate or a single-crystal SiC substrate. The semiconductor layer 2 is an epitaxial layer formed on the semiconductor substrate 1. A main surface 2a of the semiconductor layer 2 corresponds to, but is not limited to, the first main surface 3 of the chip 101. The device region 10 is defined by a buried region BL, an element region ER located on the buried region BL, and a trench structure 50 surrounding the element region ER in a planar view. The buried region BL is formed in at least the semiconductor layer 2. The buried region BL may be formed in the semiconductor substrate 1 in addition to the semiconductor layer 2.

[0016] In this example, each semiconductor region constituting the semiconductor device has a first conductivity type of n-type and a second conductivity type different from the first conductivity type of p-type, but these conductivity types are interchangeable. That is, the first conductivity type may be p-type and the second conductivity type may be n-type. An exemplary p-type impurity (trivalent element) is boron (B). An exemplary n-type impurity (pentavalent element) is phosphorus (P) or arsenic (As). The material of the semiconductor substrate 1 in this example is Si. In this embodiment, the semiconductor substrate 1 exhibits the second conductivity type, the semiconductor layer 2 exhibits the first conductivity type, and the buried region BL exhibits the first conductivity type.

[0017] The impurity concentration of the semiconductor substrate 1 is 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 500 μm or less. The impurity concentration of the buried region BL may be 1.0×10 17 cm -3 Over 1.0 x 10 20 cm -3 The impurity concentration of the semiconductor layer 2 may be 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3The thickness of the semiconductor layer 2 may be 5 μm or more and 50 μm or less.

[0018] The structure of the element region is not particularly limited. The following describes the structure of the element region ER according to this embodiment. In this embodiment, the element region ER includes a vertical transistor. The element region ER includes an impurity region 11 located in the semiconductor layer 2, trench structures 12 and 13 formed in the semiconductor layer 2 and adjacent to the impurity region 11, a first contact region 14 located in the semiconductor layer 2 on the impurity region 11, and a second contact region 15 located in the semiconductor layer 2. In addition, the element region ER may include a wiring L1 connected to the trench structure 12, a wiring L2 connected to the first contact region 14, and a wiring L3 connected to the second contact region 15. In the element region ER, a portion of the semiconductor layer 2, the impurity region 11, the trench structure 12, the first contact region 14, and the second contact region 15 form a vertical MOSFET 6. In this embodiment, the MOSFET 6 is a depletion-type MOSFET. Therefore, the MOSFET 6 is normally on.

[0019] The impurity region 11 is a well region having the second conductivity type, and is provided in the center of the element region ER. By providing the impurity region 11, when a predetermined potential is applied to the gate (described later) of the MOSFET 6, the MOSFET 6 is turned off. The impurity region 11 is spaced apart from the buried region BL. That is, the impurity region 11 is located above the buried region BL in the Z-axis direction. The impurity region 11 is formed, for example, by introducing (adding, doping) an impurity having the second conductivity type into a part of the semiconductor layer 2. The impurity concentration of the impurity region 11 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 19 cm -3 The dimension of the impurity region 11 along the Z-axis direction is, for example, not less than 0.5 μm and not more than 1.5 μm.

[0020] The trench structure 12 is a portion (shallow trench) adjacent to the outer end 11a of the impurity region 11 in a plan view, and is spaced apart from the buried region BL. That is, the trench structure 12 is located above the buried region BL in the Z-axis direction. The trench structure 12 has a trench 21 (first trench) having the semiconductor layer 2 as its bottom surface, an insulator 22 covering the surface of the trench 21, and a conductor 23 (first conductor) located within the trench 21 and spaced apart from the semiconductor layer 2.

[0021] The groove 21 is a depression (trench) provided in the semiconductor layer 2, extends from the first main surface 3 toward the second main surface 4 in the Z-axis direction, and has a bottom in the semiconductor layer 2. The groove 21 has, for example, a ring shape surrounding the impurity region 11 and the first contact region 14 in a plan view, but is not limited to this. The groove 21 may have, for example, a shape surrounding a portion of the impurity region 11 in a plan view. A bottom surface 21a of the groove 21 (a portion of the surface of the groove 21) is located closer to the semiconductor substrate 1 in the Z-axis direction than the impurity region 11, but is spaced apart from the buried region BL. In other words, the bottom surface 21a is located below the impurity region 11. From the viewpoint of miniaturizing the MOSFET 6, the short side (width W1) of the groove 21 in a plan view is, for example, not less than 0.5 μm and not more than 2.4 μm. The dimension (depth D1) of the groove 21 along the Z-axis direction is, for example, not less than 1.5 μm and not more than 9.5 μm. Therefore, the ratio of the width W1 of the groove 21 to the depth D1 of the groove 21 is, for example, 0.05 or more and 1.6 or less. Note that the width W1 is constant, but is not limited to this. For example, the width W1 may become narrower as it goes downward in the Z-axis direction. In other words, the width at the bottom of the groove 21 may be the narrowest. Therefore, in this embodiment, the width W1 corresponds to the maximum value of the short side of the groove 21 in a planar view.

[0022] A side surface 21b of the trench 21 (another part of the surface of the trench 21) is located in the semiconductor layer 2 and is defined by a second impurity region 16 having the first conductivity type. The second impurity region 16 is a region formed along the side surface 21b in the semiconductor layer 2, and can function as a depletion region (channel) of the MOSFET 6. In this embodiment, the second impurity region 16 is a region provided during the formation of the trench structure 12, as will be described later, and is therefore considered to be a part of the trench structure 12 and the side surface 21b of the trench 21. For this reason, the trench structure 12 (actually, the second impurity region 16) is adjacent to the impurity region 11. From the viewpoint of the channel performance of the MOSFET 6, the impurity concentration of the second impurity region 16 is set to, for example, 1.0×10 14 cm -3 Over 1.0 x 10 17 cm -3 The thickness of the second impurity region 16 along the direction orthogonal to the Z-axis direction is, for example, not less than 30 nm and not more than 300 nm.

[0023] The insulator 22 is an insulating member that functions as a gate insulating film of the MOSFET 6 and covers the bottom surface 21 a and the side surface 21 b of the trench 21. The insulator 22 is formed of, for example, an oxide insulating film such as a silicon oxide film or an aluminum oxide film, a nitride insulating film such as a silicon nitride film, or an oxynitride insulating film such as a silicon oxynitride film. From the viewpoints of the channel performance of the MOSFET 6 and preventing short circuits within the MOSFET 6, the thickness of the insulator 22 is, for example, not less than 3 nm and not more than 200 nm. The thickness of the portion of the insulator 22 that is in contact only with the bottom surface 21 a and the thickness of the portion that is in contact only with the side surface 21 b may be different from each other or may be the same.

[0024] The conductor 23 functions as the gate of the MOSFET 6 and is located inside the trench 21 relative to the insulator 22. The amount of current flowing through the portion of the second impurity region 16 located between the conductor 23 and the impurity region 11 (i.e., the channel) can be adjusted depending on the voltage applied to the conductor 23. The bottom surface 23a and side surface 23b of the conductor 23 are each covered by the insulator 22. The top surface 23c of the conductor 23 is exposed from the insulator 22 and connected to the wiring L1. From the perspective of the gate performance of the conductor 23, the bottom surface 23a of the conductor 23 is located closer to the semiconductor substrate 1 in the Z-axis direction than the impurity region 11. That is, the bottom surface 23a of the conductor 23 is located below the impurity region 11. The conductor 23 is, for example, a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), or tungsten (W), or polysilicon having a first conductivity type or a second conductivity type.

[0025] The trench structure 13 is a shallow trench that penetrates the center of the impurity region 11 in a plan view and is spaced apart from the buried region BL. That is, the trench structure 13 is located above the buried region BL in the Z-axis direction. The trench structure 13 may be electrically connected to the trench structure 12. In this case, the trench structure 13 can also function as the gate of the MOSFET 6. Therefore, the trench structure 13 can widen the current path of the MOSFET 6. Alternatively, the trench structure 13 does not need to be electrically connected to the trench structure 12. In this case, a potential different from that of the trench structure 12 can be applied to the trench structure 13. Therefore, in the device region 10, in addition to the MOSFET 6 that uses the trench structure 12 as its gate, a MOSFET that uses the trench structure 13 as its gate may be provided. The trench structure 13 includes a trench 31 with the semiconductor layer 2 as its bottom surface, an insulator 32 that covers the surface of the trench 31, and a conductor 33 that is located in the trench 31 and spaced apart from the semiconductor layer 2.

[0026] As described below, the trench structure 13 is formed simultaneously with the trench structure 12. Therefore, the trench 31, the insulator 32, and the conductor 33 have similar characteristics and configurations to the trench 21, the insulator 22, and the conductor 23 of the trench structure 12, respectively. The following describes the portions of the trench 31 that differ from the trench 21 and the portions of the conductor 33 that differ from the conductor 23. For example, the trench 31 is surrounded by the impurity region 11 in a planar view, but this is not a limitation. The short sides of the trench 31 are approximately the same as the width W1 of the trench 21, and the depth of the trench 31 is approximately the same as the depth D1 of the trench 21. The side surfaces 31b of the trench 31 are defined by the third impurity region 17, which is considered to be the side surfaces of the trench 31, similar to the trench 21, but this is not a limitation. The impurity concentration and thickness of the third impurity region 17 are approximately the same as the impurity concentration and thickness of the second impurity region 16, respectively. The conductor 33 is in a floating state, but this is not a limitation. When a predetermined voltage is applied to the conductor 23, a voltage different from the predetermined voltage may be applied to the conductor 33, or the predetermined voltage may be applied to the conductor 33.

[0027] The first contact region 14 is a region that functions as one of the source and drain of the MOSFET 6, is in contact with the side surface 21b of the trench 21 and the side surface 31b of the trench 31, and has the first conductivity type. The first contact region 14 is located inside the trench structure 12 in a plan view, and surrounds at least a part of the trench structure 13. Therefore, the first contact region 14 is in contact with the inner surface of the side surface 21b of the trench 21. In this embodiment, the first contact region 14 and the part of the second impurity region 16 that is located above the impurity region 11 in the Z-axis direction have different configurations, but this is not limited to this. A part of the inner surface may be formed by the first contact region 14. The impurity concentration of the first contact region 14 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0028] The second contact region 15 is a region that functions as the other of the source and drain of the MOSFET 6, is in contact with the side surface 21b of the trench 21, and has the first conductivity type. The second contact region 15 is located outside the trench structure 12 in a plan view. Therefore, the second contact region 15 is in contact with the outer surface of the side surface 21b of the trench 21. The second contact region 15 has, for example, a ring shape that surrounds the trench structure 12 including the trench 21 in a plan view, but is not limited to this. In this embodiment, the second contact region 15 and the portion of the second impurity region 16 that is located above the impurity region 11 in the Z-axis direction have different configurations, but are not limited to this. A part of the inner surface may be formed by the second contact region 15. The impurity concentration of the second contact region 15 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0029] One of the source voltage and the drain voltage is applied to the first contact region 14 via the wiring L2. The other of the source voltage and the drain voltage is applied to the second contact region 15 via the wiring L3. At this time, a current C flows from the second contact region 15 to the first contact region 14 via, for example, the semiconductor layer 2 and the second impurity region 16. When a gate voltage is applied to the conductor 23 of the trench structure 12 via the wiring L1, the current C is blocked or limited in the portion of the second impurity region 16 between the trench structure 12 and the impurity region 11.

[0030] Next, the trench structure 50 will be described in detail. The trench structure 50 is an element isolation structure for electrically isolating the element region ER from other device regions 10, and is a deep trench isolation (DTI) provided in the semiconductor substrate 1. The trench structure 50 has a ring shape in a plan view and surrounds the element region ER. Therefore, the element region ER is surrounded by the trench structure 50 and the buried region BL. The trench structure 50 is spaced apart from the element region ER but is in contact with the buried region BL. The trench structure 50 has a groove 51 (second groove), an insulating layer 52 covering a portion of the surface of the groove 51, and a conductor 53 (second conductor) located in the groove 51 and spaced apart from the semiconductor layer 2.

[0031] The trench 51 is a depression (trench) that penetrates the semiconductor layer 2, extends from the first main surface 3 to the second main surface 4 in the Z-axis direction, and has a bottom surface in the semiconductor substrate 1. The trench 51 has, for example, a ring shape in plan view that surrounds each component of the MOSFET 6 (e.g., the impurity region 11, the trench 21, the first contact region 14, the second contact region 15, etc.). A bottom surface 51a of the trench 51 (a part of the surface of the trench 51) is located below the buried region BL in the Z-axis direction and is spaced apart from the buried region BL. A short side (width W2) of the trench 51 in plan view is larger than the width W1 of the trench 21, and is, for example, not less than 2.5 μm and not more than 4.5 μm. The width W2 of the trench 51 is, for example, not less than 104% and not more than 900% of the width W1 of the trench 21. The dimension (depth D2) of the groove 51 along the Z-axis direction is larger than the dimension (depth D1) of the groove 21, and is, for example, 20 μm or more and 40 μm or less. The width W2 is constant, but is not limited to this. For example, the width W2 may be narrower downward in the Z-axis direction. Therefore, in this embodiment, the width W2 corresponds to the maximum value of the short side of the groove 51 in a planar view. The ratio of the width W2 of the groove 51 to the depth D2 of the groove 51 is, for example, 0.06 or more and 0.225 or less. In addition, the ratio of the width W1 of the groove 21 to the depth D1 of the groove 21 is 22% or more and 2667% or less, or 3.7% or more and 450% or less of the ratio of the width W2 of the groove 51 to the depth D2 of the groove 51. As will be described later, the groove 51 is formed simultaneously with the grooves 21 and 31.

[0032] A side surface 51b of the trench 51 (another part of the surface of the trench 51) is defined by a fourth impurity region 18 that is located in the semiconductor substrate 1 and the semiconductor layer 2 and has the first conductivity type. The fourth impurity region 18 is a region formed along the side surface 51b in the semiconductor substrate 1 and the semiconductor layer 2. In this embodiment, the fourth impurity region 18 is a region that is provided during the formation of the trench structure 50, as will be described later, and is therefore considered to be a part of the trench structure 50 and the side surface 51b of the trench 51. As will be described later, the fourth impurity region 18 is formed simultaneously with the second impurity region 16. Therefore, the impurity concentration and thickness of the fourth impurity region 18 are approximately the same as those of the second impurity region 16, respectively.

[0033] The insulating layer 52 is a member for preventing contact between the semiconductor layer 2 and the conductor 53, and covers at least the side surface 51b of the groove 51. In this embodiment, the insulating layer 52 covers not only the side surface 51b of the groove 51 but also a portion of the bottom surface 51a of the groove 51. In other words, another portion of the bottom surface 51a of the groove 51 is exposed from the insulating layer 52. The insulating layer 52 is formed, for example, from the above-mentioned oxide insulating film, nitride insulating film, or oxynitride insulating film. From the viewpoint of preventing contact with the semiconductor layer 2, the thickness of the insulating layer 52 is, for example, not less than 3 nm and not more than 200 nm. As will be described later, the insulating layer 52 is formed simultaneously with the insulators 22 and 32.

[0034] The conductor 53 is a member located inside the insulating layer 52 in the trench 51 and in contact with the semiconductor substrate 1. The conductor 53 is a frame-shaped conductor surrounded by the insulating layer 52 in a plan view, and extends from the first main surface 3 to the second main surface 4 in the Z-axis direction. The conductor 53 fills the trench 51 and contacts a portion of the semiconductor substrate 1 located below the buried region BL. This makes the potential of the conductor 53 the same as the potential of the semiconductor substrate 1. The conductor 53 is, for example, a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), or tungsten (W), or polysilicon having a first conductivity type or a second conductivity type. As will be described later, the conductor 53 is formed simultaneously with the conductors 23 and 33.

[0035] Although not shown, from the viewpoint of reducing leakage current, an STI (shallow trench isolation) or the like may be formed between the second contact region 15 and the trench structure 50. The STI is, for example, a portion in which an insulator is buried in a recess provided in a portion of the semiconductor layer 2 located between the second contact region 15 and the trench structure 50. The STI has, for example, a ring shape surrounding the second contact region 15 in a plan view, but is not limited to this. The bottom surface of the STI is, for example, located lower than the bottom surface of the second contact region 15, but is not limited to this.

[0036] Next, an example of a method for manufacturing the semiconductor device 100 according to this embodiment will be described with reference to Figures 3 to 8. Each of Figures 3 to 8 is a schematic cross-sectional view for explaining an example of a method for manufacturing the semiconductor device 100 according to this embodiment.

[0037] First, as shown in Fig. 3, a semiconductor layer 2 located on a semiconductor substrate 1 and having a first conductivity type is formed (first step). In the first step, the semiconductor layer 2 is formed by epitaxially growing a semiconductor on the semiconductor substrate 1. In the first step, the semiconductor layer 2 is formed while forming a buried region BL by controlling the amount of impurity added, etc. Note that the introduction of impurities into the semiconductor substrate 1 and / or the semiconductor layer 2 is carried out by a known method such as ion implantation.

[0038] 4, impurity regions 111 and 112 having the second conductivity type are formed in parts of the semiconductor layer 2 (second step). In the second step, for example, a mask (not shown) disposed on the semiconductor layer 2 is used to introduce impurities having the second conductivity type into parts of the semiconductor layer 2. This forms the impurity region 111 and the impurity region 112 that will later function as the impurity region 11.

[0039] 5, trench structures 12 and 13 located in the semiconductor layer 2 and trench structures 50 and 55 penetrating the semiconductor layer 2 are simultaneously formed (third step). Although a portion of the impurity region 111 is removed in accordance with the formation of the trench structures 12 and 13, this is not limitative. The impurity region 111 does not necessarily have to be removed by the formation of the trench structure 12. The trench structures 50 and 55 are formed at positions spaced apart from the impurity regions 111 and 112, respectively.

[0040] The third step will be described in detail below with reference to FIGS. 9A to 9E. Each of FIGS. 9A to 9E is a schematic cross-sectional view illustrating an example of a manufacturing method for each trench structure. While the manufacturing method for trench structures 12 and 50 will be described with reference to FIGS. 9A to 9E, trench structures 13 and 55 are also formed in the same manner. Trench structure 55 has similar characteristics and structure to trench structure 50. Trench structure 55 functions as an isolation region for, for example, a lateral MOSFET 7 (see FIG. 8 described later) and is formed separately from trench structure 50. Trench structure 55 may be connected to trench structure 50 or may be integrated with trench structure 50. A portion of trench structure 55 and a portion of trench structure 50 may be common to each other.

[0041] First, as shown in FIG. 9A, a trench 21 having the semiconductor layer 2 as its bottom surface and a trench 51 penetrating the semiconductor layer 2 are simultaneously formed (Step 3A). In Step 3A, a hard mask M having openings O1 and O2 is first formed on the main surface 2a of the semiconductor layer 2. Next, the trenches 21 and 51 are formed by etching the portions of the semiconductor layer 2 exposed through the opening O1 and the opening O2. The hard mask M is made of a material having a low etching rate with respect to the etchant for the semiconductor layer 2, such as a silicon oxide film. The opening width W3 of the opening O1 is equal to the maximum value of the width W1 of the trench 21, and the opening width W4 of the opening O2 is equal to the maximum value of the width W2 of the trench 51. Note that the hard mask M has a different shape from the mask used in Step 2.

[0042] In step 3A, the grooves 21 and 51 are formed by anisotropic etching, such as a Bosch process using F radicals. This allows the width W1 of the groove 21 to be controlled to be equal to or less than the opening width W3, and the width W2 of the groove 51 to be controlled to be equal to or less than the opening width W4. The difference between the opening widths W3 and W4 is the main factor in differentiating the etching rates of the portions of the semiconductor layer 2 exposed through the opening O1 from the portions of the semiconductor layer 2 exposed through the opening O2. Specifically, by making the opening widths W3 and W4 different from each other, the etching rate of the portions of the semiconductor layer 2 exposed through the opening O1 is made higher than the etching rate of the portions of the semiconductor layer 2 exposed through the opening O2. This allows the depth D1 of the groove 21 to be shallower than the depth D2 of the groove 51, even though the grooves 21 and 51 are formed simultaneously. Therefore, in step 3A, the groove 21, whose bottom surface is the semiconductor layer 2, and the groove 51, whose bottom surface is the semiconductor substrate 1, can be formed.

[0043] Next, as shown in FIG. 9B , impurities having the first conductivity type are introduced into the side surface 21b of the trench 21 and the side surface 51b of the trench 51 (step 3B). This forms a second impurity region 16 along the side surface 21b and a fourth impurity region 18 along the side surface 51b. In step 3B, the impurities are introduced simultaneously into the side surfaces 21b and 51b by, for example, oblique ion implantation using a hard mask M. In step 3B, the impurities are not introduced into the bottom surface 21a of the trench 21 and the bottom surface 51a of the trench 51, but this is not a limitation.

[0044] Next, as shown in FIG. 9C , an insulator 122 filling the groove 21 and an insulating layer 152 covering the groove 51 are simultaneously formed (Step 3C). In Step 3C, the insulator 122 and the insulating layer 152 are simultaneously formed by a known method, such as chemical vapor deposition (CVD). In this embodiment, due to differences in the widths and depths of the grooves 21 and 51, the groove 21 is completely filled with the insulator 122, while the groove 51 is not completely filled with the insulating layer 152. For this reason, a portion 152a of the insulating layer 152 located on the bottom surface 51a of the groove 51 is thinner than the remaining portion. In particular, the thickness of the portion 152a is thinner than the depth dimension of the insulator 122 (i.e., the depth D1 of the groove 21). Note that in Step 3C, the groove 21 does not necessarily have to be completely filled with the insulator 122. Although not shown, a hard mask M may or may not be used in Step 3C. In the latter case, for example, before the 3C step, the hard mask M is removed. The hard mask M is removed by, for example, chemical mechanical polishing (CMP). Then, an insulator may also be deposited on the main surface 2a of the semiconductor layer 2.

[0045] Next, as shown in FIG. 9D , a portion of the insulator 122 is removed so as not to expose the bottom surface 21a of the groove 21, and a portion 152a of the insulating layer 152 is removed so as to expose the semiconductor substrate 1 in the groove 51 (step 3D). In step 3D, the insulator 122 and the insulating layer 152 are etched, for example, by anisotropic etching. In step 3D, the insulator 122 and the insulating layer 152 are etched to the extent that the portion 152a of the insulating layer 152 is removed. As described above, the thickness of the portion 152a of the insulating layer 152 is thinner than the depth dimension of the insulator 122. This forms the insulator 22 covering the groove 21 and the insulating layer 52 covering the side surface 51b of the groove 51. In step 3D, the insulator deposited on the main surface 2a may be partially or entirely etched. In step 3D, a portion of the insulator remains on the main surface 2a, but this is not a limitation. Each of the semiconductor substrate 1 and the semiconductor layer 2 can function as an etching stopper in the 3D step.

[0046] Next, as shown in FIG. 9E, the conductor 23 spaced from the semiconductor layer 2 is embedded in the groove 21, and the conductor 53 in contact with the semiconductor substrate 1 is embedded in the groove 51 (Step 3E). In Step 3E, first, a conductor (not shown) is formed to embed the grooves 21 and 51 using a known method such as sputtering or CVD. The conductor is formed not only in the grooves 21 and 51 but also on the main surface 2a of the semiconductor layer 2. Next, the portion of the conductor located on the main surface 2a of the semiconductor layer 2 is removed using a known method such as CMP. If an insulator, hard mask M, or the like remains on the main surface 2a of the semiconductor layer 2, the insulator may be removed simultaneously with the portion of the conductor located on the main surface 2a of the semiconductor layer 2. By performing Steps 3A to 3E described above, trench structures 12 and 50 are simultaneously formed as shown in FIG. 9E. Although not shown, trench structures 13 and 55 are also formed simultaneously with the trench structures 12 and 50.

[0047] Next, returning to FIG. 6 , STIs 61 and 62 are formed (fourth step). In the fourth step, first, recesses 63 and 64 are formed in parts of the semiconductor layer 2. The recess 63 has, for example, a ring shape surrounding the impurity region 11 in a planar view. The recess 63 is located outside the trench structure 12 and inside the trench structure 50 in a planar view. The recess 63 may be in contact with a part of the insulating layer 52 of the trench structure 50. The recess 64 has, for example, a ring shape surrounding the impurity region 112 in a planar view. The recess 64 may be in contact with another part of the insulating layer 52 of the trench structure 50. When the recess 64 is formed, a part of the impurity region 112 is removed, but this is not limiting. Subsequently, insulators 65 and 66 are formed to fill the recesses 63 and 64, respectively. As a result of the above, an STI 61 including the recess 63 and the insulator 65 and an STI 62 including the recess 64 and the insulator 66 are formed.

[0048] 7, a gate insulating film 71 and a gate electrode 72 are formed in this order on the impurity region 112 (fifth step). In the fifth step, the gate insulating film 71 and the gate electrode 72 are formed in this order by a known method. The gate insulating film 71 is, for example, an oxide insulating film. The gate electrode 72 is, for example, a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), or tungsten (W), or polysilicon having a first conductivity type or a second conductivity type.

[0049] Next, as shown in FIG. 8 , an impurity having a first conductivity type is introduced into the semiconductor layer 2 and the impurity regions 111 and 112 to form a first contact region 14 in the impurity region 111, a second contact region 15 in the semiconductor layer 2, and a third contact region 81 and a fourth contact region 82 in the impurity region 112. The third contact region 81 is a high-concentration impurity region that functions as one of the source and drain, and the fourth contact region 82 is a high-concentration impurity region that functions as the other of the source and drain. By performing the first to sixth steps described above, a vertical MOSFET 6 having the impurity region 11, the trench structure 12, the first contact region 14, and the second contact region 15, and a horizontal MOSFET 7 having the impurity region 112, the third contact region 81, the fourth contact region 82, the gate insulating film 71, and the gate electrode 72 are simultaneously formed. Unlike the MOSFET 6, the MOSFET 7 is an enhancement-type FET.

[0050] In the semiconductor device 100 manufactured by the manufacturing method according to the present embodiment described above, trench structures 12 and 50 having different depths are simultaneously formed. Specifically, by making the width W1 of the groove 21 of the trench structure 12 different from the opening width W3 of the groove 51 of the trench structure 50, the groove 21 having the semiconductor layer 2 as its bottom surface and the groove 51 penetrating the semiconductor layer 2 can be simultaneously formed in the step 3A. In addition, the insulator 22 of the trench structure 12 and the insulating layer 52 of the trench structure 50 can be simultaneously formed in the steps 3C and 3D, and the conductor 23 of the trench structure 12 and the conductor 53 of the trench structure 50 can be simultaneously formed in the step 3E. As described above, according to the present embodiment, multiple types of trench structures 12 and 50 can be simultaneously formed while minimizing the number of manufacturing steps for the semiconductor device 100. Therefore, by applying the manufacturing method for the semiconductor device 100 according to the present embodiment, multiple types of trench structures can be efficiently manufactured.

[0051] Furthermore, in this embodiment, by simultaneously forming multiple types of trench structures (i.e., trench structures 12 and 50), it is possible to simultaneously form the trench structure 50, which is a DTI, and the gate of the vertical MOSFET 6. Therefore, in this embodiment, it is possible to omit the process for forming only the trench structure for the vertical MOSFET. In other words, it is possible to omit the mask for forming only the trench structure for the vertical depletion-type MOSFET. Therefore, it is possible to effectively reduce the manufacturing cost of the semiconductor device 100 including the MOSFET 6 and the trench structure 50 (DTI).

[0052] Furthermore, in this embodiment, it is possible to simultaneously form the vertical MOSFET 6 and the horizontal MOSFET 7. This allows efficient manufacture of the semiconductor device 100 including multiple types of FETs.

[0053] In one example, the ratio of the width W1 of the groove 21 to the depth D1 of the groove 21 is 22% or more and 2667% or less of the ratio of the width W2 of the groove 51 to the depth D2 of the groove 51. In this case, when the groove 51 penetrating the semiconductor layer 2 is formed, the bottom surface 21a of the groove 21 can be easily defined by the semiconductor layer 2.

[0054] In one example, the manufacturing method includes a step 3B of introducing an impurity having the first conductivity type into the side surface 21b of the trench 21 and the side surface 51b of the trench 51 before forming the insulator 22 and the insulating layer 52. In this case, the second impurity region 16 functioning as a depletion region can be formed simultaneously with the formation of the fourth impurity region 18 included in the trench structure 50, thereby effectively simplifying the manufacturing process.

[0055] In one example, the manufacturing method includes a second step of forming impurity regions 111, 112 of the second conductivity type in the semiconductor layer 2 before forming the grooves 21 and 51, and a fifth step of introducing impurities of the first conductivity type into the semiconductor layer 2 and the impurity regions 111, 112 to form one of a source and a drain in the semiconductor layer 2 and the other of the source and drain in the impurity region 111, each of which is in contact with the side surface 21b of the groove 21. In this case, the MOSFETs 6, 7 can be formed well.

[0056] In one example, the bottom surface 21a of the trench 21 is located closer to the semiconductor substrate 1 in the Z-axis direction than the impurity region 11. In this case, the MOSFET 6 can exhibit good on / off performance.

[0057] In one example, when viewed from the Z-axis direction, the groove 21 is surrounded by the groove 51. In this case, leakage current from the MOSFET 6 to the outside and leakage current from the outside to the MOSFET 6 can be reduced.

[0058] In one example, the conductors 23 and 53 are each made of polysilicon, which allows the conductors 23 and 53 to be easily embedded in the trenches 21 and 51, respectively.

[0059] In one example, the trench structure 12 including the groove 21 surrounds the impurity region 11 and the first contact region 14 in a plan view, and the second contact region 15 surrounds the trench structure 12 including the groove 21 in a plan view. In this case, the current path of the MOSFET 6 can be effectively increased.

[0060] Below, a description will be given of essential parts of a semiconductor device according to a modified example with reference to FIG. 10. In the following, descriptions of parts that overlap with the above embodiment will be omitted. FIG. 10 is a cross-sectional perspective view of essential parts of a semiconductor device according to a modified example. As shown in FIG. 10, in this modified example, not only a first contact region 14 but also a back gate region BG is formed in the impurity region 11. The back gate region BG is an impurity region that functions as a back gate of the MOSFET, has the second conductivity type, and is electrically connected to the wiring L4. The back gate region BG extends from the second impurity region 16 to the third impurity region 17, but is not limited to this. The impurity concentration of the back gate region BG is higher than the impurity concentration of the impurity region 11, and may be, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The above-described modified examples can also achieve the same effects as those of the above-described embodiment.

[0061] Although the embodiment and modifications according to one aspect of the present disclosure have been described above, the present disclosure can also be embodied in other forms.

[0062] In the above embodiments, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for a solar cell, a wind power generator, or other power generation device. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0063] Although the embodiments and modifications according to one aspect of the present disclosure have been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims. As explained above, various embodiments of the present disclosure can be defined as follows:

[0064] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0065] [A1] forming a semiconductor layer overlying a semiconductor substrate and having a first conductivity type; simultaneously forming a first trench having a bottom surface in the semiconductor layer and a second trench penetrating the semiconductor layer; simultaneously forming an insulator filling the first trench and an insulating layer covering the second trench; removing a portion of the insulator so as not to expose the bottom surface of the first trench, and removing a portion of the insulating layer so as to expose the semiconductor substrate in the second trench; a step of embedding a first conductor spaced apart from the semiconductor layer in the first trench and embedding a second conductor in contact with the semiconductor substrate in the second trench; Equipped with The width of the second groove is greater than the width of the first groove. A method for manufacturing a semiconductor device.

[0066] [A2] The method for manufacturing a semiconductor device according to [A1], wherein the width of the second trench is 104% or more and 900% or less of the width of the first trench.

[0067] [A3] The method for manufacturing a semiconductor device according to [A1] or [A2], wherein the ratio of the width of the first groove to the depth of the first groove is 3.7% or more and 450% or less of the ratio of the width of the second groove to the depth of the second groove.

[0068] [A4] The method for manufacturing a semiconductor device according to any one of [A1] to [A3], further comprising a step of introducing an impurity having the first conductivity type into a side surface of the first trench and a side surface of the second trench before forming the insulating layer and the insulator.

[0069] [A5] forming an impurity region having a second conductivity type different from the first conductivity type in the semiconductor layer before forming the first trench and the second trench; doping the semiconductor layer and the impurity region with an impurity having the first conductivity type to form one of a source and a drain in the semiconductor layer and the other of a source and a drain in the impurity region; The method for manufacturing a semiconductor device according to any one of [A1] to [A4], wherein the source and the drain are in contact with a surface of the first trench.

[0070] [A6] The method for manufacturing a semiconductor device according to [A5], wherein the bottom surface of the first trench is located closer to the semiconductor substrate than the impurity region in the thickness direction of the semiconductor layer.

[0071] [A7] The method for manufacturing a semiconductor device according to [A5] or [A6], wherein the first conductor functions as a gate.

[0072] [A8] The method for manufacturing a semiconductor device according to any one of [A1] to [A7], wherein the first trench is surrounded by the second trench when viewed in the thickness direction of the semiconductor layer.

[0073] [A9] The method for manufacturing a semiconductor device according to any one of [A1] to [A8], wherein the first conductor and the second conductor are each made of polysilicon.

[0074] [A10] a semiconductor layer located on a semiconductor substrate and having a first conductivity type; an impurity region located in the semiconductor layer and having a second conductivity type different from the first conductivity type; a first trench having a bottom surface in the semiconductor layer and adjacent to the impurity region; a first conductor located in the first groove and spaced apart from the semiconductor layer; a first contact region having the first conductivity type, the first contact region being located on the impurity region within the semiconductor layer and in contact with a side surface of the first trench; a second contact region located in the semiconductor layer and in contact with the side surface of the first trench, the second contact region having the first conductivity type; a second groove that penetrates the semiconductor layer and surrounds the first groove; a second conductor located in the second groove and in contact with the semiconductor substrate; Equipped with The width of the second groove is greater than the width of the first groove. Semiconductor device.

[0075] [A11] The semiconductor device according to [A10], wherein the width of the second trench is 104% or more and 900% or less of the width of the first trench.

[0076] [A12] The semiconductor device according to [A10] or [A11], wherein the ratio of the width of the first groove to the depth of the first groove is 3.7% or more and 450% or less of the ratio of the width of the second groove to the depth of the second groove.

[0077] [A13] The semiconductor device according to any one of [A10] to [A12], wherein the first conductor functions as a gate.

[0078] [A14] The semiconductor device according to any one of [A10] to [A13], wherein the first conductor and the second conductor are each made of polysilicon.

[0079] [A15] The semiconductor device according to any one of [A10] to [A14], wherein the side surface of the first trench is defined by a second impurity region located in the semiconductor layer and having the first conductivity type.

[0080] [A16] the first trench surrounds the impurity region and the first contact region in a plan view; The semiconductor device according to any one of [A10] to [A15], wherein the second contact region surrounds the first trench in a plan view. [Explanation of symbols]

[0081] 1...Semiconductor substrate 2...Semiconductor layer 6...MOSFET 10...Device area 11...Impurity region 11a...outer end 12...Trench structure 13...Trench structure 14...First contact area 15...Second contact area 16…Second impurity region 17…Third impurity region 18...Fourth impurity region 21...Groove (1st groove) 21a...bottom surface (part of the surface of groove 21) 21b...side surface (another part of the surface of the groove 21) 22...Insulator 23...Conductor (first conductor) 23a…Bottom surface 23b…side 31...Groove 31b...side 32...Insulation section 33...Conductor 50...Trench structure 51...Groove (2nd groove) 51a...bottom surface (part of the surface of groove 51) 51b...side surface (another part of the surface of the groove 51) 52...insulating layer 53...Conductor (second conductor) 100...Semiconductor device BL...Buried region ER: Element region W1, W2...width.

Claims

1. forming a semiconductor layer overlying a semiconductor substrate and having a first conductivity type; simultaneously forming a first trench having a bottom surface in the semiconductor layer and a second trench penetrating the semiconductor layer; simultaneously forming an insulator filling the first trench and an insulating layer covering the second trench; removing a portion of the insulator so as not to expose the bottom surface of the first trench, and removing a portion of the insulating layer so as to expose the semiconductor substrate in the second trench; a step of embedding a first conductor spaced from the semiconductor layer in the first trench and embedding a second conductor in contact with the semiconductor substrate in the second trench; Equipped with The width of the second groove is greater than the width of the first groove. A method for manufacturing a semiconductor device.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the width of the second trench is 104% or more and 900% or less of the width of the first trench.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a ratio of the width of the first trench to the depth of the first trench is 3.7% or more and 450% or less of a ratio of the width of the second trench to the depth of the second trench.

4. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of doping an impurity having the first conductivity type into a side surface of the first trench and a side surface of the second trench before forming the insulating layer and the insulator.

5. forming an impurity region having a second conductivity type different from the first conductivity type in the semiconductor layer before forming the first trench and the second trench; forming one of a source and a drain in the semiconductor layer and the other of a source and a drain in the impurity region by introducing an impurity having the first conductivity type into the semiconductor layer and the impurity region; The method for manufacturing a semiconductor device according to claim 1 , wherein each of the source and the drain is in contact with a surface of the first trench.

6. The method for manufacturing a semiconductor device according to claim 5 , wherein the bottom surface of the first trench is located closer to the semiconductor substrate than the impurity region in the thickness direction of the semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 5 , wherein the first conductor functions as a gate.

8. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first trench is surrounded by the second trench when viewed in a thickness direction of the semiconductor layer.

9. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductor and the second conductor are each made of polysilicon.

10. a semiconductor layer located on a semiconductor substrate and having a first conductivity type; an impurity region located in the semiconductor layer and having a second conductivity type different from the first conductivity type; a first trench having a bottom surface in the semiconductor layer and adjacent to the impurity region; a first conductor located in the first trench and spaced apart from the semiconductor layer; a first contact region having the first conductivity type, the first contact region being located on the impurity region within the semiconductor layer and in contact with a side surface of the first trench; a second contact region located in the semiconductor layer and in contact with the side surface of the first trench, the second contact region having the first conductivity type; a second groove that penetrates the semiconductor layer and surrounds the first groove; a second conductor located in the second groove and in contact with the semiconductor substrate; Equipped with The width of the second groove is greater than the width of the first groove. Semiconductor device.

11. The semiconductor device according to claim 10 , wherein the width of the second trench is 104% or more and 900% or less of the width of the first trench.

12. 11. The semiconductor device according to claim 10, wherein a ratio of the width of the first trench to the depth of the first trench is 3.7% or more and 450% or less of a ratio of the width of the second trench to the depth of the second trench.

13. The semiconductor device according to claim 10 , wherein the first conductor functions as a gate.

14. 12. The semiconductor device according to claim 10, wherein the first conductor and the second conductor are each made of polysilicon.

15. 12. The semiconductor device according to claim 10, wherein the side surface of the first trench is defined by a second impurity region located in the semiconductor layer and having the first conductivity type.

16. the first trench surrounds the impurity region and the first contact region in a plan view; The semiconductor device according to claim 10 , wherein the second contact region surrounds the first trench in a plan view.

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