Image sensor and method for manufacturing image sensor

Abstract

To provide an image sensor which can be reduced in power consumption and area.SOLUTION: An image sensor includes a logic chip and a pixel chip, the logic chip includes a logic circuit that processes a signal received from the pixel chip, the pixel chip includes a SPAD element 100 that is an avalanche photodiode, a vertical gate-all-around clip transistor 200 that includes a channel 230 formed of a part of a columnar active pillar 201 having one end connected to a cathode 120 of the avalanche photodiode and a planar gate 240 surrounding the channel, and a hybrid bump 260 that is an electrode pad connected to the other end of the columnar active pillar, and the logic chip and the pixel chip are connected via the electrode pad.SELECTED DRAWING: Figure 4A

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for manufacturing an image sensor. [Background technology]

[0002] In recent years, attention has been focused on SPADs (Single Photon Avalanche Diodes), which amplify the charge generated by the photoelectric conversion of incident light through avalanche amplification and output it as an electrical signal. SPADs are photon counting sensors that can detect individual light particles, have extremely high time resolution, and count incident photons one by one for each pixel, and are attracting attention as a technology that enables high dynamic range and noise-free readout.

[0003] Each pixel of the image sensor includes a photodiode such as a SPAD and a logic circuit that processes the signal detected by the photodiode.

[0004] The following Patent Document 1 discloses the following image sensor: The image sensor includes a plurality of photodiodes arranged on a substrate, a plurality of active pillars connected to the photodiodes and extending vertically on the lower surface of the substrate, at least two transistors stacked vertically using a portion of the active pillar as a channel region, and a floating diffusion region arranged below the transfer transistor, which is the uppermost transistor, and through which charges are transferred from the photodiodes via the transfer transistor and a portion of the active pillar.

[0005] The following Patent Document 2 discloses the following light receiving element: The light receiving element is configured by laminating a first substrate on which an avalanche photodiode and a polysilicon TFT forming a clamp circuit connected to the cathode of the avalanche photodiode are formed, and a second substrate on which MOSFETs forming quenching resistors and inverters connected to the polysilicon TFTs are formed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2022-184799 [Patent Document 2] International Publication No. 2022 / 149467 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the image sensor disclosed in Patent Document 1, all transistors included in the pixel circuit are formed on the same substrate as the photodiode. Therefore, when the pixel circuit is configured with multiple transistors with different threshold voltages, the power supply voltage cannot be reduced because it is limited to transistors with high threshold voltages, making it impossible to achieve low power consumption. Furthermore, in the photodetector disclosed in Patent Document 2, pixel miniaturization is limited by the arrangement space for polysilicon TFTs, which are planar transistors, making it impossible to achieve a small pixel area.

[0008] The present invention has been made to solve the above problems, and aims to provide an image sensor and a method for manufacturing the image sensor that can achieve low power consumption and a small area. [Means for solving the problem]

[0009] 1. An image sensor having a logic chip and a pixel chip, wherein the logic chip has a logic circuit that processes signals received from the pixel chip, and the pixel chip has an avalanche photodiode, a vertical gate-all-around transistor having a channel formed by a part of a columnar active pillar, one end of which is connected to a cathode of the avalanche photodiode, and a planar gate surrounding the channel, and an electrode pad connected to the other end of the columnar active pillar, and the logic chip and the pixel chip are connected via the electrode pad. [Effects of the Invention]

[0010] The image sensor is composed of a logic chip having a logic circuit and a pixel chip having an avalanche photodiode. The pixel chip is provided with a vertical gate-all-around transistor, which has a channel made of a part of a columnar active pillar, one end of which is connected to the cathode of the avalanche photodiode provided on the pixel chip, and the other end of which is connected to an electrode pad for connection to the logic chip, and a planar gate. This enables the image sensor to achieve low power consumption and a small area. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor 1. FIG. [Figure 2] FIG. 2 is a circuit diagram illustrating an example of a schematic configuration of a pixel. [Figure 3] FIG. 2 is a diagram showing a stacked structure of a pixel array. [Figure 4A] FIG. 2 is a cross-sectional view showing the structure of a unit element. [Figure 4B] FIG. 2 is a plan view of a unit element. [Figure 5A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 5B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 6A]10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 6B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 7A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 7B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 8A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 8B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 9A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 9B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 10A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 10B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 11A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 11B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 12A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 12B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 13A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 13B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 14A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 14B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 15A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 15B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 16A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 16B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 17] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 18A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 18B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 19A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 19B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 20] 1 is a flowchart illustrating a method of manufacturing an image sensor. [Figure 21] 10A and 10B are explanatory diagrams showing examples of layout intervals of each layer when the clip transistor is reduced within a range that satisfies the layout rule for each layer that constitutes the clip transistor; [Figure 22] FIG. 10 is a diagram showing the configuration of a gate that also serves as a reflector. [Figure 23A] 10 is an explanatory diagram for explaining resistance control between the cathode of a SPAD element and a P-type diffusion layer of a clip transistor. FIG. [Figure 23B] 10 is an explanatory diagram for explaining resistance control between the cathode of a SPAD element and a P-type diffusion layer of a clip transistor. FIG. [Figure 24] FIG. 2 is a circuit diagram illustrating an example of a schematic configuration of a pixel. [Figure 25A] FIG. 2 is a cross-sectional view showing the structure of a unit element. [Figure 25B] FIG. 2 is a plan view of a unit element. [Figure 26A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 26B]10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 27A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 27B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 28A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 28B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 29A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 29B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 30A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 30B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 31A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 31B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 32A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 32B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 33A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 33B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 34A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 34B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 35A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 35B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 36A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 36B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 37A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 37B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 38A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 38B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 39A] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 39B] 10A to 10C are explanatory diagrams for explaining a manufacturing method of a unit pixel. [Figure 40] 1 is a flowchart illustrating a method of manufacturing an image sensor. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an image sensor and a method for manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings. The described embodiments are merely exemplary, and various modifications may be made to the embodiments. Hereinafter, the same reference numerals in the drawings refer to the same components, and the dimensions of the components in the drawings are not proportional to the actual size for the sake of clarity and convenience of description.

[0013] Hereinafter, the expressions "upper" or "above" include not only what is directly above / below / left / right in contact, but also what is above / below / left / right without contact.

[0014] Terms such as "first" and "second" are used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the materials or structures of the components.

[0015] An element expressed in the singular includes a plurality of elements unless the context clearly dictates otherwise. Furthermore, when a part "comprises" a certain element, this does not mean that other elements are excluded, but that other elements may also be included, unless otherwise specified to the contrary.

[0016] In addition, terms such as "unit" and "module" used in the specification refer to a unit that processes one or more functions or operations, and may be realized by hardware or software, or a combination of hardware and software.

[0017] (First embodiment) <Image sensor 1> FIG. 1 is a block diagram showing a schematic configuration of an image sensor 1. The image sensor 1 is, for example, a back-illuminated image sensor 1. The image sensor 1 may also be a front-illuminated image sensor 1. In a back-illuminated image sensor 1, the surface opposite to the element-forming surface of a substrate 510 (see FIG. 4A) is the light incident surface. In a front-illuminated image sensor 1, the element-forming surface is the light incident surface. For ease of explanation, the following description will be given taking as an example a case where the image sensor 1 is a back-illuminated image sensor 1. Hereinafter, the element-forming surface of the substrate 510 will also be referred to as the "front surface." The surface of the substrate 510 opposite to the element-forming surface will also be referred to as the "back surface."

[0018] The image sensor 1 includes a pixel array 10, a control circuit 20, a drive circuit 30, and an output circuit 40.

[0019] The pixel array 10 includes a plurality of pixels 11 arranged in a matrix. Each pixel 11 is connected to a pixel drive line 50 for each column and to an output signal line 60 for each row. The pixel drive lines 50 are connected to output terminals of a drive circuit 30 corresponding to each column. The output signal lines 60 are connected to input terminals of an output circuit 40 corresponding to each row.

[0020] The drive circuit 30 includes a shift register, an address decoder, etc., and drives all of the pixels 11 in the pixel array 10 simultaneously or column by column. The drive circuit 30 includes a circuit that applies a quench voltage VQ, which will be described later, to each pixel 11. When driving each pixel 11 column by column, the drive circuit 30 may include a circuit that applies a selection signal voltage VSEL to each pixel 11 in a selected column. In this case, each pixel 11 is selected by the selection signal voltage VSEL, a power supply voltage is applied only to the selected pixel 11, and a detection signal VOUT is output from that pixel 11.

[0021] The detection signals VOUT output from the pixels 11 are input to the output circuit 40 through the output signal lines 60. The output circuit 40 outputs the detection signals VOUT input from the pixels 11 as image signals.

[0022] The control circuit 20 includes a timing generator that generates various timing signals, and controls the drive circuit 30 and the output circuit 40 based on the various timing signals generated by the timing generator.

[0023] <Pixel 11> FIG. 2 is a circuit diagram showing an example of a schematic configuration of the pixel 11.

[0024] Each pixel 11 includes a SPAD element 100, a clip transistor 200, a quench resistor 300, and an inverter 400. The quench resistor 300 may be a recharge transistor. The SPAD element 100 is an example of an avalanche photodiode. For simplicity, the following description will be given assuming that the avalanche photodiode is the SPAD element 100. As will be described later, the SPAD element 100 and the clip transistor 200 are formed on a pixel chip 500 (see FIG. 3), and the quench resistor 300 and the inverter 400 are formed on a logic chip 600. The pixel chip 500 and the logic chip 600 are aligned for each pixel 11 and bonded together by hybrid bumps 260 (see FIG. 4A), thereby forming each pixel 11. In FIG. 2, the connection point where the clip transistor 200 and the quench resistor 300 are connected by the junction between the pixel chip 500 and the logic chip 600 is indicated as node N1. The boundary between the pixel chip 500 and the logic chip 600 is indicated by a dashed line.

[0025] The SPAD element 100 is a light receiving element, and when a photon is incident while a reverse bias voltage equal to or greater than the breakdown voltage is applied between the anode and cathode, an avalanche current is generated. An anode voltage VA is applied to the anode of the SPAD element 100, and a cathode voltage VC is applied to the cathode via a quench resistor 300 and a clip transistor 200. The anode voltage VA is set to, for example, −15 V to −30 V. The cathode voltage VC is set to, for example, 3 V. When a reverse bias voltage equal to or greater than the breakdown voltage is applied to the SPAD element 100, it operates in Geiger mode and is capable of detecting a single photon.

[0026] The clip transistor 200 has a clip voltage HV supplied to its gate and clips the source voltage so that it does not fall below a predetermined value. That is, the clip transistor 200 clips the voltage of the node N1, which is the connection point between the logic chip 600 and the pixel chip 500. The clip transistor 200 is configured, for example, by a PMOS (Metal Oxide Semiconductor).

[0027] The quench resistor 300 operates as a quench resistor when a quench voltage VQ supplied from the drive circuit 30 is applied to its gate. The quench resistor 300 also has a recharge function that returns the voltage supplied to the SPAD element 100 to VC by passing a current equivalent to the voltage drop caused by the quench operation. The quench resistor 300 is configured, for example, by a PMOS transistor.

[0028] The current flowing through the SPAD element 100 is converted into a voltage by the quench resistor 300 and output to the inverter 400 .

[0029] The inverter 400 is configured by connecting a PMOS transistor 400P and an NMOS transistor 400N in series. The source of the PMOS transistor 400P is connected to the power supply VHV for driving the digital circuit, and the drain is connected to the drain of the NMOS transistor 400N. The drain of the NMOS transistor 400N is connected to the drain of the PMOS transistor 400P, and the source of the NMOS transistor 400N is grounded. The gates of the PMOS transistor 400P and the NMOS transistor 400N are connected to each other, and their connection point serves as the input of the inverter 400. The connection point of the drain of the PMOS transistor 400P and the drain of the NMOS transistor 400N serves as the output of the inverter 400. The input of the inverter 400 is connected to a node N1, which is the connection point between the SPAD element 100 and the quench resistor 300.

[0030] The inverter 400 converts the input voltage into a digital signal and outputs it as a detection signal VOUT. Note that a buffer for impedance conversion may be provided at the output of the inverter 400, so that an impedance-converted detection signal VOUT may be output from each pixel 11.

[0031] The detection signal VOUT is input to the output circuit 40. The output circuit 40 outputs the detection signal VOUT to a processor (not shown), for example, via a TDC (Time to Digital Converter) (not shown). The detection signal VOUT is subjected to various processes by the processor.

[0032] The quench resistor 300, the inverter 400, the control circuit 20, the drive circuit 30, and the output circuit 40 constitute a logic circuit that processes a signal received from the pixel chip 500. The logic circuit may further include a circuit that processes the detection signal VOUT output from the inverter 400. The threshold voltage of the transistor in the logic circuit can be set lower than the threshold voltage of the clip transistor 200. This allows the power consumption of the image sensor 1 to be reduced.

[0033] <Operation of pixel 11> When a photon is incident on the SPAD element 100 while a reverse bias voltage VSPAD equal to or greater than the breakdown voltage is being applied to the SPAD element 100 via the quench resistor 300 and the clip transistor 200, an avalanche current is generated in the SPAD element 100. The reverse bias voltage VSPAD is the sum of the absolute value of the anode voltage VA and the absolute value of the cathode voltage VC. As the avalanche current flows through the quench resistor 300, the voltage at the node N1 drops. When the voltage at the node N1 falls below the threshold voltage of the PMOS transistor 400P of the inverter 400, the PMOS transistor 400P becomes conductive, causing the inverter 400 to output the power supply VHV as a high-level detection signal.

[0034] Thereafter, as the voltage at node N1 continues to decrease, the gate-source voltage of the clipping transistor 200 falls below the threshold, preventing current from flowing through the clipping transistor 200, and the voltage at node N1 is clipped. Furthermore, the voltage applied to the SPAD element 100 falls below the breakdown voltage. This prevents avalanche current from flowing, causing the voltage at node N1 to increase. When the voltage at node N1 becomes higher than the threshold voltage of the NMOS transistor 400N of the inverter 400, the NMOS transistor 400N becomes conductive, causing the inverter 400 to output the ground voltage as a low-level detection signal.

[0035] <Stacked structure of pixel array 10> FIG. 3 is a diagram showing the layered structure of the pixel array 10. As shown in FIG.

[0036] The pixels 11 are arranged in an array to form a pixel array 10. The SPAD elements 100 are arranged in an array to form an element array 70. The pixel array 10 has a structure in which a pixel chip 500 and a logic chip 600 are stacked. The pixel chip 500 is a semiconductor chip on which the SPAD elements 100 and clip transistors 200 are formed in an array. The logic chip 600 is a semiconductor chip on which quench resistors 300 and inverters 400 are formed at positions corresponding to the SPAD elements 100. The logic chip 600 may further include a control circuit 20, a drive circuit 30, and an output circuit 40. The logic chip 600 may also include the aforementioned buffer for impedance conversion of the detection signal VOUT.

[0037] Hereinafter, a unit of an element group formed on the pixel chip 500, including the SPAD element 100 and the clip transistor 200, will also be referred to as a "unit element 150."

[0038] The pixel chip 500 and the logic chip 600 can be bonded, for example, by flattening their respective bonding surfaces and bringing them into contact with each other. Specifically, the pixel chip 500 and the logic chip 600 can be bonded by metal bonding between the hybrid bumps 260 exposed on the bonding surface of the pixel chip 500 and the metal pads exposed on the bonding surface of the logic chip 600.

[0039] <Structure of unit element 150> Fig. 4A is a cross-sectional view showing the structure of unit element 150. Fig. 4B is a plan view of unit element 150. In Fig. 4A, incident light incident on the light incident surface of unit element 150 is indicated by an arrow.

[0040] A plurality of unit elements 150 are formed on a substrate 510 of a pixel chip 500. The substrate 510 is, for example, a single crystal silicon substrate.

[0041] The unit element 150 includes a pixel separation layer 160. The pixel separation layer 160 separates the SPAD element 100 from other SPAD elements 100. The pixel separation layers 160 of the multiple SPAD elements 100 formed on the substrate 510 can be connected to each other to form a lattice shape when viewed in plan from the light incident surface.

[0042] The photoelectric conversion region 140 of the SPAD element 100 is a region that converts incident light into electricity and generates electron-hole pairs. The photoelectric conversion region 140 is designed to have a potential such that electrons generated by photoelectric conversion are gathered in the avalanche region 125.

[0043] The anode electrode layer 110 functions as the anode of the SPAD element 100. The anode electrode layer 110 has a first conductivity type, which may be, for example, the P type.

[0044] The cathode electrode layer 120 functions as the cathode of the SPAD element 100. The cathode electrode layer 120 may have a second conductivity type, which may be, for example, N-type.

[0045] For simplicity of explanation, the following description will be given taking as an example a case where the first conductivity type is P type and the second conductivity type is N type.

[0046] The P-type semiconductor layer 130 is in contact with the cathode electrode layer 120. The P-type semiconductor layer 130 and the N-type cathode electrode layer 120 are joined to form a PN junction of the SPAD element 100. The PN junction constitutes an avalanche region 125, and functions as an amplification region that accelerates charges that have flowed into the P-type semiconductor layer 130 to generate an avalanche current.

[0047] The anode electrode layer 110 of the SPAD element 100 is symmetrical to the cathode electrode layer 120 on the surface of the substrate 510 of the pixel chip 500 .

[0048] An anti-reflection film (not shown) is formed on the light incident surface of the substrate 510 to prevent reflection of incident light.

[0049] Color filters (not shown) and on-chip lenses (not shown) corresponding to each SPAD element 100 may be formed on the anti-reflection film. The color filters may be any of a color filter that selectively transmits light of a red (R) wavelength component, a color filter that selectively transmits light of a green (G) wavelength component, and a color filter that selectively transmits light of a blue (B) wavelength component, corresponding to each SPAD element 100. Each color filter may be formed to form a Bayer array.

[0050] A clip transistor 200 is formed on the surface of the substrate 510. The clip transistor 200 is a gate-all-around MOS transistor. Specifically, the clip transistor 200 is a gate-all-around PMOS transistor including a pillar-shaped channel 230 made of a part of a pillar-shaped active pillar 201, one end of which is connected to the cathode electrode layer 120 of the SPAD element 100, and a planar gate 240 surrounding the channel 230. A hybrid bump 260 is connected to the other end of the pillar-shaped channel 230 of the clip transistor 200. The hybrid bump 260 constitutes an electrode pad.

[0051] The gate 240 can be polysilicon and / or metal.

[0052] One end of the columnar active pillar 201 can be connected to the cathode electrode layer 120 in an area including the center of the cathode electrode layer 120 on the surface of the substrate 510 .

[0053] The active pillar 201 is made of, for example, polysilicon or single crystal silicon. A source 220 and a drain 210 are formed on both sides of a channel 230 in the active pillar 201. A gate oxide film 250 is formed on the surface of the region of the active pillar 201 where the channel 230 is to be formed. This forms the clip transistor 200.

[0054] A gate wiring 280, an anode wiring 290, and a hybrid bump 260 are formed on the clip transistor 200. The gate wiring 280 is connected to the gate 240 through a via. The anode wiring 290 is connected to the anode electrode layer 110 through a via. The anode wiring 290 is a wiring for supplying an anode voltage VA to the SPAD element 100. The gate wiring 280 is a wiring for supplying a clip voltage HV to the clip transistor 200. The hybrid bump 260 is exposed on the surface of the unit element 150.

[0055] The hybrid bumps 260 can be bonded by metal bonding to the connection pads exposed on the surface of the logic chip 600. In this way, the pixel chip 500 and the logic chip 600 can be bonded together.

[0056] The layers constituting the clip transistor 200, as well as the layers constituting the gate wiring 280, the anode wiring 290, and the hybrid bump 260, are insulated from one another by an interlayer insulating film 203 and an insulating layer 204.

[0057] A pillar 202 made of insulating material may be provided around the pillar-shaped active pillar 201.

[0058] <Logic chip 600 structure> The logic chip 600 may be composed of a substrate and a wiring layer. In this case, elements constituting the logic circuit, including transistors constituting the quench resistor 300 and the inverter 400, are formed on the substrate at positions corresponding to the unit elements 150. Furthermore, wiring for constituting the logic circuit, including wiring connecting the quench resistor 300 and the inverter 400, and wiring including connection pads are formed on the wiring layer.

[0059] <Method of Manufacturing Unit Element 150> A method for manufacturing the unit element 150 will be described.

[0060] 5A to 19B are explanatory diagrams for explaining the manufacturing method of the unit element 150. The figures at the end A are cross-sectional views for explaining the manufacturing method of the unit element 150, and the figures at the end B with the same numbers are plan views corresponding to the cross-sectional views at the end A.

[0061] 5A and 5B, a stacked film 2100 including a first sacrificial layer 2051, a gate film 2041, and a second sacrificial layer 2052 is formed on a substrate 510 of a pixel chip 500 on which a SPAD element 100 is formed. More specifically, the stacked film 2100 is formed by depositing the first sacrificial layer 2051, a first interlayer insulating film 2032, a gate film 2041, a second interlayer insulating film 2033, and the second sacrificial layer 2052 in this order on the substrate 510. The stacked film 2100 may also be formed by depositing a bottom-layer interlayer insulating film 2031 and a top-layer interlayer insulating film 2034 below the first sacrificial layer 2051 and above the second sacrificial layer 2052, respectively. The first sacrificial layer 2051 and the second sacrificial layer 2052 may be made of silicon nitride (SiN). The first interlayer insulating film 2032 and the second interlayer insulating film 2033 may be made of silicon dioxide (SiO2). The gate film 2041 may be made of at least one of polysilicon and metal. After being formed, the first sacrificial layer 2051, the first interlayer insulating film 2032, the gate film 2041, the second interlayer insulating film 2033, and the second sacrificial layer 2052 are patterned by anisotropic etching using a resist, and after patterning, are backfilled with silicon dioxide (SiO2) and the surface is planarized. The bottom interlayer insulating film 2031 and the top interlayer insulating film 2034 may be made of silicon dioxide (SiO2).

[0062] 6A and 6B, the cathode electrode layer 120 is exposed by forming a first hole 206 that penetrates the laminated film 2100. The first hole 206 constitutes a hole. The first hole 206 is formed by, for example, anisotropic etching.

[0063] 7A and 7B, a gate oxide film 250 is formed on the sidewall of the formed first hole 206. The gate oxide film 250 may be made of silicon dioxide (SiO2).

[0064] 8A and 8B, the portion of the gate oxide film 250 that contacts the cathode electrode layer 120 at the bottom of the first hole 206 and the portion on the uppermost interlayer insulating film 2034 are removed by anisotropic etching, thereby exposing the cathode electrode layer 120.

[0065] 9A and 9B, a columnar active pillar 201 is formed in the first hole 206 so as to connect to the cathode electrode layer 120 of the SPAD element 100. The active pillar 201 can be made of, for example, polysilicon.

[0066] 10A and 10B, the portion of the active pillar 201 on the uppermost interlayer insulating film 2034 is removed. The portion of the active pillar 201 on the uppermost interlayer insulating film 2034 is removed by, for example, CMP (Chemical Mechanical Polishing).

[0067] 11A and 11B, for example, two second holes 207 are formed around the active pillar 201, penetrating the laminated film 2100. The second holes 207 are formed by, for example, anisotropic etching.

[0068] 12A and 12B, insulating material is filled into second hole 207 to form insulating pillar 202. Insulating pillar 202 may be made of silicon dioxide (SiO2). Forming insulating pillar 202 can prevent stacked film 2100 from collapsing in the process of removing first sacrificial layer 2051 and second sacrificial layer 2052, which will be described later.

[0069] 13A and 13B, a trench 208 penetrating the stacked film 2100 is formed for each SPAD element 100 so that, for example, at least a portion of the trench 208 overlaps with the pixel isolation layer 160 that separates the SPAD elements 100 from one another. The trench 208 is formed by, for example, anisotropic etching.

[0070] 14A and 14B, the first sacrificial layer 2051 and the second sacrificial layer 2052 are removed to expose the gate oxide film 250. The first sacrificial layer 2051 and the second sacrificial layer 2052 can be removed by wet etching with an adjusted selectivity.

[0071] 15A and 15B, a portion of the exposed gate oxide film 250 is removed to expose a portion of the active pillar 201. The portion of the gate oxide film 250 can be removed by wet etching with an adjusted selectivity.

[0072] 16A and 16B, a diffusion layer is formed in the exposed portion of the active pillar 201 to form the source 220 and the drain 210 of the clip transistor 200. The source 220 and the drain 210 can be formed by plasma doping or solid phase diffusion.

[0073] 17, the source 220 and the drain 210 can be formed by self-alignment by doping the active pillar 201 with an acceptor, which is a P-type impurity, using the bottom interlayer insulating film 2031, the first interlayer insulating film 2032, the second interlayer insulating film 2033, and the top interlayer insulating film 2034 as a mask. This reduces variations in the characteristics of the clip transistor 200.

[0074] 18A and 18B, the spaces between the bottom interlayer insulating film 2031, the first interlayer insulating film 2032, the second interlayer insulating film 2033, and the top interlayer insulating film 2034, as well as the trench 208, are filled with an insulating layer 204. The insulating layer 204 may be made of silicon dioxide (SiO2).

[0075] As shown in FIGS. 19A and 19B, a wiring layer 299 including gate wiring 280, anode wiring 290, and hybrid bump 260 electrically connected to the gate film 2041 is formed.

[0076] FIG. 20 is a flowchart showing a method for manufacturing the image sensor 1.

[0077] The SPAD element 100 is formed on the substrate 510 of the pixel chip 500 (S101). The SPAD element 100 may be formed using any known technique.

[0078] A laminated film 2100 including a first sacrificial layer 2051, a gate film 2041, and a second sacrificial layer 2052 is formed on the SPAD element 100 (S102).

[0079] A first hole 206 is formed through the laminated film 2100 (S103).

[0080] A gate oxide film 250 is formed on the sidewall of the formed first hole 206 (S104).

[0081] A columnar active pillar 201, one end of which is connected to the cathode electrode layer 120 of the SPAD element 100, is formed in the first hole 206 (S105).

[0082] A pillar 202 made of insulating material is formed around the active pillar 201 (S106).

[0083] A trench 208 is formed for each SPAD element 100, passing through the stacked film 2100, so as to overlap the pixel isolation layer 160 that isolates the SPAD elements 100 from one another (S107).

[0084] A portion of the gate oxide film 250 exposed by removing the first sacrificial layer 2051 and the second sacrificial layer 2052 is removed, thereby exposing a portion of the active pillar 201 (S108).

[0085] A diffusion layer is formed in the exposed part of the active pillar 201 to form the source 220 and the drain 210 of the clip transistor 200 (S109).

[0086] <Miniaturization of pixel 11> FIG. 21 is an explanatory diagram showing an example of the layout spacing of each layer when the clip transistor 200 is reduced within a range that satisfies the layout rules defined to ensure the reliability of each layer that constitutes the clip transistor 200.

[0087] The layout rules may include the minimum diameter of the first hole 206 where the active pillar 201 is formed, the minimum distance between the first hole 206 and the edge of the gate 240 overlapping with the first hole 206, and the like.

[0088] In the example of FIG. 21, it is shown that when laying out under the constraint of separating the gate 240, the first hole 206, and the anode wiring 290 by at least 0.1 μm, the pixel 11 can be miniaturized to 0.9 μm × 0.9 μm.

[0089] <Function as a reflector of the gate 240> FIG. 22 is a diagram showing the configuration of the gate 240 that also serves as a reflector. By reflecting the light that reaches the gate 240 without causing photoelectric conversion in the pixel 11 and returning it to the pixel 11, the crosstalk of light to adjacent pixels can be reduced.

[0090] By increasing the area of the gate 240 in plan view, the gate 240 can also serve as a reflector. When the gate 240 also serves as a reflector, it is preferable to form the gate 240 with metal, but even if the gate 240 is formed with polysilicon, the gate 240 can function as a reflector.

[0091] In the example of FIG. 22, the area of the gate 240 is maximized while maintaining the distance from the anode connection hole 290a for connecting the anode electrode layer 110 and the anode wiring 290. In the example of FIG. 22, due to the shape of the gate 240 and the reduction of the area of the anode electrode layer 110, etc., the pixel 11 has been miniaturized to a size of 0.72 μm × 0.72 μm.

[0092] <Resistance control between the cathode of the SPAD element 100 and the P-type diffusion layer of the clipping transistor 200> 23A and 23B are explanatory diagrams for explaining the control of the resistance between the cathode of the SPAD element 100 and the P-type diffusion layer of the clip transistor 200. As shown in Fig. 23A and Fig. 23B, the resistance between the cathode of the SPAD element 100 and the P-type diffusion layer of the clip transistor 200 can be adjusted by adjusting the film thickness of the lowest interlayer insulating film 2031.

[0093] 23A and 23B, the distance between the cathode electrode layer 120 of the SPAD element 100 and the drain 210 of the clip transistor 200 can be controlled by controlling the film thickness of the lowermost interlayer insulating film 2031. This controls the length of the active pillar 201 between the cathode electrode layer 120 and the drain 210, and therefore the resistance between the cathode electrode layer 120 and the drain 210 can be easily controlled.

[0094] (Second embodiment) The second embodiment will be described. The present embodiment differs from the first embodiment in the following points. In the first embodiment, the clip transistor 200 is configured by one PMOS transistor. On the other hand, in the present embodiment, the clip transistor 200 is configured by two PMOS transistors connected in series. In other respects, the present embodiment is similar to the first embodiment, so duplicated explanations will be omitted or simplified.

[0095] <Pixel 11> FIG. 24 is a circuit diagram showing an example of a schematic configuration of the pixel 11.

[0096] The pixel 11 includes a SPAD element 100, a clip transistor 200, a quench resistor 300, and an inverter 400. The clip transistor 200 is formed by connecting a first transistor 200a and a second transistor 200b in series. Specifically, the clip transistor 200 is formed by two transistors, with the drain of the first transistor 200a and the source of the second transistor 200b connected together.

[0097] 24, the connection point where the clip transistor 200 and the quench resistor 300 are connected by the junction between the pixel chip 500 and the logic chip 600 is shown as node N1. The boundary between the pixel chip 500 and the logic chip 600 is also shown by a dashed line.

[0098] A first clipping voltage HV1 and a second clipping voltage HV2 are supplied to the gates of the first transistor 200a and the second transistor 200b of the clipping transistor 200, respectively. The clipping transistor 200 clips the source voltage of the first transistor 200a so that it does not fall below a predetermined value. That is, the clipping transistor 200 clips the voltage of the node N1, which is the connection point between the logic chip 600 and the pixel chip 500. The first transistor 200a and the second transistor 200b are configured, for example, by PMOS.

[0099] The gates of the first transistor 200a and the second transistor 200b may be shorted to each other. In this case, a common clip voltage HV is supplied to the gates of the first transistor 200a and the second transistor 200b. For ease of explanation, unless otherwise specified, the following description will be given assuming that the gates of the first transistor 200a and the second transistor 200b are shorted to each other and that a common clip voltage HV is supplied to both gates.

[0100] <Operation of pixel 11> When a photon is incident on the SPAD element 100 while a reverse bias voltage VSPAD equal to or greater than the breakdown voltage is being applied to the SPAD element 100 via the quench resistor 300, an avalanche current is generated in the SPAD element 100. The reverse bias voltage VSPAD is the sum of the absolute value of the anode voltage VA and the absolute value of the cathode voltage VC. As the avalanche current flows through the quench resistor 300, the voltage at the node N1 drops. When the voltage at the node N1 falls below the threshold voltage of the PMOS transistor 400P of the inverter 400, the PMOS transistor 400P becomes conductive, causing the inverter 400 to output the power supply VHV as a high-level detection signal.

[0101] Thereafter, as the voltage at node N1 continues to decrease, the gate-source voltage of the first transistor 200a falls below the threshold, preventing current from flowing through the first transistor 200a and the second transistor 200b, and the voltage at node N1 is clipped. Furthermore, the voltage applied to the SPAD element 100 falls below the breakdown voltage. This prevents avalanche current from flowing, causing the voltage at node N1 to increase. When the voltage at node N1 becomes higher than the threshold voltage of the NMOS transistor 400N of the inverter 400, the NMOS transistor 400N becomes conductive, causing the inverter 400 to output the ground voltage as a low-level detection signal.

[0102] <Structure of unit element 150> 25A is a cross-sectional view showing the structure of the unit element 150. FIG.

[0103] A plurality of unit elements 150 are formed on a substrate 510 of a pixel chip 500. The substrate 510 is, for example, a single crystal silicon substrate.

[0104] The P-type semiconductor layer 130 is in contact with the cathode electrode layer 120. The P-type semiconductor layer 130 and the N-type cathode electrode layer 120 are joined to form a PN junction of the SPAD element 100. The PN junction constitutes an avalanche region 125, and functions as an amplification region that accelerates charges that have flowed into the P-type semiconductor layer 130 to generate an avalanche current.

[0105] The anode electrode layer 110 of the SPAD element 100 is symmetrical to the cathode electrode layer 120 on the surface of the substrate 510 of the pixel chip 500 .

[0106] A clip transistor 200 is formed on the surface of the substrate 510. The clip transistor 200 is composed of a first transistor 200a and a second transistor 200b connected in series. The first transistor 200a and the second transistor 200b are gate-all-around MOS transistors. Specifically, the second transistor 200b is a gate-all-around PMOS transistor including a pillar-shaped second channel 230b formed by a part of a pillar-shaped active pillar 201, one end of which is connected to the cathode electrode layer 120 of the SPAD element 100, and a planar second gate 240b surrounding the second channel 230b. The first transistor 200a is a gate-all-around PMOS transistor including a pillar-shaped first channel 230a formed by another part of the active pillar 201, and a planar first gate 240a surrounding the first channel 230a. A hybrid bump 260 is connected to the other end of the active pillar 201.

[0107] The first gate 240a of the first transistor 200a and the second gate 240b of the second transistor 200b may be made of at least one of polysilicon and metal, and the first gate 240a and the second gate 240b intersect in a crisscross pattern (three-dimensional intersection) in a plan view (see FIG. 26B).

[0108] One end of the active pillar 201 can be connected to the cathode electrode layer 120 in an area including the center of the cathode electrode layer 120 on the surface of the substrate 510 .

[0109] A second source 220b and a second drain 210b are formed on both sides of the second channel 230b of the second transistor 200b in the active pillar 201. A second gate oxide film 250b is formed on the surface of the region of the active pillar 201 where the second channel 230b of the second transistor 200b is to be formed. This completes the second transistor 200b.

[0110] A first source 220a and a first drain 210a are formed on both sides of a first channel 230a of a first transistor 200a in the active pillar 201. A first gate oxide film 250a is formed on the surface of a region of the active pillar 201 where the first channel 230a of the first transistor 200a is to be formed. This completes the formation of the first transistor 200a.

[0111] Therefore, the clip transistor 200 is composed of two transistors connected in series, each of which has two parts of a columnar active pillar 201, one end of which is connected to the cathode of the SPAD element 100, as its channel, and each channel has a structure surrounded by two planar gates.

[0112] A first gate wiring 280a, a second gate wiring 280b, an anode wiring 290, and a hybrid bump 260 are formed on the first transistor 200a. The second gate wiring 280b is connected to the second gate 240b through a via. The first gate wiring 280a is connected to the first gate 240a through a via. The anode wiring 290 is connected to the anode electrode layer 110 through a via. The anode wiring 290 is a wiring for supplying an anode voltage VA to the SPAD element 100. The first gate wiring 280a is a wiring for supplying a first clipping voltage HV1 to the first transistor 200a. The second gate wiring 280b is a wiring for supplying a second clipping voltage HV2 to the second transistor 200b.

[0113] The hybrid bumps 260 can be bonded by metal bonding to the connection pads exposed on the surface of the logic chip 600. In this way, the pixel chip 500 and the logic chip 600 can be bonded together.

[0114] The layers constituting the clip transistor 200, and the layers constituting the first gate wiring 280a, the second gate wiring 280b, the anode wiring 290, and the hybrid bump 260 are insulated from one another by an interlayer insulating film 203 and an insulating layer 204.

[0115] A pillar 202 made of insulating material may be provided around the pillar-shaped active pillar 201.

[0116] <Method of Manufacturing Unit Element 150> A method for manufacturing the unit element 150 will be described.

[0117] 26A to 39B are explanatory diagrams for explaining the manufacturing method of the unit element 150. The figures at the end A are cross-sectional views for explaining the manufacturing method of the unit element 150, and the figures at the end B with the same numbers are plan views corresponding to the cross-sectional views at the end A.

[0118] 26A and 26B, a first sacrificial layer 2051, a second gate film 2041b, a second sacrificial layer 2052, a first gate film 2041a, and a third sacrificial layer 2053 are formed on a substrate 510 of a pixel chip 500 on which a SPAD element 100 is formed. More specifically, a stacked film 2100 is formed by depositing the first sacrificial layer 2051, a first interlayer insulating film 2032, a second gate film 2041b, a second interlayer insulating film 2033, the second sacrificial layer 2052, a third interlayer insulating film 2035, the first gate film 2041a, a fourth interlayer insulating film 2036, and the third sacrificial layer 2053 in this order on the substrate 510. A stacked film 2100 may be formed in which a bottom interlayer insulating film 2031 and a top interlayer insulating film 2034 are respectively formed below the first sacrificial layer 2051 and above the third sacrificial layer 2053. The first sacrificial layer 2051 to the third sacrificial layer 2053 may be made of silicon nitride (SiN). The first interlayer insulating film 2032 to the fourth interlayer insulating film 2036 may be made of silicon dioxide (SiO2). The gate film 2041 may be made of at least one of polysilicon and metal. Here, the first gate film 2041a and the second gate film 2041b cross each other in a planar view (multi-level crossing). This is to prevent interference with the first gate wiring 280a and the second gate wiring 280b, which will be formed later. After being formed, the first sacrificial layer 2051, the first interlayer insulating film 2032, the second gate film 2041b, the second interlayer insulating film 2033, and the second sacrificial layer 2052 are patterned by anisotropic etching using resist, and then backfilled with silicon dioxide (SiO2) to planarize the surface. After being formed, the first gate film 2041a is patterned by anisotropic etching using resist, and then backfilled with silicon dioxide (SiO2) to planarize the surface. The bottom interlayer insulating film 2031 and the top interlayer insulating film 2034 may be made of silicon dioxide (SiO2).

[0119] 27A and 27B, the cathode electrode layer 120 is exposed by forming a first hole 206 that penetrates the laminated film 2100. The first hole 206 constitutes a hole. The first hole 206 is formed by, for example, anisotropic etching.

[0120] 28A and 28B, a gate oxide film 250 is formed on the sidewall of the formed first hole 206. The gate oxide film 250 may be made of silicon dioxide (SiO2).

[0121] 29A and 29B, the portion of the gate oxide film 250 that contacts the cathode electrode layer 120 at the bottom of the first hole 206 and the portion on the uppermost interlayer insulating film 2034 are removed by anisotropic etching, thereby exposing the cathode electrode layer 120.

[0122] 30A and 30B, a columnar active pillar 201 is formed in the first hole 206 so as to connect to the cathode electrode layer 120 of the SPAD element 100. The active pillar 201 can be made of, for example, polysilicon.

[0123] 31A and 31B, the portion of the active pillar 201 above the uppermost interlayer insulating film 2034 is removed. The portion of the active pillar 201 above the uppermost interlayer insulating film 2034 is removed by, for example, CMP.

[0124] 32A and 32B, two second holes 207 are formed around the active pillar 201, penetrating the laminated film 2100. The second holes 207 are formed by, for example, anisotropic etching.

[0125] 33A and 33B, insulating material is filled into second hole 207 to form insulating pillar 202. Insulating pillar 202 may be made of silicon dioxide (SiO2). Forming insulating pillar 202 can prevent stacked film 2100 from collapsing in the process of removing first to third sacrificial layers 2051 to 2053, which will be described later.

[0126] 34A and 34B, a trench 208 that penetrates the stacked film 2100 is formed for each SPAD element 100 so that at least a portion of the trench overlaps the pixel isolation layer 160 that separates the SPAD elements 100 from one another. The trench 208 is formed by, for example, anisotropic etching.

[0127] 35A and 35B, the first to third sacrificial layers 2051 to 2053 are removed to expose the gate oxide film 250. The first to third sacrificial layers 2051 to 2053 can be removed by wet etching with an adjusted selectivity.

[0128] 36A and 36B, a portion of the exposed gate oxide film 250 is removed to expose a portion of the active pillar 201. The portion of the gate oxide film 250 can be removed by wet etching with an adjusted selectivity.

[0129] 37A and 37B, a diffusion layer is formed in an exposed portion of the active pillar 201 to form a first source 220a and a first drain 210a of the first transistor 200a and a second source 220b and a second drain 210b of the second transistor 200b. The first source 220a and the first drain 210a of the first transistor 200a and the second source 220b and the second drain 210b of the second transistor 200b may be formed by plasma doping. Note that the first drain 210a of the first transistor 200a and the second source 220b of the second transistor 200b may be formed as a single common diffusion layer.

[0130] By doping the active pillar 201 with an acceptor, which is a P-type impurity, using the bottom interlayer insulating film 2031, the first interlayer insulating film 2032, the second interlayer insulating film 2033, the third interlayer insulating film 2035, the fourth interlayer insulating film 2036, and the top interlayer insulating film 2034 as a mask, the first source 220a and the first drain 210a of the first transistor 200a and the second source 220b and the second drain 210b of the second transistor 200b can be formed by self-alignment. This reduces variations in the characteristics of the clip transistor 200.

[0131] 38A and 38B, spaces between the bottom interlayer insulating film 2031, the first interlayer insulating film 2032, the second interlayer insulating film 2033, the third interlayer insulating film 2035, the fourth interlayer insulating film 2036, and the top interlayer insulating film 2034, as well as the trench 208, are filled with an insulating layer 204. The insulating layer 204 may be made of silicon dioxide (SiO2).

[0132] 39A and 39B, the first gate wiring 280a is formed to be electrically connected to the first gate film 2041a, and the second gate wiring 280b is formed to be electrically connected to the second gate film 2041b. Also, a wiring layer 299 including an anode wiring 290 and a hybrid bump 260 is formed.

[0133] FIG. 40 is a flowchart showing a method for manufacturing the image sensor 1.

[0134] The SPAD element 100 is formed on the substrate 510 of the pixel chip 500 (S201).

[0135] A laminated film 2100 including a first sacrificial layer 2051, a second gate film 2041b, a second sacrificial layer 2052, a first gate film 2041a, and a third sacrificial layer 2053 is formed on the SPAD element 100 (S202).

[0136] A first hole 206 is formed through the laminated film 2100 (S203).

[0137] A gate oxide film 250 is formed on the sidewall of the formed first hole 206 (S204).

[0138] A columnar active pillar 201, one end of which is connected to the cathode electrode layer 120 of the SPAD element 100, is formed in the first hole 206 (S205).

[0139] An insulating pillar is formed around the active pillar 201 (S206).

[0140] A trench 208 is formed for each SPAD element 100, passing through the stacked film 2100, so as to overlap the pixel isolation layer 160 that isolates the SPAD elements 100 from one another (S207).

[0141] A portion of the gate oxide film 250 exposed by removing the first sacrificial layer 2051 and the second sacrificial layer 2052 is removed to expose a portion of the active pillar 201 (S208).

[0142] A diffusion layer is formed in the exposed portion of the active pillar 201 to form the first source 220a and drain 201a of the first transistor 200a, and the second source 220b and second drain 210b of the second transistor 200b (S209).

[0143] The embodiment has the following advantages.

[0144] The image sensor is composed of a logic chip having a logic circuit and a pixel chip having an avalanche photodiode. The pixel chip is provided with a vertical gate-all-around transistor, which has a channel made of a part of a columnar active pillar, one end of which is connected to the cathode of the avalanche photodiode provided on the pixel chip, and the other end of which is connected to an electrode pad for connection to the logic chip, and a planar gate. This enables the image sensor to achieve low power consumption and a small area.

[0145] Furthermore, the threshold voltage of the logic circuit transistors is set lower than that of the gate-all-around transistors, which makes it possible to simply and effectively reduce the power consumption of the image sensor.

[0146] In addition, the avalanche photodiode is formed on the substrate of the pixel chip, and the anode is symmetrical to the cathode on the surface of the substrate. One end of the columnar active pillar is connected to the cathode in an area including the center of the cathode on the surface of the substrate. This makes it possible to simply and effectively reduce the area of ​​the image sensor.

[0147] Furthermore, the gate of a gate-all-around transistor is made of at least one of polysilicon and metal, which allows the gate of the transistor to function as a reflector.

[0148] In addition, pillars of insulating material are provided around the pillar-shaped active pillars, which reduces the possibility of the stacked film collapsing during the manufacturing of the image sensor.

[0149] Furthermore, the gate-all-around transistor is used as a clip transistor that clips the voltage at the connection point between the logic chip and the pixel chip, which makes it possible to simply and effectively reduce the power consumption of the logic chip.

[0150] In addition, the gate-all-around transistor is configured by connecting two transistors in series, each channel of which is made up of two parts of a columnar active pillar connected at one end to the cathode of the avalanche photodiode, and each channel is surrounded by two planar gates, which further reduces the power consumption of the image sensor.

[0151] Furthermore, a stacked film including a first sacrificial layer, a gate film, and a second sacrificial layer is formed on a pixel chip substrate having an avalanche photodiode formed on its surface. A hole is formed through the stacked film, and a gate oxide film is formed on the sidewall of the formed hole. A columnar active pillar is then formed in the hole so as to connect to the cathode of the avalanche photodiode. A portion of the gate oxide film exposed by removing the first and second sacrificial layers is then removed to expose a portion of the active pillar. A diffusion layer is then formed in the exposed portion of the active pillar, forming a vertical gate-all-around transistor having a channel formed from a portion of the columnar active pillar, one end of which is connected to the cathode, and a planar gate surrounding the channel. This reduces variation in the characteristics of vertical gate-all-around transistors, thereby reducing manufacturing variation in image sensors.

[0152] Furthermore, a trench penetrating the stacked film is formed for each avalanche photodiode so that at least a portion of the trench overlaps with a pixel isolation layer that separates the avalanche photodiodes from one another. The trench is then used to remove portions of the first sacrificial layer, the second sacrificial layer, and the gate oxide film, and the trench is used to perform plasma doping and solid-phase diffusion on portions of the channel to form a source and a drain. This makes it possible to more easily form a vertical gate-all-around transistor with minimal variation in characteristics.

[0153] Additionally, before removing the first and second sacrificial layers, pillars of insulating material are formed around the pillar-shaped channels, which reduces the possibility of collapse of the film stack during fabrication of the image sensor.

[0154] Furthermore, a laminated film having a first sacrificial layer, a second gate film, a second sacrificial layer, a first gate film, and a third sacrificial layer is formed. The three portions of the gate oxide film exposed by removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are then removed, thereby exposing three portions of the active pillar. Then, a diffusion layer is formed in the three exposed portions of the active pillar, forming a vertical gate-all-around transistor in which two transistors, each with one end connected to the cathode and two portions of the columnar active pillar as channels, are connected in series, and each channel is surrounded by two planar gates. This further reduces the power consumption of the image sensor.

[0155] The above-described embodiments are merely examples, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the disclosed embodiments should be considered from an illustrative perspective, not a restrictive one. The scope of the invention is defined in the claims, and all structures within the scope of the claims should be construed as being within the scope of the invention. [Explanation of symbols]

[0156] 1 image sensor, 10 pixel array, 11 pixels, 20 control circuit, 30 drive circuit, 40 output circuit, 50 pixel drive lines, 60 output signal line, 70 element array, 100 SPAD elements, 110 anode electrode layer, 120 cathode electrode layer, 125 avalanche region, 130 P-type semiconductor layer, 140 Photoelectric conversion region, 200 clip transistor, 200a first transistor, 200b second transistor, 201 Active Pillar, 202 insulating pillars, 203 Interlayer insulating film, 2031 Bottom interlayer insulating film, 2032 first interlayer insulating film, 2033 Second interlayer insulating film, 2035 Third interlayer insulating film, 2036 Fourth interlayer insulating film, 2034 Top layer interlayer insulating film, 204 insulating layer, 2041 gate membrane, 2041a first gate film, 2041b second gate film, 2051 First Sacrificial Layer, 2052 Second Sacrificial Layer, 2053 Third Sacrificial Layer, 206 1st Hall, 207 2nd Hall, 210 drain, 210a first drain, 210b second drain; 220 Source, 220a First Source, 220b Second Source, 230 channels, 230a Channel 1, 230b second channel, 2100 laminated film, 240 gates, 240a Gate 1, 240b 2nd Gate, 250 gate oxide, 250a first gate oxide film, 250b second gate oxide, 260 Hybrid Bump, 280 gate wiring, 280a first gate wiring, 280b second gate wiring, 290 anode wiring, 299 wiring layer, 300 quench resistance, 400 inverter, 500 pixel chip, 510 semiconductor substrate, 600 logic chips.

Claims

1. An image sensor having a logic chip and a pixel chip, The logic chip comprises: a logic circuit for processing a signal received from the pixel chip; The pixel chip comprises: an avalanche photodiode; a vertical gate-all-around transistor having a channel formed of a part of a columnar active pillar, one end of which is connected to the cathode of the avalanche photodiode, and a planar gate surrounding the channel; an electrode pad connected to the other end of the columnar active pillar, The image sensor includes the logic chip and the pixel chip connected via the electrode pads.

2. 2. The image sensor according to claim 1, wherein a threshold voltage of the transistor of the logic circuit is lower than a threshold voltage of the gate-all-around transistor.

3. the avalanche photodiode is formed on a substrate of the pixel chip, and an anode is symmetrical with respect to the cathode on a surface of the substrate; The image sensor according to claim 1 , wherein the one end of the columnar active pillar is connected to the cathode in a range including the center of the cathode on the surface of the substrate.

4. 2. The image sensor according to claim 1, wherein the gate of the gate-all-around transistor is made of at least one of polysilicon and metal.

5. The image sensor according to claim 1 , further comprising insulating pillars around the columnar active pillars.

6. 2. The image sensor according to claim 1, wherein the gate-all-around transistor is a clip transistor that clips a voltage at a connection point between the logic chip and the pixel chip.

7. 2. The image sensor according to claim 1, wherein the gate-all-around transistor is formed by connecting two transistors in series, each of which has two portions of the columnar active pillar, one end of which is connected to the cathode of the avalanche photodiode, as channels, and each of the channels is surrounded by two planar gates of the two transistors.

8. (a) forming a stacked film having a first sacrificial layer, a gate film, and a second sacrificial layer on a substrate of a pixel chip having an avalanche photodiode formed on a surface thereof; a step (b) of forming a hole penetrating the stacked film, forming a gate oxide film on a sidewall of the formed hole, and then forming a columnar active pillar in the hole so as to be connected to the cathode of the avalanche photodiode; (c) exposing a portion of the active pillar by removing a portion of the gate oxide film exposed by removing the first sacrificial layer and the second sacrificial layer; (d) forming a diffusion layer in the exposed portion of the active pillar to form a vertical gate-all-around transistor having a channel made of a portion of the columnar active pillar, one end of which is connected to the cathode, and a planar gate surrounding the channel; A method for manufacturing an image sensor having the above structure.

9. 9. The method of manufacturing an image sensor according to claim 8, wherein step (a) forms the stacked film by depositing the first sacrificial layer, a first interlayer insulating film, a gate film, a second interlayer insulating film, the second sacrificial layer, and a third interlayer insulating film in this order.

10. 9. The method of manufacturing an image sensor according to claim 8, wherein in step (d), the source and drain of the gate-all-around transistor are formed by performing plasma doping or solid-phase diffusion on the exposed part of the active pillar.

11. The method further includes the step (e) of forming a trench through the film stack; In the step (c), the first sacrificial layer, the second sacrificial layer, and a portion of the gate oxide film are removed using the trench; 11. The method of claim 10, wherein in step (d), the source and the drain are formed by performing the plasma doping and the solid phase diffusion on a part of the channel using the trench.

12. 9. The method of claim 8, wherein in step (c), a pillar of insulating material is formed around the pillar-shaped channel before removing the first sacrificial layer and the second sacrificial layer.

13. In the step (a), the laminated film is formed, the laminated film having the first sacrificial layer, the second gate film, the second sacrificial layer, the first gate film, and a third sacrificial layer; In the step (c), three portions of the gate oxide film exposed by removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are removed to expose three portions of the active pillar; 9. The method for manufacturing an image sensor according to claim 8, wherein in the step (d), by forming the diffusion layer in the three exposed portions of the active pillar, two transistors are connected in series, each having two portions of the columnar active pillar as a channel, one end of which is connected to the cathode, and each channel is surrounded by two planar gates of the two transistors, thereby forming the vertical gate-all-around transistor.

Images