Semiconductor device, method of manufacturing semiconductor device, and electronic device

Abstract

To provide a semiconductor device of high quality and high performance.SOLUTION: The semiconductor element 10A includes a substrate 20, a conductive layer 30, a conductive layer 40, and an interconnect 50. The layer 30 is provided on the surface 20a part side of the substrate 20 and has a first part 30a and a second part 30b having a surface area larger than that of the part LA. The conductive layer 40 is provided on the side of the second portion 30b opposite to the substrate 20. The wiring 50 penetrates the substrate 20 and is connected to the conductor layer 40. The conductor layer 40 has a function of a connection conductor connected to the source electrode 82 of the transistor element 80, and has a function of an etching stopper when a via hole 61 for providing the wiring 50 is formed. By providing the conductive layer 40 on the second portion 30b having a relatively large surface area, the adhesion with the conductive layer 30 is enhanced. This suppresses peeling of the conductor layer 40 and conduction failure such as disconnection between the conductor layer 40 and the wiring 50.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] A known technique involves forming a metal film containing Ni or Al on the nitride semiconductor layer side of a substrate product including a substrate and a nitride semiconductor layer thereon, forming a via hole by etching from the substrate side of the substrate product to reach the metal film, and forming a conductive film in the via hole (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-17647 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device in which a conductor layer is provided on a semiconductor layer provided on a substrate and wiring is provided to penetrate the substrate and connect to the conductor layer, if the adhesion between the semiconductor layer and the conductor layer is insufficient, the conductor layer may peel off from the semiconductor layer, causing poor conductivity between the conductor layer and the wiring. Peeling of the conductor layer and poor conductivity with the wiring can lead to a deterioration in the quality and performance of the semiconductor device.

[0005] In one aspect, the present invention aims to realize a high-quality, high-performance semiconductor device. [Means for solving the problem]

[0006] In one aspect, a semiconductor device is provided that includes a substrate, a semiconductor layer provided on a first surface side of the substrate and having a first portion and a second portion having a surface area larger than that of the first portion, a conductor layer provided on the opposite side of the second portion from the substrate side, and wiring that penetrates the substrate and is connected to the conductor layer.

[0007] In another aspect, there is provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. [Effects of the Invention]

[0008] In one aspect, it becomes possible to realize a high-quality, high-performance semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1A to 1C are diagrams illustrating an example of a method for forming wiring in a semiconductor device. [Figure 2] 1A and 1B are diagrams illustrating a first configuration example of a semiconductor device according to a first embodiment. [Figure 3] 1A to 1C are diagrams (part 1) illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 1A to 1C are diagrams (part 2) illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] 4A and 4B are diagrams illustrating a second configuration example of the semiconductor device according to the first embodiment. [Figure 6] 10A and 10B are diagrams illustrating a third configuration example of the semiconductor device according to the first embodiment. [Figure 7] 10A and 10B are diagrams illustrating a fourth configuration example of the semiconductor device according to the first embodiment. [Figure 8] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 9] 10A to 10C are diagrams (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] 10A and 10B are diagrams (part 2) illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 11] 10A to 10C are views (part 3) illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 12]10A and 10B are diagrams (part 4) illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 13] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a third embodiment. [Figure 14] 10A to 10C are views (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 15] 10A and 10B are diagrams (part 2) illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 16] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a fourth embodiment. [Figure 17] 10A to 10C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 18] 10A to 10C are diagrams illustrating an example of a semiconductor package according to a fifth embodiment. [Figure 19] FIG. 10 is a diagram illustrating an example of a power factor correction circuit according to a sixth embodiment. [Figure 20] FIG. 13 is a diagram illustrating an example of a power supply device according to a seventh embodiment. [Figure 21] FIG. 13 is a diagram illustrating an example of an amplifier according to an eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Figure 1 is a diagram illustrating an example of a method for forming wiring in a semiconductor device. Figure 1(A) shows a schematic cross-sectional view of a main part of an example of a conductor layer forming step. Figure 1(B) shows a schematic cross-sectional view of a main part of an example of a via hole forming step. Figure 1(C) shows a schematic cross-sectional view of a main part of an example of a wiring forming step.

[0011] As an example, FIG. 1(A) shows a structure including a substrate 120 and a semiconductor layer 130 provided on one surface 120a of the substrate 120. Various materials are used for the substrate 120. For example, SiC (silicon carbide), Si (silicon), etc. are used for the substrate 120. Various semiconductor materials are used for the semiconductor layer 130. For example, a semiconductor or a compound semiconductor is used for the semiconductor layer 130. As shown in FIG. 1(A), a conductor layer 140 is provided on one surface 130a of the semiconductor layer 130. Various conductor materials are used for the conductor layer 140. For example, a metal such as Ni (nickel) or aluminum (Al) is used for the conductor layer 140.

[0012] 1(B), a via hole 160 is formed in the structure shown in FIG. 1(A) so as to penetrate the substrate 120 and the semiconductor layer 130 and reach the conductor layer 140. The via hole 160 is formed by etching the substrate 120 and the semiconductor layer 130 from the other surface 120b side of the substrate 120. The conductor layer 140 functions as a stop layer for this etching, i.e., an etching stopper. The conductor layer 140 is made of a material that is resistant to the etching used to form the via hole 160.

[0013] After the via hole 160 is formed, as shown in FIG. 1(C), the wiring 150 is formed in the via hole 160. The wiring 150 is provided so as to cover the inner surface of the via hole 160. The wiring 150 is connected to the conductor layer 140. The conductor layer 140 functions as an etching stopper and also as a connecting conductor connected to the wiring 150. A metal such as Au (gold) is used for the wiring 150. The wiring 150 is formed on the inner surface of the via hole 160 using, for example, a plating method. Note that the wiring 150 may be formed on the surface 120b side of the substrate 120, in addition to the inner surface of the via hole 160.

[0014] In a semiconductor device, for example, a method such as that shown in Figures 1(A) to 1(C) is used, in which a conductor layer 140 provided on the surface 120a side of a substrate 120 is drawn to the surface 120b side of the substrate 120 by wiring 150 that penetrates the semiconductor layer 130 and the substrate 120.

[0015] However, in the structure shown in FIG. 1(C) formed using the above method, peeling of the conductor layer 140 from the semiconductor layer 130 may occur, for example, between the conductor layer 140 and the semiconductor layer 130 as shown in part Q1 of FIG. 1(C).

[0016] For example, when metals are used for the conductor layer 140 and the wiring 150, relatively high stress may be generated in the metal due to heating during the manufacturing of the semiconductor device or heat generation during operation. The stress generated in the conductor layer 140 and the wiring 150 may cause swelling. Furthermore, the adhesion between the conductor layer 140 and the semiconductor layer 130, which use different materials, i.e., a conductor and a semiconductor, may be relatively weaker than the adhesion between the same materials.

[0017] Therefore, if the adhesion between the conductor layer 140 and the semiconductor layer 130 is insufficient, the connection therebetween may not be able to withstand the stress or swelling that occurs in the conductor layer 140 and the wiring 150, and the conductor layer 140 may peel off from the semiconductor layer 130. Peeling of the conductor layer 140 from the semiconductor layer 130 may cause poor conductivity between the conductor layer 140 and the wiring 150, such as a break in the wiring 150 connected to the conductor layer 140. Peeling of the conductor layer 140 and poor conductivity with the wiring 150 may lead to a deterioration in the quality and performance of the semiconductor device.

[0018] In view of the above, the configuration shown below as an embodiment is adopted to realize a high-quality, high-performance semiconductor device. [First embodiment] Fig. 2 is a diagram illustrating a first configuration example of the semiconductor device according to the first embodiment, which diagrammatically shows a cross-sectional view of a main part of an example of the semiconductor device.

[0019] The semiconductor device 1A shown in FIG. 2 includes a substrate 2, a semiconductor layer 3, a conductor layer 4, and wiring 5. A semiconductor layer 3 (including a first portion 3a and a second portion 3b) is provided on one surface 2a of the substrate 2. A conductor layer 4 is provided on the side of the semiconductor layer 3 opposite the substrate 2. The wiring 5 penetrates the substrate 2 and the semiconductor layer 3 and is connected to the conductor layer 4. In the semiconductor device 1A, various transistor elements are formed using the semiconductor layer 3 or the substrate 2. For example, a high electron mobility transistor (HEMT) may be formed using the semiconductor layer 3 or the substrate 2. Alternatively, a metal insulator semiconductor field effect transistor (MISFET) may be formed using the semiconductor layer 3 or the substrate 2. However, for ease of explanation, the focus here is on the region of the semiconductor device 1A where the wiring 5 is provided, and the transistor elements are not shown.

[0020] Various materials can be used for the substrate 2. For example, SiC is used for the substrate 2. Other materials such as Si, AlN (aluminum nitride), GaN (gallium nitride), and sapphire may also be used for the substrate 2. The substrate 2 may have a single layer structure made of one type of material, or may have a layered structure made of one or more types of materials.

[0021] The semiconductor layer 3 is provided on one surface 2a of the substrate 2. Various semiconductor materials can be used for the semiconductor layer 3. For example, a semiconductor or a compound semiconductor is used for the semiconductor layer 3. As an example, a nitride semiconductor such as GaN or AlGaN (aluminum gallium nitride) is used for the semiconductor layer 3.

[0022] The semiconductor layer 3 has a first portion 3a and a second portion 3b having a larger surface area than the first portion 3a. The second portion 3b may have irregularities on its surface. The second portion 3b may have larger or more irregularities than the surface of the first portion 3a. The second portion 3b may have a larger surface roughness than the surface roughness of the first portion 3a. For example, the second portion 3b is provided so that its surface has irregularities or surface roughness of a different size or number than the surface of the first portion 3a, and has a larger surface area than the first portion 3a.

[0023] As an example, the second portion 3b is provided in a recess 3aa formed in the semiconductor layer 3 or the first portion 3a thereof. The portion of the semiconductor layer 3 outside the second portion 3b, i.e., the portion on the side of the second portion 3b or the portion on the side and below the second portion 3b, may be considered to be the first portion 3a. The surface of the first portion 3a includes the surface of the first portion 3a opposite to the substrate 2 side (if a recess 3aa is formed, the inner surface of the recess 3aa may also be included). The surface of the second portion 3b includes the surface of the second portion 3b opposite to the substrate 2 side. The surface of the second portion 3b has a larger surface area than the surface of the first portion 3a.

[0024] The first portion 3a and the second portion 3b of the semiconductor layer 3 may be made of the same type of semiconductor material or different types of semiconductor material. The second portion 3b may be made of an n-type semiconductor doped with n-type impurities. The first portion 3a may have a single layer structure of one type of semiconductor material or a laminate structure of one or more types of semiconductor materials. The second portion 3b may have a single layer structure of one type of semiconductor material or a laminate structure of one or more types of semiconductor materials.

[0025] The conductor layer 4 is provided on the side of the second portion 3b of the semiconductor layer 3 opposite to the substrate 2 side. For example, the conductor layer 4 is provided so as to be in contact with the surface of the second portion 3b, i.e., the surface opposite to the substrate 2 side. Various conductor materials can be used for the conductor layer 4. For example, a metal is used for the conductor layer 4. As an example, Ni is used for the conductor layer 4. Other metals such as Au and Al may be used for the conductor layer 4 instead of or in addition to Ni. The conductor layer 4 may have a single-layer structure of one type of conductor material, or may have a laminated structure of one or more types of conductor materials.

[0026] The wiring 5 penetrates the substrate 2 and the semiconductor layer 3 and is connected to the conductor layer 4. The wiring 5 is formed in a via hole 6 that penetrates the substrate 2 and the semiconductor layer 3 and reaches the conductor layer 4. Various conductor materials can be used for the wiring 5. For example, a metal is used for the wiring 5. As an example, Au is used for the wiring 5. Other metals such as Ti (titanium) and Cu (copper) may be used for the wiring 5 instead of or in addition to Au. The wiring 5 may have a single-layer structure of one type of conductor material, or may have a laminated structure of one or more types of conductor materials. The wiring 5 may be formed on the surface 2b side of the substrate 2, in addition to the inner surface of the via hole 6.

[0027] The wiring 5 is connected to, for example, a GND potential. The conductor layer 4 is connected to an electrode (for example, a source electrode) of a transistor element (not shown), and can function as a connection conductor that connects the electrode to the wiring 5 that is at a GND potential.

[0028] In the semiconductor device 1A having the above configuration, the conductor layer 4 is provided in the second portion 3b of the semiconductor layer 3, which has a larger surface area than the first portion 3a. Therefore, the anchor effect of the second portion 3b, which has a relatively larger surface area, enhances the adhesion of the conductor layer 4 to the semiconductor layer 3 (its second portion 3b). This maintains the connection between the conductor layer 4 and the semiconductor layer 3 against stress or swelling that occurs in the conductor layer 4 and the wiring 5 due to heating during manufacturing of the semiconductor device 1A or heat generation during operation, and prevents the conductor layer 4 from peeling off from the semiconductor layer 3. By preventing the conductor layer 4 from peeling off from the semiconductor layer 3, poor electrical continuity between the conductor layer 4 and the wiring 5, such as breakage of the wiring 5 connected to the conductor layer 4, is prevented. The above configuration achieves a high-quality, high-performance semiconductor device 1A in which peeling of the conductor layer 4 and poor electrical continuity between the conductor layer 4 and the wiring 5 are prevented. Furthermore, the yield of the semiconductor device 1A is improved.

[0029] Next, a method for manufacturing the semiconductor device 1A having the above-described configuration will be described with reference to the following FIGS. 3 and 4 and the above-described FIG. 3 and 4 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 3(A) to 3(C) and 4(A) to 4(C) each show a schematic cross-sectional view of a main part of each step in the manufacturing of a semiconductor device.

[0030] 3(A), a semiconductor layer 3 is formed on one surface 2a of a substrate 2. The semiconductor layer 3 is formed by crystal growth using, for example, a metal organic chemical vapor deposition (MOCVD) method or the like.

[0031] After the semiconductor layer 3 is formed, a mask 7 having an opening 7a in a region where the second portion 3b is to be formed is formed, as shown in FIG. 3(B). The mask 7 is made of a material such as silicon nitride (SiN). After the mask 7 is formed, a portion of the semiconductor layer 3 exposed in the opening 7a is removed by etching to form the recess 3aa. In this example, the portion of the semiconductor layer 3 that remains after the recess 3aa is formed, i.e., the outside of the recess 3aa or the outside and inside of the recess 3aa, becomes the first portion 3a, which has a relatively small surface area.

[0032] After the recess 3aa is formed, a second portion 3b having a relatively large surface area is formed in the recess 3aa, as shown in Fig. 3(C). The second portion 3b is formed by further regrowing a predetermined semiconductor by MOCVD or the like in the recess 3aa formed in the semiconductor layer 3 grown by MOCVD or the like. The second portion 3b formed by regrowth in this manner is also called a "regrowth layer."

[0033] The surface of the second portion 3b formed by regrowth is more likely to be uneven and have a larger surface area than the surface of the first portion 3a. Also, by adjusting the regrowth conditions, such as the temperature, pressure, and amount of source gas supplied, it is possible to form the second portion 3b with a relatively large surface area. By forming the second portion 3b by regrowth, the second portion 3b with a larger surface area than the first portion 3a is formed.

[0034] For example, by forming the second portion 3b in this manner, the semiconductor layer 3 is formed having the first portion 3a and the second portion 3b having a larger surface area than the first portion 3a. After the second portion 3b is formed, the mask 7 is removed, for example, as shown in FIG. 4(A).

[0035] Next, as shown in Fig. 4(B), a conductor layer 4 is formed. The conductor layer 4 is formed on the surface of the second portion 3b of the semiconductor layer 3, which has a larger surface area than the first portion 3a. For example, a metal containing Ni is formed as the conductor layer 4 on the surface of the second portion 3b of the semiconductor layer 3 by a vapor deposition method or the like. By being formed on the surface of the second portion 3b, which has a larger surface area than the first portion 3a, the conductor layer 4 is connected to the semiconductor layer 3 (its second portion 3b) with relatively high adhesive strength due to an anchor effect.

[0036] After the formation of the conductor layer 4, a via hole 6 is formed as shown in FIG. 4(C). The via hole 6 is formed so as to penetrate the substrate 2 and the semiconductor layer 3 and reach the conductor layer 4. The via hole 6 is formed by etching the substrate 2 and the semiconductor layer 3 from the other surface 2b side of the substrate 2. The conductor layer 4 functions as an etching stopper during this etching. The conductor layer 4 is made of a material that is resistant to the etching used when forming the via hole 6.

[0037] After the via hole 6 is formed, the wiring 5 is formed in the via hole 6. This results in the state shown in FIG. 2 above. As shown in FIG. 2, the wiring 5 is provided so as to cover the inner surface of the via hole 6. The wiring 5 is connected to the conductor layer 4 at the bottom of the via hole 6. The conductor layer 4 functions as an etching stopper as well as a connecting conductor connected to the wiring 5. For example, a metal containing Au is formed on the inner surface of the via hole 6 by plating or the like to form the wiring 5. Note that the wiring 5 may be formed on the surface 2b side of the substrate 2, in addition to the inner surface of the via hole 6.

[0038] For example, the semiconductor device 1A (FIG. 2) is manufactured using the methods shown in FIGS. 3(A) to 3(C) and 4(A) to 4(C). It is also possible to omit the formation of the recess 3aa as shown in Fig. 3(B) and to form a regrown layer to become the second portion 3b in the semiconductor layer 3 grown as shown in Fig. 3(A) according to the example of Fig. 3(C). This makes it possible to reduce the number of steps required to form the second portion 3b of the semiconductor layer 3.

[0039] Furthermore, after forming the second portion 3b by regrowth as shown in Fig. 3(C), it is also possible to omit the removal of the mask 7 made of SiN or the like as shown in Fig. 4(A). In this way, it is also possible to omit the removal of the mask 7 and, with the mask 7 remaining, form the conductor layer 4, the via hole 6, and the wiring 5 according to the examples of Figs. 4(B), 4(C), and 2. The remaining mask 7 can function as a passivation film that protects the surface of the first portion 3a of the semiconductor layer 3.

[0040] 3(C), n-type impurities may be introduced to re-grow the second portion 3b, thereby allowing the second portion 3b to function as a connecting conductor electrically connected to the conductor layer 4 and the wiring 5.

[0041] Fig. 5 is a diagram illustrating a second configuration example of the semiconductor device according to the first embodiment, which diagrammatically shows a cross-sectional view of a main part of an example of the semiconductor device. 5, a transistor element such as a HEMT is formed using a semiconductor layer 3 or a substrate 2. However, for the sake of convenience, attention is focused on the region of the semiconductor device 1B where the wiring 5 is provided, and the transistor element is not shown.

[0042] The semiconductor device 1B shown in FIG. 5 has a configuration in which the second portion 3b of the semiconductor layer 3 is n-type, and the wiring 5 is provided so as to penetrate the substrate 2 and reach the second portion 3b. In the semiconductor device 1B, the wiring 5 is provided so as not to penetrate the second portion 3b and not to reach the conductor layer 4 provided on the surface thereof. In the semiconductor device 1B, the wiring 5 is directly connected to the n-type second portion 3b. The wiring 5 is electrically connected to the conductor layer 4 via the n-type second portion 3b. The semiconductor device 1B differs from the semiconductor device 1A described above in that it has such a configuration.

[0043] In the manufacture of the semiconductor device 1B, for example, after the formation of the semiconductor layer 3 and recess 3aa as shown in FIGS. 3A and 3B, a semiconductor doped with n-type impurities is regrown in the step of FIG. 3C to form the n-type second portion 3b. The n-type impurity is selected based on the type of semiconductor used in the second portion 3b. For example, Si, Ge (germanium), etc. may be used as the n-type impurity. Depending on the type of semiconductor used in the second portion 3b, P (phosphorus), As (arsenic), etc. may also be used as the n-type impurity.

[0044] Then, for example, through the step of Fig. 4(A), or by omitting the step of Fig. 4(A), a conductor layer 4 is formed on the surface of the n-type second portion 3b according to the example of the step of Fig. 4(B). Thereafter, in the manufacture of the semiconductor device 1B, a via hole 6 is formed according to the example of the step of Fig. 4(C), which penetrates the substrate 2 to reach the second portion 3b but does not reach the conductor layer 4. Then, a wiring 5 is formed in the formed via hole 6, thereby obtaining the state shown in Fig. 5. Note that the wiring 5 may be formed on the surface 2b side of the substrate 2, in addition to the inner surface of the via hole 6.

[0045] For example, such a method is used to manufacture a semiconductor device 1B as shown in FIG. In semiconductor device 1B, wiring 5 does not penetrate second portion 3b. Therefore, in semiconductor device 1B, the contact area between the surface of second portion 3b and conductor layer 4 is larger than when wiring 5 penetrates second portion 3b. Therefore, in semiconductor device 1B, adhesion of conductor layer 4 to semiconductor layer 3 is further improved. This more effectively prevents detachment of conductor layer 4 from semiconductor layer 3, and more effectively prevents poor conductivity between conductor layer 4 and wiring 5, such as disconnection of wiring 5 connected to conductor layer 4.

[0046] Furthermore, in the semiconductor device 1B, by making the second portion 3b n-type, etching can be stopped at the second portion 3b when forming the via hole 6. Therefore, compared to when etching is performed down to the conductor layer 4, the etching depth can be made shallower and the etching time can be shortened.

[0047] Furthermore, in the semiconductor device 1B, etching when forming the via hole 6 is stopped at the second portion 3b. Therefore, it is not necessary to use a material that is resistant to the etching for the conductor layer 4. Therefore, in the semiconductor device 1B, various conductive conductor materials can be used for the conductor layer 4, not limited to metals such as Ni.

[0048] Furthermore, if the second portion 3b is n-type, for example, when attempting to form a via hole 6 reaching the conductor layer 4 by etching, even if the etching is stopped at the position of the second portion 3b, electrical connection between the wiring 5 and the conductor layer 4 is possible. That is, the wiring 5 formed in the via hole 6 that is stopped at the position of the second portion 3b can be electrically connected to the conductor layer 4 on the surface of the second portion 3b via the n-type second portion 3b. Therefore, if the second portion 3b is n-type, restrictions on the position at which etching is stopped when forming the via hole 6 can be relaxed.

[0049] 6A and 6B are diagrams illustrating a third configuration example of the semiconductor device according to the first embodiment. Here, the third configuration example will be described together with its manufacturing method. FIG. 6A shows a schematic cross-sectional view of a main part of an example of a semiconductor layer forming process. FIG. 6B shows a schematic cross-sectional view of a main part of an example of a conductor layer forming process. FIG. 6C shows a schematic cross-sectional view of a main part of an example of a wiring forming process.

[0050] The formation of the second portion 3b of the semiconductor layer 3, which has a larger surface area than the first portion 3a, is not limited to the above-described method of semiconductor regrowth. For example, after forming the semiconductor layer 3 as shown in Fig. 3(A) above, a mask 7 having openings 7a is formed in the region where the second portions 3b are to be formed, and a portion of the surface of the semiconductor layer 3 exposed in the openings 7a is processed to roughen the surface, as shown in Fig. 6(A). The processing to roughen the portion of the surface of the semiconductor layer 3 can be performed by dry etching, wet etching, plasma treatment, or the like. The portion of the semiconductor layer 3 that is not processed in this way, i.e., the portion outside the processed portion, becomes the first portion 3a.

[0051] In this way, a method of processing the semiconductor layer 3 to roughen a portion of the surface thereof may be used to form a second portion 3b as shown in FIG. 6(A), i.e., a second portion 3b having a larger surface area than the first portion 3a.

[0052] After the second portion 3b is formed, a conductor layer 4 is formed on the surface of the second portion 3b, which has a surface area larger than that of the first portion 3a, as shown in Fig. 6(B). Then, as shown in Fig. 6(C), a via hole 6 is formed that penetrates the substrate 2 and the semiconductor layer 3 to reach the conductor layer 4, and a wiring 5 is formed in the via hole 6. The wiring 5 may be formed on the surface 2b side of the substrate 2, as well as on the inner surface of the via hole 6.

[0053] This results in the manufacture of a semiconductor device 1C having the configuration shown in Fig. 6(C). In the semiconductor device 1C, a semiconductor layer 3 or a substrate 2 is used to form a transistor element such as a HEMT. However, for the sake of convenience, attention is focused on the region of the semiconductor device 1C where the wiring 5 is provided, and the transistor element is not shown.

[0054] 6(C), the conductor layer 4 is provided on the second portion 3b formed by processing the semiconductor layer 3 to roughen a portion of the surface thereof, thereby improving the adhesion of the conductor layer 4 to the semiconductor layer 3. The improved adhesion of the conductor layer 4 prevents the conductor layer 4 from peeling off from the semiconductor layer 3, and prevents poor conduction between the conductor layer 4 and the wiring 5, such as breakage of the wiring 5 connected to the conductor layer 4.

[0055] In the semiconductor device 1C, n-type impurities may be introduced into the second portion 3b of the semiconductor layer 3 before or after the above-described processing. When n-type impurities are introduced into the second portion 3b, the via hole 6 and the wiring 5 do not necessarily need to be formed so as to penetrate the substrate 2 and the semiconductor layer 3 and reach the conductor layer 4. In other words, a via hole 6 may be formed that penetrates the substrate 2 and reaches the n-type second portion 3b of the semiconductor layer 3 but does not reach the conductor layer 4, and the wiring 5 may be formed in the via hole 6. In this case, the wiring 5 is electrically connected to the conductor layer 4 via the n-type second portion 3b.

[0056] 7A and 7B are diagrams illustrating a fourth configuration example of the semiconductor device according to the first embodiment. Here, the fourth configuration example will be described together with its manufacturing method. FIG. 7A shows a schematic cross-sectional view of a main part of an example of a semiconductor layer forming process. FIG. 7B shows a schematic cross-sectional view of a main part of an example of a conductor layer forming process. FIG. 7C shows a schematic cross-sectional view of a main part of an example of a wiring forming process.

[0057] The second portion 3b of the semiconductor layer 3, which has a larger surface area than the first portion 3a, may be formed by patterning so as to have a predetermined pattern shape having projections and depressions. For example, after forming the semiconductor layer 3 as shown in FIG. 3A, a mask 7 having openings 7a is formed in the region where the recesses in the second portion 3b are to be formed, as shown in FIG. 7A. The openings 7a of the mask 7 can have various patterns, such as a line shape, a dot shape, or a matrix shape. After forming the mask 7 having the openings 7a in a predetermined pattern, a portion of the surface of the semiconductor layer 3 exposed in the openings 7a is removed by etching and patterned. The portion of the semiconductor layer 3 that is not patterned, i.e., the portion outside the patterned portion, becomes the first portion 3a.

[0058] In this way, a method of patterning a portion of the surface of the semiconductor layer 3 by etching may be used to form the second portion 3b as shown in Figure 7(A), i.e., the second portion 3b having a larger surface area than the first portion 3a.

[0059] After the second portion 3b is formed, a conductor layer 4 is formed on the surface of the second portion 3b, which has a surface area larger than that of the first portion 3a, as shown in Fig. 7(B). Then, as shown in Fig. 7(C), a via hole 6 is formed that penetrates the substrate 2 and the semiconductor layer 3 to reach the conductor layer 4, and a wiring 5 is formed in the via hole 6. The wiring 5 may be formed on the surface 2b side of the substrate 2, as well as on the inner surface of the via hole 6.

[0060] 7(C) is manufactured. In the semiconductor device 1D, a transistor element such as a HEMT is formed using the semiconductor layer 3 or the substrate 2. However, for the sake of convenience, attention is focused on the region of the semiconductor device 1D where the wiring 5 is provided, and the transistor element is not shown.

[0061] In the semiconductor device 1D, the conductor layer 4 is provided on the second portion 3b formed by patterning a portion of the surface of the semiconductor layer 3, thereby improving the adhesion of the conductor layer 4 to the semiconductor layer 3. The improved adhesion of the conductor layer 4 prevents the conductor layer 4 from peeling off from the semiconductor layer 3, and prevents poor conductivity between the conductor layer 4 and the wiring 5, such as breakage of the wiring 5 connected to the conductor layer 4.

[0062] In the semiconductor device 1D, n-type impurities may be introduced into the second portion 3b of the semiconductor layer 3 before or after the above-described patterning. When n-type impurities are introduced into the second portion 3b, the via hole 6 and the wiring 5 do not necessarily need to be formed so as to penetrate the substrate 2 and the semiconductor layer 3 and reach the conductor layer 4. In other words, a via hole 6 may be formed that penetrates the substrate 2 and reaches the n-type second portion 3b of the semiconductor layer 3 but does not reach the conductor layer 4, and the wiring 5 may be formed in the via hole 6. In this case, the wiring 5 is electrically connected to the conductor layer 4 via the n-type second portion 3b.

[0063] [Second embodiment] Fig. 8 is a diagram illustrating an example of a semiconductor device according to the second embodiment, which is a schematic cross-sectional view of a main part of the example of the semiconductor device.

[0064] 8 is an example of a HEMT, and includes a substrate 20, a semiconductor layer 30, a conductor layer 40, wiring 50, and a transistor element 80. For example, a SiC substrate is used for the substrate 20. Alternatively, a Si substrate, an AlN substrate, a GaN substrate, a sapphire substrate, a diamond substrate, or the like may be used for the substrate 20. The substrate 20 may have a single-layer structure of one type of substrate, or may have a stacked structure of one or more types of substrate.

[0065] The semiconductor layer 30 is provided on one surface 20a of the substrate 20. A nitride semiconductor is used for the semiconductor layer 30. The semiconductor layer 30 includes a channel layer 31 and a barrier layer 32. The channel layer 31 is also called an "electron transit layer." The barrier layer 32 is also called an "electron supply layer."

[0066] The channel layer 31 is made of a nitride semiconductor such as GaN. The barrier layer 32 is made of a nitride semiconductor such as AlGaN. The barrier layer 32 is made of a nitride semiconductor having a larger band gap than the channel layer 31. In the semiconductor layer 30, a two-dimensional electron gas (2DEG) region is generated in the channel layer 31 due to spontaneous polarization of the barrier layer 32 and piezoelectric polarization generated in the barrier layer 32 due to strain caused by the difference in lattice constant between the barrier layer 32 and the channel layer 31.

[0067] Although not shown, a layer of AlN or the like may be provided between the substrate 20 and the channel layer 31 as an initial layer, a layer of AlGaN or the like may be provided as a buffer layer, or a layer of GaN or the like doped with Fe (iron). In addition, a layer of AlN, AlGaN, or the like may be provided between the substrate 20 and the channel layer 31 as a barrier layer (back barrier layer) for realizing a quantum well (quantum confinement) structure. A layer of AlN, AlGaN, or the like may be provided between the channel layer 31 and the barrier layer 32 as a spacer layer. A layer of GaN or the like may be provided on the barrier layer 32 as a cap layer. In addition to the channel layer 31 and the barrier layer 32, the semiconductor layer 30 may include one or more of the initial layer, buffer layer, back barrier layer, spacer layer, cap layer, etc.

[0068] The semiconductor layer 30 has a first portion 30a and a second portion 30b having a surface area larger than that of the first portion 30a. The second portion 30b may have an uneven surface. The second portion 30b is provided in a recess 33 formed in the semiconductor layer 30. The recess 33 is formed, for example, to penetrate the barrier layer 32 and reach the channel layer 31. A nitride semiconductor such as GaN is used for the second portion 30b. A nitride semiconductor such as GaN doped with n-type impurities (an n-type nitride semiconductor) may also be used for the second portion 30b.

[0069] The conductor layer 40 is provided on the side of the second portion 30b of the semiconductor layer 30 opposite to the substrate 20 side. For example, the conductor layer 40 is provided so as to be in contact with the surface of the second portion 30b, i.e., the surface opposite to the substrate 20 side. For example, the conductor layer 40 is made of a metal such as Ni or Au. The conductor layer 40 may have a single-layer structure of one type of metal, or may have a laminated structure of one or more types of metal.

[0070] A metal layer 60 is provided on the other surface 20b side of the substrate 20. The wiring 50 penetrates the metal layer 60, the substrate 20, and the semiconductor layer 30 to reach the conductor layer 40 and is connected to the conductor layer 40. In the example of FIG. 8 , the wiring 50 penetrates the metal layer 60, the substrate 20, and the channel layer 31 and the second portion 30b of the semiconductor layer 30, and is connected to the conductor layer 40. The wiring 50 is provided in a via hole 61 formed to penetrate the metal layer 60, the substrate 20, and the semiconductor layer 30.

[0071] The metal layer 60 is an etching mask used when forming via holes 61 in the substrate 20 and the semiconductor layer 30 by etching. The metal layer 60 is made of a material that is resistant to the etching used when forming the via holes 61. Ni is used for the metal layer 60. Other metals such as Au and Cu may be used for the metal layer 60 instead of or in addition to Ni. The metal layer 60 may have a single-layer structure of one type of conductive material, or may have a stacked structure of one or more types of conductive materials. Furthermore, the conductor layer 40 functions as an etching stopper when forming the via holes 61 by etching using the metal layer 60 as an etching mask, and also functions as a connecting conductor that is connected to the wiring 50 formed in the via holes 61.

[0072] The wiring 50 includes a seed layer 51 and a wiring layer 52. For example, the seed layer 51 includes a metal such as Ti or Au. The wiring layer 52 includes a metal such as Au. The seed layer 51 and the wiring layer 52 may each have a single-layer structure of one type of metal, or may have a stacked structure of one or more types of metal.

[0073] The transistor element 80 includes a gate electrode 81, a source electrode 82, and a drain electrode 83 provided on a surface 30d of the semiconductor layer 30 opposite to the substrate 20. The gate electrode 81 is provided between the source electrode 82 and the drain electrode 83. To achieve a high breakdown voltage, the gate electrode 81 may be arranged asymmetrically, that is, closer to the source electrode 82 than to the drain electrode 83.

[0074] The gate electrode 81 is made of a metal such as Ni or Au. The gate electrode 81 is provided to function as, for example, a Schottky electrode. Although not shown here, the gate electrode 81 may be provided on the surface 30d side of the semiconductor layer 30 via a gate insulating film, thereby forming an MIS gate structure. The gate insulating film may be made of SiN, SiO (silicon oxide), AlO (aluminum oxide), or the like.

[0075] The source electrode 82 and the drain electrode 83 are made of a metal such as Ti or Al. The source electrode 82 and the drain electrode 83 are provided to function as ohmic electrodes. Although not shown here, the source electrode 82 and the drain electrode 83 may be provided in recesses formed on the surface 30d side of the semiconductor layer 30. In this way, the distance between the source electrode 82 and the drain electrode 83 and the 2DEG region generated in the channel layer 31 is shortened, and the ohmic resistance can be reduced. Furthermore, the source electrode 82 and the drain electrode 83 may be provided on a contact layer made of an n-type nitride semiconductor regrown in the recesses formed on the surface 30d side of the semiconductor layer 30.

[0076] When the semiconductor device 10A is in operation, a voltage relatively high with respect to the potential of the source electrode 82 is applied to the drain electrode 83, and a predetermined voltage is applied to the gate electrode 81. The electric field effect caused by the voltage applied to the gate electrode 81 controls the amount of charge passing through the 2DEG region below the gate electrode 81 between the source electrode 82 and the drain electrode 83, thereby controlling the drain current that serves as the output.

[0077] A passivation film 71 is provided on the surface 30d of the semiconductor layer 30 on which the conductor layer 40 and the gate electrode 81, source electrode 82, and drain electrode 83 of the transistor element 80 are provided. An insulating film 72 is provided so as to be stacked on the passivation film 71. The passivation film 71 and the insulating film 72 are made of an insulating material such as SiN.

[0078] The insulating film 72 has an opening 72b and an opening 72c that connect from its surface 72a to the conductor layer 40 and the source electrode 82, respectively. Connection wiring 90 made of a metal such as Ti or Au is provided on the surface 72a and in the openings 72b and 72c. The conductor layer 40 and the source electrode 82 are connected by the connection wiring 90. The source electrode 82 connected to the conductor layer 40 is also simply referred to as an "electrode."

[0079] In this manner, the source electrode 82 of the transistor element 80 is connected to the conductor layer 40 through the connection wiring 90. The conductor layer 40 is connected to the wiring 50. The wiring 50 penetrates the semiconductor layer 30 and the substrate 20 and extends to the surface 20b side of the substrate 20. The wiring 50 is connected to, for example, a GND potential. Therefore, in the semiconductor device 10A, the source electrode 82 is connected to GND through the connection wiring 90, the conductor layer 40, and the wiring 50.

[0080] In the semiconductor device 10A, by adopting such a configuration, the source inductance is reduced compared to when the source electrode 82 is connected to GND by a wire or the like on the side where the source electrode 82 is provided. In other words, in order to reduce the source inductance, the semiconductor device 10A adopts a configuration in which the source electrode 82 is drawn out to the surface 20b side of the substrate 20 through the connection wiring 90, the conductor layer 40, and the wiring 50 and connected to GND.

[0081] In the semiconductor device 10A, the conductor layer 40, which serves as an etching stopper when forming the via hole 61 and is part of the connection conductor that connects the source electrode 82 to GND, is provided in the second portion 30b of the semiconductor layer 30, which has a larger surface area than the first portion 30a. Therefore, the anchor effect of the second portion 30b, which has a relatively larger surface area, enhances the adhesion of the conductor layer 40 to the semiconductor layer 30 (its second portion 30b). This maintains the connection between the conductor layer 40 and the semiconductor layer 30 against stress or swelling that occurs in the conductor layer 40 and the wiring 50 due to heating during manufacturing of the semiconductor device 10A or heat generation during operation, and prevents the conductor layer 40 from peeling off from the semiconductor layer 30. By preventing the conductor layer 40 from peeling off from the semiconductor layer 30, poor conductivity between the conductor layer 40 and the wiring 50, such as disconnection of the wiring 50 connected to the conductor layer 40, is reduced. The above configuration realizes a high-quality, high-performance semiconductor device 10A, i.e., a HEMT, that suppresses peeling of the conductor layer 40 and poor electrical continuity with the wiring 50. Also, the yield of the semiconductor device 10A is improved.

[0082] Next, a method for manufacturing the semiconductor device 10A having the above configuration will be described. 9 to 12 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. Figures 9(A) to 9(C), 10(A) to 10(C), 11(A) to 11(C), 12(A) and 12(B) each show a schematic cross-sectional view of a main part of each step in the manufacturing of a semiconductor device.

[0083] 9(A), a semiconductor layer 30 is formed on one surface 20a of a substrate 20. The semiconductor layer 30 is formed by crystal growth using an MOCVD method or the like. For example, a channel layer 31 made of GaN or the like is formed on the surface 20a of the substrate 20. A barrier layer 32 made of AlGaN or the like is formed on the side of the formed channel layer 31 opposite to the substrate 20 side. Here, an example is shown in which the semiconductor layer 30 is formed including two layers, the channel layer 31 and the barrier layer 32; however, the semiconductor layer 30 may further include other layers such as the initial layer, buffer layer, back barrier layer, spacer layer, and cap layer as described above.

[0084] After the semiconductor layer 30 is formed, an inter-element isolation region (not shown) that defines the region where the transistor element 80 is to be formed is formed by ion implantation of Ar (argon) or the like. 9(B), a mask 70 having openings 70a in regions where the second portions 30b of the semiconductor layer 30 are to be formed is formed. For example, SiN is used for the mask 70. For example, SiN is formed on the surface 30d of the semiconductor layer 30 using plasma CVD or thermal CVD, and the SiN in the regions where the second portions 30b are to be formed is removed by etching using an F (fluorine)-based gas. This forms a SiN mask 70 having openings 70a in regions where the second portions 30b are to be formed.

[0085] After the mask 70 is formed, as shown in FIG. 9C , a portion of the semiconductor layer 30 exposed in the opening 70a is removed by etching, thereby forming a recess 33. For example, the portion of the semiconductor layer 30 exposed in the opening 70a is removed by etching using a Cl (chlorine)-based gas. As an example, the recess 33 is formed to a depth that penetrates the barrier layer 32 of the semiconductor layer 30 and reaches the channel layer 31. The portion of the semiconductor layer 30 that remains after the recess 33 is formed, i.e., the outside of the recess 33 or the outside and inside of the recess 33, becomes a first portion 30a with a relatively small surface area.

[0086] As will be described later, the second portion 30b is formed in the recess 33 by regrowth. If the second portion 30b can be formed by regrowth, the depth of the recess 33 is not limited to a depth that penetrates the barrier layer 32 and reaches the channel layer 31. Furthermore, if the second portion 30b can be formed by regrowth directly on the surface 30d of the semiconductor layer 30 formed by crystal growth as shown in FIG. 9A, according to an example that will be described later, the step of forming the recess 33 as shown in FIGS. 9B and 9C can be omitted. However, for convenience, the case where the recess 33 is formed to a depth that reaches the channel layer 31 will be described here as an example.

[0087] After the recess 33 is formed, a second portion 30b having a relatively large surface area is formed in the recess 33, as shown in FIG. 10(A). In this example, the second portion 30b is formed by further regrowing a predetermined semiconductor by MOCVD or the like in the recess 33 formed in the semiconductor layer 30 grown by MOCVD or the like. For example, a nitride semiconductor such as GaN is regrown in the recess 33 as the second portion 30b. An n-type impurity may be introduced into the nitride semiconductor such as GaN regrown in the recess 33. That is, a nitride semiconductor such as GaN or a nitride semiconductor such as GaN containing n-type impurities (n-type nitride semiconductor) is formed in the recess 33 of the semiconductor layer 30 as the second portion 30b having a relatively large surface area.

[0088] The surface of the second portion 30b formed by regrowth is more likely to be uneven and have a larger surface area than the surface of the first portion 30a. Also, by adjusting the regrowth conditions, such as the temperature, pressure, and amount of source gas supplied, it is possible to form the second portion 30b with a relatively large surface area. By forming the second portion 30b by regrowth, the second portion 30b with a larger surface area than the first portion 30a is formed.

[0089] After the second portion 30b is formed by regrowth, the mask 70 is removed, for example, as shown in FIG. 10(B). For example, hydrofluoric acid or the like is used to remove the SiN mask 70. It is also possible to leave the mask 70 as it is and use it as a passivation film 71. However, for convenience, the case where the mask 70 is removed will be described here as an example.

[0090] After removing the mask 70, the source electrode 82 and the drain electrode 83 are formed as shown in Fig. 10(C). For example, Ti and Al are formed in this order on the surface 30d side of the semiconductor layer 30 by vapor deposition, and then heat treatment is performed to establish ohmic contact. As a result, the source electrode 82 and the drain electrode 83 that function as ohmic electrodes are formed.

[0091] Although not shown here, before forming the source electrode 82 and the drain electrode 83, recesses may be formed in advance in the semiconductor layer 30 in the regions where the electrodes are to be formed, and the source electrode 82 and the drain electrode 83 may be formed in the recesses. In this way, the distance between the source electrode 82 and the drain electrode 83 and the 2DEG region generated in the channel layer 31 is shortened, and the ohmic resistance may be reduced. Alternatively, a contact layer made of an n-type nitride semiconductor may be formed in the recesses formed in advance, and the source electrode 82 and the drain electrode 83 may be formed thereon.

[0092] After the source electrode 82 and the drain electrode 83 are formed, the conductor layer 40 is formed as shown in FIG. 11(A). The conductor layer 40 is formed on the surface of the second portion 30b, which has a relatively large surface area and is formed by regrowth in the recess 33 of the semiconductor layer 30. For example, Ni and Au are sequentially formed by vapor deposition to form the conductor layer 40. In this case, the Ni formed on the lower layer side of the conductor layer 40 is formed as a material that is resistant to etching that occurs when a via hole 61 is formed as described below. The Au formed on the upper layer side of the conductor layer 40 is formed as a material that suppresses a decrease in electrical conductivity between the conductor layer 40 and the connection wiring 90, which is formed as described below. The conductor layer 40 is formed on the surface of the second portion 30b, which has a larger surface area than the first portion 30a, and is thereby connected to the semiconductor layer 30 (the second portion 30b) with relatively high adhesive strength due to an anchor effect.

[0093] 11(A), after the conductor layer 40 is formed, a passivation film 71 is formed. For example, SiN is used for the passivation film 71. For example, SiN is formed on the surface 30d side of the semiconductor layer 30 using a plasma CVD method or a thermal CVD method, and the SiN passivation film 71 is formed. Note that the passivation film 71 may be formed before the conductor layer 40 is formed.

[0094] 11(B), after the formation of the conductor layer 40 and the passivation film 71, a gate electrode 81 is formed. For example, first, a portion of the passivation film 71 in a region where the gate electrode 81 is to be formed is removed by etching using an F-based gas, and an opening 71a that leads to the semiconductor layer 30 is formed. Then, Ni and Au are sequentially formed by vapor deposition in the formed opening 71a, to form the gate electrode 81. In this way, a transistor element 80 is formed, which includes the gate electrode 81, a source electrode 82, and a drain electrode 83 provided on the surface 30d side of the semiconductor layer 30.

[0095] When the material used for the conductor layer 40 is the same as the material used for the gate electrode 81, the conductor layer 40 may be formed simultaneously with the formation of the gate electrode 81. In this case, for example, after the source electrode 82, the drain electrode 83, and the passivation film 71 are formed, openings are formed in the region where the gate electrode 81 is to be formed and in the region where the conductor layer 40 is to be formed. Then, Ni, Au, or the like is formed in the formed openings by vapor deposition, thereby simultaneously forming the gate electrode 81 and the conductor layer 40.

[0096] After the gate electrode 81 is formed, an insulating film 72 and a connection wiring 90 are formed, as shown in FIG. 11(C). For example, SiN is used for the insulating film 72. For example, SiN is first formed on the entire surface using plasma CVD or thermal CVD, to form the insulating film 72 that covers the gate electrode 81, the source electrode 82, the drain electrode 83, the conductor layer 40, and the passivation film 71. Next, openings 72b and 72c that lead to the conductor layer 40 and the source electrode 82, respectively, are formed from the surface 72a of the formed insulating film 72 by etching using an F-based gas. Then, a metal such as Ti or Au is formed on the surface 72a and in the openings 72b and 72c using plating, sputtering, or both, to form the connection wiring 90. As a result, the conductor layer 40 and the source electrode 82 are connected by the connection wiring 90.

[0097] After the insulating film 72 and the connection wiring 90 are formed, as shown in FIG. 12(A), a metal layer 60 having an opening 60a in a region corresponding to the second portion 30b of the semiconductor layer 30 and the conductor layer 40 thereon, i.e., a region where a via hole 61 will be formed, is formed on the surface 20b of the substrate 20. The metal layer 60 functions as an etching mask when forming the via hole 61 as described below. The metal layer 60 is made of a material that is resistant to the etching used to form the via hole 61. For example, Ni is used for the metal layer 60. When forming the via hole 61, the metal layer 60 is exposed to etching for a relatively long period of time. Therefore, it is preferable that the metal layer 60 be formed to a thickness that will not be lost by the etching used to form the via hole 61, for example, a thickness of 1 μm or more. For example, the metal layer 60 is formed by forming Ni to a predetermined thickness by plating.

[0098] After the metal layer 60 is formed, a via hole 61 is formed as shown in FIG. 12(B). That is, using the metal layer 60 as an etching mask, the substrate 20 exposed through the opening 60a and the semiconductor layer 30 are etched, thereby forming the via hole 61 reaching the conductor layer 40. When the substrate 20 is made of a Si-based semiconductor material such as SiC, an F-based gas is used for etching the via hole 61. As the F-based gas, for example, a mixed gas of SF6 (sulfur hexafluoride) and O2 (oxygen) is used. Note that, in forming the via hole 61, a Cl-based gas may be used for etching the semiconductor layer 30 made of a nitride semiconductor. Using the metal layer 60 with the opening 60a as an etching mask, etching is performed using a predetermined gas. The etching is stopped at the position of the conductor layer 40. As a result, the via hole 61 is formed, penetrating the substrate 20 and the semiconductor layer 30 and reaching the conductor layer 40.

[0099] After the via hole 61 is formed, the wiring 50 is formed, thereby obtaining the state shown in FIG. 8 above. When forming the wiring 50, first, a seed layer 51 is formed. For example, Ti and Au are formed in this order by a sputtering method to form the seed layer 51. Next, a wiring layer 52 is formed on the formed seed layer 51. For example, Au is formed by a plating method to form the wiring layer 52. In this way, the wiring 50 including the seed layer 51 and the wiring layer 52 is formed. The wiring 50 is formed so as to be connected to the conductor layer 40 at the bottom of the via hole 61. The wiring 50 may be formed on the inner surface of the via hole 61, or on a metal layer 60 provided on the surface 20b side of the substrate 20.

[0100] Through the steps described above, the semiconductor device 10A having the configuration shown in FIG. 8 is manufactured. In the semiconductor device 10A, the conductor layer 40 is provided in the second portion 30b of the semiconductor layer 30, which has a larger surface area than the first portion 30a. Therefore, the anchor effect enhances the adhesion of the conductor layer 40 to the semiconductor layer 30. This prevents the conductor layer 40 from peeling off from the semiconductor layer 30 during manufacturing and operation of the semiconductor device 10A, and prevents electrical continuity defects such as disconnections between the conductor layer 40 and the wiring 50. Therefore, a high-quality, high-performance semiconductor device 10A, i.e., a HEMT, is realized. Furthermore, the yield of the semiconductor device 10A is improved.

[0101] [Third embodiment] Fig. 13 is a diagram illustrating an example of a semiconductor device according to the third embodiment, which is a schematic cross-sectional view of a main part of the example of the semiconductor device.

[0102] The semiconductor device 10B shown in Fig. 13 is an example of a HEMT. The semiconductor device 10B has a configuration in which a third portion 30c having a larger surface area than the first portion 30a is provided in a region of the semiconductor layer 30 where the source electrode 82 and the drain electrode 83 of the transistor element 80 are provided. The third portion 30c contains n-type impurities. The semiconductor device 10B differs from the semiconductor device 10A described in the second embodiment in that it has such a configuration.

[0103] The third portion 30c of the semiconductor layer 30 may have an uneven surface. The third portion 30c is provided in a recess 33 formed in the semiconductor layer 30. The recess 33 is formed, for example, to penetrate the barrier layer 32 and reach the channel layer 31. A nitride semiconductor such as GaN is used for the third portion 30c. A nitride semiconductor such as GaN doped with n-type impurities (an n-type nitride semiconductor) is used for the third portion 30c.

[0104] The third portion 30c functions as a contact layer that reduces the contact resistance between the source electrode 82 and the drain electrode 83 and the semiconductor layer 30. By providing the source electrode 82 and the drain electrode 83 in the third portion 30c, which has a relatively large surface area, the anchor effect of the third portion 30c increases the adhesion of the source electrode 82 and the drain electrode 83 to the semiconductor layer 30 (the third portion 30c). This prevents the source electrode 82 and the drain electrode 83 from peeling off from the semiconductor layer 30.

[0105] Furthermore, in the semiconductor device 10B, similarly to the semiconductor device 10A, the conductor layer 40 is provided in the second portion 30b, which has a relatively large surface area, and the anchor effect of the second portion 30b enhances the adhesion of the conductor layer 40 to the semiconductor layer 30 (the second portion 30b). This prevents the conductor layer 40 from peeling off from the semiconductor layer 30.

[0106] Next, a method for manufacturing the semiconductor device 10B having the above configuration will be described. 14 and 15 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. Figures 14(A) to 14(C), 15(A) and 15(B) each show a schematic cross-sectional view of a main part of each step in the manufacturing of a semiconductor device.

[0107] In manufacturing the semiconductor device 10B, as shown in FIG. 14(A), a mask 70 having openings 70a in the areas where the second portion 30b and the third portion 30c of the semiconductor layer 30 are to be formed is formed on the semiconductor layer 30 formed on one surface 20a of the substrate 20 using an MOCVD method or the like.

[0108] For example, a SiC substrate is used for the substrate 20. For example, the semiconductor layer 30 includes a channel layer 31 made of GaN or the like and a barrier layer 32 made of AlGaN or the like. The semiconductor layer 30 may further include other layers such as an initial layer, a buffer layer, a back barrier layer, a spacer layer, and a cap layer. The mask 70 is made of SiN. The SiN of the mask 70 is formed using a plasma CVD method or a thermal CVD method. A portion of the formed SiN is removed by etching using an F-based gas to form the mask 70 having openings 70a in regions where the second portion 30b and the third portion 30c are to be formed.

[0109] 14A, after the mask 70 is formed, a portion of the semiconductor layer 30 exposed in the opening 70a is removed by etching, and a recess 33 is formed in the region where the second portion 30b and the third portion 30c of the semiconductor layer 30 will be formed. The recess 33 is formed to a depth that penetrates the barrier layer 32 of the semiconductor layer 30 and reaches the channel layer 31. The portion of the semiconductor layer 30 that remains after the formation of the recess 33, i.e., the outside of the recess 33 or the outside and inside of the recess 33, becomes the first portion 30a with a relatively small surface area.

[0110] After the recess 33 is formed, as shown in FIG. 14(B), second portions 30b and third portions 30c having relatively large surface areas are formed in the recess 33. The second portions 30b and third portions 30c are formed by further regrowing a predetermined semiconductor using a method such as MOCVD in the recess 33 formed in the semiconductor layer 30 grown using a method such as MOCVD. The second portions 30b and third portions 30c are simultaneously formed by this regrowth. For example, a nitride semiconductor such as GaN is regrown in the recess 33 as the second portions 30b and the third portions 30c. An n-type impurity is introduced into the nitride semiconductor such as GaN regrown in the recess 33. That is, a nitride semiconductor such as GaN containing an n-type impurity is formed in the recess 33 of the semiconductor layer 30 as the second portion 30b having a relatively large surface area.

[0111] Here, in the semiconductor device 10B, the second portion 30b formed by regrowth serves as a base for the conductor layer 40, which will be formed as described below. The third portion 30c formed by regrowth serves as a base and contact layer for the source electrode 82 and the drain electrode 83, which will be formed as described below. In the manufacture of the semiconductor device 10B, the second portion 30b, which will serve as a base for the conductor layer 40, is formed simultaneously with the third portion 30c, which will be formed by regrowth as a contact layer for the source electrode 82 and the drain electrode 83. In other words, in the manufacture of the semiconductor device 10B, the second portion 30b, which will serve as a base for the conductor layer 40, is regrown at the same time as the third portion 30c, which will serve as a contact layer for the source electrode 82 and the drain electrode 83, is regrown.

[0112] The surfaces of the second portion 30b and the third portion 30c formed by regrowth are more likely to be uneven and have a larger surface area than the surface of the first portion 30a. Also, by adjusting the regrowth conditions, such as the temperature, pressure, and amount of source gas supplied during regrowth, it is possible to form the second portion 30b and the third portion 30c with a relatively large surface area. By forming the second portion 30b and the third portion 30c by regrowth, the second portion 30b and the third portion 30c with a larger surface area than the first portion 30a are formed.

[0113] 14(B), after the second portion 30b and the third portion 30c are formed by regrowth, the mask 70 may be removed. Alternatively, the mask 70 may be left as it is and used as a passivation film 71. Here, an example will be described in which the mask 70 is left and used as a passivation film 71 in the steps from FIG. 14(C) onwards.

[0114] After the second portion 30b and the third portion 30c are formed, a source electrode 82 and a drain electrode 83 are formed as shown in FIG. 14(C). The source electrode 82 and the drain electrode 83 are formed on the surface of the third portion 30c, which has a relatively large surface area and is formed by regrowth in the recess 33 of the semiconductor layer 30. For example, Ti and Al are formed in this order on the surface 30d of the semiconductor layer 30 by evaporation, and then heat treatment is performed to establish ohmic contact. This forms the source electrode 82 and the drain electrode 83, which function as ohmic electrodes. The source electrode 82 and the drain electrode 83 are formed on the surface of the third portion 30c, which has a larger surface area than the first portion 30a, and are therefore connected to the semiconductor layer 30 (the third portion 30c) with relatively high adhesion due to the anchor effect.

[0115] Furthermore, as shown in FIG. 14(C), a conductor layer 40 is formed. The conductor layer 40 is formed on the surface of the second portion 30b, which has a relatively large surface area and is formed by regrowth in the recess 33 of the semiconductor layer 30. For example, Ni and Au are sequentially formed by vapor deposition to form the conductor layer 40. In this case, the Ni formed on the lower layer side of the conductor layer 40 is formed as a material that is resistant to etching that occurs when a via hole 61 is formed as described below. The Au formed on the upper layer side of the conductor layer 40 is formed as a material that suppresses a decrease in electrical conductivity between the conductor layer 40 and the connection wiring 90, which is formed as described below. The conductor layer 40 is formed on the surface of the second portion 30b, which has a larger surface area than the first portion 30a, and is thereby connected to the semiconductor layer 30 (the second portion 30b) with relatively high adhesive strength due to an anchor effect.

[0116] After the source electrode 82, the drain electrode 83 and the conductor layer 40 are formed, the gate electrode 81, the insulating film 72, the connection wiring 90 and the metal layer 60 are formed as shown in FIG. 15(A). For example, first, a portion of the passivation film 71 in a region where the gate electrode 81 is to be formed is removed by etching using an F-based gas, thereby forming an opening 71a. Then, Ni and Au are sequentially formed in the formed opening 71a by vapor deposition, thereby forming the gate electrode 81. Note that if the material used for the conductor layer 40 is the same as the material used for the gate electrode 81, the conductor layer 40 may be formed simultaneously with the formation of the gate electrode 81.

[0117] After the gate electrode 81 is formed, an insulating film 72 made of, for example, SiN is formed on the entire surface using plasma CVD or thermal CVD. Next, openings 72b and 72c, which lead to the conductor layer 40 and the source electrode 82, respectively, are formed from a surface 72a of the formed insulating film 72 by etching using an F-based gas. Then, a metal such as Ti or Au is formed on the surface 72a and in the openings 72b and 72c using plating or sputtering, or both, to form a connection wiring 90. As a result, the conductor layer 40 and the source electrode 82 are connected by the connection wiring 90.

[0118] Furthermore, a metal layer 60 having an opening 60a in a region corresponding to the second portion 30b of the semiconductor layer 30 and the conductor layer 40 thereon, i.e., a region where a via hole 61 is to be formed, is formed on the surface 20b of the substrate 20. The metal layer 60 functions as an etching mask when the via hole 61 is formed as described below. The metal layer 60 is made of a material that is resistant to the etching used to form the via hole 61. For example, the metal layer 60 is formed by plating Ni to a predetermined thickness that will not be lost by the etching used to form the via hole 61.

[0119] After the gate electrode 81, the insulating film 72, the connection wiring 90, and the metal layer 60 are formed, a via hole 61 is formed as shown in FIG. 15(B). That is, using the metal layer 60 as an etching mask, the substrate 20 exposed in the opening 60a and the semiconductor layer 30 are etched, thereby forming the via hole 61 reaching the conductor layer 40. If the substrate 20 is made of a Si-based semiconductor material such as SiC, an F-based gas is used for etching the via hole 61. Note that, in forming the via hole 61, a Cl-based gas may be used for etching the semiconductor layer 30 made of a nitride semiconductor. Using the metal layer 60 with the opening 60a as an etching mask, etching is performed using a predetermined gas. The etching is stopped at the position of the conductor layer 40. As a result, the via hole 61 is formed, penetrating the substrate 20 and the semiconductor layer 30 and reaching the conductor layer 40.

[0120] After the via hole 61 is formed, the wiring 50 is formed, thereby obtaining the state shown in FIG. 13 above. When forming the wiring 50, for example, Ti and Au are formed in this order by sputtering to form a seed layer 51. Next, for example, Au is formed by plating on the formed seed layer 51 to form a wiring layer 52. In this way, the wiring 50 including the seed layer 51 and the wiring layer 52 is formed. The wiring 50 is formed so as to be connected to the conductor layer 40 at the bottom of the via hole 61. The wiring 50 may be formed on the inner surface of the via hole 61, or on a metal layer 60 provided on the surface 20b side of the substrate 20.

[0121] Through the steps described above, the semiconductor device 10B having the configuration shown in FIG. 13 is manufactured. In the semiconductor device 10B, the conductor layer 40 is provided in the second portion 30b of the semiconductor layer 30, which has a larger surface area than the first portion 30a. Therefore, the anchor effect enhances the adhesion of the conductor layer 40 to the semiconductor layer 30. This prevents the conductor layer 40 from peeling off from the semiconductor layer 30 during manufacturing and operation of the semiconductor device 10B, thereby preventing electrical continuity defects such as disconnections between the conductor layer 40 and the wiring 50. This results in a high-quality, high-performance semiconductor device 10B, i.e., a HEMT. Furthermore, the yield of the semiconductor device 10B is improved.

[0122] In manufacturing the semiconductor device 10B, the second portion 30b that serves as the base of the conductor layer 40 is formed by regrowth simultaneously with the third portion 30c that serves as the contact layer for the source electrode 82 and the drain electrode 83. This allows the high-quality, high-performance semiconductor device 10B that includes the contact layer and the highly adhesive conductor layer 40 to be manufactured with minimal increase in the number of steps.

[0123] In the manufacturing process of the semiconductor device 10B, in the step of forming the via hole 61 (FIG. 15(B)), the via hole 61 may be formed so as to penetrate the metal layer 60 and the substrate 20 and reach the second portion 30b of the semiconductor layer 30 but not reach the conductor layer 40. This is because the second portion 30b is regrown simultaneously with the third portion 30c to be of n-type. Therefore, even if the via hole 61 that does not reach the conductor layer 40 is formed and an interconnect 50 is formed therein, the interconnect 50 and the conductor layer 40 can be electrically connected via the n-type second portion 30b.

[0124] [Fourth embodiment] Fig. 16 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device.

[0125] The semiconductor device 10C shown in FIG. 16 is an example of a HEMT. The semiconductor device 10C has a configuration in which the second portion 30b of the semiconductor layer 30 is n-type, and the wiring 50 is provided to penetrate the substrate 20 and reach the second portion 30b. In the semiconductor device 10C, the wiring 50 is provided so as not to penetrate the second portion 30b and not to reach the conductor layer 40. In the semiconductor device 10C, the wiring 50 is directly connected to the n-type second portion 30b. The wiring 50 is electrically connected to the conductor layer 40 via the n-type second portion 30b. The semiconductor device 10C differs from the semiconductor device 10A described in the second embodiment in having such a configuration.

[0126] In the semiconductor device 10C, the wiring 50 does not penetrate the second portion 30b. Therefore, in the semiconductor device 10C, the contact area between the second portion 30b and the conductor layer 40 is larger than when the wiring 50 penetrates the second portion 30b. Therefore, in the semiconductor device 10C, the adhesion of the conductor layer 40 to the semiconductor layer 30 (its second portion 30b) is further improved. This more effectively prevents the conductor layer 40 from peeling off from the semiconductor layer 30, and more effectively prevents poor conductivity between the conductor layer 40 and the wiring 50, such as breakage of the wiring 50 connected to the conductor layer 40.

[0127] Furthermore, in the semiconductor device 10C, etching can be stopped at the second portion 30b when forming the via hole 61. Therefore, compared to when etching is continued down to the conductor layer 40, the etching depth can be made shallower and the etching time can be shortened.

[0128] Furthermore, in the semiconductor device 10C, etching when forming the via hole 61 is stopped at the second portion 30b. Therefore, it is not necessary to use a material that is resistant to the etching for the conductor layer 40. Therefore, in the semiconductor device 10C, various conductive conductor materials can be used for the conductor layer 40, not limited to metals such as Ni.

[0129] Furthermore, in the semiconductor device 10C, even if etching to form a via hole 61 reaching the conductor layer 40 stops at the position of the second portion 30b, the wiring 50 formed in the via hole 61 can be electrically connected to the conductor layer 40 via the n-type second portion 30b. Therefore, restrictions on the position where etching can be stopped when forming the via hole 61 can be relaxed.

[0130] Next, a method for manufacturing the semiconductor device 10C having the above configuration will be described. 17A and 17B are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the fourth embodiment. Each of Fig. 17A and Fig. 17B is a schematic cross-sectional view of a main part of a step in the manufacturing of a semiconductor device.

[0131] The semiconductor device 10C can be manufactured in the same manner as described above for the steps shown in Figures 9(A) to 9(C), 10(A) to 10(C), 11(A) to 11(C), and 12(A) in the second embodiment.

[0132] However, in the manufacture of semiconductor device 10C, in the step of forming second portion 30b by regrowth (FIG. 10(A)), it is preferable that second portion 30b be regrown to a relatively thick thickness. In the manufacture of semiconductor device 10C, second portion 30b is the stopping position for etching when forming via hole 61, so it is preferable that second portion 30b be regrown in advance to a relatively thick thickness so that via hole 61 does not penetrate second portion 30b during etching. For example, second portion 30b is regrown to a thickness of 1 μm or more. N-type impurities are introduced into regrown second portion 30b.

[0133] Furthermore, in the manufacturing process of the semiconductor device 10C, in the step of forming the conductor layer 40 (FIG. 11(A)), the conductor layer 40 may be formed using various conductive conductor materials, not limited to metals such as Ni and Au. This is because the etching used to form the via hole 61 stops at the second portion 30b, and therefore the conductor layer 40 does not necessarily need to be made of a material that is resistant to the etching.

[0134] In manufacturing the semiconductor device 10C, for example, the thickness of the second portion 30b, the introduction of the n-type impurity, and the material of the conductor layer 40 are taken into consideration, and each of the steps is carried out according to the examples described above with reference to Figures 9(A) to 9(C), Figures 10(A) to 10(C), Figures 11(A) to 11(C), and Figure 12(A).

[0135] After the state shown in FIG. 12A is achieved, a via hole 61 is formed in the semiconductor device 10C, reaching the second portion 30b but not the conductor layer 40, as shown in FIG. 17A. When the substrate 20 is made of a Si-based semiconductor material such as SiC, an F-based gas is used for etching the via hole 61. When the semiconductor layer 30 is made of a nitride semiconductor, a Cl-based gas may be used for etching the via hole 61. Using the metal layer 60 with the opening 60a as an etching mask, etching is performed using a predetermined gas. The etching is stopped at the position of the second portion 30b. As a result, a via hole 61 is formed that penetrates the metal layer 60 and the substrate 20, reaching the second portion 30b, but not reaching the conductor layer 40.

[0136] 17(A), a via hole 61 is formed, and then a wiring 50 is formed in the via hole 61, thereby obtaining the state shown in FIG. 16. That is, a seed layer 51 and a wiring layer 52 are formed in this order using predetermined materials, respectively, to form the wiring 50. The wiring 50 is formed so as to be connected to the second portion 30b at the bottom of the via hole 61. The wiring 50 may be formed on the inner surface of the via hole 61, or on a metal layer 60 provided on the surface 20b side of the substrate 20.

[0137] Through the steps described above, the semiconductor device 10C having the configuration shown in FIG. 16 is manufactured. In the semiconductor device 10C shown in FIG. 16, the conductor layer 40 is provided in the second portion 30b of the semiconductor layer 30, which has a larger surface area than the first portion 30a. In the semiconductor device 10C, the wiring 50 does not penetrate the second portion 30b but is electrically connected to the conductor layer 40 through the second portion 30b. Therefore, the contact area between the second portion 30b and the conductor layer 40 is larger than when the wiring 50 penetrates the second portion 30b. Therefore, in the semiconductor device 10C, the adhesion of the conductor layer 40 to the semiconductor layer 30 (its second portion 30b) is further improved. This effectively prevents the conductor layer 40 from peeling off from the semiconductor layer 30 during manufacturing and operation of the semiconductor device 10C, and effectively prevents electrical continuity defects such as disconnections between the conductor layer 40 and the wiring 50. Therefore, a high-quality, high-performance semiconductor device 10C, i.e., a HEMT, is realized. Furthermore, the yield of the semiconductor device 10C is improved.

[0138] In the semiconductor device 10C, the second portion 30b may be regrown simultaneously with the third portion 30c formed as a contact layer for the source electrode 82 and the drain electrode 83, as described in the third embodiment. In this case, the thickness of the second portion 30b, the introduction of n-type impurities, and the material of the conductor layer 40 are considered, and the steps are performed according to the examples described with reference to FIGS. 14(A) to 14(C) and 15(A). After the state shown in FIG. 15(A) is achieved, a via hole 61 is formed that reaches the second portion 30b but does not reach the conductor layer 40, as shown in FIG. 17(B). Then, the wiring 50 is formed.

[0139] The semiconductor devices 1A-1D, 10A-10C, etc. described above can be applied to various electronic devices. As an example, the following describes cases where the semiconductor devices 1A-1D, 10A-10C, etc. having the above-described configurations are applied to semiconductor packages, power factor correction circuits, power supply devices, and amplifiers.

[0140] [Fifth embodiment] Here, an example of application of the semiconductor devices 1A-1D, 10A-10C, etc. having the above-described configuration to a semiconductor package will be described as a fifth embodiment.

[0141] Fig. 18 is a diagram illustrating an example of a semiconductor package according to the fifth embodiment, which diagrammatically shows a plan view of a main part of the example of the semiconductor package. 18 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 10A (FIG. 8) described in the second embodiment, a lead frame 210 on which the semiconductor device 10A is mounted, and a resin 220 that seals them.

[0142] The semiconductor device 10A is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 10A is provided with a pad 81a connected to the gate electrode 81, a pad 82a connected to the source electrode 82, and a pad 83a connected to the drain electrode 83. The pads 81a, 82a, and 83a are connected to the gate lead 211, source lead 212, and drain lead 213 of the lead frame 210, respectively, using wires 230 made of Au, Al, or the like. The lead frame 210, the semiconductor device 10A mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that portions of the gate lead 211, source lead 212, and drain lead 213 are exposed.

[0143] An external connection electrode connected to the source electrode 82 may be provided on the surface of the semiconductor device 10A opposite to the surface on which the pad 81a connected to the gate electrode 81 and the pad 83a connected to the drain electrode 83 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

[0144] For example, the semiconductor device 10A described in the second embodiment is used to obtain a semiconductor package 200 having such a configuration. Although the semiconductor device 10A is used as an example here, it is also possible to obtain a semiconductor package in a similar manner using other semiconductor devices 1A-1D, 10B, 10C, etc.

[0145] As described above, in the semiconductor devices 1A-1D, 10A-10C, etc., the conductor layer, which functions as an etching stopper when forming via holes and also functions as part of the connecting conductor, is provided in a portion of the semiconductor layer with a relatively large surface area. Therefore, the anchor effect of this portion enhances the adhesion of the conductor layer to the semiconductor layer. This reduces conduction defects such as peeling of the conductor layer from the semiconductor layer and disconnection between the conductor layer and the wiring. Therefore, high-quality, high-performance semiconductor devices 1A-1D, 10A-10C, etc. are realized. Using such semiconductor devices 1A-1D, 10A-10C, etc., a high-performance semiconductor package 200 is realized.

[0146] [Sixth embodiment] Here, an example of application of the semiconductor devices 1A-1D, 10A-10C, etc. having the above-described configuration to a power factor correction circuit will be described as a sixth embodiment.

[0147] Fig. 19 is a diagram illustrating an example of a power factor correction circuit according to the sixth embodiment, showing an equivalent circuit diagram of the example of the power factor correction circuit. The power factor correction (PFC) circuit 300 shown in FIG. 19 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0148] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out between both terminals of the capacitor 350.

[0149] For example, the semiconductor devices 1A-1D, 10A-10C, etc. are used as the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in semiconductor devices 1A-1D, 10A-10C, etc., a conductor layer that functions as an etching stopper when forming via holes and also functions as part of a connecting conductor is provided in a portion of the semiconductor layer with a relatively large surface area. Therefore, the anchor effect of this portion enhances the adhesion of the conductor layer to the semiconductor layer. This reduces conduction defects such as peeling of the conductor layer from the semiconductor layer and disconnection between the conductor layer and wiring. Therefore, high-quality, high-performance semiconductor devices 1A-1D, 10A-10C, etc. are realized. A high-performance PFC circuit 300 is realized using such semiconductor devices 1A-1D, 10A-10C, etc.

[0150] [Seventh embodiment] Here, an example in which the semiconductor devices 1A-1D, 10A-10C, etc. having the above-described configuration are applied to a power supply device will be described as the seventh embodiment.

[0151] Fig. 20 is a diagram illustrating an example of a power supply device according to the seventh embodiment, showing an equivalent circuit diagram of the example of the power supply device. The power supply device 400 shown in FIG. 20 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0152] The primary side circuit 410 includes the PFC circuit 300 as described in the sixth embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of (for example, four in this case): a switch element 441, a switch element 442, a switch element 443, and a switch element 444.

[0153] The secondary side circuit 420 includes a plurality of switch elements, three of which are a switch element 421, a switch element 422, and a switch element 423, as an example. For example, the semiconductor devices 1A-1D, 10A-10C, etc. are used for the switch element 310 of the PFC circuit 300 and the switch elements 441-444 of the full-bridge inverter circuit 440 included in the primary side circuit 410 of the power supply device 400 having such a configuration. For example, the semiconductor devices 1A-1D, 10A-10C, etc. are used for the switch elements 421, 422, 423 of the secondary side circuit 420 of the power supply device 400.

[0154] As described above, in semiconductor devices 1A-1D, 10A-10C, etc., a conductor layer that functions as an etching stopper when forming via holes and also functions as part of a connecting conductor is provided in a portion of the semiconductor layer with a relatively large surface area. Therefore, the anchor effect of this portion enhances the adhesion of the conductor layer to the semiconductor layer. This reduces conduction defects such as peeling of the conductor layer from the semiconductor layer and disconnection between the conductor layer and wiring. Therefore, high-quality, high-performance semiconductor devices 1A-1D, 10A-10C, etc. are realized. A high-performance power supply device 400 is realized by using such semiconductor devices 1A-1D, 10A-10C, etc.

[0155] [Eighth embodiment] Here, an example of application of the semiconductor devices 1A-1D, 10A-10C, etc. having the above-described configuration to an amplifier will be described as an eighth embodiment.

[0156] Fig. 21 is a diagram illustrating an example of an amplifier according to the eighth embodiment, showing an equivalent circuit diagram of the example amplifier. The amplifier 500 shown in FIG. 21 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0157] The digital predistortion circuit 510 compensates for nonlinear distortion in the input signal. The mixer 520 mixes the input signal SI, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal resulting from mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0158] The power amplifier 540 of the amplifier 500 having such a configuration uses the semiconductor devices 1A-1D, 10A-10C, etc. described above. As described above, in semiconductor devices 1A-1D, 10A-10C, etc., a conductor layer that functions as an etching stopper when forming via holes and also functions as part of a connecting conductor is provided in a portion of the semiconductor layer with a relatively large surface area. Therefore, the anchor effect of this portion enhances the adhesion of the conductor layer to the semiconductor layer. This reduces conduction defects such as peeling of the conductor layer from the semiconductor layer and disconnection between the conductor layer and wiring. Therefore, high-quality, high-performance semiconductor devices 1A-1D, 10A-10C, etc. are realized. A high-performance amplifier 500 is realized using such semiconductor devices 1A-1D, 10A-10C, etc.

[0159] Various electronic devices to which the semiconductor devices 1A-1D, 10A-10C, etc. are applied (such as the semiconductor package 200, PFC circuit 300, power supply device 400, and amplifier 500 described in the fifth to eighth embodiments) can be mounted in various electronic devices, such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing equipment, transmitters, receivers, and radar devices.

[0160] The following additional notes are provided regarding the above-described embodiment. (Appendix 1) A substrate, a semiconductor layer provided on a first surface side of the substrate, the semiconductor layer having a first portion and a second portion having a surface area larger than that of the first portion; a conductor layer provided on the second portion on the opposite side to the substrate; Wiring that penetrates the substrate and is connected to the conductor layer; 10. A semiconductor device comprising:

[0161] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the wiring penetrates the substrate and the second portion and is connected to the conductor layer. (Supplementary Note 3) The semiconductor device according to Supplementary Note 1, wherein the second portion contains an n-type impurity.

[0162] (Supplementary Note 4) The semiconductor device according to Supplementary Note 3, wherein the wiring penetrates the substrate, reaches the second portion, and is connected to the conductor layer via the second portion. (Supplementary Note 5) The semiconductor layer is a first semiconductor layer provided on the first surface side of the substrate; a second semiconductor layer provided on the opposite side of the first semiconductor layer from the substrate side and having a surface area larger than that of the first semiconductor layer; Including, the first portion is provided in the first semiconductor layer, 2. The semiconductor device according to claim 1, wherein the second portion is provided in the second semiconductor layer.

[0163] (Supplementary Note 6) The semiconductor device according to Supplementary Note 1, further comprising an electrode provided on the side of the first portion opposite to the substrate side and connected to the conductor layer. (Supplementary Note 7) The semiconductor layer further has a third portion having a surface area larger than that of the first portion, the third portion contains an n-type impurity, 2. The semiconductor device according to claim 1, further comprising an electrode provided on the side of the third portion opposite the substrate side and connected to the conductor layer.

[0164] (Supplementary Note 8) A step of forming a semiconductor layer on a first surface side of a substrate, the semiconductor layer having a first portion and a second portion having a surface area larger than that of the first portion; forming a conductor layer on the second portion on a side opposite to the substrate; forming wiring that penetrates the substrate and is connected to the conductor layer; A method for manufacturing a semiconductor device, comprising:

[0165] (Appendix 9) The method for manufacturing a semiconductor device according to Appendix 8, wherein the step of forming the wiring includes a step of forming the wiring so that it penetrates the substrate and the second portion and is connected to the conductor layer.

[0166] (Supplementary Note 10) The method for manufacturing a semiconductor device according to Supplementary Note 8, wherein the second portion contains an n-type impurity. (Appendix 11) A method for manufacturing a semiconductor device according to Appendix 10, wherein the step of forming the wiring includes a step of forming the wiring so that it penetrates the substrate, reaches the second portion, and is connected to the conductor layer via the second portion.

[0167] (Supplementary Note 12) The step of forming the semiconductor layer includes: forming a first semiconductor layer on the first surface side of the substrate; forming a second semiconductor layer having a surface area larger than that of the first semiconductor layer on the side opposite to the substrate side of the first semiconductor layer; Including, the first portion is provided in the first semiconductor layer, 9. The method for manufacturing a semiconductor device according to claim 8, wherein the second portion is provided in the second semiconductor layer.

[0168] (Supplementary Note 13) The method for manufacturing a semiconductor device according to Supplementary Note 8, further comprising forming an electrode connected to the conductor layer on the side of the first portion opposite to the substrate side. (Supplementary Note 14) The semiconductor layer further has a third portion having a surface area larger than that of the first portion, the third portion contains an n-type impurity, 9. The method for manufacturing a semiconductor device according to claim 8, further comprising forming an electrode connected to the conductor layer on the side of the third portion opposite the substrate side.

[0169] (Appendix 15) A substrate; a semiconductor layer provided on a first surface side of the substrate, the semiconductor layer having a first portion and a second portion having a surface area larger than that of the first portion; a conductor layer provided on the second portion on the opposite side to the substrate; Wiring that penetrates the substrate and is connected to the conductor layer; An electronic device comprising a semiconductor device including: [Explanation of symbols]

[0170] 1A, 1B, 1C, 1D, 10A, 10B, 10C Semiconductor device 2, 20, 120 board 2a, 2b, 20a, 20b, 30d, 72a, 120a, 120b, 130a side 3, 30, 130 Semiconductor layer 3a, 30a 1st part 3aa, 33 recess 3b, 30b 2nd part 4, 40, 140 conductor layers 5, 50, 150 wiring 6, 61, 160 Beer Hall 7, 70, 70a masks 7a, 60a, 71a, 72b, 72c opening 30c 3rd part 31 Channel Layer 32 Barrier Layer 51 seed layer 52 wiring layer 60 metal layer 71 Passivation film 72 insulating film 80 Transistor element 81a, 82a, 83a pads 81 gate electrode 82 Source electrode 83 Drain electrode 90 Connection wiring 200 Semiconductor Packages 210 Lead Frame 210a die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch elements 320 Diode 330 Choke Coil 340, 350 capacitors 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 transformer 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520, 530 Mixer 540 Power Amplifier

Claims

1. A substrate; a semiconductor layer provided on a first surface side of the substrate, the semiconductor layer having a first portion and a second portion having a surface area larger than that of the first portion; a conductor layer provided on the second portion on the opposite side to the substrate; Wiring that penetrates the substrate and is connected to the conductor layer; 10. A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the wiring passes through the substrate and the second portion and is connected to the conductor layer.

3. The semiconductor device according to claim 1 , wherein said second portion contains an n-type impurity.

4. 4. The semiconductor device according to claim 3, wherein the wiring penetrates the substrate, reaches the second portion, and is connected to the conductor layer via the second portion.

5. The semiconductor layer is a first semiconductor layer provided on the first surface side of the substrate; a second semiconductor layer provided on the opposite side of the first semiconductor layer from the substrate side and having a surface area larger than that of the first semiconductor layer; Including, the first portion is provided in the first semiconductor layer, The semiconductor device according to claim 1 , wherein the second portion is provided in the second semiconductor layer.

6. The semiconductor device according to claim 1 , further comprising an electrode provided on the side of said first portion opposite to said substrate side, said electrode being connected to said conductor layer.

7. the semiconductor layer further has a third portion having a surface area larger than that of the first portion, the third portion includes an n-type impurity, The semiconductor device according to claim 1 , further comprising an electrode provided on the opposite side of said third portion from said substrate side and connected to said conductor layer.

8. forming a semiconductor layer on a first surface side of a substrate, the semiconductor layer having a first portion and a second portion having a surface area larger than that of the first portion; forming a conductor layer on the second portion on a side opposite to the substrate; forming wiring that penetrates the substrate and is connected to the conductor layer; A method for manufacturing a semiconductor device, comprising:

9. A substrate; a semiconductor layer provided on a first surface side of the substrate, the semiconductor layer having a first portion and a second portion having a surface area larger than that of the first portion; a conductor layer provided on the second portion on the opposite side to the substrate; Wiring that penetrates the substrate and is connected to the conductor layer; An electronic device comprising a semiconductor device including:

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