Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of improving switching performance while suppressing an increase in threshold voltage.SOLUTION: A semiconductor device of an embodiment includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first region facing the second semiconductor region via a gate insulating portion in a second direction crossing a first direction from the first electrode toward the first semiconductor region, and a second region provided on the first region and including, via the gate insulating portion in the second direction: And a second electrode electrically connected to the third semiconductor region, wherein the gate electrode has a first length in the first direction from a lower surface of the first region to an upper surface of the second region, and a second length in the first direction from the lower surface of the first region to an upper surface of the first region contacting the gate insulating unit, and the first length is greater than the second length.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are used for power conversion and other applications. When a voltage applied to the gate electrode is equal to or greater than a threshold voltage Vth, a channel (inversion layer) is generated in the semiconductor layer, allowing current to flow and turning the semiconductor device on. When a voltage applied to the gate electrode is made smaller than the threshold voltage Vth, current stops flowing and the semiconductor device transitions to an off state. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-47625 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving switching performance while suppressing an increase in threshold voltage. [Means for solving the problem]

[0005] a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode having a first region facing the second semiconductor region via a gate insulating portion in a second direction intersecting a first direction from the first electrode toward the first semiconductor region; and a second region provided on the first region facing the third semiconductor region via the gate insulating portion in the second direction; and a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region, wherein the gate electrode has a first length in the first direction from a lower surface of the first region to an upper surface of the second region and a second length in the first direction from the lower surface of the first region to an upper surface of the first region that contacts the gate insulating portion, and the first length is greater than the second length.

[0006] The method for manufacturing a semiconductor device of the embodiment includes the steps of forming an insulating film on the surface of a trench formed by removing the upper surface of a substrate in the first direction, forming the gate electrode to fill the trench, selectively removing the gate electrode in the first direction near the insulating film, and forming an insulating layer on the gate electrode and the insulating film. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 2] 2 is a cross-sectional view illustrating the structure of a gate electrode of the semiconductor device according to the first embodiment. FIG. [Figure 3] 3 is a diagram showing fluctuations in threshold voltage Vth of the semiconductor device according to the first embodiment. FIG. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 6]FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 7A] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7B] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7C] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7D] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7E] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7F] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7G] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7H] 2A to 2C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8A] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8B] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8C] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8D] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8E] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0009] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0010] For example, in the cross-sectional views shown in the present specification, some laminated structures are shown, but the thickness ratio of each layer in the laminated structure is not necessarily the same as that in reality. Even if one layer is shown thicker than another layer in the cross-sectional view, in reality, the thicknesses of one layer and the other layer may be approximately the same, or one layer may be thinner than the other layer. In other words, the dimensions such as thicknesses shown in the drawings in the present specification may differ from the actual dimensions.

[0011] The direction from the first electrode 71 to the second electrode 72 is defined as the Z direction (first direction). The direction perpendicular to the Z direction is defined as the X direction (second direction), and the direction intersecting the X and Z directions is defined as the Y direction (third direction). Note that although the X direction, Y direction, and Z direction are shown as being orthogonal to each other in this embodiment, they are not limited to being orthogonal as long as they intersect with each other.

[0012] For the sake of explanation, the positive direction in the Z direction is referred to as "up" and the negative direction in the Z direction is referred to as "down." However, the "up" and "down" directions are not limited to the direction of gravity or the directions when the semiconductor device is mounted. When describing the vertical positional relationship between regions at different positions on the XY plane, the positions of the respective regions in the Z direction are compared.

[0013] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p,- indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - The shape is simply n-type, p-type + shape, p - The shape is sometimes simply referred to as p-shape.

[0014] In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0015] (First embodiment) FIG. 1 is a cross-sectional view illustrating a semiconductor device 100 according to the first embodiment.

[0016] The semiconductor device 100 shown in FIG. 1 is, for example, a MOSFET. The semiconductor device 100 includes a first semiconductor region 1 (n ― a second semiconductor region 2 of the second conductivity type (p-type base region), a third semiconductor region 3 of the first conductivity type (n + a source region of the second conductivity type), a fourth semiconductor region 4 (p + a first conductive type fifth semiconductor region 5 (n + The gate electrode 40 includes a gate insulating layer 60, a gate electrode 71 (a drain electrode), a gate insulating layer 72 (a source electrode), a gate insulating layer 73, a gate insulating layer 74, a gate electrode 75, a gate insulating layer 76, a gate insulating layer 77, a gate insulating layer 78, a gate insulating layer 79, a gate insulating layer 80, a gate insulating layer 81, a gate insulating layer 82, a gate insulating layer 83, a gate insulating layer 84, a gate insulating layer 85, a gate insulating layer 86, a gate insulating layer 87, a gate insulating layer 88, a gate insulating layer 89, a gate insulating layer 90, a gate insulating layer 91, a drain insulating layer 92, a gate insulating layer 92, a gate insulating layer 93, a gate insulating layer 94, a gate insulating layer 95, a gate insulating layer 96, a gate insulating layer 97, a gate insulating layer 98, a gate

[0017] A fifth semiconductor region 5 is provided on the first electrode 71. The first semiconductor region 1 is provided on the fifth semiconductor region 5 and is electrically connected to the first electrode 71 via the fifth semiconductor region 5. The second semiconductor region 2 is provided on the first semiconductor region 1. The third semiconductor region 3 and the fourth semiconductor region 4 are selectively provided on the second semiconductor region 2.

[0018] The conductive portion 30 is provided in the first semiconductor region 1 via a first insulating portion 10. The gate electrode 40 is provided spaced apart from the conductive portion 30 in the positive Z direction. A second insulating portion 20 is provided between the gate electrode 40 and the conductive portion 30. The specific structure of the gate electrode 40 will be described later.

[0019] The second electrode 72 is provided on the third semiconductor region 3 and the fourth semiconductor region 4. In the example shown in FIG. 1 , the insulating layer 60 is provided on the third semiconductor region 3. A portion of the second electrode 72 is electrically connected to the third semiconductor region 3 and the fourth semiconductor region 4 via a first plug P1 provided in the insulating layer 60.

[0020] The gate electrode 40 faces the second semiconductor region 2 and the third semiconductor region 3 in the X direction via the lateral insulating portion 50. An insulating layer 60 is provided between the gate electrode 40 and the second electrode 72, and the gate electrode 40 and the second electrode 72 are electrically insulated from each other.

[0021] The gate electrode 40 has a first region 41 and a second region 42 provided on the first region 41. The shape of the gate electrode 40 will be described in detail later with reference to FIG.

[0022] For example, the second semiconductor region 2, the third semiconductor region 3, the fourth semiconductor region 4, the conductive portion 30, the first insulating portion 10, the second insulating portion 20, the gate electrode 40, and the lateral insulating portion 50 are provided in plurality in the X direction and extend in the Y direction. However, the shapes of the plurality of conductive portions 30 provided in the X direction may be different. Also, there may be a portion between the conductive portion 30 and the insulating layer 60 where the gate electrode 40 is not provided. For example, as will be shown in FIG. 5 later, in the portion where the gate electrode 40 is not provided, the conductive portion 30 extends in the positive direction of the Z direction to below the insulating layer 60 (between the second semiconductor regions 2 adjacent in the X direction).

[0023] Next, the structure of the gate electrode 40 will be described with reference to FIG.

[0024] 2 is a cross-sectional view showing a portion of the semiconductor device 100 near the gate electrode 40. Hatching of the first insulating portion 10, the second insulating portion 20, the side insulating portion 50, and the insulating layer 60 is omitted.

[0025] The first region 41 is a portion provided on the conductive portion 30 via the second insulating portion 20. The first region 41 faces the first semiconductor region 1 and the second semiconductor region 2 via the lateral insulating portion 50. It is desirable for the first region 41 to also face the third semiconductor region 3 via the lateral insulating portion 50 in order to suppress an increase in the threshold voltage Vth.

[0026] The lower surface 41b of the first region 41 is located at the same position in the Z direction as the interface between the first semiconductor region 1 and the second semiconductor region 2, or lower than the interface between the first semiconductor region 1 and the second semiconductor region 2. The lower surface 41b of the first region 41 is located, for example, lower than a portion of the interface between the first semiconductor region 1 and the second semiconductor region 2 that contacts the lateral insulating portion 50. Furthermore, it is desirable that the portion of the lower surface 41b of the first region 41 that is located below the upper surface 42t of the second region 42 is located lower than the interface between the first semiconductor region 1 and the second semiconductor region 2. The lower surface 41b of the first region 41 is a plane that intersects with the Z direction. It is desirable that the lower surface 41b of the first region 41 be formed in a flat shape that is perpendicular to the Z direction.

[0027] The insulating region in contact with the lower surface 41b of the first region 41 is called the lower insulating portion 52. The portions of the first insulating portion 10 and the second insulating portion 20 in FIG. 2 that are in contact with the lower surface 41b of the first region 41 are the lower insulating portion 52. The gate electrode 40 is covered by the lateral insulating portion 50 and the lower insulating portion 52. The lateral insulating portion 50 and the lower insulating portion 52 are collectively called the gate insulating portion 54. The gate electrode 40 is covered by the gate insulating portion 54 and is electrically insulated from the first semiconductor region 1, the second semiconductor region 2, and the third semiconductor region 3. Note that even when the conductive portion 30, the first insulating portion 10, and the second insulating portion 20 are not provided, by forming the lower insulating portion 52 between the first semiconductor region 1 and the gate electrode 40, the gate electrode 40 and the first semiconductor region 1 are insulated by the lower insulating portion 52. That is, regardless of the presence or absence of the conductive portion 30, the gate electrode 40 is covered with the gate insulating portion 54 and is electrically insulated from the first semiconductor region 1, the second semiconductor region 2, and the third semiconductor region 3.

[0028] The first region 41 of the gate electrode 40 has a side surface 41s. The side surface 41s is in direct contact with the gate insulating portion 54 in the X direction and faces the second semiconductor region 2 in the X direction with the gate insulating portion 54 interposed therebetween. The side surface 41s is in direct contact with the lateral insulating portion 50 and faces the second semiconductor region 2 in the X direction with the lateral insulating portion 50 interposed therebetween. The side surface 41s is preferably provided along the Z direction.

[0029] The second region 42 is provided on the first region 41. An upper surface 41t of the first region 41 is in direct contact with the gate insulating portion 54. The upper surface 41t of the first region 41 is in direct contact with the side insulating portion 50. The upper surface 41t has, for example, a plane that intersects with the Z direction. A side surface 41s of the first region 41 connects the lower surface 41b of the first region 41 and the upper surface 41t of the first region 41.

[0030] The side surface 42s of the second region 42 is in direct contact with the gate insulating portion 54. The side surface 42s of the second region 42 faces the third semiconductor region 3 via the gate insulating portion 54. The side surface 42s of the second region 42 connects the top surface 41t of the first region 41 and the top surface 42t of the second region 42. The top surface 41t of the first region 41 and the side surface 42s of the second region 42 intersect. It is desirable that the side surface 42s of the second region 42 be provided along the Z direction.

[0031] The gate electrode 40 has a convex shape in the XZ plane shown in Fig. 2. Here, the convex shape includes a shape having surfaces corresponding to the lower surface 41b, side surfaces 41s, and upper surface 41t of the first region 41, and the side surfaces 42s and upper surface 42t of the second region 42, for example.

[0032] The upper surface 41t of the first region 41 is preferably located above the interface between the second semiconductor region 2 and the third semiconductor region 3. The upper surface 42t of the second region 42 is preferably located below the upper surface of the third semiconductor region 3 (the interface between the third semiconductor region 3 and the insulating layer 60).

[0033] The length of the first region 41 in the X direction is defined as L1. The length of the second region 42 in the X direction is defined as L2. L1 is greater than L2.

[0034] The length of the first region 41 in the Z direction is defined as L3. The length of the second region 42 in the Z direction is defined as L4. Length L3 is the length of the side surface 41s of the first region 41 in the Z direction, and is the length in the Z direction from the lower surface 41b to the upper surface 41t. Note that length L3 is, for example, equal to the length in the Z direction of the portion of the first region 41 that is located below the second region 42, but this is not necessarily the case. Length L4 is the length of the side surface 42s in the Z direction, and is the length in the Z direction from the upper surface 41t of the first region 41 to the upper surface 42t of the second region 42. L3 + L4 is referred to as the first length, and L3 is referred to as the second length. The first length is greater than the second length.

[0035] The length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is greater than the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 41t of the first region 41. Here, the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is the length in the Z direction of the gate electrode 40 in the portion where the second region 42 is provided above the first region 41, and is equal to, for example, L3 + L4, but is not necessarily equal to L3 + L4. The length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is, for example, the length in the Z direction at the center of the gate electrode 40 in the X direction. The length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 41t of the first region 41 is, for example, the length at the interface between the first region 41 and the side insulating portion 50, and is the length L3 in the Z direction of the side surface 41s of the first region 41.

[0036] Let the length in the Z direction at the interface between the third semiconductor region 3 and the side insulating portion 50 be Ls. Let the length in the Z direction at the interface between the second semiconductor region 2 and the side insulating portion 50 be Lb. L3 + L4 is not less than Lb. Furthermore, it is desirable that L3 is not less than Lb for reducing the on-resistance.

[0037] The upper surface 42t of the second region 42 is located in the negative Z direction with respect to the upper surface of the third semiconductor region 3. Let the length in the Z direction from the upper surface 42t of the second region 42 to the upper surface of the third semiconductor region 3 be Dz.

[0038] Dz and Ls satisfy, for example, 0 < Dz ≤ Ls. In order to suppress a short circuit between the gate electrode 40 and the third semiconductor region 3, it is desirable to satisfy 40 nm ≤ Dz ≤ Ls. More desirably, 90 nm ≤ Dz ≤ Ls is satisfied.

[0039] Let the length in the X direction of the side insulating portion 50 between the first region 41 and the second semiconductor region 2 be the first distance D1. Let the length in the X direction of the side insulating portion 50 between the second region 42 and the third semiconductor region 3 be the second distance D2. The first distance D1 is smaller than the second distance D2.

[0040] Figure 3 shows the relationship between the second distance D2 and the threshold voltage Vth. With the first distance D1 fixed, the values of the threshold voltage Vth obtained by simulation when the second distance D2 is changed are plotted. Here, the threshold voltage Vth is the voltage of the gate electrode 40 necessary to turn on the semiconductor device 100. In other words, the threshold voltage Vth is the voltage of the gate electrode 40 necessary to form a channel in the second semiconductor region 2 near the lateral insulating portion 50. Depending on the type of device in which a transistor such as a MOSFET is incorporated, a range of values for the threshold voltage Vth of the transistor for the operation of the device, for example about 1.7V, may be specified. It is desirable to reduce the on-resistance, switching losses, etc. while suppressing fluctuations in the threshold voltage Vth so as not to deviate from the specified range of values for each device to be incorporated.

[0041] The horizontal axis of Figure 3 represents the second distance D2 of the lateral insulating portion 50. The vertical axis represents the ratio of the variation ΔVth of Vth (taking a positive value when Vth increases and a negative value when it decreases) with respect to the threshold voltage Vth (for example, about 1.7V) when D2 = 50nm. Note that the threshold voltage Vth may be, for example, about 3V or about 5V in addition to 1.7V. Also, ΔVth / Vth is an index of the magnitude of the variation of the threshold voltage Vth in a form independent of the reference value of the threshold voltage Vth, and it is desirable to keep the absolute value of ΔVth / Vth small.

[0042] As shown in Figure 3, as the second distance D2 increases, the variation of Vth increases in the positive direction. This is because as the portion where the length of the lateral insulating portion 50 in the X direction is formed larger increases, it becomes more difficult to form a channel in the second semiconductor region 2. When the second distance D2 becomes larger than 150nm, the threshold voltage Vth increases rapidly.

[0043] In order to suppress the variation of the threshold voltage Vth, it is desirable that the second distance D2 satisfies D1 < D2 ≤ 150nm. More preferably, it satisfies D1 < D2 ≤ 100nm.

[0044] Next, the cross-sectional structure of the semiconductor device 100 will be further described with reference to Fig. 4. Fig. 4 is a cross-sectional view taken at a position different from the cross section shown in Fig. 1, and shows a structure for supplying a potential to the gate electrode 40.

[0045] 4, a third electrode 73 is provided on the insulating layer 60. The third electrode 73 is, for example, a gate wiring and is provided electrically separated from the second electrode. The third electrode 73 is electrically connected to the gate electrode 40 via a second plug P2 formed in the insulating layer 60. The second plug P2 is connected to the second region 42 of the gate electrode 40 and has a length in the X direction smaller than that of the second region 42.

[0046] 4, the third semiconductor region 3 does not need to be provided below the third electrode 73. In other words, the second semiconductor region 2 and the insulating layer 60 may be in contact with each other.

[0047] 5 is a cross-sectional view taken at a position different from that shown in FIG. 1, and shows a structure for supplying a potential to the conductive portion 30. The second electrode 72 and the conductive portion 30 are electrically connected via a third plug P3 formed in the insulating layer 60. The length of the third plug P3 in the X direction is smaller than the length of the upper end of the conductive portion 30 in the X direction.

[0048] 5, it is not necessary to provide the third semiconductor region 3 below the second electrode 72. In other words, the second semiconductor region 2 and the insulating layer 60 may be in contact with each other.

[0049] The second electrode 72 is electrically connected to the third semiconductor region 3 by a first plug P1 as shown in FIG. 1, and is also electrically connected to the conductive portion 30 by a third plug P3 as shown in FIG.

[0050] The upper end of the conductive portion 30 shown in Fig. 5 is preferably located lower than the upper surface of the second semiconductor region 2 shown in Fig. 5. The upper end of the conductive portion 30 is preferably located higher than the interface between the second semiconductor region 2 and the third semiconductor region 3 shown in Fig. 1 and lower than the upper surface of the third semiconductor region 3 shown in Fig. 1. More preferably, the upper end of the conductive portion 30 is located higher than the upper surface 41t (see Fig. 2) of the first region 41 of the gate electrode 40 shown in Fig. 1.

[0051] 5, the conductive portion 30 connected to the second electrode 72 has been described. However, the second electrode 72 may be replaced with a fourth electrode 74 arranged at a distance from the second electrode 72 and the third electrode 73. The fourth electrode 74 is provided in an equivalent potential ring (EQPR) region located around the second electrode 72 and the third electrode 73 in the XY plane, for example. The fourth electrode 74 has the same potential as the first electrode 71 (drain electrode), for example.

[0052] The semiconductor device 100 has a plurality of electrodes spaced apart from one another, such as a second electrode 72, a third electrode 73, and a fourth electrode 74, and has a structure below each electrode, such as that shown in Figures 1, 4, and 5.

[0053] 1, 4, and 5, the operation of the semiconductor device 100 will be described. With a positive voltage applied to the first electrode 71 (drain electrode) relative to the second electrode 72 (source electrode), a voltage equal to or greater than the threshold voltage Vth is applied to the gate electrode 40 via the third electrode 73 shown in Fig. 4. This forms a channel (inversion layer) in the second semiconductor region 2 (p-type base region) facing the lateral insulating portion 50, and the semiconductor device 100 enters an on state.

[0054] Generally, in semiconductor devices such as MOSFETs, the larger the opposing area between the base region and the gate electrode in the semiconductor region and the shorter the opposing distance, the lower the threshold voltage Vth and the lower the electrical resistance in the on-state. That is, the larger the opposing area between the gate electrode 40 and the second semiconductor region 2 (p-type base region) and the thinner the lateral insulating portion 50 located therebetween, the easier it is to form a channel in the base region, thereby reducing the threshold voltage Vth and the on-resistance.

[0055] The electrons are transported from the second electrode 72 to the third semiconductor region 3(n + a channel formed in the second semiconductor region 2; a first semiconductor region 1 (n ― shaped drift region), and fifth semiconductor region 5(n + The current flows through the gate electrode 40 (the gate electrode 40) and the second semiconductor region 2 (the drain region) to the first electrode 71. Thereafter, when the voltage applied to the gate electrode 40 becomes smaller than the threshold voltage Vth, the channel in the second semiconductor region 2 disappears, and the semiconductor device 100 enters an off state.

[0056] When the semiconductor device 100 is switched to the off state and the positive voltage applied to the first electrode 71 with respect to the second electrode 72 increases, a depletion layer spreads from the interface between the first insulating portion 10 and the first semiconductor region 1 toward the first semiconductor region 1. The spread of the depletion layer in the first semiconductor region 1 increases the breakdown voltage of the semiconductor device 100 in the off state. As shown in FIG. 5 , the conductive portion 30 connected to the second electrode 72 extends the depletion layer spreading in the first semiconductor region 1 in the Z direction, thereby suppressing the concentration of the electric field. In addition, the conductive portion 30 connected to the fourth electrode 74 is disposed at the terminal end of the semiconductor device 100, thereby suppressing the concentration of the electric field at the terminal end.

[0057] An example of the material of each component of the semiconductor device 100 will be described.

[0058] The first semiconductor region 1, the second semiconductor region 2, the third semiconductor region 3, the fourth semiconductor region 4, and the fifth semiconductor region 5 may contain, for example, silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony may be used as an n-type impurity. Boron may be used as a p-type impurity.

[0059] The conductive portion 30 and the gate electrode 40 include a conductive material such as polysilicon. The conductive material may contain impurities.

[0060] The first insulating section 10, the second insulating section 20, the side insulating section 50, and the insulating layer 60 contain an insulating material such as silicon oxide. The second insulating section 20 may be, for example, a BPSG (Boron Phosphorus Silicon Glass) film. The BPSG film has the advantage that it can be easily planarized by applying a heat treatment after deposition to cause reflow.

[0061] The first electrode 71, the second electrode 72, the third electrode 73, and the fourth electrode 74 are metal layers containing, for example, aluminum or gold. The first plug P1, the second plug P2, and the third plug P3 contain, for example, a metal such as aluminum. The first plug P1, the second plug P2, and the third plug P3 may also contain, for example, tungsten (W) or titanium nitride (TiN).

[0062] The semiconductor device 100 according to this embodiment can suppress an increase in threshold voltage Vth to reduce on-resistance, and can also reduce switching loss to improve switching performance. Suppressing an increase in threshold voltage Vth and reducing switching loss are generally in a trade-off relationship, and this embodiment can improve this trade-off by adjusting the shape of the gate electrode 40. First, the reduction in on-resistance will be described.

[0063] 1, the lower surface of the first region 41 of the gate electrode 40 is located below the interface between the first semiconductor region 1 and the second semiconductor region 2, and the upper surface 41t of the first region 41 is located above the interface between the second semiconductor region 2 and the third semiconductor region 3. That is, in the gate electrode 40, it is the first region 41 that faces the second semiconductor region 2 across the lateral insulating portion 50. By having the first region 41 of the gate electrode 40 and the second semiconductor region 2 face each other across a portion of the lateral insulating portion 50 that has the first distance D1, it is possible to reduce the threshold voltage Vth and the on-resistance.

[0064] 3, the threshold voltage tends to increase as the second distance D2 of the side insulating portion 50 in contact with the second region 42 increases. By setting the second distance D2 to 150 nm or less, the increase in the threshold voltage can be further suppressed.

[0065] Next, we will explain the improvement of switching performance. Generally, in semiconductor devices such as MOSFETs, if the capacitance between the source region in the semiconductor region and the gate electrode (hereinafter referred to as gate-source capacitance) is large, that is, if the amount of charge stored for a given potential difference is large, the switching speed will decrease and the switching loss will increase.

[0066] The gate-source capacitance decreases as the length in the X direction of the lateral insulating portion 50 provided between the gate electrode 40 and the third semiconductor region 3 increases. Also, the gate-source capacitance decreases as the area where the gate electrode 40 and the third semiconductor region 3 face each other via the lateral insulating portion 50 decreases.

[0067] 1, the lateral insulating portions 50 located between the second region 42 of the gate electrode 40 and the third semiconductor region 3 have a greater length in the X direction (D2>D1) than the lateral insulating portions 50 located between the first region 41 and the second semiconductor region 2. For example, compared to when the length in the X direction of the lateral insulating portions 50 located between the gate electrode 40 and the third semiconductor region 3 is uniformly thin, the capacitance between the second region 42 and the third semiconductor region 3 can be reduced, and the gate-source capacitance can be reduced.

[0068] Furthermore, by having the side surface 42s of the second region 42 intersect with the top surface 41t of the first region 41, a lateral insulating portion 50 having the second distance D2 in the X direction can be provided in a wide portion between the second region 42 and the third semiconductor region 3. Note that if the top surface 41t of the first region 41 is perpendicular to the Z direction and the side surface 42s of the second region 42 is aligned along the Z direction, a lateral insulating portion 50 having the second distance D2 in the X direction can be provided in an even wider portion between the second region 42 and the third semiconductor region 3. The longer the lateral insulating portion 50 is formed in the X direction in a wider portion between the second region 42 and the third semiconductor region 3, the more the gate-source capacitance can be reduced. By having the side surface 42s of the second region 42 intersect with the top surface 41t of the first region 41, the gate-source capacitance can be reduced.

[0069] As described above, in the semiconductor device 100 according to this embodiment, the first region 41 and the second region 42 of the gate electrode 40 are provided so as to be in contact with the lateral insulating portions 50 having different lengths in the X direction, thereby making it possible to suppress an increase in the threshold voltage Vth, reduce the on-resistance, and reduce the gate-source capacitance.

[0070] Furthermore, the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 42t of the second region 42 is greater than the length in the Z direction from the lower surface 41b of the first region 41 to the upper surface 41t of the first region 41. This longer length in the Z direction of the gate electrode 40 in the portion where the second region 42 is provided on the first region 41 reduces the electrical resistance of the gate electrode 40. When the portion of the lower surface 41b of the first region 41 that is located below the upper surface 42t of the second region 42 is located below the interface between the first semiconductor region 1 and the second semiconductor region 2, the length in the Z direction of the gate electrode 40 can be further increased to reduce the electrical resistance of the gate electrode 40. This reduces the time delay when applying a voltage to the gate electrode 40 to switch the semiconductor device 100. That is, the semiconductor device 100 can reduce switching loss.

[0071] It is desirable that the lower surface of the first region 41 of the gate electrode 40 be formed in a flat shape perpendicular to the Z direction. The flatter the lower surface of the first region 41 is, the larger the radius of curvature of the lower surface of the gate electrode 40 (the smaller the curvature), and therefore, the concentration of the electric field can be suppressed at the interface between the gate electrode 40 and the surrounding insulating material (the first insulating portion 10, the second insulating portion 20, or the side insulating portion 50).

[0072] In addition, since the upper surface 42t of the second region 42 of the gate electrode 40 is positioned below the upper surface of the third semiconductor region 3 (0 < Dz), a short circuit between the gate and the source can be suppressed. For comparison, when the upper surface 42t of the second region 42 of the gate electrode 40 is positioned above the upper surface of the third semiconductor region 3, when the gate electrode 40 is deformed in the X direction or the Y direction, the conductive material of the portion of the gate electrode 40 positioned above the upper surface of the third semiconductor region 3 may adhere to the upper surface of the third semiconductor region 3. That is, there is a risk that the gate electrode 40 and the third semiconductor region 3 may be electrically connected. On the other hand, according to the semiconductor device according to the present embodiment, since the upper surface of the third semiconductor region is positioned above the gate electrode 40, the risk that the conductive material contained in the gate electrode 40 adheres to the upper surface of the third semiconductor region 3 can be reduced. By setting the length Dz to 40 nm or more, a short circuit between the gate and the source can be further suppressed.

[0073] In addition, according to the semiconductor device 100 according to the present embodiment, the second plug P2 and the third plug P3 respectively connected to the conductive portion 30 that enables improvement of the breakdown voltage and the gate electrode 40 can be simultaneously formed, and the manufacturing efficiency of the semiconductor device can be improved. This is because, by reducing the difference in the Z-direction position between the upper surface 42t of the second region 42 of the gate electrode 40 and the upper end of the conductive portion 30 shown in FIG. 5, the openings for embedding the second plug P2 and the third plug P3 can be formed and embedded in the same process.

[0074] For comparison, considering the case where the gate electrode 40 does not have the second region 42, while the gate capacitance can be reduced, the second plug P2 needs to be formed deeper than in the case of the present embodiment. Therefore, the manufacturing process of the second plug P2 and the manufacturing process of the third plug P3 need to be separated.

[0075] (Second Embodiment) FIG. 6 is a cross-sectional view of a semiconductor device 200 according to the second embodiment. Parts common to the semiconductor device 100 according to the first embodiment are partially omitted.

[0076] The gate electrode 40 of the semiconductor device 200 according to this embodiment has a first region 41, a second region 42, and a third region 43 provided in the first region 41.

[0077] The third region 43 contains a different material from the first region 41. The third region 43 contains an insulating material such as silicon oxide. The third region 43 contains, for example, a Tetra Eth Oxy Silane (TEOS) film. Note that the third region 43 is not limited to being made of an insulating material, and may contain a conductive material.

[0078] The semiconductor device 200 according to this embodiment can also shorten the process of forming the gate electrode 40, improving manufacturing efficiency and reducing manufacturing costs. Details will be described when explaining the manufacturing method.

[0079] According to at least one of the embodiments described above, it is possible to suppress an increase in threshold voltage Vth, reduce on-resistance, and reduce gate-source capacitance, thereby improving switching performance.

[0080] In the above description, an example has been described in which the gate electrode 40 is located above the conductive portion 30. However, the conductive portion 30 and the gate electrode 40 may be spaced apart in the XY plane. For example, the conductive portions 30 may be arranged in a dot pattern spaced apart in the X and Y directions and extend in the Z direction, and the gate electrodes 40 may be arranged in a grid pattern around each conductive portion 30 in the XY plane. The gate electrode 40 is covered with a gate insulating portion 54 including side insulating portions 50 and a lower insulating portion 52. Even when the gate electrode 40 is arranged in a grid pattern in the XY plane, it is possible to suppress an increase in the threshold voltage Vth, reduce the on-resistance, and reduce the gate-source capacitance, thereby improving switching performance.

[0081] A method for manufacturing a semiconductor device will be described below. The manufacturing method will be described with reference to the cross-sectional view shown in Figure 1. In the description of the manufacturing method, the manufacturing steps for the structure below the first semiconductor region 1 are omitted because they are not significantly different from general manufacturing methods.

[0082] 7A to 7H are cross-sectional views showing a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0083] First, a substrate Sub having a first semiconductor region 1 is prepared. A portion of the substrate Sub is removed from the upper surface of the substrate Sub to form a trench T. This can be removed by etching, for example, chemical dry etching (CDE) or reactive ion etching (RIE). Next, a first insulating portion 10 is formed on the upper surface of the substrate Sub and on the surface of the trench T to obtain the structure shown in FIG. 7A. The first insulating portion 10 includes an insulator such as silicon oxide obtained by thermally oxidizing the substrate Sub. Alternatively, the first insulating portion 10 may be formed by chemical vapor deposition (CVD).

[0084] Next, as shown in FIG. 7B, a conductive portion 30 is formed on the first insulating portion 10 and inside the trench T. The conductive portion 30 is formed by CVD of a conductive material such as polysilicon. Then, a portion of the conductive portion 30 is removed by CDE or the like to set back the upper end of the conductive portion 30 in the negative Z direction. This forms a plurality of conductive portions 30 provided inside the plurality of trenches T, respectively, as shown in FIG. 7B.

[0085] Note that the step of recessing the upper ends by CDE or the like may be omitted for some of the conductive portions 30 among the plurality of conductive portions 30. For example, among the plurality of conductive portions 30 provided in the X direction, a portion not shown in FIG. 7B may include the conductive portion 30 shown in FIG.

[0086] Furthermore, a second insulating section 20 is formed on the first insulating section 10 and the conductive section 30. The second insulating section 20 is an insulator containing silicon oxide formed by, for example, CVD. Alternatively, the second insulating section may be a BPSG film. In this way, the structure shown in FIG. 7B is obtained.

[0087] Next, portions of the first insulating portion 10 and the second insulating portion 20 are removed by wet etching or the like. By removing the portions of the first insulating portion 10 and the second insulating portion 20, a portion of the first semiconductor region 1 is exposed. The upper surface of the substrate Sub is subjected to, for example, thermal oxidation to form an insulating film 55. The insulating film 55 contains, for example, silicon oxide. In this way, the structure shown in FIG. 7C is obtained.

[0088] Furthermore, a gate electrode 40 is formed on the first insulating portion 10, the second insulating portion 20, and the insulating film 55, and then partially removed to obtain the gate electrode 40 remaining in the trench as shown in FIG. 7D. The gate electrode 40 is formed by, for example, CVD and contains polysilicon. A method for partially removing the gate electrode 40 is, for example, chemical mechanical polishing (CMP). Alternatively, the gate electrode 40 may be partially removed by, for example, CDE or wet etching. Note that the gate electrode 40 shown in FIG. 7D has a different shape from the gate electrode shown in FIG. 1 because its shape will change in subsequent processes.

[0089] 3 is defined as a portion interposed between the first insulating portion 10 and the second insulating portion 20 and the gate electrode 40 in, for example, FIG. 7D. That is, the region of the first insulating portion 10 and the second insulating portion 20 that contacts the lower surface 41b of the gate electrode 40 is referred to as the lower insulating portion 52. Therefore, in the step shown in FIG. 7D, it is not necessary to further provide the lower insulating portion 52.

[0090] Furthermore, when the conductive portion 30, the first insulating portion 10, and the second insulating portion 20 are not provided, the first insulating portion 10 and the second insulating portion 20 are not formed after the trench T is formed, and instead the insulating film 55 is formed on the surface of the trench T so as to be in contact with the first semiconductor region 1, thereby making it possible to form the lower insulating portion 52 interposed between the gate electrode 40 and the first semiconductor region 1. Even when the conductive portion 30, the first insulating portion 10, and the second insulating portion 20 are not provided, the lower insulating portion 52 can be provided in the process of forming the insulating film 55, and therefore an additional process for providing the lower insulating portion 52 is not necessary.

[0091] A second semiconductor region 2 and a third semiconductor region 3 are obtained by sequentially ion-implanting p-type impurities and n-type impurities into the first semiconductor region 1 between the trenches T. In this way, the structure of the substrate Sub shown in FIG. 7D is obtained.

[0092] Next, an oxide film 80 is formed on the gate electrode 40 and the lateral insulating portions 50 by selectively oxidizing the upper surface of the gate electrode 40. For example, the oxide film 80 may be a TEOS film, a BPSG film, or a film containing both. Then, portions of the upper surface of the gate electrode 40 on which the oxide film 80 is not formed are selectively removed. Parts of the upper surface of the gate electrode 40 near the insulating film 55 are removed. This is done by, for example, RIE or CDE. Alternatively, a resist may be used instead of the oxide film 80. In this way, the structure shown in FIG. 7E is obtained.

[0093] Next, the oxide film 80 on the gate electrode 40 is removed. A step of adjusting the position of the upper surface of the gate electrode 40 in the Z direction by removing the gate electrode 40 by RIE or CDE may be further included. Fig. 7F shows a step of receding the upper surface of the gate electrode 40 (the upper surfaces of the first region and the second region 42) in the negative Z direction.

[0094] Next, an insulating layer 60 is formed on the gate electrode 40 and the insulating film 55. An opening OP is formed in the insulating layer 60 so as to reach the second semiconductor region 2. P-type impurity ions are implanted into the second semiconductor region 2 through the opening OP to form the fourth semiconductor region 4. In this manner, the structure shown in FIG. 7G is obtained. Note that a portion of the insulating layer 60 (the region indicated as 60g in FIG. 7G) may be located between the gate electrode 40 and the insulating film 55. The insulating film 55 and the insulating layer 60g located between the gate electrode 40 and the second semiconductor region 2 or the third semiconductor region 3 are collectively referred to as the lateral insulating portion 50.

[0095] Finally, the second electrode 72 is formed on the insulating layer 60. The first plug P1 is buried in the opening OP by, for example, CVD. The second electrode 72 on the insulating layer 60 is formed by, for example, sputtering.

[0096] In the manufacturing process shown in FIG. 7, only the manufacturing process of the cross-sectional structure shown in FIG. 1 has been described. However, the structure including the second plug P2 and the third plug P3 shown in FIGS. 4 and 5 can be manufactured in parallel with the structure including the first plug P1.

[0097] 4 can be formed in the process between Figures 7G and 7H. Furthermore, the openings for embedding the second plug P2 and the third plug P3 can be formed in the same process, and the embedding of the plugs can also be performed in the same process.

[0098] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Some parts common to the method for manufacturing the semiconductor device 100 according to the first embodiment will be omitted. The steps up to the step shown in FIG. 7C are common to the method for manufacturing the semiconductor device 100 according to the first embodiment, and therefore will be omitted.

[0099] 8A to 8E are cross-sectional views showing a method for manufacturing the semiconductor device 200 according to the second embodiment.

[0100] 8A shows a process of forming a first conductive layer 91 on the first insulating section 10, the second insulating section 20, and the insulating film 55 for the structure shown in FIG. 7C. The first conductive layer 91 is formed by CVD of a conductive material containing polysilicon, for example. Note that it may also be formed by Low Pressure-CVD (LP-CVD).

[0101] 8A is obtained by forming a buried portion 92 on the first conductive layer 91. The buried portion 92 includes, for example, a TEOS film, and is formed by CVD of an insulating material including silicon oxide. Note that a conductive material may also be used for the buried portion 92.

[0102] Next, the buried portion 92 is planarized to obtain the structure shown in Fig. 8B. The step of planarizing the buried portion 92 is performed by, for example, CMP. The buried portion 92 is left so as to fill the trench T.

[0103] Next, as shown in FIG. 8C , the first conductive layer 91 and the buried portion 92 are selectively removed. For example, the first conductive layer 91 and the buried portion 92 are removed at different removal rates by CDE. It is possible to remove the first conductive layer 91 and the buried portion 92 to different depths. The ratio of the removal rates of each film is called the removal ratio (selectivity). The removal ratio (selectivity) of the first conductive layer 91 to the buried portion 92 is, for example, greater than 1, and the first conductive layer 91 is removed to a greater depth in the Z direction than the buried portion 92. The first conductive layer 91 is, for example, conductive polysilicon containing impurities, and the buried portion 92 is, for example, a TEOS film. By appropriately selecting gases used for etching so that the etching rates of the first conductive layer 91 and the buried portion 92 are different, removal at different removal rates is possible.

[0104] Next, a second conductive layer 93 is further formed on the first conductive layer 91 and the buried portion 92 to obtain the gate electrode 40. Here, the formation of the second conductive layer 93 is performed by selective growth of a conductive material containing, for example, polysilicon. Therefore, it is desirable that the buried portion 92 be formed by selective growth of a material containing silicon, such as an oxide film such as a TEOS film. In this way, the structure shown in FIG. 8D is obtained.

[0105] According to this manufacturing method, the Z-direction positions of the upper surface 41t of the first region 41 and the upper surface 42t of the second region 42 of the gate electrode 40 can be controlled by the Z-direction thickness of the second conductive layer 93 formed on the first conductive layer 91 and the buried portion 92. Therefore, it is possible to omit the step of recessing the upper surface of the gate electrode 40 in the negative Z direction to prevent the conductive material from adhering to the upper surface of the third semiconductor region 3. This allows the manufacturing process to be shortened.

[0106] Finally, similar to the method for manufacturing the semiconductor device 100 according to the first embodiment, an insulating layer 60 is formed on the gate electrode 40 and the insulating film 55. Then, a first plug P1 and a second electrode 72 are formed by, for example, CVD or sputtering. In this way, the structure shown in FIG. 8E is obtained.

[0107] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, designs that are appropriately modified by a person skilled in the art from these specific examples are also included within the scope of the embodiments as long as they have the characteristics of the embodiments. The elements, as well as their arrangement, materials, conditions, shapes, sizes, etc., of the above-mentioned specific examples are not limited to those exemplified and can be modified as appropriate.

[0108] Furthermore, the elements of each of the above-described embodiments can be combined to the extent technically possible, and combinations of these are also included within the scope of the embodiments as long as they include the features of the embodiments. In addition, within the scope of the concept of the embodiments, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the embodiments.

[0109] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0110] 1. First semiconductor region 2. Second semiconductor region 3. Third semiconductor region 4. Fourth semiconductor region 5. Fifth semiconductor region 10. First insulating part 20 Second insulating section 30 Conductive part 40 Gate electrode 41...1st area 42...Second area 43...Third area 50 Side insulation 52 Lower insulation part 54 Gate insulation 60...insulating layer 71...1st electrode 72...Second electrode 73...Third electrode 74...4th electrode P1: First plug P2: Second plug P3: Third plug 55....Insulating film 80...Oxide film 91... First conductive layer 92 Embedded part 93...Second conductive layer 100, 200... Semiconductor device

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first region facing the second semiconductor region via a gate insulating portion in a second direction intersecting a first direction from the first electrode toward the first semiconductor region; a second region provided on the first region and facing the third semiconductor region in the second direction with the gate insulating portion interposed therebetween; a gate electrode having a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; Equipped with The gate electrode is a first length in the first direction from a lower surface of the first region to an upper surface of the second region; a second length in the first direction from the lower surface of the first region to an upper surface of the first region that is in contact with the gate insulating portion; and The first length is greater than the second length. Semiconductor device.

2. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first region facing the second semiconductor region via a gate insulating portion in a second direction intersecting a first direction from the first electrode toward the first semiconductor region; a second region provided on the first region and facing the third semiconductor region in the second direction with the gate insulating portion interposed therebetween; a gate electrode having a second electrode provided on the third semiconductor region and electrically connected to the third semiconductor region; Equipped with The gate electrode has a convex shape. Semiconductor device.

3. the second region has a side surface connecting the top surface of the first region and the top surface of the second region, the top surface of the first region and the side surface of the second region intersect with each other; The semiconductor device according to claim 1 .

4. Below the upper surface of the second region, the lower surface of the first region is located below the interface between the first semiconductor region and the second semiconductor region. The semiconductor device according to claim 1 .

5. The lower surface of the first region has a flat portion. The semiconductor device according to claim 4 .

6. the gate electrode has a center in the second direction; the first length is a length in the first direction passing through the center, the second length is a length in the first direction of a side surface of the first region that connects the lower surface of the first region and the upper surface of the first region; The semiconductor device according to claim 1 .

7. the upper surface of the first region of the gate electrode is located above the interface between the second semiconductor region and the third semiconductor region; The semiconductor device according to claim 1 .

8. an upper surface of the second region of the gate electrode is located above an interface between the second semiconductor region and the third semiconductor region and below an upper surface of the third semiconductor region; The semiconductor device according to claim 1 .

9. a conductive portion provided below the gate electrode; a first insulating portion provided between the conductive portion and the first semiconductor region; a second insulating portion provided between the conductive portion and the gate electrode; further comprising The semiconductor device according to claim 8 .

10. the gate electrode further includes a third region in the first region, the third region containing a material different from that of the first region; The semiconductor device according to claim 1 .

11. 10. The method for manufacturing a semiconductor device according to claim 1, forming an insulating film on a surface of a trench formed by removing the upper surface of the substrate in the first direction; forming the gate electrode filling the trench; selectively removing the gate electrode in the first direction in the vicinity of the insulating film; forming an insulating layer on the gate electrode and the insulating film; A method for manufacturing a semiconductor device comprising:

12. 11. The method for manufacturing a semiconductor device according to claim 10, forming an insulating film on a surface of a trench formed by removing the upper surface of the substrate in the first direction; forming a first conductive layer on the insulating film; forming a buried portion provided on the first conductive layer and filling the trench; removing the first conductive layer and a portion of the buried portion in the first direction at different removal rates; forming a second conductive layer on the first conductive layer and the buried portion to form the gate electrode; forming an insulating layer on the gate electrode and the insulating film; A method for manufacturing a semiconductor device comprising:

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