Semiconductor cell and semiconductor device
The semiconductor cell design addresses latch-up in semiconductor integrated circuits by using overlapping back-gate portions to reduce resistance and prevent parasitic thyristor activation, ensuring circuit stability.
Patent Information
- Application Number
- JP2024110952
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2026-01-23
AI Technical Summary
There is an increasing demand for suppressing latch-up in semiconductor cells used in semiconductor integrated circuits, which is not effectively addressed by existing technologies.
The semiconductor cell design includes a first MOS region with a P-channel MOS transistor and a second MOS region with an N-channel MOS transistor, featuring back-gate portions that overlap with power and ground lines to reduce resistance and suppress latch-up by sharing back-gate portions between adjacent cells.
This design effectively suppresses latch-up by reducing resistance values in the parasitic thyristor, preventing through currents and maintaining circuit stability.
Smart Images
Figure 2026010867000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor device. [Background technology]
[0002] In the design of semiconductor integrated circuits, an EDA (Electronic Design Automation) tool is sometimes used, which automatically places semiconductor cells based on connection information of the semiconductor cells and connects the semiconductor cells (see, for example, Patent Document 1). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2021-27187 A
[0004] [overview] As shown in Patent Document 1, there is an increasing demand for suppressing latch-up in semiconductor cells used in semiconductor integrated circuits.
[0005] A semiconductor cell according to one embodiment of the present disclosure is used in a logic circuit. The semiconductor cell includes: a first MOS region including a P-channel MOS transistor; a second MOS region adjacent to the first MOS region in a first direction and including an N-channel MOS transistor; a first back-gate portion in the first MOS region that constitutes the back-gate of the P-channel MOS transistor; and a second back-gate portion in the second MOS region that constitutes the back-gate of the N-channel MOS transistor. The first back-gate portion has a first portion located at an end opposite the second MOS region in the first direction and a second portion extending from the first portion toward the second MOS region. The second back-gate portion has a third portion located at an end opposite the first MOS region in the first direction and a fourth portion extending from the third portion toward the first MOS region. [Brief explanation of the drawings]
[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view of an example of a semiconductor cell. [Figure 3] FIG. 3 is a diagram showing a stacked state of the semiconductor cells shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor cell shown in FIG. 2 taken along line IV-IV. [Figure 5] FIG. 5 is a cross-sectional view of the semiconductor cell shown in FIG. 2 taken along line VV. [Figure 6] FIG. 6 is a circuit diagram showing an equivalent circuit of the semiconductor cell shown in FIG. [Figure 7] FIG. 7 is a circuit diagram of a parasitic thyristor configured inside a semiconductor cell. [Figure 8] FIG. 8 is a schematic plan view of a semiconductor cell of the first modified example. [Figure 9] FIG. 9 is a cross-sectional view of the semiconductor cell shown in FIG. 8 taken along line IX-IX. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor cell shown in FIG. 8 taken along line XX. [Figure 11] FIG. 11 is a schematic plan view of a semiconductor cell of the second modified example. [Figure 12] FIG. 12 is an enlarged plan view showing a schematic configuration of a semiconductor cell of the third modified example. [Figure 13] FIG. 13 is a cross-sectional view of the semiconductor cell shown in FIG. 12 taken along line XIII-XIII. [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor cell shown in FIG. 12 taken along line XIV-XIV. [Figure 15] FIG. 15 is an equivalent circuit diagram of a semiconductor cell of the third modified example. DETAILED DESCRIPTION OF THE INVENTION
[0007] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. A MOS field effect transistor may also be simply referred to as a MOS transistor. A P-channel MOS transistor will be referred to as a PMOS transistor, and an N-channel MOS transistor will be referred to as an NMOS transistor.
[0008] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are designated by the same reference numerals, and duplicated descriptions of the same parts will be omitted as a general rule.
[0009] When referring to multiple components, such as elements and lines, that form a circuit, the term "connection" includes both mechanical connection and electrical connection, i.e., a state in which electricity flows. In other words, "connection" includes "electrical connection." In addition, in the semiconductor cell 10 shown in FIG. 2, the vertical direction is defined as the first direction y, and the horizontal direction is defined as the second direction x. In addition, in the plan views of FIGS. 1 and 2, the power supply line 21, the ground line 22, the first wiring 14, the second wiring 15, and the third wiring 16 are hatched with grid lines to facilitate understanding.
[0010] <Semiconductor device 100> Fig. 1 is a schematic plan view of a semiconductor device 100 according to an embodiment of the present disclosure. As shown in Fig. 1, in the semiconductor device 100, semiconductor cells 10 called standard cells are automatically arranged based on pre-given connection information, and power supply lines 21 and ground lines 22 (described later) of the arranged semiconductor cells 10 are connected to each other. In the semiconductor device 100, the plurality of semiconductor cells 10 are arranged side by side in a first direction y and a second direction x.
[0011] <Semiconductor cell 10> Fig. 2 is a schematic plan view of an example of a semiconductor cell 10. In the semiconductor cell 10 shown in Fig. 2, parts of the first back gate portion 31 and the second back gate portion 32 of the adjacent semiconductor cell 10 are also shown.
[0012] 2, the semiconductor cell 10 has a rectangular shape with sides extending in a first direction y and a second direction x. The length of the semiconductor cell 10 in the first direction y is a fixed length. The length of the semiconductor cell 10 in the first direction y may vary depending on the circuit configuration. In addition, the width of the semiconductor cell 10 in the second direction x, which intersects with the first direction y, in a plan view varies depending on the circuit configuration.
[0013] 2, the semiconductor cell 10 has a first MOS region 10n and a second MOS region 10p. The first MOS region 10n and the second MOS region 10p are arranged side by side in the first direction y.
[0014] In plan view, the first MOS configuration region 10n is arranged on a first side in the first direction y of the semiconductor cell 10 (upper side in FIG. 2). A PMOS transistor 11 is configured in the first MOS configuration region 10n. In plan view, the second MOS configuration region 10p is arranged on a second side in the first direction y of the semiconductor cell 10 (lower side in FIG. 2). An NMOS transistor 12 is configured in the second MOS configuration region 10p. Note that, although the first MOS configuration region 10n is configured on the first side and the second MOS configuration region 10p is configured on the second side of the semiconductor cell 10, this may be reversed.
[0015] A power supply line 21 is arranged in the first MOS region 10n. The power supply line 21 is arranged at the end opposite the second MOS region 10p in the first direction y. The power supply line 21 is elongated and extends in the second direction x. In the semiconductor cell 10, the power supply line 21 has a shape that reaches both ends of the semiconductor cell 10 in the second direction x, but is not limited to this. If the power supply line 21 has a shape that reaches both ends in the second direction x, it has the effect of facilitating connection of the power supply lines 21 to each other when the semiconductor cells 10 are lined up in the second direction x.
[0016] In addition, the power supply line 21 is provided with a first wiring 14 extending in the first direction y, and the first wiring 14 is connected to the source of the PMOS transistor 11 configured in the first MOS configuration region 10n, and supplies the power supply voltage VDD to the source of the PMOS transistor 11.
[0017] A ground line 22 is arranged in the second MOS region 10p. The ground line 22 is arranged at the end opposite the first MOS region 10n in the first direction y. The ground line 22 is elongated and extends in the second direction x. In the semiconductor cell 10, the ground line 22 has a shape that reaches both ends of the semiconductor cell 10 in the second direction x, but is not limited to this. If the ground line 22 has a shape that reaches both ends in the second direction x, it has the effect of facilitating connection of the ground lines 22 to each other when the semiconductor cells 10 are lined up in the second direction x.
[0018] In addition, the ground line 22 is provided with a second wiring 15 extending in the first direction y, and the second wiring 15 is connected to the source of the NMOS transistor 12 configured in the second MOS configuration region 10p, and supplies a ground voltage VSS to the source of the NMOS transistor 12.
[0019] A first back gate portion 31 is formed in the first MOS forming region 10n of the semiconductor cell 10. The first back gate portion 31 is the back gate of the PMOS transistor 11 formed in the first MOS forming region 10n. The first back gate portion 31 has a first portion 311 and two second portions 312.
[0020] The first portion 311 of the first back gate portion 31 is arranged on the opposite side of the first MOS forming region 10n from the second MOS forming region 10p in the first direction y. The first portion 311 has an elongated shape extending in the second direction x. The first portion 311 of the first back gate portion 31 is arranged so as to overlap with the power supply line 21 in a third direction z that intersects with the first direction y and the second direction x, and is connected to the power supply line 21 via a contact 40 described later. As a result, the power supply voltage VDD is supplied to the first back gate portion 31 from the power supply line 21.
[0021] The two second portions 312 extend from both ends of the first portion 311 in the second direction x toward the second MOS configuration region 10p. The two second portions 312 are connected to the first portion 311. Note that it is sufficient that the first portion 311 and the second portion 312 are electrically connected, and for example, in the semiconductor cell 10, the first portion 311 and the second portion 312 of the first back gate portion 31 are integrally formed by an N diffusion layer 106 described later.
[0022] In the semiconductor cell 10 shown in FIG. 2, the second portion 312 of the first back gate unit 31 extends along the first direction y, but is not limited to this. Although two second portions 312 are provided in the first MOS configuration region 10n, the number may be one, or three or more. By arranging the second portions 312 at both ends in the second direction x as shown in FIG. 2, the second portions 312 can be connected to each other when the semiconductor cells 10 are arranged in the second direction x. This allows the semiconductor cells 10 adjacent to each other in the second direction x to share the second portion 312, thereby suppressing an increase in the width of the semiconductor cell 10 in the second direction x.
[0023] A second back gate portion 32 is configured in the second MOS configuration region 10p of the semiconductor cell 10. The second back gate portion 32 is the back gate of the NMOS transistor 12 configured in the second MOS configuration region 10p. The second back gate portion 32 has a third portion 321 and two fourth portions 322.
[0024] The third portion 321 of the second back gate portion 32 is disposed on the opposite side of the second MOS region 10p from the first MOS region 10n in the first direction y. The third portion 321 has an elongated shape extending in the second direction x. The third portion 321 of the second back gate portion 32 is disposed so as to overlap with the ground line 22 in a third direction z that intersects with the first direction y and the second direction x, and is connected to the ground line 22 via a contact 40 (see FIG. 3 and other figures described below). This allows the ground voltage VSS to be supplied to the second back gate portion 32 from the ground line 22.
[0025] The two fourth portions 322 extend from both ends of the third portion 321 in the second direction x toward the first MOS configuration region 10n. The two fourth portions 322 are connected to the third portion 321. Note that the third portion 321 and the fourth portion 322 only need to be electrically connected, and may be configured to be integrally formed. For example, in the semiconductor cell 10, the third portion 321 and the fourth portion 322 of the second back gate portion 32 are integrally configured by a P diffusion layer 109 described later.
[0026] In the semiconductor cell 10 shown in FIG. 2, the fourth portion 322 of the second back gate unit 32 extends along the first direction y, but is not limited to this. Although two fourth portions 322 are provided in the second MOS configuration region 10p, the number of fourth portions 322 may be one, or three or more. By arranging the fourth portions 322 at both ends in the second direction x as shown in FIG. 2, the fourth portions 322 can be connected to each other when the semiconductor cells 10 are arranged in the second direction x. This allows the semiconductor cells 10 adjacent to each other in the second direction x to share the fourth portion 322, thereby suppressing an increase in the width of the semiconductor cell 10 in the second direction x.
[0027] Next, the stacked structure of the semiconductor cell 10 will be described with reference to the drawings. Fig. 3 is a diagram showing the stacked state of the semiconductor cell 10 shown in Fig. 2. As shown in Fig. 3, in the semiconductor cell 10, a P well 102 made of a P semiconductor is disposed on the upper surface of an N substrate 101 made of an N semiconductor. Furthermore, as shown in Fig. 3, an N well 103 made of an N semiconductor is disposed above one side (the left side in Fig. 3) of the P well 102.
[0028] In the semiconductor cell 10, the region where the N-well 103 is disposed is the first MOS region 10n. The region of the semiconductor cell 10 opposite the first MOS region 10n (the right side in FIG. 3) is the second MOS region 10p. An oxide film 10t made of SiO2 or the like is disposed on the upper surface of the semiconductor cell 10, and a power supply line 21, a ground line 22, a first wiring 14, a second wiring 15, a third wiring 16, and a gate wiring 17 are disposed above the oxide film 10t (see FIG. 2, etc.). In addition, contacts 40 are provided in the oxide film 10t to connect each wiring to each diffusion layer described later.
[0029] P diffusion layers 104 and 105 are arranged on the upper surface of the first MOS configuration region 10n of the semiconductor cell 10. The P diffusion layer 104 forms the source of the PMOS transistor 11, and the P diffusion layer 105 forms the drain of the PMOS transistor 11. An N diffusion layer 106 is also arranged in the first MOS configuration region 10n. The N diffusion layer 106 has a higher concentration of N dopant than the N well 103, and has a lower electrical resistance than the N well 103. The first back gate portion 31 is formed by the N diffusion layer 106.
[0030] N diffusion layers 107 and 108 are arranged on the upper surface of the second MOS configuration region 10p of the semiconductor cell 10. The N diffusion layer 107 forms the source of the NMOS transistor 12, and the N diffusion layer 108 forms the drain of the NMOS transistor 12. A P diffusion layer 109 is also arranged in the second MOS configuration region 10p. The P diffusion layer 109 has a higher concentration of P dopant than the P well 102, and has a lower electrical resistance than the P well 102. The second back gate portion 32 is formed by the P diffusion layer 109.
[0031] The stacked structure of the semiconductor cell 10 is not limited to the above-described structure. For example, an N-well may be disposed on top of a P-substrate, and a P-well may be disposed on one side of the N-well. In this structure, the portion where the P-well is disposed is the second MOS region, and the remaining portion is the first MOS region.
[0032] Alternatively, a P-well may be disposed above one side of an N-substrate. In this configuration, the portion where the P-well is disposed is the second MOS region, and the remainder is the first MOS region. Furthermore, an N-well may be disposed above one side of the P-substrate. In this configuration, the portion where the N-well is disposed is the first MOS region, and the remainder is the second MOS region. In such a semiconductor cell with a different stacked configuration from that described above, the first MOS region and the second MOS region have the same configuration as the semiconductor cell 10 described above.
[0033] Here, detailed configurations of the first MOS configuration region 10n and the second MOS configuration region 10p of the semiconductor cell 10 will be described with reference to the drawings. Fig. 4 is a cross-sectional view taken along line IV-IV of the semiconductor cell 10 shown in Fig. 2. Fig. 5 is a cross-sectional view taken along line VV of the semiconductor cell 10 shown in Fig. 2. Fig. 6 is a circuit diagram showing an equivalent circuit of the semiconductor cell 10 shown in Fig. 2.
[0034] 2 and 4, the first MOS configuration region 10n is provided with two P diffusion layers 104 extending in the first direction y. The two P diffusion layers 104 are spaced apart in the second direction x. In addition, one P diffusion layer 105 is spaced apart from each of the two P diffusion layers 104 in the second direction x between the two P diffusion layers 104. In FIG. 4, the P diffusion layer 104 on the left side is referred to as P diffusion layer 1041, and the P diffusion layer 104 on the opposite side is referred to as P diffusion layer 1042.
[0035] A part of the N well 103 is disposed between the P diffusion layer 1041 and the P diffusion layer 105 on the upper surface of the first MOS configuration region 10n of the semiconductor cell 10. In this way, on the upper surface of the first MOS configuration region 10n, the P diffusion layer 1041, the P diffusion layer 105, and the N well 103 disposed therebetween form a PMOS transistor 111. In the PMOS transistor 111, the P diffusion layer 1041 is the source, the P diffusion layer 105 is the drain, and a gate wiring 171 (described later) disposed between the P diffusion layer 1041 and the P diffusion layer 105 is the gate.
[0036] As shown in FIGS. 2, 4, etc., a first wiring 14 and a third wiring 16 are arranged above the first MOS configuration region 10n. The first wiring 14 is a wiring extending in the first direction y from the power supply line 21. The first wiring 14 is also connected to a P diffusion layer 1041 that configures the source of the PMOS transistor 111 by a contact 40. As a result, the power supply voltage VDD is supplied to the source of the PMOS transistor 111 via the first wiring 14.
[0037] The third wiring 16 is connected to the P diffusion layer 105 that constitutes the drain of the PMOS transistor 111 via a contact 40. The third wiring 16 is connected to the N diffusion layer 108 that constitutes the drain of the NMOS transistor 122 in the second MOS configuration region 10p. A gate wiring 17 (referred to as gate wiring 171) made of polysilicon or the like is disposed above the gate of the PMOS transistor 111. The gate wiring 171 is capable of applying a voltage to the gate of the PMOS transistor 111. As shown in FIG. 6, the gate wiring 171 is an input terminal to which one of the input signals is input.
[0038] Furthermore, a PMOS transistor 112 having a P diffusion layer 1042 as a source and a P diffusion layer 105 as a drain is configured in the first MOS configuration region 10n of the semiconductor cell 10. On the upper surface of the first MOS configuration region 10n, a part of the N well 103 is disposed between the P diffusion layer 1042 and the P diffusion layer 105, and this part serves as a gate.
[0039] In the first MOS region 10n, the first wiring 14 is connected to the P diffusion layer 1042 that constitutes the source of the PMOS transistor 112 by the contact 40. As a result, the source of the PMOS transistor 112 is supplied with the power supply voltage VDD.
[0040] The drain of the PMOS transistor 112 is common to the drain of the PMOS transistor 111. In other words, the P diffusion layer 105 also serves as the drain of the PMOS transistor 112.
[0041] Moreover, a gate wiring 17 (hereinafter referred to as gate wiring 172) made of polysilicon or the like is disposed above the gate of the PMOS transistor 112. The gate wiring 172 is capable of applying a voltage to the gate of the PMOS transistor 112. As shown in FIG. 6, the gate wiring 172 is an input terminal to which one of the input signals is input.
[0042] 4, two second portions 312 of the first back gate portion 31 are arranged in the first MOS region 10n. The two second portions 312 are arranged on the outer sides of the two P diffusion layers 1041, 1042 in the second direction x. As described above, the second portion 312 of the first back gate portion 31 is connected to the power supply line 21. Therefore, in the first MOS region 10n of the semiconductor cell 10, each of the two second portions 312 of the first back gate portion 31 may be configured to contact (butt) the P diffusion layers 1041, 1042.
[0043] 2 and 5, N diffusion layers 107, 108, and 110 extending in the first direction y are provided in the second MOS region 10p. The N diffusion layers 107, 108, and 110 are spaced apart from each other in the second direction x. In the second MOS region 10p, the N diffusion layer 110 is disposed between the N diffusion layer 107 and the N diffusion layer 108.
[0044] In the first MOS configuration region 10n of the semiconductor cell 10, a part of the P well 102 is disposed between the N diffusion layer 107 and the N diffusion layer 110. In this way, in the second MOS configuration region 10p, the N diffusion layer 107, the N diffusion layer 110, and the P well 102 disposed therebetween form an NMOS transistor 122. In the NMOS transistor 122, the N diffusion layer 107 is the source, the N diffusion layer 110 is the drain, and the gate wiring 171 disposed between the N diffusion layer 107 and the N diffusion layer 110 is the gate.
[0045] 2, 5, etc., a second wiring 15 and a third wiring 16 are arranged above the second MOS configuration region 10p. The second wiring 15 is a wiring extending from the ground line 22, and the voltage of the second wiring 15 is the same as that of the ground line 22, that is, the ground voltage VSS. The second wiring 15 is also connected to the N diffusion layer 107 that configures the source of the NMOS transistor 122 by a contact 40. As a result, the ground voltage VSS is supplied to the source of the NMOS transistor 122.
[0046] Moreover, a gate wiring 171 is disposed above the gate of the NMOS transistor 122. The gate wiring 171 is capable of applying a voltage to the gate of the NMOS transistor 122. In the semiconductor cell 10, the same input signal input to the gate wiring 171 is input to the gate of the PMOS transistor 111 and the gate of the NMOS transistor 122.
[0047] An NMOS transistor 122 having the N diffusion layer 110 as its source and the N diffusion layer 108 as its drain is configured in the second MOS configuration region 10p of the semiconductor cell 10. On the upper surface of the second MOS configuration region 10p, a part of the P well 102 is disposed between the N diffusion layer 110 and the N diffusion layer 108, and this part serves as the gate.
[0048] In the second MOS region 10p, the third wiring 16 is connected to the N diffusion layer 108 that constitutes the drain of the NMOS transistor 122 via the contact 40. That is, the third wiring 16 connects the P diffusion layer 105 that is the common drain of the PMOS transistors 111 and 112 in the first MOS region 10n to the N diffusion layer 108 that is the drain of the second MOS region 10p. The third wiring 16 is an output terminal.
[0049] In the NMOS transistors 121 and 122, the source and drain are both formed of N diffusion layers. The N diffusion layer 110 is used as the source and drain. That is, in the NMOS transistor 121, the N diffusion layer 110 is the drain, and in the NMOS transistor 122, the N diffusion layer 110 is the source. With this configuration, the NMOS transistors 121 and 122 are connected in series, with the drain of the NMOS transistor 121 and the source of the NMOS transistor 122 connected together.
[0050] A gate wiring 171 is disposed above the gate of the NMOS transistor 121. The gate wiring 171 is capable of applying a voltage to the gate of the NMOS transistor 121. In the semiconductor cell 10, the same input signal input to the gate wiring 171 is input to the gate of the PMOS transistor 111 and the gate of the NMOS transistor 112.
[0051] Furthermore, a gate wiring 172 is disposed above the gate of the NMOS transistor 122. The gate wiring 172 is capable of applying a voltage to the gate of the NMOS transistor 122. In the semiconductor cell 10, the same input signal input to the gate wiring 172 is input to the gate of the PMOS transistor 112 and the gate of the NMOS transistor 122.
[0052] 5, the fourth portion 322 of the second back gate portion 32 is disposed in the second MOS region 10p. The two fourth portions 322 are disposed at both ends of the second MOS region 10p in the second direction x. As described above, the fourth portion 322 of the second back gate portion 32 is connected to the ground line 22.
[0053] In the second MOS region 10p of the semiconductor cell 10, the fourth portion 322 of the second back gate unit 32 may be configured to be in contact with (butt against) the N diffusion layer 107 connected to the ground line 22. Note that in the second MOS region 10p, the voltage of the N diffusion layer 108 is not always the same as the ground voltage VSS. Therefore, the fourth portion 322 of the second back gate unit 32 is arranged so as not to be in contact with the N diffusion layer 108.
[0054] A logic circuit configured with a semiconductor cell 10 will be described. As shown in FIG. 6, the semiconductor cell 10 is a NAND circuit. That is, in the semiconductor cell 10, the sources of two PMOS transistors 111 and 112 are connected to a power supply line 21 via a first wiring 14. As a result, a power supply voltage VDD is supplied to the sources of the two PMOS transistors 111 and 112. The drains of the two PMOS transistors 111 and 112 are common. That is, in the logic circuit shown in FIG. 6, the drains of the two PMOS transistors 111 and 112 are connected. The common drain of the PMOS transistors 111 and 112 is connected to the drain of an NMOS transistor 122 via a third wiring 16.
[0055] <Latch-up> Next, latch-up in the semiconductor cell 10 will be described. When a P diffusion layer, an N diffusion layer, a P well, and an N well are arranged closely to each other, as in the semiconductor cell 10, a PNP transistor and an NPN transistor are formed by the respective semiconductor layers. The PNP transistor and NPN transistor formed in this way are referred to as a parasitic PNP transistor and a parasitic NPN transistor.
[0056] In the semiconductor cell 10, a parasitic thyristor may be formed by a parasitic PNP transistor and a parasitic NPN transistor, and when the parasitic thyristor is turned on, a latch-up occurs in which a through current flows. Here, the parasitic thyristor will be described with reference to the drawings.
[0057] 7 is a circuit diagram of a parasitic thyristor T1 formed inside the semiconductor cell 10. For example, a parasitic PNP transistor Q1 is formed by a P diffusion layer 104, an N well 103, and a P well 102. A parasitic NPN transistor Q2 is formed by an N diffusion layer 107, a P well 102, and an N well 103.
[0058] In the parasitic PNP transistor Q1, the P diffusion layer 104 is the emitter, the N well 103 is the base, and the P well 102 is the collector. In the parasitic NPN transistor Q2, the N diffusion layer 107 is the emitter, the P well 102 is the base, and the N well 103 is the collector.
[0059] 3 and 7, the emitter of the parasitic PNP transistor Q1 is connected to the power supply line 21 which is connected to the P diffusion layer 104. Furthermore, the N well 103 which is the base of the parasitic PNP transistor Q1 is connected to the N diffusion layer 106 which is connected to the power supply line 21. That is, the base of the parasitic PNP transistor Q1 is connected to the power supply line 21 via a first resistance R1 formed by the N well 103. The P well 102 which is the collector of the parasitic PNP transistor Q1 is connected to the P diffusion layer 109 which is connected to the ground line 22. That is, the collector of the parasitic PNP transistor Q1 is connected to the ground line 22 via a second resistance R2 formed by the P well 102.
[0060] 3 and 7, N well 103, which is the collector of parasitic NPN transistor Q2, is connected to N diffusion layer 106, which is connected to power supply line 21. That is, the collector of parasitic NPN transistor Q2 is connected to power supply line 21 via first resistor R1 formed by N well 103. N well 103, which is the collector of parasitic NPN transistor Q2, is the base of parasitic PNP transistor Q1. That is, the collector of parasitic NPN transistor Q2 is connected to the base of parasitic PNP transistor Q1.
[0061] The base of the parasitic NPN transistor Q2 is the P-well 102 and is connected to the collector of the parasitic PNP transistor Q1, which is also the P-well 102. That is, in the semiconductor cell 10 configured as shown in FIG. 3, the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 form a parasitic thyristor T1 (see FIG. 7).
[0062] The parasitic thyristor of the semiconductor cell 10 will now be described. When the parasitic PNP transistor Q1 turns on, a current is supplied from the collector of the parasitic PNP transistor Q1 to the base of the parasitic NPN transistor Q2, switching the parasitic NPN transistor Q2 on. At this time, a current flows from the collector to the emitter of the parasitic NPN transistor Q2, drawing current from the base of the parasitic PNP transistor Q1 and holding the parasitic PNP transistor Q1 on. This causes latch-up, in which both the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 are held on.
[0063] In addition, when the parasitic NPN transistor Q2 turns on, the parasitic PNP transistor Q1 of the parasitic thyristor T1 turns on. This causes a large amount of current to flow from the collector of the parasitic PNP transistor Q1 to the base of the parasitic NPN transistor Q2. This causes latch-up, in which both the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 are held on.
[0064] In the semiconductor cell 10, for example, by keeping the resistance value of the first resistor R1 low, it is possible to keep the voltage rise between the emitter and base of the parasitic PNP transistor Q1 low when a current due to noise flows, and as a result, it is possible to suppress latch-up that occurs when the parasitic PNP transistor Q1 is turned on.
[0065] Furthermore, by keeping the resistance value of the second resistor R2 low, it is possible to keep the voltage rise between the base and emitter of the parasitic NPN transistor Q2 low when a current due to noise flows, thereby suppressing latch-up that occurs when the parasitic NPN transistor Q2 is turned on.
[0066] That is, the occurrence of latch-up can be suppressed by keeping the resistance values of the first resistor R1 and the second resistor R2 low in the semiconductor cell 10. Here, a configuration for keeping the first resistor R1 and the second resistor R2 low in the semiconductor cell 10 will be described.
[0067] The first resistor R1 is formed by an N well 103 that connects the base of the parasitic PNP transistor Q1 and an N diffusion layer 106 that is connected to the power supply line 21. The resistance value of the first resistor R1 can be reduced by shortening the distance between the boundary 13 between the first MOS region 10n and the second MOS region 10p and the first back gate portion 31.
[0068] 2, in the semiconductor cell 10, the second portion 312 of the first back gate portion 31 is configured to be close to the boundary 13 between the first MOS region 10n and the second MOS region 10p. As described above, the first back gate portion 31 is configured of the N diffusion layer 106. As a result, the distance from the second portion 312 of the first back gate portion 31 to the boundary 13 between the first MOS region 10n and the second MOS region 10p becomes the wiring distance in the N well 103. This makes it possible to reduce the resistance value of the first resistor R1 configured by the N well 103. As a result, the occurrence of latch-up due to the parasitic PNP transistor Q1 being turned on is suppressed.
[0069] The second resistor R2 is formed by a P-well 102 that connects the base of the parasitic NPN transistor Q2 to a P-diffusion layer 109 that is connected to the ground line 22. As shown in FIG. 2, in the semiconductor cell 10, the fourth portion 322 of the second back gate portion 32 is configured to be close to the boundary 13 between the first MOS region 10n and the second MOS region 10p. As described above, the second back gate portion 32 is formed by the P-diffusion layer 109. This shortens the distance from the fourth portion 322 of the second back gate portion 32 to the boundary 13 between the first MOS region 10n and the second MOS region 10p, thereby reducing the resistance value of the second resistor R2. This suppresses latch-up caused by the parasitic NPN transistor Q2 being turned on.
[0070] Furthermore, in the semiconductor cell 10, the two second portions 312 of the first back gate portion 31 are arranged at both ends in the second direction x. Furthermore, in the semiconductor cell 10, the two fourth portions 322 of the second back gate portion 32 are arranged at both ends in the second direction x. With this configuration, when the semiconductor cells 10 are arranged side by side in the second direction x, the second portions 312 of the first back gate portions 31 and the fourth portions 322 of the second back gate portions 32 of the adjacent semiconductor cells 10 are connected to each other. In other words, a configuration can be achieved in which the second portions 312 of the first back gate portions 31 and the fourth portions 322 of the second back gate portions 32 of the adjacent semiconductor cells 10 are shared (see FIGS. 1 and 2). This makes it possible to suppress an increase in the width of the semiconductor cell 10 in the second direction x.
[0071] The logic circuit configured by the semiconductor cell 10 is not limited to the NAND circuit described above. For example, the logic circuit configured by the semiconductor cell 10 can be a wide variety of logic circuits configured by a combination of PMOS transistors, NMOS transistors, and other elements, such as an inverter circuit and an AND circuit supporting multiple inputs.
[0072] <First Modification> FIG. 8 is a schematic plan view of a semiconductor cell 10A of a first modified example. FIG. 9 is a cross-sectional view of the semiconductor cell 10A shown in FIG. 8 taken along line IX-IX. FIG. 10 is a cross-sectional view of the semiconductor cell 10A shown in FIG. 8 taken along line XX. The semiconductor cell 10A of the first modified example differs from the semiconductor cell 10 in that a first conductor 51 is disposed above the second portion 312 of the first back gate portion 31 of the semiconductor cell 10A in the third direction z, and a second conductor 52 is disposed above the fourth portion 322 of the second back gate portion 32 in the third direction z. Other parts of the semiconductor cell 10A have the same configuration as the semiconductor cell 10, and therefore, substantially the same parts are denoted by the same reference numerals, and detailed description of the same parts will be omitted.
[0073] 9 , the second portion 312 of the first back gate portion 31 is configured to be spaced apart from the P diffusion layer 104. A first conductor 51 is provided above the second portion 312 of the first back gate portion 31 in the third direction z. The first conductor 51 is connected to the power supply line 21. The first conductor 51 may be made of the same material as the power supply line 21 and may be configured integrally with the power supply line 21. The first conductor 51 is connected to the second portion 312 of the first back gate portion 31 by a contact 40.
[0074] For example, even if the resistance of the N diffusion layer 106 constituting the second portion 312 increases, the resistance of the first resistor R1 is kept low because the first conductor 51, which has a resistance as low as that of the power supply line 21, is brought into contact with the second portion 312. This prevents the parasitic PNP transistor Q1 from turning on, thereby preventing the parasitic thyristor T1 from turning on.
[0075] 10 , the fourth portion 322 of the second back gate portion 32 is configured to be spaced apart from the N diffusion layer 107. A second conductor 52 is provided above the fourth portion 322 of the second back gate portion 32 in the third direction z. The second conductor 52 is connected to the ground line 22. The second conductor 52 may be made of the same material as the ground line 22 and may be configured integrally with the ground line 22. The second conductor 52 is connected to the fourth portion 322 of the second back gate portion 32 by a contact 40.
[0076] For example, even if the resistance of the P diffusion layer 109 constituting the fourth portion 322 increases, the resistance of the second resistor R2 can be kept low because the second conductor 52, which has a resistance as low as that of the ground line 22, is in contact with the fourth portion 322. This prevents the parasitic NPN transistor Q2 from turning on, thereby preventing the parasitic thyristor T1 from turning on.
[0077] As described above, even in the semiconductor cell 10A having the configuration shown in the first modified example, the resistance values of the first resistor R1 and the second resistor R2 due to the parasitic thyristor T1 can be kept low, and the turning on of the parasitic thyristor T1 due to the turning on of at least one of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2, i.e., the occurrence of latch-up, is suppressed.
[0078] <Second Modification> 11 is a schematic plan view of a semiconductor cell 10B of the second modification. In the semiconductor cell 10B of the second modification, the first conductor 61 and the second conductor 62 are different from the first conductor 61 and the second conductor 62 of the semiconductor cell 10A of the first modification. Other parts of the semiconductor cell 10B have the same configuration as the semiconductor cell 10A, and therefore, the same reference numerals are used to designate substantially the same parts, and detailed description of the same parts will be omitted.
[0079] As shown in FIG. 11 , the first conductor 61 has an extension portion 611 and a land portion 612. The extension portion 611 is elongated and extends in the first direction y, and is connected to the power line 21. The extension portion 611 is integrally formed with the power line 21 using the same material as the power line 21, and extends in the first direction y. The land portion 612 is integrally formed at the tip of the extension portion 611 using the same material as the extension portion 611. The land portion 612 has a width in the second direction x that is wider than that of the extension portion 611. This makes it possible to form the contact 40 on the land portion 612 even if the extension portion 611 is too narrow to form the contact 40 thereon.
[0080] As a result, even if the resistance of the N diffusion layer 106 constituting the second portion 312 increases, the resistance of the first resistor R1 can be kept low because the first conductor 61, which has a resistance as low as that of the power supply line 21, is in contact with the second portion 312. This prevents the parasitic PNP transistor Q1 from turning on, thereby preventing the parasitic thyristor T1 from turning on.
[0081] 11, the second conductor 62 has an extension portion 621 and a land portion 622. The extension portion 621 is elongated and extends in the first direction y, and is connected to the ground line 22. The extension portion 621 is made of the same material as the ground line 22 and is integral with the extension portion 621, and extends in the first direction y. The land portion 622 is made of the same material as the extension portion 621 and is integral with the tip of the extension portion 621. The land portion 622 has a width in the second direction x that is wider than that of the extension portion 621. This makes it possible to form a contact 40 on the land portion 622, even if the width of the extension portion 621 is too narrow to form a contact 40 thereon.
[0082] As a result, even if the resistance of the P diffusion layer 109 constituting the fourth portion 322 increases, the resistance of the second resistor R2 can be kept low because the second conductor 62, which has a resistance as low as that of the ground line 22, is in contact with the fourth portion 322. This prevents the parasitic NPN transistor Q2 from turning on, thereby preventing the parasitic thyristor T1 from turning on.
[0083] As described above, even in the semiconductor cell 10B having the configuration shown in the second modified example, the resistance values of the first resistor R1 and the second resistor R2 due to the parasitic thyristor T1 can be kept low, and the turning on of the parasitic thyristor T1 due to the turning on of at least one of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2, i.e., the occurrence of latch-up, is suppressed.
[0084] In this modification, the land portion 612 of the first conductor 61 and the land portion 622 of the second conductor 62 are both configured to be provided at the tip ends of the extension portions 611 and 621, but this is not limitative and they may be formed in the intermediate portions. Also, a plurality of land portions 612 and 622 may be formed at the tip and intermediate portions.
[0085] <Third Modification> FIG. 12 is an enlarged plan view showing a schematic configuration of a semiconductor cell 10C of a third modified example. FIG. 13 is a cross-sectional view of the semiconductor cell 10C shown in FIG. 12 taken along line XIII-XIII. FIG. 14 is a cross-sectional view of the semiconductor cell 10C shown in FIG. 12 taken along line XIV-XIV. FIG. 15 is an equivalent circuit diagram of the semiconductor cell 10C of the third modified example. The semiconductor cell 10C of the third modified example has a power supply line 21, a ground line 22, a first back gate portion 31C, a second back gate portion 32C, a first wiring 14C, a second wiring 15C, and a third wiring 16C. The semiconductor cell 10C of the third modified example has a layer structure similar to that of the semiconductor cell 10, although the arrangement is different. Therefore, in the semiconductor cell 10C, parts that are substantially the same as those of the semiconductor cell 10 are designated by the same reference numerals, and detailed description thereof will be omitted.
[0086] In the semiconductor cell 10C of the third modification, the power supply line 21 and the ground line 22 have the same configuration as the power supply line 21 and the ground line 22 shown in Fig. 2 etc. Also, like the semiconductor cell 10, the semiconductor cell 10C has a first MOS configuration region 10n and a second MOS configuration region 10p.
[0087] 13, the upper surface of the first MOS region 10n has a P diffusion layer 104C and a P diffusion layer 105C. The P diffusion layer 104C has the same configuration as the P diffusion layer 104 of the semiconductor cell 10. That is, the P diffusion layer 104C configures the sources of the PMOS transistors 113 and 114 configured in the first MOS region 10n, and the P diffusion layer 105C configures the drains of the PMOS transistors 113 and 114.
[0088] In the semiconductor cell 10C, the P diffusion layer 104C is disposed in the center in the second direction x. At both ends of the P diffusion layer 104C in the second direction x, a portion of the N well 103 is exposed from the upper surface. Two P diffusion layers 105C are disposed at both ends of the P diffusion layer 104C in the second direction x, sandwiching the exposed portion of the N well 103. In FIG. 13 , the P diffusion layer 105C disposed on the left side is referred to as P diffusion layer 1051, and the P diffusion layer 105C on the right side is referred to as P diffusion layer 1052.
[0089] 12, the third wirings 16C are arranged on the left and right sides in the second direction x. The third wiring 16C arranged on the left side is referred to as third wiring 161, and the third wiring 16C arranged on the right side is referred to as third wiring 162. Furthermore, in the semiconductor cell 10C shown in FIG. 12, the gate wirings 17C are arranged on the left and right sides in the second direction x. The gate wiring 17C arranged on the left side is referred to as gate wiring 173, and the gate wiring 17C arranged on the right side is referred to as gate wiring 174.
[0090] In the first MOS configuration region 10n of the semiconductor cell 10C, a PMOS transistor 113 is configured by the P diffusion layer 1051, the P diffusion layer 104C, and a part of the N well 103. In the PMOS transistor 113, the P diffusion layer 104C is the source, the P diffusion layer 1051 is the drain, and the gate wiring 173 arranged between the P diffusion layer 104C and the P diffusion layer 1051 is the gate.
[0091] The P diffusion layer 104C is connected to a first wiring 14C, which is connected to the power supply line 21, via a contact 40. This allows the power supply voltage to be supplied to the P diffusion layer 104C. A third wiring 161 is connected to the P diffusion layer 1051 of the PMOS transistor 113 via the contact 40. The third wiring 161 is connected to an N diffusion layer 1081 that forms the drain of an NMOS transistor 123, which will be described later.
[0092] The gate wiring 173 is also the gate of an NMOS transistor 123, which will be described later. As shown in Fig. 15, the gate wiring 173 is an input terminal to which an input signal IN is input.
[0093] In the first MOS configuration region 10n of the semiconductor cell 10C, a PMOS transistor 114 is configured by the P diffusion layer 1052, the P diffusion layer 104C, and a part of the N well 103. In the PMOS transistor 114, the P diffusion layer 104C is the source, the P diffusion layer 1052 is the drain, and the gate wiring 174 arranged between the P diffusion layer 104C and the P diffusion layer 1052 is the gate.
[0094] The P diffusion layer 104C is common to the PMOS transistor 113. A third wiring 162 is connected to the P diffusion layer 1052 via a contact 40. The third wiring 162 is connected to an N diffusion layer 1082 that constitutes the drain of an NMOS transistor 124, which will be described later.
[0095] 12, in the first MOS configuration region 10n of the semiconductor cell 10C, the PMOS transistor 113 and the PMOS transistor 114 share a common source. That is, in the equivalent circuit shown in FIG. 15, the PMOS transistor 113 and the PMOS transistor 114 have their respective sources connected to the power supply line 21 and are connected in parallel.
[0096] 13, a first back gate portion 31C formed of an N diffusion layer 106C is disposed in the first MOS region 10n. The first back gate portion 31C has a first portion 311 and a second portion 312C. The first portion 311 of the first back gate portion 31C corresponds to the first portion 311 of the first back gate portion 31. The second portion 312C extends from the first portion 311 toward the second MOS region 10p.
[0097] As described above, in the first MOS region 10n, the P diffusion layer 104C that constitutes the sources of the PMOS transistors 113 and 114 is formed in the middle portion in the second direction x. Since the P diffusion layer 104C has a width in the second direction x, the second portion 312C of the first back gate unit 31C extends from the middle portion of the first portion 311 in the second direction x toward the second MOS region 10p.
[0098] The second portion 312C may be configured to have the same potential as the P diffusion layer 104C and to be in contact (butting) with it. This configuration shortens the distance from the boundary between the first MOS region 10n and the second MOS region 10p to the first back gate portion 31C, thereby reducing the first resistance R1 of the parasitic thyristor T1. This prevents the parasitic PNP transistor Q1 from being turned on, thereby preventing the parasitic thyristor T1 from being turned on.
[0099] 14, the upper surface of the second MOS region 10p has an N diffusion layer 107C and an N diffusion layer 108C. The N diffusion layer 107C has the same configuration as the N diffusion layer 107 of the semiconductor cell 10. That is, the N diffusion layer 107C configures the sources of the NMOS transistors 123 and 124 configured in the second MOS region 10p, and the N diffusion layer 108C configures the drains of the NMOS transistors 123 and 124.
[0100] In the semiconductor cell 10C, the N diffusion layer 107C is disposed in the center in the second direction x. At both ends of the N diffusion layer 107C in the second direction x, a portion of the P well 102 is exposed from the upper surface. Two N diffusion layers 108C are disposed at both ends of the N diffusion layer 107C in the second direction x, sandwiching the exposed portion of the P well 102. In FIG. 14 , the N diffusion layer 108C disposed on the left side is referred to as N diffusion layer 1081, and the N diffusion layer 108C on the right side is referred to as N diffusion layer 1082.
[0101] In the second MOS configuration region 10p of the semiconductor cell 10C, an NMOS transistor 123 is configured by the N diffusion layer 1081, the N diffusion layer 107C, and a part of the P well 102. In the NMOS transistor 123, the N diffusion layer 107C is the source, the N diffusion layer 1081 is the drain, and the gate wiring 173 arranged between the N diffusion layer 107C and the N diffusion layer 1081 is the gate.
[0102] The N diffusion layer 107C is connected to the second wiring 15C, which is connected to the ground line 22, via the contact 40. This allows the ground voltage to be supplied to the N diffusion layer 107C. Furthermore, the third wiring 161 is connected to the N diffusion layer 1081 of the NMOS transistor 123 via the contact 40. As shown in FIG. 15, the drain of the PMOS transistor 113 in the first MOS configuration region 10n and the drain of the NMOS transistor 123 in the second MOS configuration region 10p are connected.
[0103] 15, the gate of the PMOS transistor 113 in the first MOS configuration region 10n and the gate of the NMOS transistor 123 in the second MOS configuration region 10p are common. In other words, the PMOS transistor 113 and the NMOS transistor 123 are connected in series by connecting their drains to each other and their gates to each other.
[0104] NMOS transistor 124 is configured by N diffusion layer 1082, N diffusion layer 107C, and part of P well 102. In NMOS transistor 123, N diffusion layer 107C is the source, N diffusion layer 1082 is the drain, and gate wiring 174 disposed between N diffusion layer 107C and N diffusion layer 1081 is the gate.
[0105] The N diffusion layer 107C is common to the NMOS transistor 123. The third wiring 162 is connected to the N diffusion layer 1082 of the NMOS transistor 124 via a contact 40. As shown in FIG. 15, the drain of the PMOS transistor 114 in the first MOS configuration region 10n is connected to the drain of the NMOS transistor 124 in the second MOS configuration region 10p.
[0106] 15, the gate of the PMOS transistor 114 in the first MOS configuration region 10n and the gate of the NMOS transistor 124 in the second MOS configuration region 10p are common. That is, the PMOS transistor 114 and the NMOS transistor 124 are connected in series by connecting their drains to each other and their gates to each other. In addition, the gate wiring 174 is connected to the third wiring 161 via the contact 40.
[0107] 14, a second back gate portion 32C formed of a P diffusion layer 109C is disposed in the second MOS region 10p. The second back gate portion 32C has a third portion 321 and a fourth portion 322C. The third portion 321 of the second back gate portion 32C corresponds to the third portion 321 of the second back gate portion 32. The fourth portion 322C extends from the third portion 321 toward the first MOS region 10n.
[0108] As described above, in the second MOS region 10p, the N diffusion layer 107C that constitutes the sources of the NMOS transistor 123 and the NMOS transistor 124 is formed in the middle portion in the second direction x. Since the N diffusion layer 107C has a width in the second direction x, the fourth portion 322C of the second back gate unit 32C extends from the middle portion of the third portion 321 in the second direction x toward the first MOS region 10n.
[0109] The fourth portion 322C may be configured to have the same potential as the N diffusion layer 107C and to be in contact (butting) with it. This configuration shortens the distance from the boundary between the first MOS region 10n and the second MOS region 10p to the second back gate portion 32C, thereby reducing the second resistance R2 of the parasitic thyristor T1. This prevents the parasitic NPN transistor Q2 from being turned on, thereby preventing the parasitic thyristor T1 from being turned on.
[0110] 12, the PMOS transistor 113 and the NMOS transistor 123 form an inverter INV1, and the PMOS transistor 114 and the NMOS transistor 124 form another inverter INV2.
[0111] In the inverter INV1, the gate wiring 173 is an input terminal and the third wiring 161 is an output wiring. In the inverter INV2, the gate wiring 174 is an input terminal and the third wiring 162 is an output wiring. The third wiring 161 and the gate wiring 174 are connected, and the output of the inverter INV1 is input to the inverter INV2. In this way, the semiconductor cell 10C forms a circuit in which the inverter INV1 and the inverter INV2 are connected in series.
[0112] As described above, even in the semiconductor cell 10C having the configuration shown in the third modified example, the resistance values of the first resistor R1 and the second resistor R2 due to the parasitic thyristor T1 can be kept low, and the turning on of the parasitic thyristor T1 due to the turning on of at least one of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2, i.e., the occurrence of latch-up, is suppressed.
[0113] In the semiconductor cell 10C of the third modification, a conductor may be disposed so as to overlap the second portion 312C of the first back gate portion 31C in the third direction z. In this case, the second portion 312C and the conductor are connected at least at one point via the contact 40. As a result, even if the resistance value of the N diffusion layer 106 constituting the second portion 312C increases, the first conductor 61, which has a resistance as low as that of the power supply line 21, is brought into contact with the second portion 312C, thereby keeping the resistance value of the first resistor R1 low.
[0114] Furthermore, a conductor may be disposed so as to overlap the fourth portion 322C of the second back gate portion 32C in the third direction z. In this case, the fourth portion 322C and the conductor are connected at least at one point via the contact 40. This allows the resistance value of the second resistor R2 to be kept low.
[0115] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.
[0116] <Additional Notes> The semiconductor cells (10, 10A, 10B, 10C) described above are used in logic circuits. The semiconductor cells (10, 10A, 10B, 10C) include a first MOS configuration region (10n) in which P-channel MOS transistors (11, 111, 112, 113, 114) are arranged, a second MOS constituent region (10p) arranged adjacent to the first MOS constituent region (11n) in the first direction (y) and having N-channel MOS transistors (12, 122, 122, 123, 124) arranged therein; a first back gate portion (31, 31C) arranged in the first MOS configuration region (10n) and configuring the back gate of a P-channel MOS transistor (11, 111, 112, 113, 114); a second back gate portion (32, 32C) disposed in a second MOS configuration region (10p) and configuring a back gate of an N-channel MOS transistor (12, 122, 122, 123, 124); The first back gate portion (31, 32C) is a first portion (311, 311C) configured to be arranged at an end opposite to the second MOS component region (10p) in a first direction (y); a second portion (312, 312C) configured to extend from the first portion (311, 311C) toward the second MOS component region (10p); The second back gate portion (32, 32C) is a third portion (321, 321C) configured to be arranged at an end opposite to the first MOS component region (10n) in the first direction (y); and a fourth portion (322, 322C) configured to extend from the third portion (321, 321C) toward the first MOS forming region (10n), which is a configuration (first configuration).
[0117] In the semiconductor cell (10, 10A, 10B) of the first configuration, the second portion (322) is configured (second configuration) to be connected to at least one of both ends of the first portion (321) in a second direction (x) that intersects with the first direction (y).
[0118] In the semiconductor cell (10C) of the first configuration, the second portion (322C) is configured (third configuration) to extend from the middle of the first portion (321) in a second direction (y) intersecting the first direction (x) toward the second MOS configuration region (10p).
[0119] In a semiconductor cell (10, 10A, 10B, 10C) having any of the first to third configurations, the second portion (312, 312C) is adjacent to the source of the P-channel MOS transistor (11, 111, 112, 113, 114) in a second direction (x) intersecting the first direction (y) and is electrically connected to it (fourth configuration).
[0120] In a semiconductor cell (10, 10A, 10B, 10C) having any of the first to fourth configurations, the fourth portion (322, 322C) is configured (fifth configuration) to be connected to at least one of both ends of the third portion (321) in a second direction (x) that intersects with the first direction (y).
[0121] In a semiconductor cell (10C) having any of the first to fourth configurations, the fourth portion (322C) has a configuration (sixth configuration) in which it extends from the middle of the third portion (321) in the second direction (x) intersecting the first direction (y) toward the first MOS configuration region (10n).
[0122] In a semiconductor cell (10, 10A, 10B, 10C) having any of the first to sixth configurations, the fourth region (322, 322C) is adjacent to the source of the N-channel MOS transistor (12, 121, 122, 123, 124) in a second direction (x) intersecting the first direction (y) and is electrically connected to it (seventh configuration).
[0123] In the semiconductor cell (10, 10A, 10B, 10C) having any one of the first to seventh configurations, the semiconductor cell (10, 10A, 10B, 10C) has a first conductor (51, 61) configured to overlap at least the second portion (312, 312C) of the first back gate portion (31, 31C) in a third direction (z) intersecting the first direction (y) and the second direction (x), The second portions (312, 312C) and the first conductors (51, 61) are electrically connected (eighth configuration).
[0124] In the semiconductor cell (10, 10A, 10B, 10C) having any one of the first to eighth configurations, a second conductor (52, 62) is configured to overlap at least a fourth portion (322, 322C) of the second back gate portion (32, 32C) in a third direction (z) intersecting the first direction (y) and the second direction (x), The fourth portion (322, 322C) and the second conductor (52, 62) are electrically connected (ninth configuration).
[0125] The semiconductor device (100) described above has a configuration (tenth configuration) in which semiconductor cells (10, 10A, 10B, 10C) having any one of the first to ninth configurations are arranged. [Explanation of symbols]
[0126] 100 Semiconductor device 10, 10A, 10B, 10C semiconductor cells 10n 1st MOS configuration area 10p 2nd MOS configuration area 10t oxide film 101 N Substrate 102 P well 103 N-well 104, 104C, 105, 105C, 1051, 1052 P diffusion layer 106 N diffusion layer 107, 107C, 1071, 1072, 108, 108C, 110 N diffusion layer 109 P diffusion layer 11, 111, 112, 113, 114 PMOS transistors 12, 122, 122, 123, 124 NMOS transistors 13 Boundary 14, 14C 1st wiring 15, 15C 2nd wiring 16, 16C 3rd wiring 17, 17C, 171, 172, 173, 174 Gate wiring 21 Power Line 22 Ground Line 30 Composite Cells 31, 31C First back gate section 311, 311C Part 1 312, 312C 2nd part 32, 32C Second back gate section 321, 321C 3rd part 322, 322C 4th part 40 Contacts 51 First conductor 52 Second Conductor 61 First Conductor 611 Extension section 612 Land Department 62 Second Conductor 621 Extension section 622 Land Department Q1 Parasitic PNP transistor Q2 Parasitic NPN transistor T1 parasitic thyristor R1 First resistor R2 2nd resistor
Claims
1. In a semiconductor cell used in a logic circuit, a first MOS region in which a P-channel MOS transistor is arranged; a second MOS region arranged adjacent to the first MOS region in a first direction and having an N-channel MOS transistor arranged therein; a first back gate portion disposed in the first MOS configuration region and configuring a back gate of the P-channel MOS transistor; a second back gate portion disposed in the second MOS configuration region and configuring a back gate of the N-channel MOS transistor; The first back gate portion is a first portion configured to be disposed at an end opposite to the second MOS configuration region in the first direction; a second portion configured to extend from the first portion toward the second MOS configuration region, The second back gate portion is a third portion configured to be disposed at an end opposite to the first MOS configuration region in the first direction; a fourth portion configured to extend from the third portion toward the first MOS configuration region.
2. The semiconductor cell according to claim 1 , wherein the second portion is configured to be connected to at least one of both ends of the first portion in a second direction intersecting the first direction.
3. 2. The semiconductor cell according to claim 1, wherein the second portion is configured to extend from a middle portion of the first portion in a second direction intersecting the first direction toward the second MOS forming region.
4. 2 . The semiconductor cell according to claim 1 , wherein the second portion is configured to be adjacent to the source of the P-channel MOS transistor in a second direction intersecting the first direction and to be electrically connected to the source.
5. The semiconductor cell according to claim 1 , wherein the fourth portion is configured to be connected to at least one of both ends of the third portion in a second direction intersecting the first direction.
6. 2. The semiconductor cell according to claim 1, wherein the fourth portion is configured to extend from a middle portion of the third portion in a second direction intersecting the first direction toward the first MOS forming region.
7. The semiconductor cell according to claim 1 , wherein the fourth portion is adjacent to the source of the N-channel MOS transistor in the first direction and is electrically connected to the source.
8. a first conductor configured to overlap at least the second portion of the first back gate portion in the first direction and a third direction intersecting with a second direction intersecting with the first direction, The semiconductor cell according to claim 1 , wherein the second portion and the first conductor are configured to be electrically connected.
9. a second conductor configured to overlap at least the fourth portion of the second back gate portion in the first direction and a third direction intersecting with a second direction intersecting with the first direction, The semiconductor cell according to claim 1 , wherein the fourth portion and the second conductor are configured to be electrically connected.
10. A semiconductor device comprising a plurality of semiconductor cells according to any one of claims 1 to 9 arranged side by side.
Citation Information
Patent Citations
JP27187A