Semiconductor memory device and refresh control method for semiconductor memory device

Abstract

To provide a semiconductor memory device, a row redundancy circuit, and a control method of the semiconductor memory device capable of suppressing unnecessary power consumption during refresh operation.SOLUTION: A semiconductor memory device (1) comprises a memory cell array (2) having a plurality of segments each provided with a plurality of normal word lines and a plurality of redundant word lines, and a row redundancy circuit (10) for controlling the activation and inactivation of the normal word lines and the redundant word lines, wherein the row redundancy circuit (10) sequentially activates the normal word lines or the redundant word lines one by one in each segment at the time of a refresh operation, thereby activating the plurality of normal word lines or the redundant word lines. When a normal word line or a redundant word line to be activated is defective during a refresh operation, the row redundancy circuit 10 does not activate the normal word line or the redundant word line in a segment including the normal word line or the redundant word line, and does not replace the normal word line or the redundant word line with another normal word line or redundant word line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device, a row redundancy circuit, and a method for controlling a semiconductor memory device. [Background technology]

[0002] DRAM (Dynamic Random Access Memory), a type of semiconductor memory device, is a volatile memory that stores information by storing an electric charge in a capacitor, and loses the stored information when power is removed. Since DRAM memory cells store information using the amount of electric charge stored in the cell capacitor, they are periodically refreshed to prevent information loss due to leakage current. In other words, all memory cells must be refreshed before information is lost due to leakage current, and the number of cycles at which all memory cells must be refreshed is determined by the standard.

[0003] In recent years, DRAM has been undergoing process miniaturization, resulting in a decrease in memory cell capacity and a decrease in the retention time of each memory cell. Therefore, in many DRAMs, the number of refresh operations is reduced by simultaneously activating more word lines during refresh operations than during normal operation (active operation) (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Publication No. 9,269,458 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent document 1 describes a semiconductor device that includes a redundancy determination circuit that, in response to a normal memory cell belonging to at least one of a first and a second memory block being replaced with a redundant memory cell in refresh mode, deactivates the normal cell region to which the original normal memory cell belongs, and activates the redundant cell region to which the replacement redundant memory cell belongs and the normal cell region to which the unreplaced normal memory cell belongs. However, in such a semiconductor device, selection of a normal memory cell belonging to the same memory mat as the redundant memory cell to be replaced is prohibited during a refresh operation, but there is a problem in that activating the redundant cell region to which the redundant memory cell to be replaced belongs and the normal cell region to which the unreplaced normal memory cell belongs during a refresh operation unnecessarily increases power consumption.

[0006] SUMMARY OF THE INVENTION In view of the above-described problems with the prior art, an object of the present invention is to provide a semiconductor memory device, a row redundancy circuit, and a method for controlling a semiconductor memory device that can suppress unnecessary power consumption during refresh operations. [Means for solving the problem]

[0007] The semiconductor memory device of the present invention comprises a memory cell array having a plurality of segments each having a plurality of normal word lines and a plurality of redundant word lines, and a row redundancy circuit that controls activation and deactivation of the normal word lines and the redundant word lines, wherein the row redundancy circuit is configured to activate the normal word lines or the redundant word lines one by one in sequence in each of the segments during a refresh operation, thereby activating a plurality of the normal word lines or the redundant word lines, and wherein the row redundancy circuit is configured to not activate the normal word line or the redundant word line in the segment including the normal word line or the redundant word line during a refresh operation if the normal word line or the redundant word line to be activated is defective, and not replace the normal word line or the redundant word line with another normal word line or the redundant word line. In the semiconductor memory device of the present invention, the row redundancy circuit is configured such that, if the normal word line or the redundant word line to be activated is defective during a refresh operation, the normal word line or the redundant word line in the segment including that normal word line or that redundant word line is not activated, and replacement with another normal word line or redundant word line is not performed.Therefore, by not activating a defective word line during a refresh operation and not replacing it, unnecessary power consumption can be suppressed. Preferably, each of the segments comprises a first predetermined number of normal word lines and a second predetermined number of the redundant word lines, the first predetermined number being greater than the second predetermined number. An address signal is input to the row redundancy circuit, with the first address indicating the address of the segment and the second address indicating the addresses of the normal word line and the redundant word line, and it is preferable that during a refresh operation, the row redundancy circuit uses the second address to specify the normal word line or the redundant word line to be activated. It is preferable that the row redundancy circuit generates an inhibit signal for inhibiting activation of the normal word line and the redundant word line for each segment during the refresh operation, and if any of the normal word lines or redundant word lines of each segment is defective, activates and inputs the inhibit signal only to the segment that includes the defective normal word line or redundant word line. The row redundancy circuit preferably includes a normal WL control circuit that generates a normal WL inhibit signal that inhibits activation of a normal word line, and a redundant WL control circuit that generates a redundant WL inhibit signal that inhibits activation of a redundant word line, and generates the inhibit signal at a high level when either the normal WL inhibit signal or the redundant WL inhibit signal is activated. The normal WL control circuit preferably includes a WL determination unit that compares an input address signal with fuse information and generates an output signal indicating whether the normal word line corresponding to the address signal is defective, and a segment determination unit that determines whether the normal word line for each segment is defective based on the output signal from the WL determination unit and generates a normal WL prohibition signal, and if the segment determination unit determines based on the output signal that the normal word line of the segment is defective, it preferably generates the normal WL prohibition signal at a high level. It is preferable that the segment determination unit decodes the fuse information of an address signal allocated to the segment and generates the normal WL inhibit signal. It is preferable that the segment determination unit latches the output signal using an address signal assigned to the segment to generate the normal WL inhibit signal. It is preferable that the segment determination unit has an AND circuit for each segment to which the signal generated by decoding the fuse information and the output signal are input, and generates the normal WL prohibition signal for each segment using the signal generated by decoding the fuse information. It is preferable that the segment determination unit has a latch circuit corresponding to the segment, the output signal is input to the latch circuit, the output signal is latched by an address signal assigned to the segment, and the normal WL prohibition signal for each segment is generated. It is preferable that the redundant WL control unit compares the input address signal with the fuse information to determine whether the redundant word line is defective, and if there is a segment in the redundant word line that is defective, outputs the redundant WL prohibition signal at a high level. The semiconductor memory device is preferably a dynamic random access memory. The row redundancy circuit of the present invention is a row redundancy circuit that controls the activation and deactivation of normal word lines and redundant word lines of a memory cell array having a plurality of segments each having a plurality of normal word lines and a plurality of redundant word lines, and is configured such that during a refresh operation, the normal word lines or the redundant word lines are activated one by one in sequence in each of the segments, so that a plurality of the normal word lines or the redundant word lines are activated, and that during a refresh operation, if the normal word line or the redundant word line to be activated is defective, the normal word line or the redundant word line is not activated in the segment including that normal word line or that redundant word line, and is not replaced with another normal word line or redundant word line. A control method for a semiconductor memory device includes a memory cell array having a plurality of segments each having a plurality of normal word lines and a plurality of redundant word lines, and a row redundancy circuit that controls activation and deactivation of the normal word lines and the redundant word lines, and the row redundancy circuit activates the normal word lines or the redundant word lines in each of the segments in sequence during a refresh operation, thereby activating a plurality of the normal word lines or the redundant word lines, and is characterized in that during a refresh operation, the normal word lines or the redundant word lines are simultaneously activated in each of the segments in sequence during the refresh operation, and all of the normal word lines and the redundant word lines in each of the segments are activated in sequence, and if the normal word line or the redundant word line to be activated is defective, the word line is not activated, and is not replaced with another normal word line or redundant word line. [Effects of the Invention]

[0008] According to the semiconductor memory device, row redundancy circuit, and method for controlling a semiconductor memory device of the present invention, unnecessary power consumption during refresh operations can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a block diagram showing an example of the configuration of a control circuit according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the configuration of a memory cell array. [Figure 3] FIG. 2 is a schematic diagram for explaining the relationship between a row redundancy circuit and a memory cell array. [Figure 4] FIG. 10 is a diagram for explaining control of a row redundancy circuit. [Figure 5] FIG. 10 is a diagram for explaining a specific example of control of a row redundancy circuit. [Figure 6] FIG. 2 is a schematic diagram illustrating a configuration of a row redundancy circuit. [Figure 7] FIG. 10 is a schematic diagram showing the configuration of a normal WL control circuit of a row redundancy circuit. [Figure 8] FIG. 2 is a schematic diagram showing the configuration of a redundant WL control circuit of a row redundant circuit. [Figure 9] FIG. 10 is a diagram showing a modification of the normal WL control circuit of the row redundancy circuit. [Figure 10] FIG. 10 is a diagram showing details of a modified example of a normal WL control circuit of a row redundancy circuit. [Figure 11] 10 is an example of a timing chart of a modified example of a normal WL control circuit of a row redundancy circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] A control circuit and a semiconductor memory device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, this embodiment is merely an example, and the present invention is not limited thereto. When identical components are to be distinguished by their positions, etc., they may be distinguished by adding "_n" (n is an integer) to the reference numeral.

[0011] (Embodiment 1) 1 shows an example of a circuit configuration according to an embodiment of the present invention. In this embodiment, a row redundancy circuit 10 is provided in a semiconductor memory device 1 such as a DRAM. In this embodiment, well-known components provided in a semiconductor memory device such as a DRAM (for example, an address buffer, a command decoder, a column decoder, an input / output interface unit, etc.) are not shown in order to simplify the explanation.

[0012] The semiconductor memory device 1 includes a memory cell array 2, a control circuit 3, and a row redundancy circuit 10. The structure of the memory cell array 2 will be described later. The memory cell array 2 is provided with a row decoder 4.

[0013] The control circuit 3 generates various control signals in synchronization with an internal clock signal, performs read / write operations on the memory cell array 2, and controls the semiconductor memory device 1 by performing redundancy operations using the row redundancy circuit 10. In this embodiment, the active operation and refresh operation by the row redundancy circuit 10 will be mainly described. The control circuit 3 inputs a refresh state signal REF indicating the refresh operation state to the row redundancy circuit 10. During a refresh operation, the control circuit 3 activates the refresh state signal REF to a high level.

[0014] The control circuit 3 also includes an address circuit (not shown) therein, which generates an address signal RA indicating a row address and also generates a redundancy enable signal RWL_EN. The redundancy enable signal RWL_EN is a signal for activating a redundancy word line, and when the redundancy enable signal RWL_EN is activated (high level), the redundancy word line can be activated. The address signal RA and the redundancy enable signal RWL_EN are input to the row redundancy circuit 10.

[0015] The row redundancy circuit 10 controls activation / deactivation of normal word lines and redundant word lines of the memory cell array 2. The row redundancy circuit 10 generates an inhibit signal HIT and a select signal RWLSEL based on a refresh state signal REF, an address signal RA, and a redundancy enable signal RWL_EN. The inhibit signal HIT is a signal for deactivating normal word lines. When the inhibit signal HIT is generated at a high level, activation of normal word lines is inhibited, and the normal word lines are deactivated (low level). The select signal RWLSEL is a signal for replacing normal word lines with redundant word lines. When the select signal RWLSEL is generated at a high level, the redundant word line to which the select signal RWLSEL generated at that high level is input is activated (high level).

[0016] The memory cell array 2 will be described with reference to Fig. 2. Note that, although the following description uses specific numbers, the present invention is not limited to these. The memory cell array 2 consists of word lines extending in a first direction and column lines extending in a second direction perpendicular to the first direction, which form the memory cells. Each word line and column line has a redundant word line and redundant column line, which can be considered a spare, to repair each word line and column line in the event of a defect. Furthermore, bit lines are formed along the column lines, and the bit lines are connected to multiple memory cells. Note that the bit lines and memory cells are omitted from the diagram.

[0017] The memory cell array 2 is divided into segments 5, each of which has a first predetermined number of normal word lines and a second predetermined number of redundant word lines, the first predetermined number being greater than the second predetermined number. In this embodiment, the memory cell array 2 has 32,756 normal word lines and 256 redundant word lines, and is composed of four segments 5. Each segment 5 includes normal word lines and redundant word lines (collectively referred to as word lines), and each segment is an area configured so that only one word line is activated during a refresh operation. Each segment 5 is configured to have the same number of normal word lines and redundant word lines.

[0018] Each segment 5 is composed of eight row blocks RBLK. The row blocks RBLK are regions in which word lines of the memory cell array 2 share bit lines sandwiched between sense amplifiers SA. There are 32 row blocks RBLK in total, numbered 00 to 31, and each row block RBLK is composed of 1024 normal word lines and 8 redundant word lines. There is no limit to the number of redundant word lines in each row block RBLK, as long as they are evenly distributed within each segment 5. That is, in this embodiment, each segment 5 includes 8244 normal word lines and 64 redundant word lines, but these may be allocated evenly to each row block RBLK. Also, for example, within segment 5_0, row blocks RBLK00 to RBLK06 may not include redundant word lines, and row block RBLK07 may include 64 redundant word lines.

[0019] The address signal RA allocated to such a memory cell array 2 is 15 bits, with addresses <14:13> of the address signal RA indicating each segment 5, addresses <12:10> indicating each row block RBLK in segment 5, and addresses <9:0> indicating the addresses of the normal word lines and redundant word lines themselves in each row block RBLK. The address <14:13> allocated to segment 5 of this address signal RA is a first address, and the address <12:0> allocated to the normal word lines and redundant word lines is a second address.

[0020] FIG. 3 is a schematic block diagram showing the relationship between the row redundancy circuit 10 and the segments 5. As described above, the row redundancy circuit 10 receives the refresh state signal REF, the address signal RA, and the redundancy enable signal RWL_EN, and generates the inhibition signal HIT and the selection signal RWLSEL based on these signals. In the row redundancy circuit 10, the inhibition signals HIT are generated individually for each of the segments 5_0 to 5_3 (HIT_0 to HIT_3). The selection signals RWLSEL are generated in the same number as the number of redundant word lines in the memory cell array 2. The row redundancy circuit 10 inputs the inhibition signal HIT and the selection signal RWLSEL to the multiple segments 5 constituting the memory cell array 2 via the row decoder 4. At this time, the inhibition signals HIT_0 to HIT_3 generated individually for each of the segments 5_0 to 5_3 are input.

[0021] The active operation and refresh operation by such row redundancy circuit 10 will be explained with reference to FIG. First, active operation (normal read and write operations) will be described. During active operation, the row redundancy circuit 10 receives a refresh state signal REF at a low level and a redundancy enable signal RWL_EN at a low level. When the row redundancy circuit 10 generates an inhibit signal HIT at a low level during active operation in this case, the normal word line corresponding to the address signal RA is activated in the memory cell array 2. On the other hand, when the inhibit signal HIT is generated at a high level, since the normal word line corresponding to the address signal RA is defective, this normal word line is not activated but the corresponding redundant word line is activated. The redundant word line to be replaced is not limited to the redundant word line of the same segment 5. For example, if a normal word line of segment 5_0 is defective, it may be replaced with a redundant word line of another segment 5, i.e., segments 5_1 to 5_3.

[0022] Next, the refresh operation will be described. During the refresh operation, the row redundancy circuit 10 receives a high-level refresh state signal REF, which activates the normal word lines and redundant word lines one by one in sequence. Specifically, when the normal word lines are activated in sequence, the row redundancy circuit 10 receives a low-level redundancy enable signal RWL_EN. The row redundancy circuit 10 generates an inhibit signal HIT for each segment 5. In a segment 5, if the input inhibit signal HIT is low, the row redundancy circuit 10 activates the normal word line corresponding to the address signal RA. If the inhibit signal HIT is high, the row redundancy circuit 10 determines that the normal word line is defective and does not activate either the normal word line or the redundant word line in the segment. In this case, the normal word line is not replaced with a redundant word line. Next, when the redundancy enable signal RWL_EN is input at a high level to the row redundancy circuit 10, the row redundancy circuit 10 generates an inhibition signal HIT for each segment 5, and in segment 5, if the input inhibition signal HIT is at a low level, it activates the redundant word line corresponding to the address signal RA, and if the inhibition signal HIT becomes a high level, it does not activate any of the normal word lines or redundant word lines in segment 5.

[0023] The refresh operation will be explained in more detail with reference to FIG. 5. Here, we will consider an example in which the normal word line WL_N_3 and the redundant word line WL_R_1 in segment 5_0 are defective, and the redundant word line WL_R_0 corresponding to normal word line WL_N_3 is relieving the normal word line during active operation, while no word lines in other segments 5 are defective. When the refresh operation starts, a redundancy enable signal RWL_EN is input at a low level to the row redundancy circuit 10, and the normal word lines are activated first. At this time, an address signal RA<12:0> is input to the row redundancy circuit 10, and word lines having the same address in each segment 5 are simultaneously activated. The input address signal RA is incremented by an address counter (not shown), and the normal word lines WL_N_0 to WL_N_8243 are simultaneously activated in each segment 5 in order. Therefore, if there is no defect, four normal word lines are activated in the entire memory cell array 2.

[0024] In this case, in segment 5, where there is no defect in the normal word line, the inhibit signal HIT continues to be input at a low level, and the normal word lines are activated in order starting from WL_N_0. On the other hand, in segment 5_0, where the normal word line WL_N_3 is defective, the row redundancy circuit 10 inputs the inhibit signal HIT at a high level when the address signal RA indicates the normal word line WL_N_3. At that time, none of the normal word lines, including the redundant word line WL_R_0 corresponding to the normal word line WL_N_3, are activated. Therefore, at this time, one normal word line for each of segments 5_1 to 5_3 (three normal word lines) is activated in the entire memory cell array 2. Next, the address counter is incremented, and since the normal word line WL_N_4 at the next address is not defective, all of the normal word lines are activated in each of segments 5_0 to 5_3. In this way, all normal word lines (if not defective) are activated in order.

[0025] Similarly, the redundancy enable signal RWL_EN is input at a high level, activating the redundant word lines. At this time, the address counter simultaneously activates the redundant word lines WL_R_0 through WL_R_63 in each segment 5, resulting in four redundant word lines being activated throughout the entire memory cell array 2. In this case, in segments 5 with no defective redundant word lines, the redundancy enable signal RWL_EN continues to be input at a high level, and the redundant word lines are activated sequentially, starting from 0. On the other hand, in segment 5_0 with a defective redundant word line WL_R_1, when the address signal RA indicates the redundant word line WL_R_1, the row redundancy circuit 10 inputs the inhibit signal HIT at a high level. At that time, neither the normal word line nor the redundant word line is activated. Therefore, three redundant word lines are activated throughout the entire memory cell array 2. The address counter is then incremented, and the redundant word line WL_R_2 at the next address is activated because it is not defective in any of the segments 5. In this way, all redundant word lines (if they are not defective) are activated in turn.

[0026] In this embodiment, the inhibition signal HIT is generated for each segment 5, allowing activation / deactivation control for each segment 5 during refresh operations. When the inhibition signal HIT is generated at a high level, neither the normal word line nor the redundant word line is activated. This deactivates both normal and redundant word lines when a defect occurs in either a normal word line or a redundant word line, thereby reducing unnecessary current consumption. Furthermore, in conventional semiconductor devices, the selection of a redundant memory cell to replace a defective normal memory cell is limited. This reduces redundancy efficiency and reduces yields. However, in this embodiment, there is no restriction on which segment 5's redundant word line to use when a defective normal word line is replaced, thereby increasing the yield of the semiconductor memory device 1.

[0027] The row redundancy circuit 10 of this embodiment will be described in detail with reference to FIGS. 6 to 8. The row redundancy circuit 10 includes a normal WL control circuit 11 and a redundant WL control circuit 12. The normal WL control circuit 11 controls whether or not to replace a normal word line with a redundant word line, and operates when a redundancy enable signal RWL_EN is at a low level. The normal WL control circuit 11 generates a normal WL inhibition signal HIT_N, which indicates that activation of a normal word line is inhibited, and a selection signal RWLSEL based on an address signal RA and the redundancy enable signal RWL_EN.

[0028] The redundant WL control circuit 12 controls the inactivation of a defective redundant word line when the redundant word line is defective, and operates when the redundant enable signal RWL_EN is at a high level. Based on the address signal RA and the redundant enable signal RWL_EN, the redundant WL control circuit 12 generates a redundant WL inhibit signal HIT_R, which indicates that activation of the redundant word line is inhibited. The redundant WL inhibit signal HIT_R stops activation of the redundant word line when the redundant word line corresponding to the address signal RA is defective.

[0029] The configuration of the normal WL control circuit 11 will be described with reference to Fig. 7. The normal WL control circuit 11 comprises a WL determination unit 11A that compares the input address signal RA with fuse information and generates an output signal COMP indicating whether or not the normal word line corresponding to the address signal RA is defective, and a segment determination unit 11B that determines whether or not the normal word line for each segment 5 is defective based on the output signal COMP from the WL determination unit 11A and generates a normal WL inhibition signal HIT_N.

[0030] The WL determination unit 11A of the normal WL control circuit 11 has a comparison unit 111, a fuse information unit 112, and a judgment fuse 113. The comparison unit 111 compares the address signal RA<12:0> input to the normal WL control circuit 11 with the address of the normal word line that needs to be replaced and is stored in the fuse information unit 112, and inputs a signal indicating the comparison result, indicating whether the normal word line indicated by the address signal RA<12:0> is defective, to the AND circuit A1. Note that the 13-bit address signal RA<12:0> is extracted from the address signal RA<14:0> input to the row redundancy circuit 10 and input to the normal WL control circuit 11, and the address signal RA<14:13> indicating segment 5 is not input to the comparison unit 111.

[0031] The judge fuse 113 also inputs a signal indicating whether the fuse is cut (whether or not a redundant word line corresponding to a normal word line is used) to the AND circuit A1. The AND circuit A1 also receives an inverted version of the redundant enable signal RWL_EN. The AND circuit A1 performs an AND operation based on these input signals and outputs the output signal COMP. That is, the output signal COMP is a signal indicating whether or not a normal word line in the segment 5 is defective when the normal word line is activated during a refresh operation. Therefore, when the redundant enable signal RWL_EN is input at a low level, the address signal RA<12:0> matches the address stored in the fuse information unit 112, and the judge fuse 113 is cut, the output signal COMP is output at a high level.

[0032] The output signal COMP is input to AND circuits A2 to A5, respectively. The output signal COMP is input at a high level as a selection signal RWLSEL to segment 5 having the corresponding redundant WL, and at a low level to other segments. The fuse information of RA<14:13> is decoded and input to the AND circuits A2 to A5, respectively, to be used for segment selection. Specifically, the AND circuit A2 receives the address signal RA <13> and an address signal RA <14> The AND circuit A3 receives an inverted signal indicating the fuse information corresponding to the address signal RA. <13> and an address signal RA <14> The AND circuit A4 further receives an inverted signal indicating the fuse information corresponding to the address signal RA. <13> and an address signal RA <14> The AND circuit A5 further receives an address signal RA <13> and an address signal RA <14> A signal indicating the fuse information corresponding to the signal is input.

[0033] The AND circuits A2 to A5 output temporary normal WL inhibition signals HIT_N_0 to HIT_N_3, respectively, from these input signals. The row redundancy circuit 10 has the same number of normal WL control circuits 11 as the number of redundant word lines in the memory cell array 2, and all normal WL control circuits 11 similarly generate and output temporary normal WL inhibition signals HIT_N_0_# to HIT_N_3_#. Therefore, this # corresponds to the number of redundant word lines in the memory cell array 2, and in this embodiment, # is any number from 0 to 255. These temporary normal WL inhibition signals HIT_N_0_0 to HIT_N_0_255 are input to the OR circuit OR1, and similarly, the temporary normal WL inhibition signal HIT_1_# is input to the OR circuits OR2 to OR4, and the normal WL inhibition signals HIT_N_0 to HIT_N_3 are output from the OR circuits OR1 to OR4, respectively. When the output signal COMP is output at a high level, any one of the normal WL inhibition signals HIT_N_0 to HIT_N_3 becomes a high level.

[0034] The redundant WL control circuit 12 will now be described. The redundant WL control circuit 12 is composed of redundant WL control circuits 12_0 to 12_3 corresponding to the segments 5. However, since the circuit configuration for each segment 5 is the same, only the circuit configuration of the redundant WL control circuit 12_0 for segment 5_0 will be described. The redundant WL control circuit 12 receives an address signal RA<5:0> indicating a redundant word line from the address signal RA and a redundancy enable signal RWL_EN. The redundant WL control circuit 12 has a judge fuse 121 for deactivating the redundant word line corresponding to the input address, and this judge fuse 121 is blown if the redundant word line is defective. The input address signal RA<5:0> and a signal indicating the state of the judge fuse 121 are input to an AND circuit A6. Then, an AND operation is performed in the AND circuit A6, and a signal indicating the result is input to the OR circuit OR5. The number of these is equal to the number of redundant word lines in segment 5_0, i.e., 64. A signal indicating the operation result in each OR circuit OR5 and the redundant enable signal RWL_EN are input to AND circuit A7, and the result is output as redundant WL inhibition signal HIT_R_0. Similarly, redundant WL inhibition signals HIT_R_1 to HIT_R_3 are generated corresponding to each of segments 5_1 to 5_3.

[0035] 6, the row redundancy circuit 10 further includes OR circuits OR7 to OR10. A normal WL inhibition signal HIT_N and a redundant WL inhibition signal HIT_R corresponding to each segment 5 are input to each OR circuit OR7 to OR10, and an OR operation is performed to generate an inhibition signal HIT for each segment 5. That is, when either the normal WL inhibition signal HIT_N or the redundant WL inhibition signal HIT_R goes high, the inhibition signal HIT is output at a high level, and the word line of the segment 5 to which the inhibition signal HIT is input is deactivated.

[0036] In this way, the inhibit signal HIT is generated and input individually to each segment 5. Therefore, during a refresh operation, the word lines can be activated simultaneously in each segment 5, but if a word line in a segment 5 is defective, all word lines in that segment are deactivated, thereby suppressing unnecessary current consumption.

[0037] (Variation) The normal WL control circuit and the redundant WL control circuit are not limited to the examples described in the above embodiments as long as they can perform the above-mentioned functions. For example, the normal WL control circuit may be configured as shown in FIG.

[0038] The normal WL control circuit 21 shown in Fig. 9 will now be described. This normal WL control circuit 21 can also perform the same function as the normal WL control circuit 11, and is made up of a WL determination unit 21A that generates an output signal COMP indicating whether or not a normal word line corresponding to the address signal RA is defective, and a segment determination unit 21B that latches the output signal COMP from the WL determination unit to determine whether or not a normal word line is defective for each segment 5 and generates a normal WL inhibition signal HIT_N that inhibits activation of the normal word line. The WL determination unit 21A is similar to the WL determination unit 11A, so a description thereof will be omitted.

[0039] The normal WL control circuit 21 generates as many output signals COMP as there are redundant word lines (i.e., 256) in the WL determination unit 21A, and these are all input to the OR circuit OR11, where they are ORed and output as temporary inhibition signals HIT_N. These output temporary inhibition signals HIT_N are input to latch circuits Latch, latched for each segment 5 by the latch signal LAT, and normal WL inhibition signals HIT_N_0 to HIT_N_3 for each segment 5 are generated.

[0040] The latch control will be described in detail with reference to FIG. 10. <14> and address signal RA <13> An inverted signal thereof and the latch signal LAT are input to each of the AND circuits A8 to A11. As a result, latch signals LAT_0 to LAT_3 are generated for each of the segments 5. The generated latch signals LAT_0 to LAT_3 are input to each of the latch circuits Latch.

[0041] For example, a timing chart showing a case where there is a defect in the normal word lines of the segments 5_1 and 5_3 is shown in Fig. 11. The generated temporary inhibition signal HIT_N is at a high level because there is a defect in the normal word lines of the segments 5_1 and 5_3.

[0042] When latch signals LAT_0 to LAT_3 for each segment 5 based on the address signal <14:13> are input to this temporary inhibition signal HIT_N, only the normal WL inhibition signals HIT_N_1 and HIT_N_3 are output at a high level among the normal WL inhibition signals HIT_N_0 to HIT_N_3. In this way, a circuit for generating the desired normal WL inhibition signals HIT_N_0 to HIT_N_3 is configured. Also, as shown in FIG. 11, after the latch signal LAT has been output at a high level four times, the WL activation signal WL_ON output from the control circuit 3 is activated. When this WL activation signal WL_ON is input at a high level to the row decoder 4, activation of the word line begins. In the above-described embodiment, the semiconductor recording device equipped with the control circuit is a DRAM, but the present invention is not limited to this. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a flash memory, or another semiconductor memory device.

[0043] The above-described embodiments and modifications have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments and modifications are intended to include all design modifications and equivalents that fall within the technical scope of the present invention. [Explanation of symbols]

[0044] 1. Semiconductor memory device 2. Memory cell array 3 Control Circuit 4 Low Decoder 5 segments 10 Row Redundancy Circuit 11 Normal WL control circuit 11A WL judgment section 11B Segment Judgment Department 12 Redundant WL control circuit 21 Normal WL control circuit 21A WL Judgment Department 21B Segment Judgment Department 111 Comparison section 112 Hughes Information Department 113 Judge Hughes COMP output signal HIT prohibition signal HIT_N Normal WL prohibition signal HIT_R Redundant WL prohibition signal LAT Latch signal Latch Latch circuit RA Address Signal RBLK Low Block REF Refresh status signal RWL_EN Redundancy enable signal RWLSEL select signal

Claims

1. a memory cell array having a plurality of segments each having a plurality of normal word lines and a plurality of redundant word lines; a row redundancy circuit that controls activation and deactivation of the normal word lines and the redundant word lines; the row redundancy circuit is configured to activate the normal word lines or the redundant word lines one by one in order in each of the segments during a refresh operation, thereby activating a plurality of the normal word lines or the redundant word lines, A semiconductor memory device characterized in that, during the refresh operation, if the normal word line or the redundant word line to be activated is defective, the row redundancy circuit does not activate the normal word line or the redundant word line in the segment including that normal word line or that redundant word line, and does not replace it with another normal word line or redundant word line.

2. 2. The semiconductor memory device according to claim 1, wherein each of said segments comprises a first predetermined number of normal word lines and a second predetermined number of said redundant word lines, and said first predetermined number is greater than said second predetermined number.

3. an address signal is input to the row redundancy circuit, the address signal being assigned so that a first address indicates an address of the segment and a second address indicates an address of the normal word line and the redundant word line; 2. The semiconductor memory device according to claim 1, wherein said row redundancy circuit uses a second address to specify said normal word line or said redundant word line to be activated during a refresh operation.

4. the row redundancy circuit generates an inhibit signal for inhibiting activation of normal word lines and redundant word lines for each of the segments during the refresh operation; 2. The semiconductor memory device according to claim 1, wherein, when any of the normal word lines or redundant word lines of the respective segments is defective, an inhibit signal is activated and input only to the segment including the defective normal word line or redundant word line.

5. the row redundancy circuit includes a normal WL control circuit that generates a normal WL inhibit signal that inhibits activation of a normal word line, and a redundant WL control circuit that generates a redundant WL inhibit signal that inhibits activation of a redundant word line; 5. The semiconductor memory device according to claim 4, wherein when either a normal WL inhibit signal or a redundant WL inhibit signal is activated, the inhibit signal is generated at a high level.

6. the normal WL control circuit comprises: a WL determination unit that compares an input address signal with fuse information and generates an output signal indicating whether or not the normal word line corresponding to the address signal is defective; and a segment determination unit that determines whether or not the normal word line is defective for each segment based on the output signal from the WL determination unit and generates a normal WL inhibit signal; 6. The semiconductor device according to claim 5, wherein the segment determination unit generates the normal WL inhibit signal at a high level when it determines, based on the output signal, that there is a defect in the normal word line of the segment.

7. 7. The semiconductor memory device according to claim 6, wherein the segment determination unit generates the normal WL inhibit signal by decoding the fuse information of the address signal allocated to the segment.

8. 7. The semiconductor memory device according to claim 6, wherein the segment determination unit latches the output signal using the address signal assigned to the segment to generate the normal WL inhibit signal.

9. 8. The semiconductor memory device according to claim 7, wherein the segment determination unit includes an AND circuit for each of the segments to which a signal generated by decoding the fuse information and the output signal are input, and generates the normal WL inhibition signal for each of the segments based on the signal generated by decoding the fuse information.

10. 9. The semiconductor memory device according to claim 8, wherein the segment determination unit has a latch circuit corresponding to the segment, the output signal is input to the latch circuit, the output signal is latched by an address signal assigned to the segment, and the normal WL inhibition signal for each segment is generated.

11. 7. The semiconductor memory device according to claim 6, wherein the redundant WL control unit compares an input address signal with the fuse information to determine whether the redundant word line is defective, and if there is a segment in which the redundant word line is defective, outputs the redundant WL prohibition signal at a high level.

12. 12. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a dynamic random access memory.

13. A row redundancy circuit for controlling activation and deactivation of normal word lines and redundant word lines of a memory cell array having a plurality of segments each having a plurality of normal word lines and a plurality of redundant word lines, During a refresh operation, the normal word lines or the redundant word lines are activated one by one in order in each of the segments, so that a plurality of the normal word lines or the redundant word lines are activated; Furthermore, during the refresh operation, if the normal word line or the redundant word line to be activated is defective, the normal word line or the redundant word line is not activated in the segment including that normal word line or that redundant word line, and is not replaced with another normal word line or redundant word line.

14. a memory cell array having a plurality of segments each having a plurality of normal word lines and a plurality of redundant word lines; a row redundancy circuit that controls activation and deactivation of the normal word lines and the redundant word lines; a control method for a semiconductor memory device in which the row redundancy circuit activates the normal word lines or the redundant word lines one by one in order in each of the segments during a refresh operation, thereby activating a plurality of the normal word lines or the redundant word lines, During the refresh operation, normal word lines or redundant word lines are simultaneously activated one by one in each of the segments; Furthermore, during the refresh operation, all of the normal word lines and redundant word lines in each segment are activated in sequence, and if the normal word line or redundant word line to be activated is defective, the word line is not activated and is not replaced with another normal word line or redundant word line.

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