Semiconductor device

Abstract

To provide a semiconductor device having a novel structure.SOLUTION: A semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, in which the first transistor is provided over a substrate including a semiconductor material and the second transistor includes an oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that is made up of transistors. Information is stored by selecting a pixel and storing charge in the capacitor.

[0004] Based on the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, after reading data, another write operation is required to store the information again. In addition, there is a leakage current in the transistors that make up the memory element, and when the transistors are not selected, Because electric charges flow out or in even under certain conditions, the data retention period is short. A write operation (refresh operation) is required every 10 seconds, which reduces power consumption sufficiently. In addition, if the power supply is cut off, the memory contents are lost, so it is difficult to store the data for a long period of time. To retain the memory, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. High voltages are required for this. Furthermore, it takes a relatively long time for the charge to be retained or removed. There is also the problem that it takes time to write and erase data, and it is not easy to speed up the writing and erasing. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using other materials. The semiconductor device has a stacked structure with a transistor formed using the above-mentioned method. Such a configuration can be adopted.

[0012] One aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, a plurality of second signal lines, and a plurality of a plurality of memory cells connected in parallel between the word lines, the source lines, and the bit lines; An address signal is input, and one of a plurality of memory cells is designated by the address signal. a second signal driving the plurality of second signal lines and the plurality of word lines to select the recells; a drive circuit for a line and a word line, and a drive circuit for a first signal line that selects one of a plurality of write potentials and applies the selected potential to the first signal line; A drive circuit for a first signal line, which outputs the potential of the bit line and a plurality of reference potentials, is inputted, and a bit line is a read circuit for reading data by comparing the potential of the bit line with a plurality of reference potentials; A write potential and a plurality of reference potentials are generated to drive a first signal line and a read circuit. a potential generating circuit for supplying a potential to the first gate electrode and the second gate electrode; a first transistor having a first source electrode and a first drain electrode; a second transistor having a first electrode, a second source electrode, and a second drain electrode; a third transistor having a third gate electrode, a third source electrode, and a third drain electrode; a first transistor provided on a substrate including a semiconductor material, and a second transistor The transistor includes an oxide semiconductor layer, a first gate electrode, and a second source electrode. The source line is electrically connected to one of the first and second drain electrodes. The first drain electrode and the third source electrode are electrically connected. The bit line and the third drain electrode are electrically connected to each other, and the first signal line and the second and the other of the source electrode and the second drain electrode is electrically connected to a plurality of second signal One of the word lines and the second gate electrode are electrically connected, and one of the plurality of word lines and the third gate electrode are electrically connected. The gate electrode is a semiconductor device electrically connected to the gate electrode.

[0013] In the above structure, the first gate electrode and the second source electrode or the second drain electrode The semiconductor device has a capacitor electrically connected to one of the electrodes.

[0014] Furthermore, one aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, and a plurality of second signal lines. A plurality of memory cells are connected in parallel between a plurality of word lines, a source line, and a bit line. An address signal is input, and one of the plurality of memory cells designated by the address signal is selected. a plurality of second signal lines and a plurality of word lines are driven to select the selected memory cell; A drive circuit for the second signal line and the word line, and a first signal line are provided by selecting one of a plurality of write potentials. a first signal line driver circuit for outputting a potential of the bit line and a plurality of reference potentials; , a reference memory cell, and the conductance of the designated memory cell and the conductance of the reference memory cell A read circuit compares the conductance and data to read out the data. and a plurality of reference potentials are generated and supplied to the drive circuit and the readout circuit of the first signal line. a generating circuit, and one of the plurality of memory cells includes a first gate electrode, a first source electrode, and a first transistor having a first drain electrode, a second gate electrode, a second source a second transistor having a first source electrode and a second drain electrode; and a third gate electrode. a third transistor having a third source electrode and a third drain electrode; The first transistor is provided on a substrate including a semiconductor material, and the second transistor is provided on an oxide a first gate electrode and a second source electrode or a second drain electrode; The source line and the first source electrode are electrically connected to each other. the first drain electrode and the third source electrode are electrically connected to each other; and the third drain electrode are electrically connected, and the first signal line and the second source electrode or The second drain electrode is electrically connected to one of the plurality of second signal lines. The gate electrode is electrically connected to one of the plurality of word lines, and the third gate electrode is electrically connected to one of the plurality of word lines. It is a semiconductor device that is electrically connected.

[0015] Furthermore, one aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, and a plurality of second signal lines. A plurality of memory cells are connected in parallel between a plurality of word lines, a source line, and a bit line. An address signal and a plurality of reference potentials are input, and the address signal is input to one of the plurality of memory cells. A plurality of second signal lines and a plurality of word lines are connected to select memory cells designated by the signal. and driving the selected word line to select one of a plurality of reference potentials and output it to the selected word line. a drive circuit for the second signal line and the word line, and ... a driver circuit for a first signal line, and a designated memory connected to the bit line; a read circuit for reading data by reading the conductance of the recell; A write potential and a plurality of reference potentials are generated to drive a first signal line and a read circuit. a potential generating circuit for supplying a potential to the first gate electrode and the second gate electrode; a first transistor having a first source electrode and a first drain electrode; a second transistor having a first electrode, a second source electrode, and a second drain electrode; a capacitor element, the first transistor being provided on a substrate including a semiconductor material, and the second The transistor includes an oxide semiconductor layer and has a first gate electrode and a second source electrode. One of the first and second drain electrodes is electrically connected to one electrode of the capacitor element. The source line and the first source electrode are electrically connected, and the bit line and the first drain electrode are electrically connected. The first signal line and the second source electrode or the second drain electrode are electrically connected to each other. The second gate electrode is electrically connected to the other of the plurality of second signal lines. and one of the word lines and the other electrode of the capacitor element are electrically connected to a semiconductor It is a body device.

[0016] In the above, the first transistor is a channel-forming transistor provided in a substrate including a semiconductor material. a region, impurity regions provided so as to sandwich the channel forming region, and a region on the channel forming region a first gate insulating layer, a first gate electrode on the first gate insulating layer, and each impurity region and and a first source electrode and a first drain electrode electrically connected to each other.

[0017] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; and,

[0018] In the above, the third transistor is a channel transistor provided in a substrate including a semiconductor material. impurity regions provided so as to sandwich the channel forming region; a third gate insulating layer on the impurity region; a third gate electrode on the third gate insulating layer; a third source electrode and a third drain electrode electrically connected to the first region, respectively.

[0019] In the above, a single crystal semiconductor substrate is preferably used as the substrate containing a semiconductor material. It is particularly preferable that the semiconductor material is silicon. An SOI substrate may be used as the substrate.

[0020] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. Furthermore, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19atoms / cm 3 The off-state current of the second transistor is preferably 1×10 or less. -13 A It is preferable to do the following:

[0021] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0022] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "the first layer on the gate insulating layer" is not limited to "directly under" the first layer. If the expression "gate electrode" is used, other components are provided between the gate insulating layer and the first gate electrode. The terms "upper" and "lower" are used for the convenience of explanation. Unless otherwise specified, the terms "top" and "bottom" are interchangeable.

[0023] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed as a single unit.

[0024] Also, the functions of "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0025] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0026] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistive elements, inductors, capacitors, and other various devices This includes elements that have functions such as:

[0027] Generally, an "SOI substrate" is a substrate with a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is used as a concept that includes the substrate with the structure. The layer is not limited to a silicon semiconductor layer. Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, and metal substrates In other words, a layer of semiconductor material on a conductive or insulating substrate is also included. Furthermore, in this specification and the like, the term "semiconductor on insulator (SOI) substrate" also includes those having "Solid substrate" does not only refer to a substrate made of semiconductor material only, but also to any substrate that contains semiconductor material. In other words, in this specification, the term "SOI substrate" is also broadly used to refer to a "semiconductor substrate." Included in. [Effects of the Invention]

[0028] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor is provided in a lower portion, and A semiconductor device including a transistor including an oxide semiconductor is provided.

[0029] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0030] Furthermore, no high voltage is required to write information, and there is no problem of element degradation. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. This can be easily realized. In addition, when rewriting information, there is no need to erase the previous information. There is also the benefit of having one.

[0031] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0032] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 2] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4]1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 10] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 11] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 12] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 13] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 14] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 15] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 16] FIG. 10 is a timing chart for explaining the operation. [Figure 17] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 18] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 19] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 20] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 21] FIG. 10 is a timing chart for explaining the operation. [Figure 22] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 23] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 24] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 25] FIG. 2 is a circuit diagram illustrating a drive circuit. [Figure 26] FIG. 10 is a timing chart for explaining the operation. [Figure 27] FIG. 10 is a diagram showing the relationship between the node A and the word line potential. [Figure 28] FIG. 2 is a diagram for explaining a driver circuit. [Figure 29] FIG. 10 is a timing chart for explaining the operation. [Figure 30] 1A and 1B are diagrams illustrating electronic devices. [Figure 31] FIG. 1 is a longitudinal cross-sectional view of a dual-gate transistor including an oxide semiconductor. [Figure 32] 32 is an energy band diagram (schematic diagram) taken along the line A-A' in FIG. 31. [Figure 33] (A) Energy band diagram showing the state when a positive potential (+VG) is applied to the gate (G1), and (B) energy band diagram showing the state when a negative potential (-VG) is applied to the gate (G1). [Figure 34] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). DETAILED DESCRIPTION OF THE INVENTION

[0034] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0035] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the actual position, size, range, etc. may not necessarily be the same as those shown in the drawings. It is not limited to the position, size, range, etc. shown.

[0036] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0037] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0038] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. The transistor 160 is made of a material and the transistor 162 is made of an oxide semiconductor. Note that in FIG. 1, it is clear that the transistor 162 is formed using an oxide semiconductor. For clarity, the OS code is also used.

[0039] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first line (1st Line) is electrically connected to one of the drain electrodes. The second line (also referred to as a source line) and the source electrode of the transistor 160 are electrically connected to each other. The wiring (2nd Line: also called bit line) and the drain electrode of the transistor 160 are electrically connected. The third wiring (3rd Line: also referred to as the first signal line) The transistor 162 is electrically connected to the other of the source electrode and the drain electrode. A fourth line (also called a second signal line) and the transistor 162 It is electrically connected to the gate electrode.

[0040] The transistor 160 using a material other than an oxide semiconductor can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed. The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 The potential of the gate electrode can be maintained for an extremely long period of time. The transistor 162 using a conductor has the advantage that the short channel effect is less likely to occur. do.

[0041] By taking advantage of the feature that the potential of the gate electrode can be maintained for a long period of time, It is possible to write, store, and read information.

[0042] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The potential is set to turn on the transistor 162, thereby turning on the transistor 162. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retention).

[0043] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is maintained over time.

[0044] Next, the reading of information will be described. As described above, when the transistor 160 is in the ON state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring As a result, the potential of the second wiring is lowered. In the OFF state, the potential of the second wiring does not change.

[0045] In this way, in a state where information is held, the potential of the first wiring and the potential of the second wiring are By comparing, information can be read out.

[0046] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (the potential related to the new information) is applied to the gate electrode of the transistor 160. The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0047] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0048] The above explanation applies to n-type transistors (n-channel transistors) that use electrons as carriers. ) is used, but instead of an n-type transistor, holes are used as carriers. It goes without saying that a p-type transistor can be used.

[0049] <Plane and cross-sectional configurations of semiconductor device> 2A and 2B show an example of the configuration of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower part. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, the transistor 160 is preferably a p-type transistor. It is possible to do this.

[0050] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate insulating layer 108a provided on the gate insulating layer 108a. The electrode 110a and the source or drain electrode 111 electrically connected to the impurity region 114 are 30a, and has a source or drain electrode 130b.

[0051] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, A high concentration impurity region 120 is provided, and a metal compound region 124 is provided on the high concentration impurity region 120. In addition, an element isolation insulating layer 10 is formed on the substrate 100 so as to surround the transistor 160. 6 is provided, and the interlayer insulating layer 126 and the interlayer insulating layer 128 are provided to cover the transistor 160. An edge layer 128 is provided. A source or drain electrode 130a, a source or drain electrode 130b, a The drain electrode 130b is formed through an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. 124. That is, the source electrode or The drain electrode 130a and the source or drain electrode 130b are formed in the metal compound region 12 4, the high concentration impurity region 120 and the impurity region 114 are electrically connected. The gate electrode 110a is connected to a source or drain electrode 130a and a source or drain electrode 130b. Alternatively, an electrode 130c provided similarly to the drain electrode 130b is electrically connected.

[0052] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d, and a gate insulating layer 138 is provided on the gate insulating layer 138. an oxide semiconductor layer 140; and a metal oxide film provided on the oxide semiconductor layer 140. The source or drain electrode 142a is electrically connected to the source or drain electrode 142b. and an inner electrode 142b.

[0053] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0054] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0055] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 In addition, the hydrogen concentration is sufficiently reduced. In the oxide semiconductor layer 140 that has been highly purified by this method, the carrier concentration is 5×10 14 / cm 3 below , preferably 5×10 12 / cm 3 In this way, the hydrogen concentration is sufficiently reduced. By using an oxide semiconductor that has been highly purified and made i-type or substantially i-type, Therefore, the transistor 162 can have excellent off-state current characteristics. When Vd is +1V or +10V, the gate voltage Vg is in the range of -5V to -20V. In this range, the off-state current is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced. The oxide semiconductor layer 140 is highly purified by the above-mentioned method, and the off-state current of the transistor 162 is reduced. By reducing the amount of oxidation, a semiconductor device with a new configuration can be realized. The hydrogen concentration in the compound semiconductor layer 140 was measured by secondary ion mass spectroscopy (SIMS). The results were measured using ion mass spectroscopy (Ion Mass Spectroscopy).

[0056] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0057] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110a of the transistor 160 and The source or drain electrode 142a of the transistor 162 is connected to the electrode 130c. 136c, the electrode 150c, the electrode 154c and the electrode 150d. There are.

[0058] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIGS.

[0059] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. In this specification, it refers to a substrate having a structure in which a conductive layer is provided on an insulating surface. The concept also includes substrates with semiconductor layers made of other materials. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The plate has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. shall be included.

[0060] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride oxide or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0061] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0062] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating layer 1 After forming the insulating film 06, the protective layer 102 is removed.

[0063] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0064] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. By oxidizing or nitriding the surface of the semiconductor region 104 through plasma treatment or thermal oxidation treatment, The insulating layer may be formed by the high density plasma treatment, for example, using He, Ar, Kr, or X. A mixture of rare gases such as e and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1n The thickness can be set to 100 nm or more and 100 m or less.

[0065] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0066] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. a) A gate electrode 110a is formed (see FIG. 3(C)).

[0067] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the semiconductor region 104 to form an impurity region with a shallow junction depth. In this case, a region 114 is formed (see FIG. 3(C)). For this purpose, phosphorus and arsenic are added, but when forming a p-type transistor, boron (B) and An impurity element such as aluminum (Al) may be added. As a result of this formation, a channel forming region 116 is formed below the gate insulating layer 108a of the semiconductor region 104. (See FIG. 3(C)). Here, the concentration of the added impurity can be set appropriately. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this case, the step of forming the impurity region 114 after forming the insulating layer 112 is adopted. However, the insulating layer 112 may be formed after the impurity region 114 is formed. stomach.

[0068] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a slow etching process, the film can be formed in a self-aligned manner. The insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the impurity region 11 It is a good idea to expose the top surface of 4.

[0069] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed in a region in contact with the impurity region 114 by ion implantation of phosphorus (P) or arsenic (Ar). By adding arsenic (As) or the like, a high concentration impurity region 120 is formed (see FIG. 3(E)). Thereafter, the insulating layer is removed, and the gate electrode 110a, the sidewall insulating layer 118, and the high-concentration impurity A metal layer 122 is formed so as to cover the pure region 120 and the like (see FIG. 3(E)). 122 is formed using various film-forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by reacting with the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the metal layer using a metal material that forms a metal compound with low resistance. Examples of metal materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum. etc.

[0070] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of Oa that comes into contact with the metal layer 122.

[0071] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0072] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the structure is a two-layer structure of an edge layer 126 and an interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is polished by CMP, etching, or the like. It is desirable to flatten the surface by using a

[0073] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 3(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by removing

[0074] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0075] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, Electrodes in contact with the port electrode 110a (for example, electrode 130c in FIG. 2(A)) The source or drain electrode 130a, the source or drain electrode 130b, and the There is no particular limitation on the material that can be used for the drain electrode 130b. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as stainless steel, aluminum, copper, neodymium, and scandium can be used. Cut.

[0076] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0077] <How to make the upper transistor> Next, referring to FIGS. 4 and 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0078] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0079] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are Openings are formed that reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by exposure or other methods. Wet etching is also used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnS, and scandium, as well as alloys and compounds thereof (e.g., nitrides), are examples of such materials. can be done.

[0080] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has a boundary. The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, a function of reducing contact resistance with the source or drain electrodes 130b, 130c, etc. In addition, the titanium nitride film formed thereafter has a burr-like property that suppresses the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, plating is performed. Alternatively, a copper film may be formed by a method.

[0081] After the conductive layer 134 is formed, the conductive layer 134 is removed by a method such as etching or CMP. 136a, 136b, and 136c are removed to expose the insulating layer 132. c, a gate electrode 136d is formed (see FIG. 4(C)). are removed to form the electrodes 136a, 136b, 136c, and gate electrode 136d. In this case, it is desirable to process the insulating layer 132 so that the surface is flat. The surfaces of the electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. As a result, in the subsequent steps, good electrodes, wiring, insulating layers, semiconductor layers, etc. can be formed. This becomes possible.

[0082] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d The gate insulating layer 138 is formed to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, etc. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0083] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0084] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made into a good one.

[0085] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, the insulating layer having good film quality as the gate insulating layer 138 may be used. At the same time, the interface state density with the oxide semiconductor layer can be reduced to form a good interface. All you have to do is form the following.

[0086] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The dangling bonds induce a drift in the threshold voltage (Vth).

[0087] In response to this, impurities in the oxide semiconductor, especially hydrogen and water, are eliminated as much as possible, and the gate electrode is By improving the interface characteristics with the base insulating layer, a stable transistor is produced even during BT tests. It is possible to obtain data.

[0088] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0089] The oxide semiconductor layer is made of quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides such as In-Sn-Ga-Zn-O. In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, and binary alloys Metal oxides such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, and S n-Mg-O, In-Mg-O, and single-component metal oxides such as In-O, Sn-O, and Zn- An oxide semiconductor layer using O or the like can be applied. SiO2 may also be included.

[0090] The oxide semiconductor layer is InMO3(ZnO) m Use a thin film expressed as (m>0) Here, M can be one or more selected from Ga, Al, Mn and Co. It represents a metal element. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m Oxide semiconductor film with a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. The thin film is called an In-Ga-Zn-O oxide semiconductor film (In-Ga-Zn-O These will be referred to as amorphous films.

[0091] In this embodiment, an oxide semiconductor layer is formed using an In-Ga-Zn-O system oxide semiconductor film forming method. An amorphous oxide semiconductor layer is formed by a sputtering method using a target. Note that adding silicon to an amorphous oxide semiconductor layer can suppress crystallization of the layer. Therefore, for example, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The oxide semiconductor layer may be formed by

[0092] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target of a metal oxide containing zinc as the main component can be used. and Zn-containing oxide semiconductor film deposition target (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1 [molar ratio]) can also be used. , and as a target for forming oxide semiconductor films containing Zn, In2O3:Ga2O3:Z nO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1:1:4 A target having a composition ratio of [molar ratio] may also be used. The target filling rate is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). By using a target for oxide semiconductor film formation with a high filling rate, dense oxide A compound semiconductor layer is formed.

[0093] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about several ppm (desired). It is preferable to use a high purity gas in which the concentration has been reduced to about several ppb.

[0094] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. Damage caused by sputtering can also be reduced. The residual moisture in the metal oxide layer is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer is formed using a target of It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A titanium sublimation pump can be used. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the film formation chamber is exhausted, The concentration of impurities contained in the layer can be reduced.

[0095] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. When a pulsed direct current (DC) power supply is used, film formation can be performed. This reduces the amount of powdery material (also called particles or dust) that is generated at times, and the film thickness distribution is uniform. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less, The thickness is 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0096] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, instead of the argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or An oxygen atmosphere may also be used.

[0097] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable etching, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. are set appropriately.

[0098] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and other gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride). Fluorine (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C HF3), hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Alternatively, a gas containing a rare gas such as argon (Ar) may be used.

[0099] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0100] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0101] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The oxide semiconductor layer can be dehydrated or dehydrogenated by the first heat treatment. The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. Avoid contact and ensure that water or hydrogen is not recontaminated.

[0102] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The GRTA device uses high-temperature gas for heat treatment. The gas used is a rare gas such as argon, or a gas that can be heated by heat treatment, such as nitrogen. The LRTA device uses an inert gas that does not react with the object to be treated. Thallium halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The material to be treated is heated by the radiation of light (electromagnetic waves) emitted from lamps such as high-pressure mercury lamps. It is a heating device.

[0103] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is taken out of the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even at temperatures exceeding the distortion point of the substrate.

[0104] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0105] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. For example, the crystallinity may be 90% or more, or 80% or more. % or more of a microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0106] In addition, microcrystals (grain size of 1 nm or less) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). In the case where the oxide semiconductor layer is a mixture of the upper and lower 20 nm or less (typically 2 nm or more and 4 nm or less) There are also cases where this is the case.

[0107] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, an In-Ga-Zn-O oxide semiconductor film formation target can be used. When forming an oxide semiconductor layer using In2Ga2ZnO7 By forming a microcrystalline portion in which the crystal grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. It is possible.

[0108] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in this direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystalline portion has a function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0109] The oxide semiconductor layer having the above-described microcrystalline portion is formed by GRTA treatment. It can be formed by surface heating. Also, the content of Zn is higher than the content of In or Ga. A more suitable formation can be achieved by using a smaller sputtering target.

[0110] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0111] The heat treatment has the effect of dehydrating or dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The oxidation treatment is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the source electrode and the drain electrode, a protective insulating layer is formed on the source electrode or the drain electrode. In addition, such dehydration treatment and dehydrogenation treatment can be carried out at the timing of The treatment may be carried out not only once but also multiple times.

[0112] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0113] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. A material containing one or more elements selected from the group consisting of aluminum, thorium, and arsenic may be used. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, Materials containing a single or multiple combinations of elements selected from chromium, chromium, and scandium can also be used. good.

[0114] The conductive layer may be formed of a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide In2O3-SnO2 alloy (sometimes abbreviated as ITO), indium oxide In2O3-ZnO or the above metal oxide material with silicon or A material containing silicon oxide can be used.

[0115] The conductive layer may have a single layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film containing titanium, and two layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and another titanium film are laminated.

[0116] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF Preferably, a laser beam is used.

[0117] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , is determined by the distance between the lower end of the source electrode or drain electrode 142b. When exposing a pattern with a channel length (L) of less than 25 nm, the exposure time is from several nm to several tens of nm. and extremely short wavelength extreme ultraviolet light. Exposure using extreme ultraviolet light provides high resolution and a large depth of focus. The channel length (L) of the transistor to be formed later is set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, Therefore, power consumption does not increase.

[0118] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0119] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The conductive layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0120] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask allows for resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0121] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. The plasma treatment is preferably performed on the exposed surface of the oxide semiconductor layer. Water and other substances adhering to the surface are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. may be performed.

[0122] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 4(G)).

[0123] The protective insulating layer 144 is formed by a method such as sputtering, which does not mix impurities such as water or hydrogen into the protective insulating layer 144. The thickness of the insulating film is 1 nm or more. Examples of materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxynitride. The structure may be a single layer structure or a multilayer structure. The substrate temperature when the protective insulating layer 144 is formed is set to be equal to or higher than room temperature and equal to or lower than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare A mixed atmosphere of gas (typically argon) and oxygen is preferred.

[0124] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. Oxygen is extracted from the oxide semiconductor layer by the oxide semiconductor layer. Therefore, the protective insulating layer 1 may have a low resistance and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 44 does not contain as much hydrogen as possible. is.

[0125] It is also preferable to form the protective insulating layer 144 while removing the remaining moisture in the processing chamber. The oxide semiconductor layer 140 and the protective insulating layer 144 are preferably formed so as not to contain hydrogen, hydroxyl groups, or moisture. This is to make it possible.

[0126] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means is a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the layer 144 can be reduced.

[0127] The sputtering gas used when forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or Impurities such as hydrides are reduced to a concentration of about several ppm (preferably, a concentration of about several ppb). It is preferable to use high purity gases that have been removed.

[0128] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors.

[0129] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment can be carried out by maintaining a constant heating temperature, or by heating from room temperature to 100°C or higher. Repeat the heating process several times to a temperature of 200°C or less and then to room temperature. This heat treatment may also be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0130] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0131] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive layer is formed so as to be embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching can be wet etching or dry etching. However, from the viewpoint of fine processing, it is recommended to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples include any conductive material, their alloys, and compounds (e.g., nitrides).

[0132] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method has a thickness of 1000 nm at the interface. The oxide film is reduced, and the lower electrodes (here, the electrodes 136a, 136b, 136c, and source or drain electrode 142a, source or drain electrode 142b, etc.) The titanium nitride formed thereafter has the function of reducing the contact resistance. It has a barrier function that suppresses the diffusion of materials. It also has a barrier function using titanium or titanium nitride. After forming the film, a copper film may be formed by plating.

[0133] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. 150a, 150b, and 150c are removed to expose the interlayer insulating layer 146. Then, the conductive layer 50c, the electrode 150d, and the electrode 150e are formed (see FIG. 5(C)). A part of 148 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming the pole 150e, it is desirable to process it so that the surface is flat. As shown, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By planarizing the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form an edge layer, etc.

[0134] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the insulating layer 150 is embedded in the opening. After forming the conductive layer as shown above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a and the like. So I will omit the details.

[0135] When the transistor 162 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 and the off-current of the transistor 162 is is 1 x 10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the resulting product is highly purified. By using the oxide semiconductor layer 140, the transistor 162 can have excellent characteristics. In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, and A semiconductor device with excellent characteristics having a transistor 162 using an oxide semiconductor in a portion thereof is manufactured. It is possible.

[0136] As a semiconductor material to be compared with oxide semiconductors, silicon carbide (e.g., 4H- Oxide semiconductors and 4H-SiC have several things in common. The Fermi-Dirac distribution at room temperature is one example of this. The minority carriers are 10 -7 / cm 3 This is estimated to be about the same as in 4H-SiC. 6.7 x 10 -11 / cm 3 This is an extremely low value, similar to the intrinsic carrier density of silicon. degree (1.4 x 10 10 / cm 3 Compared to the degree of I can understand it well.

[0137] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0138] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. In semiconductor processes using silicon carbide, the temperature is generally 1500°C to 20 Since activation heat treatment at 00°C is required, it is difficult to use in a laminated structure with semiconductor elements made of other semiconductor materials. At such high temperatures, the semiconductor substrate and semiconductor elements are destroyed. On the other hand, oxide semiconductors are heated to temperatures between 300 and 500°C (below the glass transition temperature, It can be fabricated by heat treatment (even at temperatures up to 700°C) and can be integrated with other semiconductor materials. After forming the circuit, a semiconductor element can be formed using an oxide semiconductor.

[0139] In addition, unlike silicon carbide, oxide semiconductors can be used on substrates with low heat resistance, such as glass substrates. Furthermore, it has the advantage that it can be used without high-temperature heat treatment. It has the advantage that the energy cost can be significantly lowered compared to silicon.

[0140] In oxide semiconductors, the density of state (DOS) and other physical properties are Many studies have been conducted on the localized levels in the energy gap. In one embodiment of the disclosed invention, the localized level is By removing water and hydrogen from the oxide semiconductor, a highly purified oxide semiconductor can be produced. This is based on the idea of ​​sufficiently reducing the localized level itself. This makes it possible to manufacture extremely superior industrial products.

[0141] When removing hydrogen and water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and the local By reducing the intrinsic level, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen may be formed in close proximity to the channel formation region. By performing heat treatment at a temperature of 200 to 400°C, typically around 250°C, It is possible to supply oxygen from the oxide film and reduce localized levels due to oxygen deficiency.

[0142] The second heat treatment is followed by precipitation in an oxygen atmosphere or an atmosphere from which hydrogen and water have been sufficiently removed. Oxygen can also be supplied to the oxide semiconductor through a heating process.

[0143] Defects in oxide semiconductors are caused by excess hydrogen at shallow levels 0.1 to 0.2 eV below the conduction band, or by oxide These defects are thought to be caused by deep levels due to a lack of elements. The technical idea of ​​thoroughly removing hydrogen and providing sufficient oxygen is correct. cormorant.

[0144] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type is achieved by removing water and hydrogen. It is not an i-type product made by adding impurities, so it can be said to include a technological concept that has not been seen before. .

[0145] Note that in this embodiment, the transistor 162 including an oxide semiconductor is a bottom-gate transistor. Although a specific configuration has been described, the present invention is not limited to this. The 62 configuration may be bottom gate, top gate, or dual gate. A dual-gate transistor is a transistor in which gate insulating layers are arranged above and below the channel region. A transistor with two gate electrode layers placed one over the other.

[0146] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 31 to 34. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the above necessarily reflect the actual situation. Also, the following explanation is only a guide. It should be noted that this is merely a speculation and does not affect the validity of the invention.

[0147] FIG. 31 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided thereon, and the source electrode (S) An insulating layer is provided to cover the drain electrode (D).

[0148] FIG. 32 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. In Figure 5, black circles (●) represent electrons, and white circles (○) represent holes, each of which has a charge (-q, +q) to the drain electrode. D >0), the dashed line indicates the gate When no voltage is applied to the output electrode (V G =0), the solid line indicates a positive voltage (VG >0) When no voltage is applied to the gate electrode, the potential barrier is high. Therefore, carriers (electrons) are not injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the Indicates the on status.

[0149] FIG. 33 shows an energy band diagram (schematic diagram) in the cross section taken along the line B-B' in FIG. Figure 33(A) shows the gate electrode (GE1) with a positive voltage (V G >0) is given This indicates the on state where carriers (electrons) flow between the source and drain electrodes. Also, FIG. 33(B) shows the state when a negative voltage (V G <0) was applied 10 shows the case where the transistor is in the OFF state (state where minority carriers do not flow).

[0150] Figure 34 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0151] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that cause them to become n-type. There are.

[0152] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level that it becomes genuine (type i) or as close to genuine as possible. That is, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are By removing the force, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. This allows the Fermi level (E F ) is the intrinsic Fermi level (E i ) It can be a degree.

[0153] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, In this case, no Schottky barrier is formed for electrons.

[0154] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. They move near the interface with the body (the lowest energetically stable part of the oxide semiconductor).

[0155] Also, as shown in FIG. 33(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. .

[0156] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, power frequencies from the VHF band to the microwave band are required. Insulating layers are produced by CVD using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer manufactured by a method such as the above.

[0157] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor can be reduced to 1×10 4 μm, channel length When (L) is 3 μm, 10 -13 Off-state current of less than A, sub- A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0158] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0159] <Modification> 6 to 9 show modified examples of the configuration of the semiconductor device. In the following, the following modified examples are mentioned: The following describes a case where the configuration of the transistor 162 is different from that described above. The configuration of the controller 160 is the same as above.

[0160] 6, a gate electrode 136d is provided under the oxide semiconductor layer 140, and a source electrode or drain electrode The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 14. The transistor 162 has a structure in which the lower surface of the transistor 162 is in contact with the oxide semiconductor layer 140. An example of a semiconductor device is shown below. The planar structure can be changed as needed to correspond to the cross section. Here, only the cross section will be shown.

[0161] The major difference between the configuration shown in FIG. 6 and the configuration shown in FIG. 2 is the source electrode or drain electrode. 142a or the source electrode or drain electrode 142b and the oxide semiconductor layer 140. That is, in the configuration shown in FIG. 2, the upper surface of the oxide semiconductor layer 140 is located at the source. The source or drain electrode 142a and the source or drain electrode 142b are in contact with each other. In contrast, in the configuration shown in FIG. 6, the lower surface of the oxide semiconductor layer 140 is connected to the source electrode or contacts the drain electrode 142a and the source or drain electrode 142b. Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. is different. The details of each component are the same as in Figure 2.

[0162] Specifically, the semiconductor device includes a gate electrode 136d provided on the interlayer insulating layer 128; A gate insulating layer 138 is provided on the gate electrode 136d. The source or drain electrode 142a, the source or drain electrode 142b and the source or drain electrode 142a, the source or drain electrode 142b. and an oxide semiconductor layer 140 in contact with the upper surface.

[0163] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0164] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0165] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0166] FIG. 7 shows an example of a configuration in which a gate electrode 136d is provided on an oxide semiconductor layer 140. 7A shows the source or drain electrode 142a and the source or drain electrode 142b. The oxide semiconductor layer 140 is connected to the lower surface of the oxide semiconductor layer 140 by a contact electrode 142b. 7B shows an example of a configuration in which the source electrode or drain electrode 142a and the source The drain electrode 142b is formed on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in contact with the conductor layer 140.

[0167] 7 is different from the configurations shown in FIGS. 2 and 6 in that a 7A and 7B. The major difference in the configuration is the source electrode or drain electrode 142a. The drain electrode 142b is located on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to the question of whether the other electrodes, insulators, The arrangement of layers is different. The details of each component are the same as in Figure 2.

[0168] Specifically, in FIG. 7A, the semiconductor device has a source electrode provided on an interlayer insulating layer 128. a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. an oxide semiconductor layer 140 formed on the oxide semiconductor layer 140; and a gate insulating layer 138 provided on the oxide semiconductor layer 140. , the gate electrode 136d in the region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138; , has.

[0169] 7B, the oxide semiconductor layer 140 provided over the interlayer insulating layer 128 and the oxide semiconductor layer 140 are A source electrode or a drain electrode 1 is provided in contact with the upper surface of the compound semiconductor layer 140. 42a, a source electrode or a drain electrode 142b, an oxide semiconductor layer 140, a source electrode or drain electrode 142a and the source or drain electrode 142b. The gate insulating layer 138 overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d in the region.

[0170] In the configuration shown in FIG. 7, compared to the configuration shown in FIG. 2, some components may be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in FIG. It goes without saying that components can be omitted.

[0171] FIG. 8 shows a case where the size of the element is relatively large, and a gate electrode is provided below the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the requirements for surface flatness and coverage are met. Since the requirements are relatively low, there is no need to embed wiring and electrodes in the insulating layer. For example, by patterning the conductive layer after it is formed, the gate electrode 136d and the like can be formed. Although not shown here, the transistor 160 can be formed as follows. can also be produced in the same manner.

[0172] The major difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 8(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact occurs on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0173] Specifically, in FIG. 8A, the semiconductor device has a gate electrode provided on an interlayer insulating layer 128. a gate insulating layer 138 provided on the gate electrode 136d; A source or drain electrode 142a, a source or drain electrode 142b, a source or drain electrode 142a; and an oxide semiconductor layer 140 in contact with the upper surface of the back electrode 142b.

[0174] In FIG. 8B, a gate electrode 136d is provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on the electrode 136d, and a gate electrode on the gate insulating layer 138 The oxide semiconductor layer 140 provided in a region overlapping with the oxide semiconductor layer 136d, A source electrode or drain electrode 142a provided in contact with the upper surface, a source electrode or a drain electrode 142b.

[0175] In addition, the configuration shown in FIG. 8 also omits some components compared to the configuration shown in FIG. 2. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0176] FIG. 9 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, too, consideration is given to the flatness of the surface and coverage. Since the requirements for the insulation layer are relatively low, wiring and electrodes do not need to be embedded in the insulation layer. For example, by performing patterning after forming the conductive layer, the gate electrode 136d and the like can be formed. Although not shown here, the transistor 160 can be formed as follows. It is possible to prepare it in the same way.

[0177] The major difference between the configuration shown in FIG. 9(A) and the configuration shown in FIG. 9(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact occurs on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0178] Specifically, in FIG. 9A, the semiconductor device has a source electrode provided on an interlayer insulating layer 128. a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. The oxide semiconductor layer 140, the source electrode or drain electrode 142a, The drain electrode 142b, the gate insulating layer 138 provided on the oxide semiconductor layer 140, and the gate The gate electrode 13 is provided in a region on the gate insulating layer 138 that overlaps with the oxide semiconductor layer 140. 6d and has.

[0179] 9B, the semiconductor device has an oxide semiconductor layer 124 formed on the interlayer insulating layer 128. 140, and a source electrode or A drain electrode 142a, a source or drain electrode 142b, and a source or drain electrode The drain electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 140 The gate insulating layer 138 is provided on the oxide semiconductor layer 140 and overlaps the gate insulating layer 138. and a gate electrode 136d provided in the overlapping region.

[0180] In addition, the configuration shown in FIG. 9 also omits some components compared to the configuration shown in FIG. 2. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0181] As described above, one embodiment of the disclosed invention realizes a semiconductor device with a novel structure. In this embodiment, the transistor 160 and the transistor 162 are stacked. However, the configuration of the semiconductor device is not limited to this example. In this configuration, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0182] For ease of understanding, the present embodiment will be described with reference to a semiconductor device with a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the components, it is possible to construct a more advanced semiconductor device. By using multiple devices, it is possible to configure a NAND or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0183] The semiconductor device according to this embodiment has a very low off-state current due to the low off-state current of the transistor 162. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a photo-emissive semiconductor device.

[0184] In addition, since information is written by the switching operation of the transistor 162, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. This means that there is no need to erase the information required in flash memory, etc. There are also benefits to this.

[0185] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0186] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0187] (Embodiment 2) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the present invention will be described. do.

[0188] FIG. 10 shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. The memory cell 200 shown in FIG. 10 is a multi-level type, and has a source line SL, a bit line BL, and , a first signal line S1, a second signal line S2, a word line WL, a transistor 201, and a transistor The circuit is composed of a transistor 202, a transistor 203, and a capacitance element 205. The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0189] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are The source line SL is electrically connected to one of the drain electrodes of the transistor. The source electrode of the transistor 201 is electrically connected to the drain electrode of the transistor 201. The source electrode of the transistor 203 is electrically connected to the bit line BL. The drain electrode of the transistor 203 is electrically connected to the first signal line S1. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to the second signal line. The word line S2 and the gate electrode of the transistor 202 are electrically connected to each other. The gate electrode of the transistor 203 is electrically connected to the capacitor 205. one electrode of the transistor 201 and the source electrode of the transistor 202 Alternatively, one of the drain electrodes is electrically connected to the capacitor 205, and the other electrode of the capacitor 205 is electrically connected to the A predetermined potential is applied, such as GND.

[0190] Next, the operation of the memory cell 200 shown in Fig. 10 will be described. The four states of the memory cell 200 are represented by data "00b", "01b", "10b", and "11b". " and the potentials of node A at that time are V00, V01, V10, and V11 (V00 <V01<V10<V11)とする。

[0191] When writing to the memory cell 200, the source line SL is set to 0 [V] and the word line WL is set to 0 [V]. V], the bit line BL is set to 0 [V], and the second signal line S2 is set to 2 V. When writing data "01b", the first signal line S1 is set to V00 [V]. When writing data "10b", the first signal line S1 is set to V01 [V]. The first signal line S1 is set to V10 [V]. When writing data "11b", S1 is set to V11 [V]. At this time, the transistor 203 is in the off state, and the transistor 2 When the write operation is completed, the potential of the first signal line S1 changes to Before this, the second signal line S2 is set to 0 [V] to turn off the transistor 202.

[0192] As a result, after writing data "00b", "01b", "10b", and "11b", The potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 is , approximately V00 [V], approximately V01 [V], approximately V10 [V], approximately V11 [V]. Node A A charge corresponding to the potential of the first signal line S1 is stored in the transistor 202. Since the current is extremely small or practically zero, the gate electrode of transistor 201 The potential is maintained for an extended period of time.

[0193] When reading the memory cell 200, first, the bit line BL is precharged, and Vp Then, the source line SL is set to Vs_read [V], and the word line WL is set to 2V, the second signal line S2 is set to 0V, and the first signal line S1 is set to 0V. 203 is in an on state and transistor 202 is in an off state.

[0194] As a result, a current flows from the source line SL to the bit line BL, and the bit line BL (the voltage at node A) The potential is charged to a potential expressed as (Vth) minus (Vth of the threshold voltage of the transistor 201). As a result, the bit line BL potential becomes data "00b", "01b", "10b", and "11b". V00-Vth, V01-Vth, V10-Vth, V11-Vth, respectively. The read circuit connected to the bit line BL reads the data "0 0b", "01b", "10b", and "11b" can be read.

[0195] FIG. 11 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0196] A semiconductor device according to one aspect of the present invention includes m word lines WL and second signal lines S2, and n A bit line BL, a first signal line S1, a source line SL, and a plurality of memory cells 200(1, 1) ~200(m, n) in a matrix of m rows x n columns (m, n are natural numbers) The memory cell array 210, the read circuit 211, and the first signal line driver circuit 21 2, a driving circuit 213 for the second signal line and the word line, and a peripheral circuit such as a potential generating circuit 214. As other peripheral circuits, a refresh circuit etc. may be provided. stomach.

[0197] Consider each memory cell (representatively, memory cell 200(i, j) where i is 1 or more) m is an integer equal to or less than m, and j is an integer equal to or greater than 1 and equal to or less than n) are bit lines BL(j), first signal lines S1(j ), the source line SL(j), the word line WL(i) and the second signal line S2(i), respectively. In addition, the bit lines BL(1) to BL(n) and the source lines SL(1) to SL(n) ) are connected to the readout circuit 211, and the first signal lines S1(1) to S1(n) are connected to the first signal line drive circuit In 212, the word lines WL(1) to WL(m) and the second signal lines S2(1) to S2(m) are 2 are connected to a drive circuit 213 for the signal lines and the word lines, respectively.

[0198] FIG. 12 shows an example of the driver circuit 213 for the second signal lines and word lines. The drive circuit 213 of the second signal line has a decoder 215. The decoder 215 is 2 and the word line WL via a switch. The word line WL is connected to GND (ground potential) via a switch. The switch is enabled by the read enable signal (RE signal) or the write enable signal (WE signal). The decoder 215 receives an address signal ADR from the outside.

[0199] When an address signal ADR is input to the driver circuit 213 for the second signal line and the word line, The row specified by the request (hereinafter referred to as the selected row) is asserted (enabled), and the other rows (hereinafter referred to as the The word lines WL are deasserted (deactivated). When the signal is asserted, it is connected to the output of the decoder 215 and the RE signal is deasserted. When the WE signal is asserted, the second signal line S2 is connected to the decoder 215. When the WE signal is deasserted, it is connected to the output of the

[0200] 13 shows an example of the first signal line driver circuit 212. The first signal line driver circuit 212 is a multi-channel driver circuit. The multiplexer (MUX1) has DI and write Potentials V00, V01, V10, and V11 are input. Output of multiplexer (MUX1) The terminal is connected to a first signal line S1 via a switch. The switch is connected to GND via the write enable signal (W E signal).

[0201] When DI is input to the first signal line driving circuit 212, the multiplexer (MUX1) outputs DI Depending on the value of V, the write potential Vw is selected from V00, V01, V10, and V11. The operation of the multiplexer (MUX1) is shown in Table 1. When the WE signal is asserted, the selected write potential Vw is applied to the first signal line S1, and when the WE signal is de-asserted 0V is applied to the first signal line S1 (the first signal line S1 is connected to GND).

[0202] [Table 1]

[0203] FIG. 14 shows an example of the read circuit 211. The read circuit 211 includes a plurality of sense amplifier circuits and a logic circuit 219 and the like. One input terminal of each sense amplifier circuit is connected to the bit line BL or the wiring Vpc via a switch. The other input terminal of each sense amplifier circuit receives one of the reference potentials Vref0, Vref1, Vref2. Also, the output terminal of each sense amplifier circuit is connected to the input terminal of the logic circuit 219. Note that the above switch is controlled by a read enable signal (RE signal).

[0204] By setting the values of the reference potentials Vref0, Vref1, Vref2 such that V00 - Vth < Vref0 < V 01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read as a 3-bit digital signal. For example, in the case of the data "00b", the potential of the bit line BL is V00 - Vth. This is a value smaller than any of the reference potentials Vref0, Vref1, Vref2. Therefore, the outputs SA_OUT0, SA_OUT1, SA_OUT 2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]]

[0205] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]]

[0206] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]]<0...> It seems there are some parts of the original text that are not fully shown in the provided content. If you can provide the complete text, I can give a more accurate translation. Also, please note that the tags like etc. are left as they are as per the instruction, but it's not clear if they are just part of the text or some special formatting that might need further clarification in a real-world scenario., the potential of the bit line BL is V01-Vth, and the output SA_OUT0 of the sense amplifier circuit , SA_OUT1, SA_OUT2 are "1", "0", "0" respectively, and the data In the case of "10b", the potential of the bit line BL is V10-Vth, and the sense amplifier circuit The outputs SA_OUT0, SA_OUT1, and SA_OUT2 are "1", "1", When the data is "0" and the data is "11b", the potential of the bit line BL is V11-Vth. The outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are respectively Then, the logic circuit 219 shown in the logic value table in Table 2 is is used to generate 2-bit data DO, which is output from the read circuit 211.

[0205] [Table 2]

[0206] In the illustrated read circuit 211, when the RE signal is deasserted, the source line SL is connected to GND, 0V is applied to the source line SL, and the bit line BL and A potential Vpc [V] is applied to the terminal of the sense amplifier circuit connected to the RE signal line BL. When the signal is asserted, Vs_read [V] is applied to the source line SL, resulting in The bit line BL is charged with a potential that reflects the data. The potential Vpc is set lower than V00-Vth. Vs_read is set to V11-Vt Make it higher than h.

[0207] The potential of the bit line BL to be compared during reading is set via a switch. This includes the potential of the node of the input terminal of the sense amplifier connected to the line BL. Furthermore, the potential compared in the read circuit does not necessarily have to be exactly the same as the potential of the bit line BL. There is no necessity.

[0208] FIG. 15 shows an example of the potential generation circuit 214. In the potential generation circuit 214, a desired potential can be generated by resistance division between Vdd and GND. Then, the generated potential is output via the analog buffer 220. In this way, the write potentials V00, V01, V10, V11, and the reference potentials Vref0, Vref1, Vref2 are generated. Note that, in FIG. 15, a configuration in which V00 < Vref0 < V01 < Vref1 < V10 < Vref2 < V11 is shown, but the magnitude relationship of the potentials is not limited to this. By adjusting the resistance elements and the nodes to be referred to, the necessary potentials can be generated as appropriate. Also, V00, V01, V10, V11 and Vref​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Apply potentials V1 and V2 for performing the operation. Then, set signal Sp to Low and signal Sn to High and supply power. If the potential before power supply is V1 > V2, V1 will output High, V2 will output Low. If V1 < V2, V1 will output Low and V2 will output High in this way. Thus, the difference between V1 and V2 is amplified.

[0211] An example of the timing chart for the write operation is shown in Fig. 16(A). What is shown in the figure is the timing chart when writing the data "10b" to the memory cell. The selected second signal line S2 becomes 0V earlier than the first signal line S1. The potential of the first signal line S1 during the write period is V10. Note that the word line WL, bit line BL, and source line SL are 0V. Also, An example of the timing chart for the read operation is shown in Fig. 16(B). What is shown in the figure is the timing chart when reading the data "10b" from the memory cell. When the selected word line WL is asserted and the source line SL becomes Vs_read[V], the bit line BL is charged to V10 - Vth[V] corresponding to the data "10b" of the memory cell. As a result, SA_OUT0, SA_OUT1, SA_OUT2 become "1", "1", "0" respectively. Note that the first signal line S1 and the second signal line S2 are 0V.

[0212] Here, an example of specific operating potentials (voltages) is shown. For example, the threshold voltage of transistor 201 can be set to approximately 0.3V, the power supply potential to VDD = 2V, V11 = 1.6V, V10 = 1.2 V, V01 = 0.8V, V00 = 0V, and Vref0 = 0.3V, Vref1 = ible to set the potential Vpc to, for example, 0V. 0.7V, Vref2 = 1.1V. It is also poss ible to set the potential Vpc to, for example, 0V.

[0213] In this embodiment, the first signal line S1 is arranged in the bit line BL direction (column direction), and the second signal line S2 is arranged in the bit line BL direction (column direction). Although the signal line S2 is arranged in the word line WL direction (row direction), this is not necessarily limited to this. For example, the first signal line S1 is arranged in the word line WL direction (row direction), and the The second signal line S2 may be arranged in the direction of the bit line BL (column direction). The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are appropriately Just place it.

[0214] In this embodiment, the operation of a four-level memory cell, that is, four different values ​​in one memory cell, is performed. Although the case where one of the states is written or read has been explained, the circuit configuration can be changed appropriately. By changing the value, an n-state memory cell can be placed in any of n different states (n is 2 or greater). It is possible to write and read any integer above.

[0215] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In the write operation, eight write potentials are prepared to determine the potential of node A, and eight states are generated. For readout, seven types of reference potentials are prepared that can distinguish between eight states. For readout, one sense amplifier is provided and seven comparisons can be performed to read out the data. In addition, by feeding back the comparison results, it is possible to reduce the number of comparisons to three. .

[0216] Generally, 2 k (k is an integer greater than or equal to 1)-valued memory cells have a higher memory capacity than binary memory cells. The capacity is k times larger. In the write operation, the write potential that determines the potential of node A is set to 2 k Type preparation Then, 2k Generates 2 states. k Two states that can be distinguished k -It is recommended to prepare one type of reference potential. k -1 comparison In addition, by feeding back the comparison results, It is also possible to reduce the number of times to k. 2 amplifiers k -It is also possible to set one and read it with one comparison. It is also possible to provide an amplifier and perform multiple comparisons.

[0217] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0218] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This can suppress the decrease in operating speed caused by the operation.

[0219] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0220] In addition, since the semiconductor device according to this embodiment is a multi-value type, it is possible to increase the storage capacity per area. Therefore, it is possible to achieve miniaturization and high integration of the semiconductor device. In the write operation, the potential of the floating node can be directly controlled. This makes it possible to easily control the threshold voltage with high precision, which is required for multi-value memory elements. This also eliminates the need to check the state after writing, which is required for multi-value memory elements. This allows you to reduce the time it takes to write data.

[0221] (Embodiment 3) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the present invention will be described. do.

[0222] In this embodiment, the circuit configuration of the memory element shown in FIG. 10 is used to implement a different method from that of the second embodiment. 10 shows a case where the capacitor element 205 is not provided. The memory element is a multi-valued type, and the case of a four-valued type will be explained. The state of node A is set to data "00b", "01b", "10b", and "11b". The potential is V00, V01, V10, V11 (V00 <V01<V10<V11)とする。

[0223] When writing to the memory cell 200, the source line SL is set to 0 [V] and the word line WL is set to 0 [V]. V], the bit line BL is set to 0 [V], and the second signal line S2 is set to 2 [V]. When writing, the first signal line S1 is set to V00 [V]. Data "01b" is written. In this case, the first signal line S1 is set to V01 [V]. When writing data "11b", the first signal line S1 is set to V10 [V]. The line S1 is set to V11 [V]. At this time, the transistor 203 is in the off state, When the write operation is completed, the potential of the first signal line S1 is Before the change, the second signal line S2 is set to 0 [V] to turn off the transistor 202. .

[0224] As a result, after writing data "00b", "01b", "10b", and "11b", The potentials of the nodes (hereinafter referred to as node A) connected to the gate electrodes of the transistors 201 are respectively Approximately V00 [V], approximately V01 [V], approximately V10 [V], approximately V11 [V]. At node A The charge corresponding to the potential of the first signal line S1 is accumulated in the transistor 202. Since the current is extremely small or substantially zero, the voltage of the gate electrode of the transistor 201 The position is maintained for a long time.

[0225] Next, when reading the memory cell 200, the source line SL is set to 0V and the word line WL is set to VDD, the second signal line S2 is set to 0V, the first signal line S1 is set to 0V, and the The read circuit 211 is put into an operating state. At this time, the transistor 203 is in an on state. Transistor 202 is turned off.

[0226] As a result, the effective resistance value of the memory cell 200 is determined depending on the state of the memory cell 200. The higher the potential at node A, the lower the effective resistance. The data "00b", "01b", "10b", and "11b" can be read based on the difference in value. Note that except for the state “00b” where the potential of the node A is the lowest, the transistor 201 is preferably in the ON state.

[0227] FIG. 19 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. 10 shows another example of a circuit diagram.

[0228] The semiconductor device shown in FIG. 19 includes m word lines WL and second signal lines S2, and n bit lines BL and the first signal line S1, and a plurality of memory cells 200(1, 1) to 200(m, n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (m and n are natural numbers). The array 210, the readout circuit 221, the first signal line driver circuit 212, the second signal line and It is composed of peripheral circuits such as a drive circuit 213 for the code line and a potential generating circuit 214. As other peripheral circuits, a refresh circuit or the like may be provided.

[0229] Consider each memory cell, e.g., memory cell 200(i,j), where i is between 1 and m, inclusive. where j is an integer between 1 and n). The memory cell 200(i, j) is connected to the bit line BL(j ), a first signal line S1(j), a word line WL(i) and a second signal line S2(i), a source line The bit lines BL(1) to BL(n) are connected to the read circuit 22. 1, the first signal lines S1(1) to S1(n) are connected to the first signal line driving circuit 212, and the word lines WL (1) to WL(m) and second signal lines S2(1) to S2(m) are second signal lines and word lines. Each is connected to a driving circuit 213 .

[0230] The potential generating circuit 214, the driver circuit 213 for the second signal line and the word line, the first signal line driver The configuration of the circuit 212 is the same as the configuration of FIG. 15, the configuration of FIG. 12, and the configuration of FIG. It can be concluded that

[0231] 20 shows an example of the read circuit 221. The read circuit 221 is a sense amplifier circuit , a reference cell 225, a logic circuit 219, a multiplexer (MUX2), a flip-flop circuit The reference cell 225 includes a transistor FF0, a transistor FF1, a transistor FF2, a bias circuit 223, etc. The reference cell 225 has a resistor 216, a transistor 217, and a transistor 218. The transistors 216, 217, and 218 are the transistors 201, 202 of the memory cell. 02, 203, and has the same circuit configuration as the memory cell. The transistor 6 and the transistor 218 are formed using a material other than an oxide semiconductor. The resistor 217 is preferably formed using an oxide semiconductor. If the reference cell 225 includes a capacitance element 205, the reference cell 225 also preferably includes a capacitance element. The two output terminals of the bias circuit 223 are connected to the bit lines BL and BL via switches, respectively. The reference cell 225 is connected to the drain electrode of the transistor 218. The output terminal of the sense circuit 223 is connected to the input terminal of the sense amplifier circuit. The output terminals of the paths are connected to the flip-flop circuits FF0, FF1, and FF2. The output terminals of the flop circuits FF0, FF1, and FF2 are connected to the input terminals of the logic circuit 219. The multiplexer (MUX2) receives the signals RE0, RE1, RE2, and the reference potential Vr ef0, Vref1, Vref2, and GND are input. The output terminal is connected to the source electrode or the drain electrode of the transistor 217 of the reference cell 225. Also, the bit line BL and the transistor of the reference cell 225 are connected to one of the poles. The drain electrode of the transistor 218 is connected to the wiring Vpc via a switch. The switch is controlled by a signal ΦA.

[0232] The read circuit 221 is configured to compare the conductance of the memory cell with that of the reference cell 225. This configuration has one sense amplifier circuit and performs three comparisons to read out four states. That is, for three kinds of reference potentials, the memory cell and the reference cell 2 The conductances of the signals RE0, RE1, RE2, and Φ are compared. A. The multiplexer (MUX2) is controlled by the signals RE0, RE1, and RE2. Depending on the value, three reference potentials Vref0, Vref1, Vref2 or GND are selected. The behavior of the multiplexer (MUX2) is shown in Table 3. The flip-flop circuits FF0, FF1, and FF2 are respectively connected to the signals RE0, RE1, and RE2. The value of the output signal SA_OUT of the sense amplifier is stored.

[0233] [Table 3]

[0234] The reference potential is V00 <Vref0<V01<Vref1<V10<Vref2<V11と By doing this, four states can be read out as a result of three comparisons. In the case of data "00b", the values ​​of FF0, FF1, and FF2 are "0", In the case of "0", "0", and data "01b", the values ​​of FF0, FF1, and FF2 are "1", When the data is "0", "0", or "10b", the values ​​of FF0, FF1, and FF2 are "1", "1 ", "0", data "11b", the values ​​of FF0, FF1, FF2 are "1", "1" In this way, the state of the memory cell is read out as a 3-bit digital signal. Then, using the logic circuit 219 represented by the logic value table shown in Table 2, The data DO of the bit is generated and output from the read circuit.

[0235] In the read circuit shown in FIG. 20, when the signal RE is deasserted, the bit lines BL and The reference cell 225 is connected to the wiring Vpc and precharged. The signal RE is asserted. The bit line BL and the bias circuit 223, and the reference cell 225 and the bias circuit 223 are respectively and conducts electricity.

[0236] In this circuit, the two inputs to the sense amplifier circuit are It is preferable to make the configurations of the circuits that generate the signals as similar as possible. It is preferable that the corresponding transistors in the memory cells 225 have the same configuration. It is preferable that the bias circuit 223 and the switch transistors have the same configuration.

[0237] The timing chart for the write operation is the same as that shown in FIG. An example of a timing chart is shown in Figure 21. The figure shows the data "10b" being read from a memory cell. This is a timing chart for reading. When signals RE0, RE1, and RE2 are asserted, During this period, Vref0 is applied to the output MUX2_OUT of the multiplexer (MUX2). , Vref1, and Vref2 are input. In the first half of each period, the signal ΦA is asserted, and the reference A predetermined potential is applied to node B of the transistor of cell 225. In the second half of each period, signal Φ A is deasserted, and a predetermined potential is maintained at node B of the transistor of the reference cell 225. At the same time, the drain electrode of the transistor 218 of the reference cell 225 is connected to the bias circuit The comparison result in the sense amplifier circuit is connected to the flip-flop circuit 223. It is stored in FF0, FF1, and FF2 respectively. When the data in the memory cell is "10b" The values ​​of the flip-flop circuits FF0, FF1, and FF2 are "1", "1", and "0". The first signal line S1 and the second signal line S2 are at 0V.

[0238] Next, a readout circuit and a readout method different from those shown in FIG. 20 will be described. .

[0239] 28 shows an example of the read circuit 222. The read circuit 222 is a sense amplifier circuit , a plurality of reference cells (reference cell 225a, reference cell 225b, reference cell 225c), a logic circuit The circuit 219 includes flip-flop circuits FF0, FF1, and FF2, and a bias circuit 223. do.

[0240] The plurality of reference cells 225a, 225b, and 225c are connected to the transistor 216, the transistor 217, and the transistor 218, respectively. The transistors 216, 217, and 218 are The transistors 201, 202, and 203 in the memory cell 200 correspond to the transistors 201, 202, and 203, respectively. It has the same circuit configuration as cell 200. Transistor 216 and transistor 218 are The transistor 217 is formed using a material other than an oxide semiconductor. In addition, when the memory cell has a capacitance element 205, Preferably, the reference cell also has a capacitance element. are connected to the bit line BL and the transistors 2 of the plurality of reference cells via switches, respectively. The output terminal of the bias circuit 223 is connected to the drain electrode of the sense amplifier 18. The output terminal of the sense amplifier circuit is connected to the input terminal of the flip-flop circuit. Connected to FF0, FF1, and FF2. The output terminal is connected to the input terminal of the logic circuit 219. The drain electrode of the transistor 218 of the reference cell is connected to the wiring Vpc via a switch. The above switch is controlled by a read enable signal (RE signal). do.

[0241] The read circuit 222 is configured to compare the conductance of a memory cell with that of a plurality of reference cells. This configuration has one sense amplifier circuit and performs three comparisons to read out four states. That is, the conductance of the memory cell and three reference cells are compared. The three comparisons are controlled by signals RE0, RE1, and RE2. The gate electrode of the transistor 216 is connected to Vref0 and Vr Before reading, assert the signal ΦA. Then, all the transistors 217 are turned on, and writing to the reference cell is performed. Writing to the reference cell can be done once before the read operation. It may be done once or every time the data is output. 1, FF2 are controlled by signals RE0, RE1, RE2, respectively, and the sense amplifier The value of the output signal SA_OUT is stored.

[0242] The reference potential is V00 <Vref0<V01<Vref1<V10<Vref2<V11と By doing this, four states can be read out as a result of three comparisons. In the case of data "00b", the values ​​of FF0, FF1, and FF2 are "0", In the case of "0", "0", and data "01b", the values ​​of FF0, FF1, and FF2 are "1", When the data is "0", "0", or "10b", the values ​​of FF0, FF1, and FF2 are "1", "1 ", "0", data "11b", the values ​​of FF0, FF1, FF2 are "1", "1" In this way, the state of the memory cell is read out as a 3-bit digital signal. Then, using the logic circuit 219 represented by the logic value table shown in Table 2, The data DO of the bit is generated and output from the read circuit.

[0243] In the read circuit shown in FIG. 28, when the RE signal is deasserted, the bit line BL The reference cell 225 is connected to the wiring Vpc and precharged. Then, the bit line BL and the bias circuit 223, the plurality of reference cells 225 and the bias circuit 223 are each conductive.

[0244] In this circuit, the signal input to the sense amplifier circuit is It is preferable to make the circuit configurations for generating the reference cell and the memory cell as similar as possible. It is preferable that the corresponding transistors in the corresponding bias circuits 223 have the same configuration. It is preferable that the transistors of the switches have the same configuration.

[0245] The timing chart for the write operation is the same as that shown in FIG. An example of a timing chart is shown in Figure 29. The figure shows the data "10b" being read from a memory cell. This is a timing chart for reading. Between them, reference cells 225a, 225b, and 225c are selected, respectively. The bias circuit 223 is connected to the sense amplifier circuit 224. The comparison result in the sense amplifier circuit is The data is stored in the flop circuits FF0, FF1, and FF2. In the case of "0b", the values ​​of the flip-flop circuits FF0, FF1, and FF2 are "1", "1" , "0." The first signal line S1 and the second signal line S2 are at 0V.

[0246] A specific example of the operating potential (voltage) is shown below. For example, the threshold voltage of the transistor 201 is Approximately 0.3V, power supply voltage is VDD=2V, V11=1.6V, V10=1.2V, V0 1=0.8V, V00=0V, and Vref0=0.6V, Vref1=1.0V, Vr It is possible to set ef2=1.4 V. The potential Vpc may be set to 0 V, for example.

[0247] In this embodiment, the first signal line S1 is arranged in the bit line BL direction (column direction), and the second signal line S2 is arranged in the bit line BL direction (column direction). Although the signal line S2 is arranged in the word line WL direction (row direction), this is not necessarily limited to this. For example, the first signal line S1 is arranged in the word line WL direction (row direction), and the The second signal line S2 may be arranged in the direction of the bit line BL (column direction). The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are appropriately Just place it.

[0248] In this embodiment, the operation of a four-level memory cell, that is, four different values ​​in one memory cell, is performed. Although the case where one of the states is written or read has been explained, the circuit configuration can be changed appropriately. By changing the value, an n-state memory cell can be placed in any of n different states (n is 2 or greater). It is possible to write and read any integer above.

[0249] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In the write operation, eight write potentials are prepared to determine the potential of node A, and eight states are generated. For readout, seven types of reference potentials are prepared that can distinguish between eight states. For readout, one sense amplifier is provided and seven comparisons can be performed to read out the data. In addition, by feeding back the comparison results, it is possible to reduce the number of comparisons to three. In the read method that drives the source line SL, seven sense amplifiers are provided, so that It is also possible to read out the data by comparing it once. It is also possible to configure it so that this is done.

[0250] Generally, 2 k (k is an integer greater than or equal to 1)-valued memory cells have a higher memory capacity than binary memory cells. The capacity is k times larger. In the write operation, the write potential that determines the potential of node A is set to 2 k Type preparation Then, 2 k Generates 2 states. k Two states that can be distinguished k -It is recommended to prepare one type of reference potential. k -1 comparison In addition, by feeding back the comparison results, It is also possible to reduce the number of times to k. 2 amplifiers k - One sense amplifier can be provided and read out in one comparison. It is also possible to provide a pump to perform multiple comparisons.

[0251] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0252] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This can suppress the decrease in operating speed caused by the operation.

[0253] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0254] In addition, since the semiconductor device according to this embodiment is a multi-value type, it is possible to increase the storage capacity per area. Therefore, it is possible to achieve miniaturization and high integration of the semiconductor device. In the write operation, the potential of the floating node can be directly controlled. This makes it possible to easily control the threshold voltage with high precision, which is required for multi-value memory elements. This also eliminates the need to check the state after writing, which is required for multi-value memory elements. This allows you to reduce the time it takes to write data.

[0255] (Fourth embodiment) In this embodiment, an example of a circuit configuration and operation of a semiconductor device different from those in the second and third embodiments will be described. This article explains:

[0256] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 240 includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, and a The gate line WL is composed of a transistor 201, a transistor 202, and a capacitance element 204. The transistor 201 is formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0257] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are One of the drain electrodes and one of the electrodes of the capacitor 204 are electrically connected. The source line SL and the source electrode of the transistor 201 are electrically connected, and the bit line BL and the drain electrode of the transistor 201 are electrically connected to the first signal line S1. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to The second signal line S2 and the gate electrode of the transistor 202 are electrically connected to each other. The WL and the other electrode of the capacitor 204 are electrically connected to each other.

[0258] Next, the operation of the memory cell 240 shown in Figure 22 will be described. The four states of the memory cell 240 are data "00b", "01b", "10b", "11b", and the potentials of node A at that time are V00, V01, V10, and V11 ( V00 <V01<V10<V11)とする。

[0259] When writing to the memory cell 240, the source line SL is set to 0 [V] and the word line WL is set to 0 [V]. V], the bit line BL is set to 0 [V], and the second signal line S2 is set to VDD. When writing data "01b", the first signal line S1 is set to V00 [V]. In this case, the first signal line S1 is set to V01 [V]. When writing data "10b", The first signal line S1 is set to V10 [V]. When writing data "11b", the first signal The line S1 is set to V11 [V]. At this time, the transistor 201 is in the off state, and the transistor 202 is turned on. When writing is completed, the potential of the first signal line S1 is changed. Before the conversion, the second signal line S2 is set to 0 [V] to turn off the transistor 202.

[0260] As a result, after writing data "00b", "01b", "10b", "11b" (word The potential of the line WL is set to 0V) and the node connected to the gate electrode of the transistor 201 (hereinafter The potentials of the nodes (bottom, node A) are approximately V00 [V], V01 [V], and V10 [V], respectively. The potential is approximately V11 [V]. A charge corresponding to the potential of the first signal line S1 is accumulated at node A. However, since the off-state current of the transistor 202 is extremely small or substantially zero, The potential of the gate electrode of transistor 201 is maintained for a long period of time.

[0261] When reading the memory cell 240, the source line SL is set to 0V, and the second signal line S2 is set to 0V. The first signal line S1 is set to 0V, and the read circuit connected to the bit line BL is set to an operating state. At this time, the transistor 202 is turned off.

[0262] The word line WL is set to V_WL [V]. The potential of the node A of the memory cell 240 is The potential of the word line WL is higher, and the potential of the memory cell 240 is higher. For example, for a memory cell in four different states, the potential of the word line WL is When the potential is changed from low to high, the transistor of the memory cell of data "11b" 201 is turned on first, followed by data "10b", "01b", and "00b". The memory cells are sequentially turned on. This is achieved by appropriately selecting the word line WL potential. This means that the state of the memory cell (i.e., the data in the memory cell) can be identified. By appropriately selecting the potential of the word line WL, the memory cell in which the transistor 201 is in the ON state is low. The memory cell in which the transistor 201 is off is in a high resistance state. By distinguishing this resistance state using a read circuit, data "00b", "01b", "10b" and "11b" can be read out.

[0263] FIG. 23 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. 10 shows another example of a circuit diagram.

[0264] The semiconductor device shown in FIG. 23 includes m word lines WL and second signal lines S2, and n bit lines BL and the first signal line S1, and a plurality of memory cells 240(1, 1) to 240(m, n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (m and n are natural numbers). The array 210, the readout circuit 231, the first signal line driver circuit 212, the second signal line and The circuit is composed of peripheral circuits such as a drive circuit 233 for the code line and a potential generating circuit 214. As other peripheral circuits, a refresh circuit or the like may be provided.

[0265] Consider each memory cell, e.g., memory cell 240(i,j), where i is between 1 and m, inclusive. where j is an integer between 1 and n. The memory cell 240(i, j) is connected to the bit line BL(j ), a first signal line S1(j), a word line WL(i) and a second signal line S2(i), a source line S L. The bit lines BL(1) to BL(n) are connected to the read circuit 2. 31, the first signal lines S1(1) to S1(n) are connected to the first signal line driving circuit 212, and the word lines W L(1) to WL(m) and second signal lines S2(1) to S2(m) are connected to the second signal line S2 and the work The light emitting diodes 231 and 232 are connected to the drive circuits 233 of the light emitting diodes WL.

[0266] The first signal line driver circuit 212 and the potential generating circuit 214 are configured as shown in FIG. 13 and FIG. The configuration shown in FIG. 15 can be applied.

[0267] An example of a read circuit is shown in Figure 24. The read circuit includes a sense amplifier circuit, a flip-flop circuit, and a The bias circuit 224 is connected via a switch. The bias circuit 224 is connected to the input terminal of the sense amplifier circuit. The other input terminal of the sense amplifier circuit is connected to a reference potential Vr. The output terminal of the sense amplifier circuit is connected to the input terminal of the flip-flop circuits FF0 and FF1. The above switches are controlled by the read enable signal (RE signal). The read circuit is controlled by the conduction of the specified memory cell connected to the bit line BL. Data can be read by reading the capacitance of the memory cell. Reading the inductance means checking whether the transistor 201 constituting the memory cell is in an on state or This refers to reading out the OFF state.

[0268] The read circuit shown in FIG. 24 has one sense amplifier circuit and can distinguish between four different states. The two comparisons are controlled by the signals RE0 and RE1. The flip-flop circuits FF0 and FF1 are controlled by signals RE0 and RE1, respectively. The output of the flip-flop circuit FF0 is controlled by the CLKOUT pin and stores the value of the output signal of the sense amplifier circuit. The output of the flip-flop circuit FF1 is read as DO[1] and the output of the flip-flop circuit FF2 is read as DO[0]. and output from the circuit.

[0269] In the illustrated read circuit, when the RE signal is deasserted, the bit line BL is When the RE signal is asserted, the bit line BL and bias The ass circuit 224 is conductive. Note that precharging does not have to be performed.

[0270] FIG. 25 shows another example of the drive circuit 233 for the second signal line S2 and the word line WL.

[0271] The second signal line and word line driver circuit 233 shown in FIG. 25 receives the address signal ADR. When the address is asserted, the line specified by the address (selected line) is asserted, and the other lines (non-selected lines) are deasserted. The second signal line S2 is connected to the decoder output when the WE signal is asserted. When the WE signal is deasserted, the selected word line WL is connected to GND. The output V_WL of the multiplexer (MUX3) is connected to the GND. The multiplexer (MUX3) is connected according to the values ​​of the signals RE0, RE1, and DO0. , one of three reference potentials Vref0, Vref1, Vref2, or GND. The behavior of the multiplexer (MUX3) is shown in Table 4.

[0272] [Table 4]

[0273] Three types of reference potentials Vref0, Vref1, Vref2 (Vref0 <Verf1<Vr Vref0 is the potential of the word line WL. In this case, the transistor 201 of the memory cell storing data "00b" is turned off, and the 01b" is selected to turn on the transistor 201 of the memory cell. When ref1 is selected as the potential of the word line WL, it is the memory of data "01b". The transistor 201 of the memory cell is turned off, and the transistor of the memory cell of data "10b" is turned off. The potential Vref2 is selected to turn on the word line W When the potential of the transistor 201 of the memory cell of data "10b" is selected as the potential of L, is turned off, and the transistor 201 of the memory cell with data "11b" is turned on. Select the potential.

[0274] This readout circuit performs two comparisons to read out the signal. The first comparison uses Vref1. The second time, if the comparison result using Vref1 is FF0, Vref If it is "1", it will be compared with Vref2. This allows four states to be read out by two comparisons.

[0275] The timing chart for the write operation is the same as that shown in FIG. An example of the timing chart is shown in FIG. 26. The figure shows that data “1 This is a timing chart for reading "0b". RE0 and RE1 are asserted. Between them, Vref1 and Vref2 are input to the selected word lines WL, and the sense The comparison results from the amplifier circuit are stored in flip-flop circuits FF0 and FF1. When the data in the memory cell is "10b", the flip-flop circuits FF0 and FF1 The values ​​are "1" and "0." The first signal line S1 and the second signal line S2 are at 0V.

[0276] A specific example of the operating potential (voltage) is shown below. For example, the threshold voltage V The potential of node A is determined by the capacitance C1 between the word line WL and node A and the transistor The gate capacitance C2 of the transistor 202 is Assume that C1 / C2>>1 when O2 is off and C1 / C2=1 when it is on. 1 shows the relationship between the potential of the node A and the potential of the word line WL when the source line SL is at 0V. For example, when writing data "00b", the node A potential is set to 0V, and when writing data "01b", the node A potential is set to 0V. The node A potential for data “10b” is set to 0.8V, the node A potential for data “10b” is set to 1.2V, and the node A potential for data “11 If the node A potential of b” is 1.6V, the reference potential is Vref0=0.8V, Vref It can be seen that it is best to set Vref1=1.2V and Vref2=2.0V.

[0277] After writing (when the word line WL potential is 0V), the potential of the node A of the transistor 201 is , preferably equal to or lower than the threshold voltage of the transistor 201.

[0278] In this embodiment, the first signal line S1 is arranged in the bit line BL direction (column direction), and the second signal line S2 is arranged in the bit line BL direction (column direction). Although the signal line S2 is arranged in the word line WL direction (row direction), this is not necessarily limited to this. For example, the first signal line S1 is arranged in the word line WL direction (row direction), and the The second signal line S2 may be arranged in the direction of the bit line BL (column direction). The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are appropriately Just place it.

[0279] In this embodiment, the operation of a four-level memory cell, that is, four different values ​​in one memory cell, is performed. Although the case where one of the states is written or read has been explained, the circuit configuration can be changed appropriately. By changing the value, an n-state memory cell can be placed in any of n different states (n is 2 or greater). It is possible to write and read any integer above.

[0280] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In the write operation, eight write potentials are prepared to determine the potential of node A, and eight states are generated. For readout, seven types of reference potentials are prepared that can distinguish between eight states. For readout, one sense amplifier is provided and seven comparisons can be performed to read out the data. In addition, by feeding back the comparison results, it is possible to reduce the number of comparisons to three. In the read method that drives the source line SL, seven sense amplifiers are provided, so that It is also possible to read out the data by comparing it once. It is also possible to configure it so that this is done.

[0281] Generally, 2 k (k is an integer greater than or equal to 1)-valued memory cells have a higher memory capacity than binary memory cells. The capacity is k times larger. In the write operation, the write potential that determines the potential of node A is set to 2 k Type preparation Then, 2 k Generates 2 states. k Two states that can be distinguished k -It is recommended to prepare one type of reference potential. k -1 comparison In addition, by feeding back the comparison results, It is also possible to reduce the number of times to k. 2 amplifiers k - One sense amplifier can be provided and read out in one comparison. It is also possible to provide a pump to perform multiple comparisons.

[0282] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0283] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This can suppress the decrease in operating speed caused by the operation.

[0284] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0285] In addition, since the semiconductor device according to this embodiment is a multi-value type, it is possible to increase the storage capacity per area. Therefore, it is possible to achieve miniaturization and high integration of the semiconductor device. In the write operation, the potential of the floating node can be directly controlled. This makes it possible to easily control the threshold voltage with high precision, which is required for multi-value memory elements. This also eliminates the need to check the state after writing, which is required for multi-value memory elements. This allows you to reduce the time it takes to write data.

[0286] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment is a semiconductor device that does not require power supply. Even if the data is written or erased, it is possible to retain the data. Furthermore, the operation is also fast. Therefore, it is possible to use this semiconductor device to develop new electrical circuits. It is possible to provide a sub-device. The semiconductor device is then mounted on a circuit board or the like and installed inside various electronic devices.

[0287] FIG. 30A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to one embodiment of the present invention is implemented in a notebook personal computer. By applying this technology, it is possible to retain information even when there is no power supply. There is no deterioration due to writing and erasing. Furthermore, the operation is fast. The semiconductor device according to the present invention is preferably applied to a notebook personal computer. is.

[0288] FIG. 30B shows a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. The stylus 312 is also provided as an accessory for operation. By applying the semiconductor device according to the present invention to a PDA, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one aspect of the present invention to a PDA. is.

[0289] FIG. 30C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The semiconductor device 320 can be used like a paper book. By applying this technology to electronic paper, it is possible to retain information even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply a semiconductor device according to one embodiment of the present invention to electronic paper. do.

[0290] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display section (display section 325 in FIG. 30(C)) and the text is displayed on the left display section (display section 325 in FIG. 30(C)). In (C), an image can be displayed on the display unit 327).

[0291] FIG. 30C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0292] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0293] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0294] FIG. 30D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. By applying the semiconductor device to a mobile phone, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. For this reason, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone. It is suitable.

[0295] The display panel 342 has a touch panel function, and in FIG. 30(D) an image is displayed. The multiple operation keys 345 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 9 to the voltage required for each circuit. In addition to the above configuration, it may be configured to incorporate a contactless IC chip, a small recording device, etc. It is also possible.

[0296] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0297] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication functions, television reception functions, etc.

[0298] FIG. 30(E) shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the present invention to a digital camera, information can be stored even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is suitable for a digital camera. It is preferable to use

[0299] FIG. 30F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. 371 is shown as a supported configuration.

[0300] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying information may be provided. By applying the body device to a television device, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is applied to a television set. This is preferable.

[0301] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). It is possible to do this.

[0302] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0303] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108a Gate insulating layer 110a gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 200 memory cells 201 Transistor 202 Transistor 203 Transistor 204 Capacitor element 205 Capacitor 210 memory cell array 211 Readout circuit 212 Signal line driver circuit 213 Drive Circuit 214 Potential generation circuit 215 decoder 216 Transistor 217 Transistor 218 Transistor 219 Logic Circuits 220 Analog Buffer 221 Readout circuit 222 readout circuit 223 Bias Circuit 224 Bias Circuit 225 Reference Cells 225a Reference Cell 225b Reference Cell 225c Reference Cell 231 Readout circuit 232 readout circuit 233 Drive Circuit 240 memory cells 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device

Claims

1. A plurality of circuits arranged in a matrix, At least one of the circuits includes a first transistor and a second transistor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor; a channel formation region of the first transistor includes silicon; a channel formation region of the second transistor includes an oxide semiconductor; each of the plurality of circuits is a multi-valued type; the second transistor is a semiconductor device having a function of holding a potential of n value (n is an integer of 2 or more) applied to a gate of the first transistor, a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having the same material as the second conductive layer and electrically connected to one of the source region or the drain region of the first transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the fourth conductive layer; the second conductive layer is electrically connected to the first conductive layer through an opening in the first insulating layer; the second conductive layer has an overlapping region with the first conductive layer, a width of the oxide semiconductor layer in the channel length direction of the second transistor being larger than a width of the third conductive layer in the channel length direction of the second transistor in a cross-sectional view in the channel length direction of the second transistor.

2. A plurality of circuits arranged in a matrix, At least one of the circuits includes a first transistor and a second transistor; a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor; a channel formation region of the first transistor includes silicon; a channel formation region of the second transistor includes an oxide semiconductor; each of the plurality of circuits is a multi-valued type; the second transistor is a semiconductor device having a function of holding a potential of n value (n is an integer of 2 or more) applied to a gate of the first transistor, a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having the same material as the second conductive layer and electrically connected to one of the source region or the drain region of the first transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the fourth conductive layer; the second conductive layer is electrically connected to the first conductive layer through an opening in the first insulating layer; the second conductive layer has an overlapping region with the first conductive layer, In a cross-sectional view in a channel length direction of the second transistor, a width of the oxide semiconductor layer in the channel length direction of the second transistor is larger than a width of the third conductive layer in the channel length direction of the second transistor; a channel formation region of the first transistor not overlapping with the oxide semiconductor layer;

3. In claim 1 or 2, The second conductive layer has a region overlapping with the third conductive layer.

Images