Compensation method and device for digital power amplifier

Abstract

Systems, methods, apparatus, and computer-readable media for power amplifier gain error compensation for a digital power amplifier (DPA) are provided.SOLUTION: A signal compensation method for digitally correcting gain characteristics of a DPA includes obtaining an in-phase (I) component and a quadrature-phase (Q) component of baseband samples corresponding to an in-phase input amplitude code and a quadrature-phase input amplitude code, distorting the in-phase input amplitude code based on first gain predistortion information corresponding to an in-phase signal branch of the DPA to generate an I-component predistorted output amplitude code, distorting the quadrature-phase input amplitude code based on second gain predistortion information corresponding to a quadrature-phase signal branch of the DPA to generate a Q-component predistorted output amplitude code, and the DPA is driven using the I-component and Q-component predistorted output amplitude codes to generate a radio frequency (RF) output.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Australian Provisional Patent Application No. 2024902178, filed July 15, 2024, which is incorporated herein by reference in its entirety and for all purposes.

[0002] For example, aspects of the present disclosure relate to power amplifier gain error compensation in a digital power amplifier (DPA) that transmits radio frequency signals over a wireless medium. [Background technology]

[0003] Power amplifiers (PAs) are used in radio frequency (RF) transmitters to transmit electromagnetic energy. The efficiency of a power amplifier significantly affects the power consumption of a wireless transceiver. In recent years, digital power amplifiers (DPAs) have attracted attention because DPAs can integrate multiple functions and / or functionalities, such as a digital-to-analog converter (DAC), a frequency upconverter / mixer, and a PA. Using DPAs in RF transceivers can improve the energy efficiency of the RF transceiver and reduce its power consumption. Furthermore, the chip area associated with the physical implementation of the RF transceiver can be reduced (e.g., based on multiple functions integrated into or by the DPA). High-power DPAs can be associated with relatively high power consumption and may employ various techniques to optimize efficiency. However, the efficiency optimization(s) used in existing high-power DPAs can also introduce distortion, especially when the input amplitude code driving the DAC (e.g., a DAC included or integrated within the DPA) is large.

[0004] The in-phase (I) and quadrature-phase (Q) components of an input signal can be separated and coupled to different sections of a DPA. Coding circuits within the DPA are used to map the amplitudes of the I and Q components to drive these separate sections of the DPA. The signals from each section are then summed (e.g., recombined) to generate the DPA's final output. A switched-capacitor power amplifier (ScPa) is a type of DPA that uses capacitors, along with transistors acting as switches, to achieve high linearity and efficiency, especially at high output power levels. In an ScPa architecture, capacitors in the array are selectively driven (or not) by an input clock signal, thereby turning them on or off. This selective activation of capacitors can be controlled by an amplitude code derived from the amplitudes of the I and Q components of the input signal. For example, the amplitudes of the I and Q components can be coded into amplitude codes that can be used to control which capacitors are turned on in each capacitor array of the ScPa. Summary of the Invention

[0005] The following provides a simplified summary related to one or more aspects disclosed herein. As such, the following summary should not be considered an extensive overview related to all contemplated aspects, nor should it be considered to identify essential or critical elements related to all contemplated aspects or to delineate the scope related to any particular aspect. As such, the following summary is intended only to present certain concepts related to one or more aspects related to the mechanisms disclosed herein in a simplified form, prior to the detailed description presented below.

[0006] Disclosed are systems, methods, apparatus, and computer-readable media for power amplifier gain error compensation in a digital power amplifier (DPA). According to at least one illustrative example, a signal compensation method is provided for digitally correcting the gain characteristic of a DPA. For example, a compensation method is provided for digitally correcting the gain characteristic of a digital power amplifier (DPA). The method includes the steps of obtaining in-phase (I) and quadrature-phase (Q) components of a baseband sample (the I component is associated with an in-phase input amplitude code and the Q component is associated with a quadrature-phase input amplitude code); distorting the in-phase input amplitude code based on first gain pre-compensation information corresponding to the in-phase signal branch of the DPA, thereby generating a pre-distortion output amplitude code for the I component; distorting the quadrature-phase input amplitude code based on second gain pre-compensation information corresponding to the quadrature-phase signal branch of the DPA, thereby generating a pre-distortion output amplitude code for the Q component (the first gain pre-compensation information is different from the second gain pre-compensation information); and driving the DPA using the pre-distortion output amplitude codes of the I and Q components to generate a radio frequency (RF) output.

[0007] In some embodiments, the RF output is a compensated RF output that is free of gain error distortion.

[0008] In some aspects, the nonlinear gain applied by the DPA to generate the RF output is canceled by the respective predistortions associated with the predistortion output amplitude codes of each of the I and Q components.

[0009] In some embodiments, the DPA is a multi-section DPA that includes multiple sections arranged in a multi-section DPA configuration.

[0010] In some aspects, the compensation method further comprises estimating a respective gain from each of the multiple sections in the multi-section DPA configuration, and deriving first gain pre-compensation information and second gain pre-compensation information based on the respective gains estimated from each section.

[0011] In some aspects, the first gain pre-distortion information comprises a first pre-distortion characteristic comprising a first piecewise linear function across multiple sections of the multi-section DPA configuration, and the second gain pre-distortion information comprises a second pre-distortion characteristic comprising a second piecewise linear function across multiple sections of the multi-section DPA configuration.

[0012] In some aspects, the number of linear sections included in the first or second piecewise linear function corresponds to the number of sections in the multi-section DPA configuration.

[0013] In some aspects, the DPA is a switched capacitor power amplifier (ScPa) that includes multiple sections.

[0014] In some aspects, the DPA includes at least a first section and a second section, and the range of possible output amplitude codes for the I component is divided into a first interval and a second interval, and the range of possible output amplitude codes for the Q component is divided into a first interval and a second interval.

[0015] In some aspects, a first section of the DPA is controlled by one or more of a predistortion output amplitude code of the I component in the first interval or a predistortion output amplitude code of the Q component in the second interval, and a second section of the DPA is controlled by one or more of a predistortion output amplitude code of the Q component in the first interval or a predistortion output amplitude code of the I component in the second interval.

[0016] In some aspects, the compensation method further comprises compensating for phase modulation (PM)-amplitude modulation (AM) distortion of the baseband samples related to a phase component of the baseband samples.

[0017] In some aspects, the DPA is a multi-section DPA including multiple sections, and compensating for PM-AM distortion includes converting initial I and Q components of the baseband sample into amplitude and phase components; selecting a respective section from the multiple sections of the multi-section DPA (each section is selected based on the phase component of the baseband sample, and each section is associated with a slope and intercept corresponding to the gain characteristic of the multi-section DPA within the respective section); deriving an amplitude correction value for the baseband sample based on the slope and intercept corresponding to the gain characteristic of the multi-section DPA within the respective section; and calculating a pre-distortion amplitude of the baseband sample from the amplitude component and the amplitude correction value (the I and Q components of the baseband sample are generated using the pre-distortion amplitude).

[0018] In some aspects, the compensation method further includes compensating for amplitude modulation (AM)-phase modulation (PM) distortion of the baseband samples with respect to I and Q components of the baseband samples.

[0019] In some embodiments, the DPA is a multi-section DPA including multiple sections, and compensating for AM-PM distortion includes selecting a respective section from the multiple sections of the multi-section DPA (each section is selected based on an initial Q component of a baseband sample, and each section is associated with a slope and intercept corresponding to a gain characteristic of the multi-section DPA within the respective section), deriving a phase error based on the slope and intercept corresponding to the gain characteristic of the multi-section DPA within the respective section, and calculating a pre-compensation output based on the initial I component of the baseband sample and the phase error (the I component of the baseband sample is the pre-compensation output).

[0020] In some embodiments, the DPA is a multi-section DPA including multiple sections, and compensating for AM-PM distortion includes selecting a respective section from the multiple sections of the multi-section DPA (each section is selected based on an initial I component of a baseband sample, and each section is associated with a slope and intercept corresponding to a gain characteristic of the multi-section DPA within the respective section), deriving a phase error based on the slope and intercept corresponding to the gain characteristic of the multi-section DPA within the respective section, and calculating a pre-compensation output based on the initial Q component and phase error of the baseband sample (the Q component of the baseband sample is the pre-compensation output).

[0021] In another illustrative example, a correction method is provided for digitally correcting amplitudes of baseband samples associated with transmission by a digital power amplifier (DPA), the method including obtaining amplitude and phase components of the baseband samples, selecting respective sections from a plurality of sections included in the DPA based on the phase components of the baseband samples, determining a slope and an intercept corresponding to a gain characteristic or gain error of the DPA within each section, deriving amplitude correction values ​​for the baseband samples based on the slope and intercept, calculating a predistortion amplitude of the baseband samples from the amplitude components and the amplitude correction values, generating in-phase (I) and quadrature-phase (Q) signal components for the baseband samples based on use of the predistortion amplitude and phase components, and driving the DPA using the I and Q signal components to generate a radio frequency (RF) output.

[0022] In another illustrative example, a method for digitally correcting amplitudes of baseband samples associated with transmission by a digital power amplifier (DPA) is provided, the method including: obtaining in-phase (I) and quadrature-phase (Q) components of the baseband samples; determining a selected I-segment from a plurality of I-segment ranges configured for the DPA (the selected I-segment is selected based on a value of the I-component of the baseband samples); determining an I-slope and an I-intercept corresponding to the selected I-segment; determining a selected Q-segment from a plurality of Q-segment ranges configured for the DPA (the selected Q-segment is selected based on a value of the Q-component of the baseband samples); determining a Q-slope and a Q-intercept corresponding to the selected Q-segment; deriving a Q-phase error based on the I-slope and I-intercept, deriving an I-phase error based on the Q-slope and Q-intercept, calculating a precompensated Q output from the Q-component and the Q-phase error, calculating a precompensated I output from the I-component and the I-phase error, and driving the DPA using the precompensated I-output and the Q-output to generate a radio frequency (RF) output.

[0023] In another illustrative example, a wireless device for transmitting radio frequency (RF) signals over a wireless medium is provided. The wireless device includes one or more digital filters configured to receive and upsample in-phase (I) and quadrature-phase (Q) components of baseband samples (the I component is associated with an in-phase input amplitude code and the Q component is associated with a quadrature-phase input amplitude code), a power amplifier (PA) gain error compensation module coupled to the one or more digital filters, and a digital power amplifier (DPA) coupled to the PA gain error compensation module. The PA gain error compensation module is configured to distort the in-phase input amplitude code based on first gain pre-compensation information corresponding to the in-phase signal branch of the DPA, thereby generating a pre-distortion output amplitude code for the I component, and to distort the quadrature-phase input amplitude code based on second gain pre-compensation information corresponding to the quadrature-phase signal branch of the DPA, thereby generating a pre-distortion output amplitude code for the Q component, the first gain pre-compensation information being different from the second gain pre-compensation information. The DPA is configured to generate an RF output based on the pre-distortion output amplitude codes of the I and Q components.

[0024] In some aspects, the wireless device further comprises one or more of a phase modulation (PM)-amplitude modulation (AM) compensation module coupled to the one or more digital filters and PA gain error compensation module, where the PM-AM compensation module is configured to correct PM-AM distortion of the baseband samples based on phase components of the baseband samples, and an AM-PM compensation module coupled to the one or more digital filters and PA gain error compensation module, where the AM-PM compensation module is configured to correct AM-PM distortion of the baseband samples based on phase errors derived from I and Q components of the baseband samples.

[0025] In some aspects, the wireless device further comprises a Cartesian-to-polar converter coupled to the one or more digital filters and configured to convert I and Q components of the baseband samples into amplitude and phase components. The PM-AM compensation module is configured to determine a selected section from a plurality of sections included in the DPA based on the phase component of the baseband samples (the selected section is associated with a slope and intercept corresponding to the selected section), and is further configured to derive an amplitude correction value for the baseband samples based on the slope and intercept of the selected section, and is configured to calculate a pre-distortion amplitude of the baseband samples from the amplitude component and the amplitude correction value. The PA gain error compensation module is configured to receive the I and Q components of the baseband samples derived using the pre-distortion amplitude calculated by the PM-AM compensation module.

[0026] Other objects and advantages associated with the embodiments disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. [Brief explanation of the drawings]

[0027] Exemplary aspects of the present application are described in detail below with reference to the following drawings:

[0028] [Figure 1] FIG. 1 is a block diagram illustrating an exemplary wireless communication network.

[0029] [Figure 2] FIG. 2A is a block diagram of a wireless communication device that can implement a station (STA) or an access point (AP) according to some embodiments.

[0030] FIG. 2B is a schematic block diagram of a receiver data flow architecture of the wireless communication device of FIG. 2A in accordance with some embodiments.

[0031] FIG. 2C is a schematic block diagram of a transmitter data flow architecture that can be used to transmit radio frequency (RF) signals over a wireless medium, according to some embodiments.

[0032] [Figure 3] FIG. 3 illustrates an example of a digital power amplifier (DPA) having a switched capacitor power amplifier (ScPa) including a first section corresponding to an in-phase (I) signal component and a second section corresponding to a quadrature-phase (Q) signal component, according to some embodiments.

[0033] [Figure 4] FIG. 4 is a graph illustrating an example of a gain transfer characteristic of a DPA for I and Q components of a DPA radio frequency (RF) output, according to some embodiments.

[0034] [Figure 5] FIG. 5 is a graph illustrating an example of a predistortion transfer characteristic of a predistortion module that can be used to provide precompensation for the I and Q signal components of a DPA, according to some embodiments.

[0035] [Figure 6] FIG. 6 illustrates an example direct RF transmitter architecture including a predistortion module for PA gain error compensation, according to some embodiments.

[0036] [Figure 7] FIG. 7A illustrates an example of a DPA predistortion module configured using a fixed-point implementation with a corresponding parameter set, according to some embodiments.

[0037] FIG. 7B illustrates an example architecture of the DPA predistortion module of FIG. 7A, according to some embodiments.

[0038] FIG. 7C illustrates a predistortion module according to some embodiments, comprising a first DPA predistortion block for predistorting the I signal component arm and a second DPA predistortion block for predistorting the Q signal component arm before providing an amplitude code to the DPA.

[0039] [Figure 8] FIG. 8 is a graph illustrating an example of a generalized gain characteristic of an eight-section DPA, according to some embodiments.

[0040] [Figure 9] FIG. 9 is a graph illustrating an example of corresponding gain precompensation characteristics (eg, predistortion characteristics) of the exemplary 8-section DPA of FIG. 8, according to some embodiments.

[0041] [Figure 10] FIG. 10 is a graph illustrating an example of gain error compensation for an 8-section DPA configured to apply predistortion techniques to generate a precompensated digital output according to the respective gains of each section of the 8-section DPA, in accordance with some embodiments.

[0042] [Figure 11] FIG. 11 illustrates an example of a fixed-point implementation of a DPA predistortion module for compensating for gain error in a multi-section DPA, according to some embodiments.

[0043] [Figure 12] FIG. 12 illustrates an example architecture of the DPA predistortion module of FIG. 11, according to some embodiments.

[0044] [Figure 13] FIG. 13A is a graph illustrating an example of phase modulation-amplitude modulation (PM-AM) distortion, according to some embodiments.

[0045] FIG. 13B illustrates an example of a fixed-point implementation of a phase modulation-amplitude modulation (PM-AM) compensation module, according to some embodiments.

[0046] [Figure 14] FIG. 14 is a diagram illustrating an example of true phase error corresponding to precompensated samples output on the I and Q paths, according to some embodiments.

[0047] [Figure 15] FIG. 15 illustrates an example of an AM-PM compensation module including a first phase error calculation block for determining a phase error of an I component and a second phase error calculation block for determining a phase error of a Q component, in accordance with some embodiments.

[0048] [Figure 16] FIG. 16 illustrates an example architecture for the phase error calculation block(s) of FIG. 15, according to some embodiments.

[0049] [Figure 17] FIG. 17 is a flow diagram of an exemplary process for performing signal compensation to digitally correct the gain characteristic of a digital power amplifier (DPA) according to some embodiments.

[0050] [Figure 18] FIG. 18 is a block diagram illustrating an example of a computing system for implementing certain aspects described herein, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0051] Certain aspects of the present disclosure are described below. Some of these aspects can be applied independently, and some of these can be applied in combination, as will be apparent to those skilled in the art. In the following description, for purposes of explanation, specific details are set forth to provide a thorough understanding of the aspects of the present application. However, it will be apparent that various aspects can be practiced without these specific details. The figures and description are not intended to be limiting.

[0052] The following description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of exemplary embodiments provides one skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the present application, as defined by the appended claims. overview

[0053] Aspects of the present invention can be used to provide novel and effective methods of power amplifier gain error compensation. For example, the systems and techniques described herein can be used to implement signal compensation that digitally corrects the gain characteristics of a digital power amplifier (DPA) (e.g., a DPA in a wireless device that transmits radio frequency (RF) signals over a wireless medium (WM)). In some embodiments, the DPA can include or implement one or more predistortion modules that are used to apply configured distortion to an input signal or input signal component provided to each predistortion module of the DPA.

[0054] For example, the DPA predistortion module(s) can be configured to digitally predistort baseband samples to generate predistorted samples, thereby canceling the nonlinear gain effect of the DPA. Canceling the nonlinear gain effect of the DPA can result in an ideal or near-ideal output of the DPA. In some embodiments, the DPA predistortion module can digitally predistort the baseband samples according to the nonlinear gain effect of the DPA. The resulting predistorted samples are then processed by the DPA, which applies a known nonlinear gain effect to the predistorted samples. Applying the known DPA nonlinear gain effect to the predistorted samples cancels the nonlinear gain effect, thereby resulting in an ideal or near-ideal DPA output.

[0055] Another aspect of the present invention corresponds to systems and techniques for digitally compensating for phase modulation (PM)-amplitude modulation (AM) distortion (e.g., PM-AM distortion) that may be introduced due to the architecture of a DPA. For example, amplitude components of baseband samples may be predistorted by a PM-AM compensation module. The predistortion is configured according to and / or based on corresponding phase components of the baseband samples. The predistortion of the PM-AM compensation module may be applied to the baseband samples before input to the DPA to reduce amplitude variations due to the phase of the baseband samples. Embodiment

[0056] FIG. 1 is a block diagram illustrating an exemplary wireless communication network 100. In some aspects, the wireless communication network 100 may be an example of a wireless local area network (WLAN). As used herein, a WLAN may be a Wi-Fi network. In some examples, the WLAN 100 may be a network implementing at least one of the IEEE 802.11 family of wireless communication protocol standards (e.g., those defined by the IEEE 802.11-2020 specification or an amendment thereto, including, but not limited to, 802.11ah, 802.11ay, 802.11ax, 802.11az, 802.11ba, and 802.11be). The WLAN 100 may include at least one AP 102 and multiple associated STAs 104. For example, the STAs 104 may include a first STA 104a, a second STA 104b, a third STA 104c, a fourth STA 104d, etc. Although only one AP 102 is shown, the WLAN network 100 may include multiple APs 102 .

[0057] Each STA 104a-104d may be referred to as a mobile station (MS), a mobile device, a mobile handset, a wireless handset, an access terminal (AT), a user equipment (UE), a subscriber station (SS), and / or a subscriber unit, among other examples. The STAs 104 may represent a variety of devices, such as a mobile phone, a handheld device, a netbook, a computer, a tablet computer, a laptop, a display device (e.g., a television, a computer monitor, a navigation system, etc.), a music or other audio or stereo device, a remote control device ("remote"), a printer, a kitchen appliance or other home appliance, a key fob (e.g., for a passive keyless entry and start (PKES) system), etc.

[0058] One AP 102 and the set of associated STAs 104a-104d may be referred to as a basic service set (BSS), which is managed by each AP 102. Figure 1 also shows an example coverage area 106 of an AP 102, which may represent the basic service area (BSA) of the WLAN 100. The BSS may be identified to users by a service set identifier (SSID) and to other devices by a basic service set identifier (BSSID), which may be the medium access control (MAC) address of the AP 102.

[0059] The AP 102 periodically broadcasts a beacon frame (“beacon”) that includes the BSSID to allow any STAs (e.g., one or more, or all, of the STAs 104a-104d) within radio range of the AP 102 to associate or re-associate with the AP 102 and establish respective communication links 108a-108d (e.g., hereinafter also referred to as “Wi-Fi® links”). For example, the first STA 104a can establish a respective communication link 108a with the AP 102, the second STA 104b can establish a respective communication link 108b with the AP 102, the third STA 104c can establish a respective communication link 108c with the AP 102, the fourth STA 104d can establish a respective communication link 108d with the AP 102, etc. The STAs 104a-104d may further use beacon frames broadcast by the AP 102 to maintain their respective communication links 108a-108d with the AP 102. For example, the beacon may include an identification of a primary channel used by each AP 102 and a timing synchronization function for establishing or maintaining timing synchronization with the AP 102. The AP 102 may provide various STAs within the WLAN with access to external networks via their respective communication links 108.

[0060] To establish a communication link 108a-108d with the AP 102, each STA 104a-104d may perform passive or active scanning operations ("scans") on frequency channels of one or more frequency bands. For example, to perform passive scanning, each STA 104a-104d listens for beacons transmitted by the AP 102 at periodic time intervals called target beacon transmit times (TBTTs). The TBTTs may be measured in time units (TUs). In some examples, one TU may equal 1024 microseconds (μs). In some examples, the TBTT may have a default value of 102.4 milliseconds (ms). To perform active scanning, each STA 104a-104d may generate and transmit probe requests sequentially on each scanned channel and listen for probe responses from the AP 102. Each STA 104a-104d may be configured to identify or select an AP 102 to associate with (e.g., based on scan information obtained by passive or active scanning) and perform authentication and association operations to establish a respective communication link 108a-108d with the selected AP 102. At the culmination of the association operation, the AP 102 assigns each STA 104a-104d an association identifier (AID), which the AP 102 uses to track the STA 104a-104d.

[0061] In some cases, one or more of the STAs 104a-104d may have the opportunity to select one of multiple BSSs within range of the STA or among multiple APs 102 that together form an extended service set (ESS) that includes multiple connected BSSs. Extended network stations associated with the WLAN 100 may be connected to a wired or wireless distribution system that may allow multiple APs 102 to be connected to an ESS. In some examples, one or more of the STAs 104a-104d may be covered by more than one AP 102 and may associate with different APs 102 at different times for transmission. After associating with an AP 102, one or more of the STAs 104a-104d may also be configured to periodically scan its surroundings to find a more suitable AP with which to associate. For example, a given one of the STAs 104a-104d that is far from its associated AP 102 may perform a “roaming” scan to find another AP with more desirable network characteristics (e.g., a greater received signal strength indicator (RSSI), reduced traffic load, etc.).

[0062] In some cases, the STAs 104a-104d may form a network without any other devices other than the AP 102 or the STAs 104a-104d themselves. One example of such a network is an ad hoc network. Examples of ad hoc networks include mesh networks and peer-to-peer (P2P) networks. In some cases, an ad hoc network may be implemented within a larger wireless network. In such an implementation, the STAs 104a-104d may communicate with each other through the AP 102 using their respective communication links 108a-108d, but the STAs 104a-104d may also communicate directly with each other using a direct wireless link 110. In some examples, two STAs may communicate via the direct communication link 110 regardless of whether both STAs 104 are associated with and served by the same AP 102. In such an ad hoc system, one or more of the STAs 104a-104d may assume the role played by the AP 102 in a BSS. Such a STA may be referred to as a group owner (GO) and may coordinate transmissions within the ad hoc network. Examples of direct wireless links 110 may include one or more of a Wi-Fi Direct® connection, a connection established by using a Wi-Fi Tunneled Direct Link Setup (TDLS) link, other P2P group connections, and the like.

[0063] The AP 102 and the STAs 104a-104d can function and communicate using their respective communication links 108a-108d according to at least one of the IEEE 802.11 wireless communication protocol standards. These standards define WLAN radio protocols and baseband protocols for the physical (PHY) layer and medium access control (MAC) layer. For example, the AP 102 and the STAs 104a-104d transmit and receive wireless communications with each other in the form of PHY Protocol Data Units (PPDUs) or Physical Layer Convergence Protocol (PLCP) PDUs. The AP 102 and the STAs 104a-104d in the WLAN 100 can transmit PPDUs over licensed or unlicensed spectrum. This spectrum can be a portion of the spectrum that includes frequency bands traditionally used by Wi-Fi technology, such as the 2.4 GHz, 5 GHz, 60 GHz, 3.6 GHz, and sub-1 GHz bands. Some implementations of the AP 102 and STAs 104a-104d described herein can also communicate over other frequency bands, such as the 6 GHz band, which can support both licensed and unlicensed communications. The AP 102 and STAs 104a-104d can also be configured to communicate over other frequency bands, such as shared licensed frequency bands, where multiple operators may have licenses to operate in the same or overlapping frequency bands.

[0064] Each frequency band can include multiple subbands or frequency channels. For example, PPDUs compliant with the IEEE 802.11 standard and specifications may be transmitted in a frequency band divided into multiple 20 MHz channels. In such an example, the PPDUs are transmitted in physical channels with a minimum bandwidth of 20 MHz, although other channel bandwidths are possible. In some cases, channel bonding can be used to combine multiple channels of each minimum bandwidth to form a channel with a larger bandwidth.

[0065] Each PPDU is a composite structure that includes a PHY preamble and a payload in the form of a PHY service data unit (PSDU). Information provided in the preamble can be used by a receiving device to decode the subsequent data in the PSDU. When a PPDU is transmitted over a bonded channel, the preamble field is duplicated and transmitted over each of multiple component channels. The PHY preamble can include both a legacy portion (or "legacy preamble") and a non-legacy portion (or "non-legacy preamble"). The legacy preamble can be used for packet detection, automatic gain control, and channel estimation, among other uses. The legacy preamble is also generally used to maintain compatibility with legacy devices. The format, coding, and information provided in the non-legacy portion of the preamble are based on the specific IEEE 802.11 protocol used to transmit the payload.

[0066] 2A is a high-level block diagram of an exemplary wireless communication device 200 that may be used to implement a STA or an AP in some examples. The wireless communication device 200 may include a MAC layer and a PHY layer according to one or more of the IEEE 802.11 standards.

[0067] The wireless communication device 200 includes a radio frequency (RF) transmitter module 202, an RF receiver module 204, an antenna unit 206, one or more memory banks 208, an input / output interface 210, and a communication bus 212. The RF transmit module 202 and the RF receive module 204 include modems (modulator-demodulator devices), which transmit data by modulating one or more carrier signals to encode digital information and receive data by demodulating the signals to recover the original digital information. As shown, the wireless communication device 200 also includes a MAC processor 214, a PHY processor 216, and a HOST processor 218. These processors may be any type of integrated circuit (IC), including a general-purpose processing unit, an application-specific integrated circuit (ASIC), or a RISC-V (Reduced Instruction Set Computer - Five)-based IC, among others.

[0068] The memory 208 may be used to store software and / or computer-readable instructions, including software or instructions that may be used to implement at least some of the functionality of the MAC layer. For example, each processor included in the wireless communication device 200 (e.g., the MAC processor 214, the PHY processor 216, the HOST processor 218, etc.) executes respective software to implement the functionality of its respective communication / application layer.

[0069] The PHY processor 216 includes a transmit signal processing unit and a receive signal processing unit (not shown) and may be used to manage the interface with the wireless medium (WM). The PHY processor 216 operates on the PPDU by exchanging digital samples with a radio module that includes the RF transmitter 202, the RF receiver 204, an analog-to-digital converter, and a digital filter.

[0070] The MAC processor 214 executes MAC-level instructions and manages the interface between the application software and the WM through the PHY processor 216. The MAC processor 214 is responsible for coordinating access to the WM so that the access point (AP) and in-range STAs can communicate effectively. The MAC processor 214 appends header and tail bytes to data units provided by higher levels and sends them to the PHY layer for transmission. The reverse occurs when receiving data from the PHY layer. If a frame is received in error, the MAC processor 214 manages the retransmission of the frame.

[0071] The HOST processor 218 is responsible for interfacing with the MAC layer and performing the higher level functions of the wireless communication device.

[0072] The PHY processor 216, MAC processor 214, HOST processor 218, peripheral bus 220, memory 208, and input / output interface 210 communicate with each other via peripheral bus 212. The peripheral bus 220 connects to a number of peripherals that support core functionality of the wireless communication device 200, including timers, interrupts, radio / filter / system registers, counters, UARTs, GPIO interfaces, and the like. The memory 208 may also store an operating system and applications. In some examples, the memory may store recorded information about captured frames and packets. The input / output interface unit 210 enables information exchange with a user of the wireless communication device. The antenna unit 206 may include one antenna and / or multiple antennas. For example, multiple antennas may be used to implement techniques such as multiple input multiple output (MIMO).

[0073] FIG. 2B illustrates a schematic block diagram of a receiver data flow architecture 250 that may be used to receive Wi-Fi® packets over a network. In one exemplary embodiment, the receiver data flow architecture 250 illustrated in FIG. 2B may correspond to or otherwise be associated with the wireless communication device 200 illustrated in FIG. 2A. A wireless signal is received via a WM and converted to an electrical signal by a receive antenna 252 (e.g., which may be the same as or similar to the antenna 206). The received signal is conditioned using a series of analog filters 254 (e.g., depicted as analog RF receive (Rx) filters) before being converted to a digital equivalent using an analog-to-digital converter (ADC) 256. The sampled signal output of the ADC 256 is again conditioned using a filter bank 258 before the samples are collected in an asynchronous receive first-in-first-out (FIFO) data structure 260. The filter bank 258 may include one or more digital RF filters and / or filters.

[0074] The samples in the FIFO structure 260 are accessed by multiple modules. For example, the samples may be accessed by a packet detection module and a sub-band module, both of which may be included in the lower-level PHY portion 262 depicted in FIG. 2B. In some embodiments, the lower-level PHY portion 262 is itself included in the PHY processor 216 shown in FIG. 2A.

[0075] The packet detection module included in the lower-level PHY unit 262 may include hardware and / or implemented algorithms that can be used to analyze the initial section of the PPDU in the time domain. Based on the analysis, the packet detection module can be used to recognize the received frame and synchronize the frequency and timing of the wireless communication device with the received packet. The subband module included in the lower-level PHY unit 262 may include hardware and / or implemented algorithms that can be used to detect which subchannel of the assigned frequency band is being used for the received packet.

[0076] Once a packet is detected and the associated subchannel is established, the samples are forwarded to an upper-level PHY unit 264. The upper-level PHY unit 264 is included in the PHY processor 216 shown in FIG. 2A. In some aspects, the upper-level PHY unit 264 can be used to process and decode orthogonal division multiplexing (OFDM) symbols (e.g., with the support of a co-processor module) to reconstruct the complete PPDU. The reconstructed PPDU is output by the upper-level PHY unit 264 and subsequently processed by a MAC layer processor 266. The MAC layer processor 266 can be used to extract the data payload from the PPDU and provide relevant information to the HOST layer 268 for consumption.

[0077] In some examples, the MAC layer processor 266 illustrated in Figure 2B may be the same as or similar to the MAC processor 214 illustrated in Figure 2A. In some embodiments, the HOST layer 268 illustrated in Figure 2B may be the same as or similar to the HOST processor 218 illustrated in Figure 2A.

[0078] FIG. 2C is a schematic block diagram of a transmitter data flow architecture 280 that can be used to transmit RF signals over a wireless medium, according to some embodiments. More specifically, FIG. 2C shows a simplified schematic block diagram of the transmitter data flow architecture 280 used to transmit wireless signals over a WM. Data may originate from a HOST or APP module 282 and be packaged into a MAC-level protocol data unit (MPDU) for routing over the wireless network by a MAC management module 284. A PHY module 286 interfaces with the WM and adds a PHY preamble and tail to the MPDU to compile a PPDU. Typically, a modulation coding scheme (MCS) for transmission of packets over the medium is established using a rate control algorithm by the MAC module 284 or PHY module 286. The selected modulation scheme can define the modulation technique and coding rate used to transmit data over the WM. Based on the selected modulation scheme, e.g., quadrature amplitude modulation (QAM) 64, the PPDU is modulated for transmission over the WM. The encoder module 288 generates signals corresponding to points of a QAM constellation symbol (a group of bits of a PPDU) that can be coded using polar coordinates (r-θ) or Cartesian coordinates (QI). The modulation is performed by linking the encoder module 288 to a digital phase-locked loop (DPLL) 290. The modulated signal is filtered by an analog filter 292 and transmitted using a transmit antenna 294.

[0079] As mentioned above, the systems and techniques described herein can be used to provide power amplifier gain error compensation. For example, they can be used to perform signal compensation to digitally correct the gain characteristic of a digital power amplifier (DPA). In some aspects, the DPA can be included within and / or implemented by a wireless device that transmits radio frequency (RF) signals, such as over a wireless medium (WM). In some aspects, the DPA can be a switched capacitor power amplifier (ScPa). As described in further detail below with respect to FIGS. 3-18 , in some aspects, to implement power amplifier gain error compensation and / or perform signal compensation to digitally correct the DPA gain characteristic, the DPA can include or implement one or more predistortion modules that are used to apply configured distortion to input signals or input signal components provided to each predistortion module of the DPA.

[0080] As mentioned above, DPAs can employ various techniques to optimize efficiency and / or power consumption, but such optimizations also introduce distortions into existing DPA implementations, particularly when the input amplitude code driving the DAC (e.g., a DAC included or integrated within the DPA) is large. For example, one technique that may be used to optimize DPA efficiency is based on driving only one section of the DPA for low-amplitude signals and driving two sections (e.g., summing their outputs) for high-amplitude signals. One embodiment of a DPA is a switched-capacitor power amplifier (ScPa) consisting of N sections, where N is a positive integer. FIG. 3 illustrates an example ScPa architecture 300 for an N=2-section digital power amplifier. For example, the ScPa 300 includes a first section 310 corresponding to the in-phase (I) signal component and a second section 330 corresponding to the quadrature-phase (Q) signal component. In the example of FIG. 3 (and other embodiments of DPAs that implement this technique), both the I and Q components are represented by 15-bit amplitude codes. For example, in a 16-bit digital-to-analog converter (DAC), 1 bit is used to represent the sign of the sample and 15 bits are used to represent the amplitude of the sample.

[0081] In FIG. 3, the first section 310 of the DPA (e.g., ScPa 300) is configured to convert the amplitude code of the I component from 0 to (2 14 -1), and the amplitude code of the Q component is 2 14 From (2 15 The second section 330 has an element controlled by the amplitude code of the Q component when the amplitude code of the Q component is between 0 and (2 14 -1), and the amplitude code of the I component is controlled by the amplitude code of the Q component when the amplitude code is between 2 14 From (2 15The DPA amplifier has an amplitude code controlled by the amplitude code of the I component when the amplitude code is between δ(1) and δ(1). Correct operation assumes that the gain from both DPA sections 310 and 330 to the combined output 340 is the same. However, in practice, slight differences in gain between the first section 310 and the second section 330 occur, which introduces undesirable distortion into the DPA combined output 340. For example, the gain from the first section 310 to the output 340 may be G(1+δ), while the gain from the second section 330 to the output 340 may be G(1−δ). In another example, the gain from the first section 310 to the output 340 may be G(1+δ1), and the gain from the second section 330 to the output 340 may be G(1−δ2).

[0082] 4 is a graph illustrating an example gain transfer characteristic 400 of a DPA (such as, for example, DPA 300 of FIG. 3) with respect to I component(s) 410 and Q component 430. In the example of FIG. 4, the horizontal axis represents amplitude code and the vertical axis represents the corresponding RF power level. In an ideal case (e.g., between I component 410 and Q component 430 of example DPA gain transfer characteristic graph 400), amplitude code 2 14 corresponds to an RF power level of 0.5. However, amplitude code 2 14 The actual RF output of the amplifier is offset or displaced by δ / 2 from the ideal output for both the I component 410 (e.g., +δ / 2 away from the ideal RF output level of 0.5) and the Q component 430 (e.g., −δ / 2 away from the ideal RF output level of 0.5). In the example gain transfer characteristic graph 400, the maximum gain characteristic deviation is at amplitude code 2. 14 The total deviation is δ. Note that the vertical scale in FIG. 4 is exaggerated to show the distortion to the DPA output, but in reality, the difference between the two gain paths 410, 430 is a fraction of a decibel (dB).

[0083] In some aspects, a DPA gain transfer characteristic (such as, for example, DPA gain transfer characteristic 400 of FIG. 4) can be mathematically formulated using the following equation:

number

[0084] In the example of equations (1) to (4), the terms xI and xQ represent the input amplitude codes corresponding to the in-phase and quadrature arms, respectively. The terms gI and gQ represent the slope of the initial part of the DPA gain transfer function, which also corresponds to the in-phase and quadrature arms, respectively. The terms gI = 1 + δ and gQ = 1 - δ.

[0085] Some embodiments of the disclosed gain error correction method for correcting the gain characteristic of a DPA can be implemented in the digital domain. For example, a predistortion module can be implemented in the digital baseband of a wireless communication device to generate predistorted baseband samples for input to the DPA (e.g., the predistortion is configured or applied to cancel the nonlinear gain effect applied by the DPA processing) so that the processed or final output of the DPA is output without distortion.

[0086] In some aspects, the gain characteristics of a DPA for both the I and Q components can be modeled as piecewise linear. Therefore, the predistortion characteristics of a predistortion module are also piecewise linear in nature, as shown in FIG. 5 . In particular, FIG. 5 is a graph illustrating an example of a predistortion transfer characteristic 500 of one embodiment of a predistortion module for precompensating the I and Q components. The predistortion transfer characteristic graph 500 can also be referred to as a DPA gain-predistortion transfer characteristic graph. Graph 500 includes a representation 520 of an ideal (e.g., zero distortion) case, a representation 510 of the precompensation characteristic of the I component, and a representation 530 of the precompensation characteristic of the Q component. The horizontal axis of graph 500 in FIG. 5 corresponds to the input amplitude code of the I or Q component (which may be, for example, a 15-bit input amplitude code). The vertical axis of graph 500 corresponds to the output amplitude code after the input amplitude code has been processed by the predistortion module.

[0087] In some embodiments, the disclosed power amplifier gain error compensation can be implemented using a predistortion module to predistort (e.g., also referred to as precompensation) the input to the DPA, thereby canceling the predistortion and the DPA nonlinear gain effects of subsequent DPA processing. In some aspects, in a transmitter, the predistortion module can be located proximate, near, adjacent, etc. to a digital-to-analog converter (DAC) included within or otherwise associated with the DPA. For example, the predistortion module can be located upstream of the DAC, with closer location of the predistortion module relative to the DAC improving gain error compensation performance.

[0088] 6 illustrates an example of a direct RF transmitter architecture 600 including a predistortion module 640 (e.g., interchangeably referred to herein as a PA gain error compensation module) for PA gain error compensation in a direct RF transmitter architecture. For example, the direct RF transmitter 600 can receive a baseband output 602, which is a baseband frequency f bb is associated with.

[0089] Between the input (e.g., baseband 602) and output (e.g., output to RF-DAC 670) of direct RF transmitter architecture 600, baseband 602 may be processed by one or more finite impulse response (FIR) filters 606, followed by multiple cascaded integrator comb (CIC) filters 656. This provides baseband upsampling, converting baseband output 602 to a baseband frequency (e.g., f bb ) to radio frequencies (e.g., f RF )

[0090] The output of the FIR filter bank 606 may be passed to a TX-IQ and TX-LO compensation module 622. The TX-IQ and TX-LO compensation module 622 may be configured to perform compensation for in-phase and quadrature (e.g., IQ) imbalances, local oscillator (LO) imperfections, etc., to correct for phase and / or amplitude mismatches that may exist between the I and Q components of the input signal(s) to the TX-IQ and TX-LO compensation module 622.

[0091] Downstream of the TX-IQ and TX-LO compensation module 622, a first-in first-out (FIFO) memory block 625 can be associated with the Tx resampler block 624. The FIFO memory block 625 can be configured as a buffer and can be located between adjacent clock domains.

[0092] In some embodiments, the PA gain error compensation module 640 may be located after the CIC filter block 632 and the IQ skew compensation module 634 (e.g., downstream in the signal processing pipeline or signal processing flow implemented by the direct RF transmitter architecture 600). In some examples, the CIC filter block 632 may be implemented as a CIC8 configured to upsample frequency by a factor of eight. The IQ skew compensation module 634 may be used to compensate for imbalances between the I and Q components of the signal(s) provided as inputs to the IQ skew compensation module 634. For example, the IQ skew compensation module 634 may be used to compensate for any skew or delay mismatch that may exist between the I and Q signal paths, thereby ensuring that the output from the IQ skew compensation module 634 aligns the timing of the I and Q components.

[0093] The PA gain error compensation module 640 may generate one or more I and Q amplitude codes as outputs. The I and Q amplitude codes output from the PA gain error compensation module 640 may be processed by a chain of CIC filters (e.g., a chain of CIC filters in multiple or series of CIC filters 656) for extra upsampling. In some aspects, one or more of the CIC filters, or each CIC filter, may be bypassed according to a configured mode.

[0094] The output from the chain of CIC filters 656 may be provided as an input to a thermal encoder 660, which in some embodiments may represent the final stage of the direct RF transmitter architecture 600, located before the DAC. For example, the output 670 of the thermal encoder 660 may be provided directly as an input to an RF-DAC. In some examples, the thermal encoder 660 may be configured to perform thermal encoding in which each I rail and Q rail is encoded into four signals: a sign (e.g., "sgn"), a row (e.g., "row"), a column (e.g., "col"), and a bin (e.g., "bin"). The thermal encoder 660 may be a digital thermal encoder. In some embodiments, the output of the digital thermal encoder (e.g., a frequency f RF The output power at 670 Hz is the radio frequency f RF The RF converter may be fed to a high speed RFDAC operating at

[0095] In some embodiments, the PA gain error compensation module 640 is a predistortion module with a piecewise linear transfer characteristic, which can be mathematically expressed as:

number

[0096] The terms xI and xQ represent input amplitude codes corresponding to the in-phase and quadrature arms, respectively, of the predistortion module 640. The terms zI and zQ represent output amplitude codes corresponding to the in-phase and quadrature arms, respectively, of the predistortion module 640.

[0097] 7A illustrates an example of a predistortion process 700a, which may be implemented by a predistortion module 725 configured using a fixed-point implementation with corresponding parameter sets A, B, C, etc. In some aspects, the predistortion module 725 may be the same as or similar to the predistortion module 640 of FIG. 6. In one illustrative example, the terms xI and xQ in equations (5)-(8) above may correspond to the I and Q components (respectively) of the input amplitude code 715 provided to the predistortion module 725. The terms zI and zQ in equations (5)-(8) may correspond to the I and Q components (respectively) of the output amplitude code 745 generated by the predistortion module 725.

[0098] In some embodiments, the digital predistortion module can be realized by a fixed-point implementation with six sets of parameters:

number

[0099] 7A and 7B correspond to an example in which the in-phase (I) arm and the quadrature-phase (Q) arm are provided by the same predistortion module sub-block(s). In another example, separate predistortion modules or predistortion sub-blocks may be provided for predistortion of the I and Q arms. For example, FIG. 7C illustrates a predistortion module 700c including a first DPA predistortion block 775 for predistorting the I signal component arm and a second DPA predistortion block 777 for predistorting the Q signal component arm before providing the respective I and Q amplitude codes to the DPA, according to some embodiments.

[0100] For example, the first predistortion block 775 (e.g., the first DPA predistortion processing module) may calculate a parameter A I , B I , and C I Implement predistortion processing for the I signal component arm based on using the respective sets of I and I amplitude codes I in 765, and outputs the predistortion I amplitude code I out 795. Similarly, a second predistortion block 777 (e.g., a second DPA predistortion processing module, etc.) may be configured to generate a parameter A Q , B Q , and C Q and implements predistortion processing for the Q signal component arm based on using a respective set of Q amplitude codes Q in 767, thereby predistorting the Q amplitude code Q out 797 as an output.

[0101] In some examples, simulation results have demonstrated that the efficiency of a multi-section DPA architecture exceeds that of a conventional single-section architecture. However, gain errors between sections of a multi-section DPA architecture can severely limit the error vector magnitude (EVM). For example, a single-section DPA can limit the EVM to approximately 41 dB, while an eight-section DPA with gain errors results in a significantly worse EVM. In some aspects, this limitation on gain error and / or EVM performance associated with a multi-section DPA or DPA architecture can be overcome by precompensating for the gain error in the digital domain according to embodiments of the present invention.

[0102] The gain error characteristic of an N-section DPA architecture can be modeled by an N linear-section piecewise function, where N is typically a power of 2. The range of the input code is divided into N intervals, and each interval is assigned to one section of the DPA.

[0103] For example, if the input code range is [0 2 15 -1], each port has 2 15 In one embodiment of an 8-section DPA, each section is assigned 4096 codes, with section 1 being assigned [0 4095], section 2 being [4096 8191], section 3 being [8192 12287], section 4 being [12288 16383], section 5 being [16384 20479], section 6 being [20480 24575], section 7 being [24576 28671], and section 8 being [28672 32757].

[0104] 8 is a graph illustrating an example of a generalized gain characteristic 800 for an eight-section DPA, according to some embodiments. It can be seen that the gain characteristic 800 is piecewise linear with eight linear sections, each with a different slope. The i-th section has a gain or slope g i and

number

number

number

[0105] where the term yi (e.g., i = 1, 2, ..., 8; corresponding to equations (9) to (16)) represents the output magnitude code corresponding to the ith section, and x represents the input magnitude code. The above equation can be simplified as follows:

number

[0106] It should be noted that while this gain characteristic equation given in equations (17) and (18) corresponds to the example generalized gain characteristic 800 shown in FIG. 8 for an 8-section DPA, the above gain characteristic equation can be easily extended to N-section distortion characteristics for different, larger, smaller, etc. values ​​of N other than 8.

[0107] In some examples, digital predistortion techniques are implemented in the digital baseband according to an embodiment of the present invention to correct for anomalous gain characteristics of the N-section architecture in the DPA. As mentioned above, the predistortion module(s) may be configured and used to distort the baseband samples such that the final output of the DPA is output undistorted (e.g., predistortion applied to the baseband samples prior to DPA processing cancels anomalous or inherent nonlinear gain effects applied by the DPA processing).

[0108] In some aspects, the predistortion module may be designed to distort the baseband samples according to a corresponding predistortion characteristic or predistortion characteristic information. For example, the predistortion characteristic may be obtained by plotting the horizontal axis (x-axis) of the gain characteristic against the vertical axis (y-axis). Because the gain characteristic of each section is linear (e.g., the eight piecewise linear sections of the example gain characteristic 800 of FIG. 8), each section of the corresponding predistortion characteristic is also effectively linear, as shown in the example of FIG. 9 for an eight-section DPA configuration. In particular, FIG. 9 is a graph illustrating an example of a corresponding gain predistortion characteristic 900 (e.g., a predistortion characteristic) of the example eight-section DPA gain characteristic 800 of FIG. 8, according to some examples.

[0109] The gain pre-distortion characteristic (e.g., gain pre-distortion characteristic 900) of each piecewise linear section (e.g., gain characteristic 800) is expressed as z i =m i x+c i It can be expressed mathematically as m i and c i where x is the slope and intercept of the i-th section, respectively, and x is the input magnitude code. The pre-correction characteristics when 8 linear segments are selected can be summarized as follows:

number

[0110] For equations (19)-(21), the slope and intercept are given by:

number

number

[0111] The above equation can be generalized to N segments as explained below. For example, if we define r=32768 / N, the generalized N-segment precorrection property is:

number

[0112] For equations (22)-(24), the slope and intercept are given by:

number

number

[0113] Gain {g i With knowledge of {}, the slope and intercept of each section in a piecewise-linear predistortion characteristic (e.g., gain predistortion characteristic 900) can be calculated according to the above operations. The above equations can also be generalized to various other DPA designs, implementations, configurations, architectures, etc., that have arbitrarily complex gain characteristics as a result of efficiency-enhancing techniques.

[0114] FIG. 10 is a graph illustrating an example of gain error compensation 1000, corresponding to one embodiment of compensating for gain errors in an exemplary eight-section DPA (e.g., an eight-section DPA) using the disclosed predistortion techniques. In particular, by applying the disclosed predistortion techniques to generate precompensated outputs 1030 for each individual section of the DPA, the precompensated digital outputs 1030 are generated according to the gains of each section. The precompensated digital outputs 1030 are then processed by the same sections of the DPA from which the predistortion information was previously derived and used to generate the precompensated digital outputs 1030. The compensated DPA output 1050 is obtained by passing the precompensated digital outputs 1030 through a gain error model of the eight-section DPA. As illustrated in the example graph of gain error compensation 1000 in FIG. 10 , by accurately estimating the gain of each section of the multi-section DPA, the present system and techniques are able to fully compensate for gain errors at the output of the DPA, thereby achieving ideal characteristics for the DPA output 1050.

[0115] 11 is a top-level block diagram illustrating one embodiment of a fixed-point implementation 1100 of a DPA predistortion module 1125 that can be used to compensate for gain error in a multi-section DPA, according to some examples. In some embodiments, the DPA predistortion module 1125 can receive an input amplitude code 1115 and generate a predistortion output amplitude code 1145 for gain error compensation in a DPA that receives a predistortion amplitude code 1145 as an input. For an eight-section DPA, the DPA predistortion module 1125 can be parameterized by a total of 23 parameters to achieve predistortion.

[0116] For example, the DPA pre-correction module 1125 may utilize seven parameters (e.g., I1, I2, ..., I7) indicating the end interval of the segmented section, eight parameters (e.g., m1, m2, ..., m8) indicating the respective slopes for each of the eight segmented sections, and eight parameters (e.g., c1, c2, ..., c8) indicating the respective intercepts for each of the eight segmented sections.

[0117] The values ​​{I1,I2,...,I7} represent the end intervals of the first, second, ..., and seventh segment sections, respectively. In general, the end interval I i is given by:

number

[0118] Value {m i ,c i},i=1,2,...,8 represent the slopes and intercepts (respectively) of the eight segmental sections, e.g., {m1,c1} represent the slope and intercept of the first segmental section, {m2,c2} represent the slope and intercept of the second segmental section, etc. In general, the slope and intercept parameters of each segmental section of the DPA are given by:

number

[0119] 12 is a diagram illustrating an example architecture 1200 of the DPA pre-distortion module 1125 of FIG. 11, in accordance with some examples. In some embodiments, the example architecture 1200 of FIG. 12 may represent the internal architecture of the pre-distortion module 1125 of FIG. 11.

[0120] For example, input code 1215 in Figure 12 can be the same as or similar to input code 1115 in Figure 11. Output code 1245 in Figure 12 can be a predistortion output amplitude code that is the same as or similar to predistortion output code 1145 in Figure 11. In one illustrative example, architecture 1200 of DPA precorrection module 1125 can include range selection block 1262. This range selection block 1262 can be configured to implement range selection algorithm 1264 (e.g., range selection logic) shown in Figure 12.

[0121] For example, the range selection block 1262 and / or range selection algorithm 1264 may be used by the predistortion module 1225, 1125 to select the configured parameter values ​​{m i ,c i You can choose which set of} to use.

[0122] In some embodiments, range selection block 1262 and / or range selection algorithm 1264 may be configured to compare the value of input code 1215 (e.g., input value x) with partition section range information indicated by seven parameter values ​​{I1, I2, ..., I7} corresponding to the end intervals of the first through seventh partition sections. Based on comparing the value of input code 1215 (e.g., x) with the partition section end intervals (e.g., {I1, I2, ..., I7}), the corresponding partition section of the DPA is determined, and the parameter values ​​{m i ,ci} may be selected and used to configure the predistortion module 1225 for processing x of the input code 1215. For example, the range selection block 1262 and / or the range selection algorithm 1264 may be implemented based on the logic given below: if(x≦I1) m i =m1;c i =c1 elseif(I1 <x≦I2) m i =m2;c i =c2 elseif(I2 <x≦I3) m i =m3;c i =c3 elseif(I3 <x≦I4) m i =m4;c i =c4 elseif(I4 <x≦I5) m i =m5;c i =c5 elseif(I6 <x≦I7) m i =m7;c i =c7 else(x>I7) m i =m8;c i =c8

[0123] In one illustrative example, simulation results demonstrate significant improvements in both the spectral and EVM performance of DPA gain error compensation implemented using the disclosed predistortion techniques.

[0124] In some aspects, a fixed-point implementation of an N-section DPA configuration has N-1 termination values ​​(e.g., as in the example above where an 8-section DPA configuration is parameterized by seven different section termination values), where {I1, I2,..., I (N-1)} represents the end intervals of the first, second, ..., and last segment sections (respectively). If r=32768 / N, then the end interval I i is given by:

number

[0125] Value {m i ,c i},i=1,2,...,N represent the slopes and intercepts of the N discrete sections given by:

number

[0126] In addition to the gain distortion described above, a DPA can also introduce amplitude and / or phase distortion, as well as combinations thereof. For example, another non-ideal characteristic observed in Cartesian-mode DPAs is phase modulation (PM)-amplitude modulation (AM) distortion inherent to the DPA architecture. Here, PM-AM distortion (also referred to as phase-amplitude distortion) is amplitude variation induced as a function of the phase of the IQ baseband samples. A DPA can also introduce AM-PM distortion (also referred to as amplitude-phase distortion), which is phase variation induced as a function of the amplitude of the IQ baseband samples. In some aspects, PM-AM distortion and AM-PM distortion can be types of crosstalk distortion between the I and Q paths of a DPA or RF transmitter architecture.

[0127] Typically, the number of activated DAC cells is a function of the phase of the input baseband samples, resulting in different current distributions drawn from the power supply. In some cases, as the transmitter tone sweeps across the complex plane, the activation of the I and Q DAC units varies non-proportionally with the output amplitude. The higher the current drawn by the DAC units, the greater the voltage drop across the power supply. It has been observed that DAC unit activation is greatest at 45-degree offsets (e.g., 45, 135, 225, and 315 degrees). Therefore, the current drawn by the DAC units is greatest at the 45-degree offset where DAC unit activation is greatest. This causes the largest voltage drop across the power supply, if there is resistance in the power supply, which modulates the output. For example, FIG. 13A is a graph illustrating an example of phase-modulation-amplitude-modulation (PM-AM) distortion 1300, showing the amplitude of a complex sine wave varying as a function of the phase of the I and Q baseband samples.

[0128] Embodiments of the present invention can be used to digitally correct amplitude due to PM-AM distortion with respect to the phase of IQ samples (e.g., to digitally correct amplitude variations due to PM-AM distortion where amplitude is affected by changes in phase). In some embodiments, amplitude scaling as a function of phase is first measured or estimated and then used to implement amplitude correction corresponding to PM-AM distortion compensation. For example, to measure amplitude scaling as a function of phase, the phase axis from -180 degrees to 180 degrees can be divided into eight segments. Each segment spans 45 degrees. The negative value of the amplitude distortion (in dB) versus phase in each segment is fitted with a line, and the slope and intercept of this line are obtained. The slope and intercept of the linear fit of the amplitude distortion can then be used to provide the required amplitude correction (in dB) as a function of the phase of the IQ samples.

[0129] In some embodiments, PM-AM distortion compensation includes or is based on converting the IQ samples to this polar coordinate representation, for example, by generating amplitude and phase information using a coordinate rotation digital computer (CORDIC). The phase information of the IQ samples is used to select which of the eight segments the IQ sample belongs to. The corresponding slope and intercept determined for the particular segment containing the IQ sample are then obtained and used to calculate the corresponding amplitude correction (in dB). The calculated amplitude correction for the IQ sample is converted to a linear value and multiplied by the original amplitude of the IQ sample to thereby obtain the predistorted amplitude (e.g., amplitude predistortion is implemented based on multiplying the original amplitude of the IQ sample by a linear transformation of the calculated amplitude correction). Predistortion phase information (e.g., for AM-PM distortion compensation) can be calculated in the same or similar manner as the predistortion amplitude information for PM-AM distortion compensation described above. The predistortion amplitude and phase information can be used to obtain the resulting Cartesian IQ samples after PM-AM and / or AM-PM predistortion compensation has been applied.

[0130] In some embodiments, a programmable phase offset function can be implemented to account for any shifts in the PM-AM characteristics. Furthermore, to provide more flexibility, amplitude-based correction factors can be provided and used, where the amplitude scale is divided into multiple segments, each segment having a corresponding amplitude correction factor. Figure 13B illustrates an example fixed-point implementation of the PM-AM compensation module 1310, according to one embodiment of the present invention. Cartesian IQ samples (e.g., including I samples 1312 and Q samples 1314) are converted to amplitude and phase by the CORDIC 1315.

[0131] From the CORDIC 1315, an amplitude correction value is selected using an amplitude segment selection module 1332 based on the amplitude determined by the CORDIC 1315 for the IQ sample inputs 1312, 1314. In some embodiments, the amplitude segment selection module 1332 may be configured to select or determine the corresponding amplitude correction value based on an implementation of an amplitude segment search algorithm 1322 (e.g., amplitude segment search logic).

[0132] In some embodiments, the slope (m) and intercept (c) for the linear approximation are selected by the phase segment selection module 1334 according to the phase of the IQ samples 1312, 1314 as determined by the CORDIC 1315. In some examples, the slope (m) and intercept (c) may be determined by the phase segment selection module 1334 using a phase segment search algorithm 1326 (e.g., phase segment search logic) and then used to derive a corresponding amplitude correction. The amplitude correction is then mapped to a linear value by the dB-to-Linear module 1355. In some embodiments, a cosine / sine generation block 1354 may be used to derive a cosine / sine value from the normalized phase, and the output cosine / sine value from the cosine / sine generation block 1354 may be combined with the corrected amplitude information from the output of the dB-to-Linear module 1355, thereby generating the output I new 1372 and output Q new Generates 1374.

[0133] As mentioned above, in addition to PM-AM distortion, AM-PM (e.g., crosstalk) DPA distortion is also observed. This refers to amplitude variations that cause phase distortion at the output of the DPA. This phase distortion can be caused by different clock delays for different elements of the DPA, and / or complex impedance variations due to different numbers of DAC cells being activated, and / or various other mechanisms. In multi-section DPA architectures, the amplitude code is divided into multiple sections, and the AM-PM distortion characteristics tend to have a structure that replicates the characteristics of each individual section, as each section is assigned a code in sequence. AM-PM distortion alters the original IQ complex samples, causing the I path to be distorted by portions of the Q path, and vice versa.

[0134] The complex baseband sample at sample time k is given by I[k]+jQ[k], where I[k] and Q[k] represent the in-phase and quadrature-phase components. The complex baseband sample in polar coordinate form is given by:

number

[0135] In equation (27), the terms r[k] and θ[k] represent the amplitude and modulation phase of the baseband samples, respectively. Because the AM-PM effect distorts the phase, the phase component contains a phase error proportional to the amplitude component. The distorted IQ samples can be expressed as:

number

[0136] In equation (28), the term △θ[k] represents the phase distortion component, which is a function of the amplitude component:

number

[0137] I d [k]+jQ dExpanding [k] gives:

number

[0138] formula Q d Since [k]=Q[k]cosΔθ[k]-I[k]sinΔθ[k] assumes that the phase distortion components are small, in some cases the approximations cos(Δθ[k])≈1 and sin(Δθ[k]≈Δθ[k]) can be used to simplify the implementation of AM-PM distortion pre-compensation. For example, applying these approximations, the above equation simplifies to:

number

[0139] From the bench results, a more general model can be characterized, where the phase distortion components can be expressed independently as a function of the amplitude of the in-phase (I) and quadrature (Q) phase arms:

number

[0140] θ I [k]=f(|I[k]|), △θ Q Let [k] = f(|Q[k]|), then equations (33) and (34) can be written in matrix form:

number

[0141] In equation (35), the matrix D is called the distortion matrix.

[0142] In some embodiments for precompensating AM-PM distortion, the systems and techniques described herein may be configured to transform the original complex baseband samples using a precompensation matrix C, which may be derived from the distortion matrix D:

number

[0143] The predistortion matrix C is derived to reverse the effect of AM-PM distortion on the original complex baseband samples I[k]+jQ[k], e.g., C≈1. C [k]+jQ C [k] is given by:

number

[0144] That is, the in-phase (I c ) component and quadrature phase (Q c ) components are as follows:

number

[0145] Because phase distortion is a function of the amplitude of the in-phase or quadrature-phase samples, the I and Q amplitude axes can be divided into N segments and the phase distortion can be modeled as a function of amplitude using a piecewise linear fit. The segments may or may not be of equal length. The slopes and intercepts of these segments are used to determine the phase distortion as a function of amplitude. After determining the phase distortion in both the I and Q arms, the above relationship can be used to form the precompensated sample output. The figure shows a first plot 1400 and a second plot 1450. The first plot 1400 plots the true phase error as a function of amplitude on the in-phase path, and the second plot 1450 plots the true phase error as a function of amplitude on the quadrature-phase path. Both plots 1400 and 1450 utilize piecewise linear fits across different segments.

[0146] Embodiments of the AM-PM compensation block described herein may include a phase error calculation block that takes in-phase or quadrature samples as an input and produces as an output a phase error proportional to the magnitude of the input. For example, Figure 15 illustrates an example AM-PM compensation module 1500 that includes a first phase error calculation block 1522 for determining a phase error of an I component (e.g., I samples 1512) and a second phase error calculation block 1524 for determining a phase error of a Q component (e.g., Q samples 1514), according to some examples.

[0147] For ease of implementation, some embodiments of the phase error calculation blocks 1522, 1524 may map the amplitude axis to endpoints I1, I2, ..., I N Each segment may have a different range of amplitude. In some embodiments, the phase error model across each segment may be configured with slope and intercept parameters m i ,c i The phase error calculation block 1522 of the AM-PM compensation block 1500 used for the in-phase component 1512 is represented by a straight line with Δθ I The phase error calculation block 1524 of the AM-PM compensation block 1500 used for the quadrature component 1514 produces a corresponding output of Δθ Q produces the corresponding output of

[0148] In some embodiments, the AM-PM compensation block 1500 and / or the phase error calculation blocks 1522, 1524 can be designed and / or configured to select appropriate interval endpoints, slope and intercept parameters for the in-phase component 1512 and the quadrature-phase component 1514, respectively. Q is calculated by a phase error calculation block 1524 which receives the Q component 1514 as input and combines it with the I component 1512 of the original samples to produce the pre-distortion output I c Similarly, the phase error IΔθ of the Q component 1514 is generated. Iis calculated by a phase error calculation block 1522 which receives the I component 1512 as input and is combined with the Q component 1514 of the original samples to produce the pre-distortion output Q c Generates 1554.

[0149] One embodiment of the architecture of the phase error calculation block is shown in FIG. 16. For example, FIG. 16 illustrates an example architecture 1600 of the phase error calculation block 1630, according to some examples. This can be the same as or similar to the phase error calculation block 1522 and / or the phase error calculation block 1524 of FIG. 15. Because the phase error is a function of the magnitude of the input (e.g., input IQ samples 1605), the magnitude of the incoming in-phase or quadrature-phase component is first calculated by the magnitude calculation block 1612. The determined magnitude from the magnitude calculation block 1612 can be provided as an input to a range selection module 1642, which selects which of the configured intervals (e.g., I1, I2, ..., I N After determining the corresponding one of the intervals that includes the determined magnitude, range selection module 1642 and / or range selection algorithm 1646 are used to select corresponding slope and intercept values ​​(e.g., m ) that are selected to form the final phase error output term 1655 that is generated to be output as Δθ by phase error calculation block 1630. i , c i ) can be determined. In some embodiments, range selection module 1642 of FIG. 16 can be the same as or similar to range selection module 1262 of FIG. 12 and / or range selection algorithm 1646 of FIG. 16 can be the same as or similar to range selection algorithm 1264 of FIG. 12. FIG. 17 is a flow diagram of an example process 1700 for performing signal compensation to digitally correct the gain characteristic of a digital power amplifier (DPA). For example, process 1700 may correspond to a compensation method for digitally correcting the gain characteristic of a DPA and / or ScPa. In block 1702, process 1700 may include obtaining an in-phase (I) component and a quadrature-phase (Q) component of a baseband sample. The I component is associated with an in-phase input amplitude code, and the Q component is associated with a quadrature-phase input amplitude code. In block 1704, process 1700 may include distorting the in-phase input amplitude code based on first gain pre-compensation information corresponding to the in-phase signal branch of the digital power amplifier (DPA), thereby generating a pre-distorted output amplitude code for the I component. In block 1706, process 1700 may include distorting the quadrature-phase input amplitude code based on second gain pre-compensation information corresponding to the quadrature-phase signal branch of the DPA, thereby generating a pre-distorted output amplitude code for the Q component. Here, the first gain pre-distortion information is different from the second gain pre-distortion information. At block 1708, the process 1700 may include driving a DPA using the pre-distortion output amplitude codes of the I and Q components to generate a radio frequency (RF) output.

[0150] 18 illustrates a computing device architecture 1800 of a computing device capable of implementing one or more techniques described herein. In some examples, the computing device may include a mobile device, a wearable device, an augmented reality device (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a personal computer, a laptop computer, a video server, a vehicle (or a computing device in a vehicle), or other device. The components of the computing device architecture 1800 are shown in electronic communication with each other using connections 1805, such as a bus. The computing device architecture 1800 includes a processing unit 1810 and computing device connections 1805 that couple various computing device components, including computing device memory 1815, such as read-only memory (ROM) 1820 and random access memory (RAM) 1825, to the processor 1810.

[0151] The computing device architecture 1800 may include a cache of high-speed memory directly connected to the processor 1810, close to the processor 1810, or integrated as part of the processor 1810. The computing device architecture 1800 may copy data from the memory 1815 and / or the storage device 1830 to the cache 1812 for quick access by the processor 1810. In this manner, the cache may provide a performance boost that avoids delays to the processor 1810 while waiting for data. These and other engines may be configured to control the processor 1810 or to control the processor 1810 to perform various actions. Memory 1815 of other computing devices may also be used. The memory 1815 may include multiple different types of memory with different performance characteristics. The processor 1810 may include any general-purpose processor, hardware or software services, and special-purpose processors in which software instructions are incorporated into the processor design. The hardware or software services are such as service 1 1832, service 2 1834, and service 3 1836 stored in storage device 1830 and configured to control processor 1810. Processor 1810 may be a self-contained system including multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.

[0152] To enable user interaction with computing device architecture 1800, input device(s) 1845 can represent any number of input mechanisms, such as a microphone for speech, a touch-sensitive screen for gesture or graphical input, a keyboard, a mouse, motion input, speech, etc. Output device(s) 1835 can also be one or more of numerous output mechanisms known to those skilled in the art, such as a display, projector, television, speaker device, etc. In some embodiments, a multimodal computing device allows a user to provide multiple types of input to communicate with computing device architecture 1800. Communications interface 1840 can generally control and manage user input and computing device output. There is no restriction to operating with any particular hardware arrangement, and thus the basic functionality herein can be easily replaced with improved hardware or firmware arrangements as they are developed.

[0153] The storage device 1830 is non-volatile memory and can be a hard disk or other type of computer-readable medium capable of storing data accessible by a computer, such as a magnetic cassette, a flash memory card, a solid-state memory device, a digital versatile disk, a cartridge, RAM, ROM, and hybrids thereof. The storage device 1830 can include services 1832, 1834, 1836 for controlling the processor 1810. Other hardware or software modules or engines are also contemplated. The storage device 1830 can be connected to the computing device connections 1805. In one aspect, a hardware module that performs a particular function can include software or processor-readable code stored on a computer-readable medium in association with the hardware components necessary to perform the function, e.g., the processor 1810, the connections 1805, the output devices 1835, etc.

[0154] The term "device" is not limited to one or a specific number of physical objects (such as a smartphone, a controller, a processing system, etc.) As used herein, a device can be any electronic device having one or more components that can implement at least a portion of the present disclosure.

[0155] Individual aspects may be described above as a process or method that is depicted as a flowchart or data flow diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed, but may have additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, or a subprogram. When a process corresponds to a function, this termination corresponds to a return of the function to the calling function or to the main function.

[0156] The techniques described herein may also be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such techniques may be implemented in any of a variety of devices, such as a general-purpose computer, a wireless communication device handset, or an integrated circuit device having multiple uses, including applications in wireless communication device handsets and other devices. Any functionality described as modules or components may be implemented together in an integrated logic device or as separate but interoperable logic devices. If implemented in software, the techniques may be realized at least in part by a computer-readable data storage medium comprising program code including instructions that, when executed, perform one or more of the methods described above.

[0157] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Such a processor may be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices.

Claims

1. 1. A compensation method for digitally correcting a gain characteristic of a digital power amplifier (DPA), the method comprising: generating a predistorted output amplitude code for the I component; generating a predistorted output amplitude code for the Q component; and generating a radio frequency (RF) output; obtaining in-phase (I) and quadrature (Q) components of baseband samples; the I component is related to an in-phase input amplitude code; the Q component is related to a quadrature-phase input amplitude code; In the step of generating the predistorted output amplitude code for the I component, the in-phase input amplitude code is distorted based on first gain predistortion information corresponding to an in-phase signal branch of the DPA, thereby generating the predistorted output amplitude code for the I component; generating the predistorted output amplitude code for the Q component includes distorting the quadrature-phase input amplitude code based on second gain predistortion information corresponding to a quadrature-phase signal branch of the DPA, thereby generating the predistorted output amplitude code for the Q component; the first gain pre-compensation information is different from the second gain pre-compensation information, The method of claim 1, wherein generating a radio frequency (RF) output comprises driving a DPA using the predistorted output amplitude codes of the I and Q components to generate a radio frequency (RF) output.

2. 2. The compensation method of claim 1, The method of claim 1, wherein a nonlinear gain applied by the DPA to generate the RF output is canceled by a respective predistortion associated with each of the predistorted output amplitude codes of the I and Q components.

3. 2. The compensation method of claim 1, The method, wherein the DPA is a multi-section DPA including multiple sections arranged in a multi-section DPA configuration.

4. 4. The compensation method according to claim 3, estimating a respective gain from each of the plurality of sections in the multi-section DPA configuration; and The method further comprises deriving the first gain pre-compensation information and the second gain pre-compensation information based on the respective gains estimated from each section.

5. The compensation method according to claim 3, the first gain predistortion information comprises a first predistortion characteristic comprising a first piecewise linear function across the multiple sections of the multi-section DPA architecture; and The method, wherein the second gain predistortion information comprises a second predistortion characteristic comprising a second piecewise linear function across the multiple sections of the multi-section DPA configuration.

6. 6. The compensation method according to claim 5, A method wherein the number of linear sections included in the first or second piecewise linear function corresponds to the number of sections in a multi-section DPA configuration.

7. 2. The compensation method of claim 1, The method, wherein the DPA is a switched capacitor power amplifier (ScPa) including multiple sections.

8. 2. The compensation method of claim 1, the DPA includes at least a first section and a second section; the range of possible output amplitude codes for the I component is divided into a first interval and a second interval; and A method wherein the range of possible output amplitude codes for the Q component is divided into a first interval and a second interval.

9. 9. A compensation method according to claim 8, comprising: the first section of the DPA is controlled by one or more of a predistorted output amplitude code of the I component in the first interval or a predistorted output amplitude code of the Q component in the second interval; and the second section of the DPA is controlled by one or more of a predistorted output amplitude code of the Q component in the first interval or a predistorted output amplitude code of the I component in the second interval.

10. 2. The compensation method of claim 1, The method further comprises compensating the baseband samples for phase modulation (PM)-amplitude modulation (AM) distortion associated with a phase component of the baseband samples.

11. 11. The compensation method of claim 10, the DPA is a multi-section DPA including multiple sections; the step of compensating for PM-AM distortion includes converting, selecting, deriving, and calculating; the converting step converts initial I and Q components of the baseband samples into amplitude and phase components; the selecting step includes selecting a respective section from the plurality of sections of the multi-section DPA; the respective sections are selected based on the phase components of the baseband samples; each said section being associated with a slope and intercept corresponding to a gain characteristic of the multi-section DPA within said each section; the deriving step derives amplitude correction values ​​for the baseband samples based on the slope and the intercept corresponding to the gain characteristic of the multi-section DPA in each of the sections; the calculating step calculates a predistorted amplitude of the baseband sample from the amplitude component and the amplitude correction value; The method, wherein the I and Q components of the baseband samples are generated using the predistorted amplitudes.

12. 2. The compensation method of claim 1, The method further comprises compensating the baseband samples for amplitude modulation (AM)-phase modulation (PM) distortion of the baseband samples relative to the I and Q components of the baseband samples.

13. 13. A compensation method according to claim 12, comprising: the DPA is a multi-section DPA including multiple sections; the step of compensating for AM-PM distortion includes selecting, deriving, and calculating; the selecting step includes selecting a respective section from the plurality of sections of the multi-section DPA; the respective sections are selected based on an initial Q component of the baseband samples; each said section being associated with a slope and intercept corresponding to a gain characteristic of the multi-section DPA within said each section; the deriving step derives a phase error based on the slope and the intercept corresponding to the gain characteristic of the multi-section DPA in each of the sections; the calculating step calculates a precompensated output based on an initial I component of the baseband samples and the phase error; The method of claim 1, wherein the I component of the baseband samples is the pre-compensated output.

14. 13. A compensation method according to claim 12, comprising: the DPA is a multi-section DPA including multiple sections; the step of compensating for AM-PM distortion includes selecting, deriving, and calculating; the selecting step includes selecting a respective section from the plurality of sections of the multi-section DPA; the respective sections are selected based on an initial I component of the baseband samples; each said section being associated with a slope and intercept corresponding to a gain characteristic of the multi-section DPA within said each section; the deriving step derives a phase error based on the slope and the intercept corresponding to the gain characteristic of the multi-section DPA in each of the sections; calculating a precompensated output based on an initial Q component of the baseband samples and the phase error; The method, wherein the Q component of the baseband samples is a pre-compensated output.

15. 2. The compensation method of claim 1, The method further includes obtaining, selecting, determining, deriving, and calculating steps; acquiring amplitude and phase components of the baseband samples; the selecting step includes selecting a respective section from a plurality of sections included in the DPA based on the phase components of the baseband samples; determining a slope and an intercept corresponding to a gain characteristic or a gain error of the DPA within each of the sections; the deriving step derives an amplitude correction value for the baseband sample based on the slope and the intercept; the calculating step calculates a predistorted amplitude of the baseband sample from the amplitude component and the amplitude correction value; The method, wherein the I and Q components of the baseband samples are generated using the predistorted amplitude and phase components.

16. 2. The compensation method of claim 1, The method comprises determining a selected I-segment, determining an I-slope and I-intercept, determining a Q-slope and Q-intercept, deriving, and calculating; determining a selected I-segment from a plurality of I-segment ranges configured for the DPA; the selected I-segment is selected based on values ​​of the I-components of the baseband samples; determining an I-slope and an I-intercept corresponding to the selected I-segment; determining a selected Q-segment from a plurality of Q-segment ranges configured for the DPA; the selected Q-segment is selected based on the value of the Q-component of the baseband sample; In the step of determining a Q slope and a Q intercept, a Q slope and a Q intercept corresponding to the selected Q segment are determined; In the deriving step, a Q phase error is derived based on the I slope and the I intercept, and an I phase error is derived based on the Q slope and the Q intercept; the calculating step includes calculating a precompensated Q output from the Q component and the Q phase error, and calculating a precompensated I output from the I component and the I phase error; The method, wherein the predistortion output amplitude codes for the I and Q components are derived using the precorrected I and Q outputs.

17. 1. A wireless device that transmits radio frequency (RF) signals over a wireless medium, comprising: one or more digital filters, a power amplifier (PA) gain error compensation module, and a digital power amplifier (DPA); the one or more digital filters are configured to receive and upsample in-phase (I) and quadrature-phase (Q) components of baseband samples; the I component is associated with an in-phase input amplitude code and the Q component is associated with a quadrature-phase input amplitude code; the power amplifier (PA) gain error compensation module is coupled to the one or more digital filters; The PA gain error compensation module includes: configured to distort the in-phase input amplitude code based on first gain predistortion information corresponding to an in-phase signal branch of the DPA, thereby generating a predistorted output amplitude code of the I component; and configured to distort the quadrature-phase input amplitude code based on second gain predistortion information corresponding to a quadrature-phase signal branch of the DPA, thereby generating a predistorted output amplitude code for the Q component; the first gain pre-compensation information is different from the second gain pre-compensation information, the digital power amplifier (DPA) is coupled to the PA gain error compensation module; The wireless device, wherein the DPA is configured to generate an RF output based on the predistorted output amplitude codes of the I and Q components.

18. 18. The wireless device of claim 17, further comprising one or more of a phase modulation (PM)-amplitude modulation (AM) compensation module and an AM-PM compensation module; the phase modulation (PM)-amplitude modulation (AM) compensation module is coupled to the one or more digital filters and the PA gain error compensation module; the PM-AM compensation module is configured to correct PM-AM distortion of the baseband samples based on a phase component of the baseband samples; the AM-PM compensation module is coupled to the one or more digital filters and the PA gain error compensation module; The wireless device, wherein the AM-PM compensation module is configured to correct AM-PM distortion of the baseband samples based on a phase error derived from the I and Q components of the baseband samples.

19. 20. The wireless device of claim 18, a Cartesian to polar coordinate converter coupled to the one or more digital filters and configured to convert the I and Q components of the baseband samples into amplitude and phase components; the PM-AM compensation module is further configured to determine a selected section from a plurality of sections included in the DPA based on the phase components of the baseband samples; the selected section is associated with a slope and intercept corresponding to the selected section; the PM-AM compensation module is further configured to derive amplitude correction values ​​for the baseband samples based on the slope and the intercept of the selected section; the PM-AM compensation module is further configured to calculate a predistorted amplitude of the baseband samples from the amplitude component and the amplitude correction value; A wireless device, wherein the PA gain error compensation module is configured to receive the I and Q components of the baseband samples derived using the predistorted amplitude calculated by the PM-AM compensation module.

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