Semiconductor device

Abstract

To provide a semiconductor device which is reduced in manufacturing cost, excellent in power consumption, reduced in size, and excellent in data reliability.SOLUTION: In the semiconductor device, the element layer 20 includes a transistor layer 40 including a plurality of transistor layers 41 _ 1 to 41 _ k over a transistor layer 30 including a transistor 31 for reading in the z-axis direction and a correction circuit 35 including transistors 32 to 34. Each of the transistor layers 41 _ 1 to 41 _ k includes a plurality of memory cells 42 each including a transistor 43 and a capacitor 44. The transistor 43 switches the conduction state between the local bit line LBL and the capacitor 44 according to the control of the word line WL connected to the gate. The local bit line LBL is connected to a gate of the transistor 31, and the word line WL switches on / off of the transistor 43 by a word signal supplied to the word line WL. An interconnect CSL that applies a fixed potential is connected to the capacitor 44.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and is a semiconductor element ( circuits including transistors, diodes, photodiodes, etc., and devices that have such circuits. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, integrated circuits A chip with an integrated circuit or an electronic component that houses a chip in a package is a type of semiconductor device. In addition, storage devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. The body may be a semiconductor device or may have a semiconductor device. [Background technology]

[0003] Metal oxides are attracting attention as semiconductors that can be used in transistors. In-Ga-Zn oxide, also known as "Ixo," is a representative multi-component metal oxide. In research on IGZO, it was found that the IGZO is neither single crystal nor amorphous, but CAAC (c- axis aligned crystalline structure, and nc (nanocr A crystalline structure was found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in the channel formation region (hereinafter referred to as an oxide semiconductor transistor) These transistors are sometimes called "OS transistors" or "OS transistors." It has been reported that OS transistors are used (for example, Non-Patent Documents 1 and 2). Various semiconductor devices have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process for OS transistors is the same as the CMOS process used for conventional Si transistors. The OS transistor can be stacked on the Si transistor. For example, in Patent Document 1, a layer of a memory cell array having an OS transistor is formed by using a Si transistor. The document discloses a structure in which multiple layers are stacked on a substrate provided with a resistor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2012 / 0063208 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. Therefore, it is possible to provide a semiconductor device or the like having a novel configuration, which can reduce manufacturing costs. Another object of one embodiment of the present invention is to provide a semiconductor device that functions as a memory device utilizing extremely small off-state current. To provide a semiconductor device having a novel configuration and excellent low power consumption in a semiconductor device. Another object of one embodiment of the present invention is to provide a memory device that functions as a memory device utilizing extremely small off-state current. A semiconductor device having a novel configuration that can reduce the size of the device. Another object of one embodiment of the present invention is to provide a semiconductor device using an extremely small off-state current. In a semiconductor device that functions as a memory device, a new method for improving the reliability of read data is provided. An object of the present invention is to provide a semiconductor device or the like having a new structure.

[0009] The description of a plurality of problems does not preclude the existence of each other. It is not necessary to solve all of the problems listed. Also, problems other than those listed may be solved by the present invention. This becomes self-evident, and such a problem can also be an object of one embodiment of the present invention. [Means for solving the problem]

[0010] One embodiment of the present invention is a driver circuit including a plurality of transistors each having a channel formed using a silicon substrate. a first transistor layer having a plurality of transistors each using a metal oxide as a channel; and a second transistor layer, the first transistor layer and the second transistor layer being The first transistor layer is provided on the silicon substrate and includes a first transistor and a first capacitor. a first memory cell having a first transistor electrically connected to a first local bit line; the second transistor layer has a gate electrically connected to the first local bit line; a second transistor and a first correction circuit electrically connected to the second transistor; The first correction circuit is electrically connected to the first global bit line, and the first correction circuit is connected to the second global bit line. The function of maintaining a voltage corresponding to the threshold voltage of the first transistor at the gate of the second transistor. The semiconductor device has the following features.

[0011] One embodiment of the present invention is a driver circuit including a plurality of transistors each having a channel formed using a silicon substrate. and an element layer in which a plurality of transistor layers are stacked, the element layer being made of a metal oxide. A first transistor layer and a second transistor layer each having a plurality of transistors each using a nitride as a channel. a first transistor layer and a second transistor layer on a silicon substrate; the first transistor layer is provided in a first transistor layer having a first transistor and a first capacitor; a first transistor electrically connected to a first local bit line; The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line. a first correction circuit electrically connected to the second transistor, The path is electrically connected to the first global bit line, and the first correction circuit includes a second transistor. a semiconductor having a function of holding a voltage corresponding to the threshold voltage of the second transistor at the gate of the second transistor; It is a conductor device.

[0012] In one embodiment of the present invention, the first local bit line is perpendicular to the surface of the silicon substrate. Preferably, the semiconductor device is provided in a direction or approximately vertically.

[0013] In one aspect of the present invention, the first global bit line connects the first correction circuit and the drive circuit. A semiconductor device having an electrical connection function is preferred.

[0014] In one embodiment of the present invention, the first global bit line is perpendicular to the surface of the silicon substrate. Semiconductor devices that are arranged in a perpendicular or substantially vertical direction are preferred.

[0015] In one embodiment of the present invention, the metal oxide is a semiconductor device containing In, Ga, and Zn. Positioning is preferred.

[0016] In one aspect of the present invention, the first correction circuit includes third to fifth transistors. The third transistor is connected to the gate of the second transistor and the source of the second transistor. The fourth transistor has a function of controlling the conduction state between the first transistor and either the drain or the second transistor. The other of the source or drain of the second transistor and the The fifth transistor has a function of controlling conduction between the first transistor and a wiring to which a potential is applied. between one of the source or drain of the second transistor and the first global bit line; A semiconductor device having a function of controlling the conduction state is preferred.

[0017] In one aspect of the present invention, the first transistor is non-conductive during the period in which the correction operation is performed. Preferably, the semiconductor device is in a non-volatile state.

[0018] In one aspect of the present invention, a second memory cell, a second local bit line, and a second correction circuit a second global bit line, a fifth transistor, a sixth transistor, and a seventh transistor; and a driving circuit for driving a first bit line and a second bit line which function as a bit line pair. a sense amplifier electrically connected to the bit line, and the second memory cell is a second local bit the second local bit line is electrically connected to the second correction circuit; The second correction circuit is electrically connected to the second global bit line, and the fifth transistor is connected to the first global bit line. The sixth transistor has a function of controlling the conduction state between the bit line and the first global bit line. The transistor controls the conduction state between the second bit line and the second global bit line. The seventh transistor has a function of connecting the first global bit line and the second global bit line. A semiconductor device having a function of controlling the conduction state between and is preferable.

[0019] In one embodiment of the present invention, the fifth to seventh transistors are made of metal oxide. A semiconductor device that is a transistor used in a channel is preferred.

[0020] Other aspects of the present invention will be described in the following embodiments and and as described in the drawings. [Effects of the Invention]

[0021] One embodiment of the present invention can provide a semiconductor device or the like with a novel structure. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current, It is possible to provide a semiconductor device or the like having a novel configuration, which can reduce costs. Another embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. It is possible to provide a semiconductor device or the like having a novel configuration that is excellent in low power consumption. One embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. It is possible to provide a semiconductor device or the like having a novel configuration that can reduce the size of the device. Another embodiment of the present invention is a semiconductor device that functions as a memory device utilizing extremely small off-state current. In the present invention, a semiconductor device or the like having a novel configuration and excellent reliability of read data is provided. It is possible.

[0022] The description of a plurality of effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Problems, effects, and novel features other than those described above can be easily understood from the description and drawings of this specification. It will become clear as time goes by. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are a block diagram and a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 3] 3A, 3B, and 3C are diagrams for explaining the operation of the semiconductor device. [Figure 4] 4A and 4B are a flow diagram and a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 5] 5A and 5B are a flow diagram and a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 6] 6A and 6B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 7] FIG. 7 is a flow diagram showing an example of the configuration of a semiconductor device. [Figure 8] 8A and 8B are a flow diagram and a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 9] 9A and 9B are a flow diagram and a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 10] 10A and 10B are schematic diagrams showing configuration examples of a semiconductor device. [Figure 11] FIG. 11 is a schematic diagram showing a configuration example of a semiconductor device. [Figure 12] 12A and 12B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 13] 13A and 13B are a block diagram and a circuit diagram showing a configuration example of a semiconductor device. [Figure 14] 14A and 14B are block diagrams showing configuration examples of a semiconductor device. [Figure 15] 15A, 15B, 15C, and 15D are circuit diagrams for explaining configuration examples of semiconductor devices. [Figure 16] 16A and 16B are circuit diagrams for explaining a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram for explaining a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a timing chart for explaining an example of the configuration of a semiconductor device. [Figure 19] 19A, 19B, and 19C are circuit diagrams and timing charts for explaining configuration examples of a semiconductor device. [Figure 20] FIG. 20 is a timing chart for explaining an example of the configuration of a semiconductor device. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 22]22A and 22B are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 23] 23A, 23B, and 23C are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 26] 26A, 26B, and 26C are a top view and a cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] 27A, 27B, 27C, and 27D are top views for explaining configuration examples of semiconductor devices. [Figure 28] 28A, 28B, and 28C are diagrams for explaining the classification of IGZO crystal structures, diagrams for explaining the XRD spectrum of silica glass, and diagrams for explaining the XRD spectrum of crystalline IGZO. [Figure 29] FIG. 29 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 30] FIG. 30 is a conceptual diagram showing a configuration example of a semiconductor device. [Figure 31] 31A and 31B are schematic diagrams illustrating an example of an electronic component. [Figure 32] FIG. 32 is a diagram illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0024] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified as follows. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0025] In this specification, the ordinal numbers "first," "second," and "third" refer to the constituent elements. The numbers are added to avoid confusion and do not limit the number of components. The order of the components is not limited. The element referred to as "first" in one embodiment may be used in other embodiments or in the claims. In addition, for example, the second component may be the component referred to as "second" in the specification. A component referred to as "first" in one embodiment may be used in other embodiments, or It may be omitted in the claims.

[0026] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In some cases, elements formed at the same time may be given the same reference numerals, and repeated explanations thereof will be omitted. This may occur.

[0027] In this specification, for example, the power supply potential VDD is abbreviated as potential VDD, VDD, etc. This may be due to the presence of other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.). The same applies to (etc.).

[0028] Also, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, The code is followed by an identifying code such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0029] (Embodiment 1) Structural examples of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 1 to 18. do.

[0030] Semiconductor devices are devices that utilize the characteristics of semiconductors, and are made up of semiconductor elements (transistors, In this embodiment, the present invention is a circuit including a photodiode, a photodiode, or the like, and a device having the circuit. The semiconductor device to be described functions as a memory device using a transistor with extremely low off-state current. It is possible.

[0031] FIG. 1 shows a block diagram for explaining a schematic cross-sectional structure of a semiconductor device 10. As shown in FIG.

[0032] The semiconductor device 10 includes a plurality of element layers 20_1 to 20_M (M is a self-transistor) on a silicon substrate 50. The element layers 20_1 to 20_M are transistor layers 30 and transistor The transistor layer 40 includes a plurality of transistor layers 41_1 to 41_2. It consists of 41_k (k is a natural number greater than or equal to 2).

[0033] In the schematic diagram shown in FIG. 1, the z-axis direction is defined in order to explain the arrangement of each component. The direction refers to a direction perpendicular or approximately perpendicular to the surface of the silicon substrate 50. "Straight" refers to a state in which the angle is between 85 degrees and 95 degrees. Therefore, the z-axis direction is sometimes called the vertical direction. It corresponds to the plane formed by the x-axis and y-axis, which are defined in the perpendicular or approximately perpendicular direction. For ease of understanding, the x-axis direction is sometimes called the depth direction and the y-axis direction is called the horizontal direction. .

[0034] The transistor layer 40 is made up of a plurality of transistor layers 41_1 to 41_k. The transistor layer has a plurality of memory cells (not shown). It has a transistor and a capacitor. The capacitor is sometimes called a capacitive element. The element layer is a layer on which elements such as capacitors and transistors are provided. It is a layer having members such as a body and an insulator.

[0035] The memory cells included in each of the transistor layers 41_1 to 41_k are formed in a channel forming region. A transistor having an oxide semiconductor (hereinafter referred to as an OS transistor) is used for a memory. DOSRAM (Dynamic Oxide Semiconductor Rand It can be called a ROM Access Memory. It can be configured with one capacity, which allows for high memory density. By using a transistor, the data retention period can be increased.

[0036] In one embodiment of the present invention, a memory cell including an OS transistor is used. This reduces the leakage current (hereinafter referred to as "off current") that flows between the source and drain when the device is off. By utilizing this property, a charge corresponding to the desired voltage is transferred to the capacitor on the other side of the source or drain. In other words, once written data can be stored in a memory cell, It can be retained for a long time, which reduces the frequency of data refresh and reduces power consumption. It is possible to achieve this.

[0037] In addition, in memory cells using OS transistors, the charge is charged or discharged. This allows data to be rewritten and read, so data can be written and read an unlimited number of times. The memory cell using OS transistors is capable of writing and reading data. Unlike silicon or resistive memory, this does not involve structural changes at the atomic level, so writing is In addition, memory cells using OS transistors are superior in terms of flash memory As shown, no instability due to an increase in electron trap centers is observed even with repeated rewriting operations.

[0038] Furthermore, memory cells using OS transistors have silicon in the channel formation region. It can be freely placed on a silicon substrate with a transistor (hereinafter referred to as Si transistor). Therefore, integration is easy. It can be manufactured at low cost because it can be manufactured using the same manufacturing equipment as the printer. .

[0039] In addition to the gate electrode, source electrode, and drain electrode, the OS transistor also has a buffer If a back gate electrode is included, it can be a four-terminal semiconductor element. The input and output of signals flowing between the source and drain are controlled independently according to the voltage applied to the gate electrode. Therefore, it is possible to design circuits using the same concept as LSI. In addition, OS transistors can perform the same functions as Si transistors in high-temperature environments. Specifically, it can withstand temperatures between 125°C and 150°C. Even at high temperatures, the ratio of on-current to off-current is large, ensuring good switching operation. This can be done.

[0040] The transistor layer 30 selects one of the memory cells included in the transistor layer 40. The function of writing and reading data to and from the memory cells Has.

[0041] The transistor layer 30 includes a read transistor for reading data and a data A correction function that writes data, reads data, and corrects the data that is read. The gate of the read transistor is connected to one of the plurality of memory cells. By using this configuration, the read transistor is connected to the local bit line. When reading data, the small potential difference between the local bit lines is amplified to the global bit line. The correction circuit can output the signal to the gate of the read transistor. A potential corresponding to the threshold voltage of the transistor is held. This allows the read transistor to reduce the variation in data read from the memory cell. It can be reduced.

[0042] The local bit lines are bit lines that are directly connected to the memory cells. The local bit line GBL is connected to the correction circuit by selecting one of the local bit lines. The global bit line GBL or local bit line is electrically connected to the memory cell. The data signal applied to the local bit line is the signal to be written to the memory cell, or the signal to be written to the memory cell. This corresponds to the signal read from the cell. The data signal corresponds to data 1 or data 0. The data signal will be described as a binary signal having a high or low potential. The code may be multi-valued, with three or more values.

[0043] As shown in FIG. 1, the transistor layer 40 is The transistor layer 40 included in each of the element layers 20_1 to 20_M is The transistor layer 30 includes a correction circuit. The path utilizes the difference in the amount of current flowing through the readout transistor of the transistor layer 30. By this, the data signal written in the memory cell is set to the potential of the global bit line GBL. The transformer has the function of converting the voltage change into a voltage change and outputting it to the drive circuit of the silicon substrate 50. The resistor layer 30 converts the data signals output by the drive circuit of the silicon substrate 50 into a correction circuit. It has the function of providing a selected local bit line.

[0044] The silicon substrate 50 is used for writing data to a memory cell selected by the transistor layer 30. In order to read or write data via the global bit line GBL and the local bit line GBL, The drive circuit has a plurality of Si transistors using the silicon substrate 50 as a channel. It has a transistor.

[0045] According to one embodiment of the present invention, a transistor provided in each element layer has an extremely low off-state current. OS transistors are used, so the refresh frequency of data stored in memory cells is low. Therefore, the semiconductor device can be reduced in power consumption. The transistors can be stacked and fabricated using the same manufacturing process in a vertically repeatable manner. In addition, one embodiment of the present invention is a memory. The transistors that make up the recells are arranged vertically instead of horizontally, improving memory density. Furthermore, the OS transistor can be used in high-temperature environments. Compared to Si transistors, the electrical characteristics fluctuate less even under extreme temperatures, resulting in excellent reliability. The semiconductor device can function as a memory device. By using a configuration that corrects the threshold voltage of the transistor for reading data, The semiconductor device can function as a memory device with excellent data reliability.

[0046] Next, in FIG. 2A, an element layer corresponding to any one of the element layers 20_1 to 20_M in FIG. A block diagram of 20 is shown.

[0047] As shown in FIG. 1, in the device layer 20 according to one embodiment of the present invention, the transistor A plurality of transistor layers 40 each having memory cells are provided on the memory cell layer 30. By adopting this configuration, the distance between the transistor layer 30 and the transistor layer 40 can be shortened. The shorter local bit lines can reduce the parasitic capacitance. The transistor layers 41_1 to 41_k are repeatedly fabricated in the vertical direction using the same manufacturing process. This makes it possible to reduce manufacturing costs.

[0048] FIG. 2B is a diagram showing the components in the element layer 20 shown in FIG. 2A using circuit symbols.

[0049] The transistor layer 30 includes a read transistor 31 and a correction circuit 35. The circuit 35 includes a transistor 32, a transistor 33, and a transistor . Each of the transistor layers 41_1 to 41_k includes a plurality of memory cells 42. The recell 42 includes a transistor 43 and a capacitor 44. The transistor 43 is In response to the control of the word line WL connected to the gate, the local bit line LBL and the capacitor 44 to switch between a conductive state (ON) and a non-conductive state (OFF). The local bit line LBL is connected to the gate of the transistor 31. The word line W L is a signal that is transmitted by a word signal (sometimes called a signal WL) given to a word line WL. The capacitor 44 is a wiring that provides a fixed potential. CSL is connected.

[0050] The transistors included in the correction circuit 35 are connected as shown in FIG. In this case, either the source or the drain of the transistor 33 is connected to the gate of the transistor 31. The other of the source and drain of transistor 33 is connected to the source of transistor 34. connected to either the source or drain of transistor 31. The source or drain of the transistor 33 is connected to the source of the transistor 31. The other of the source and drain of the transistor 32 is connected to The other of the source and drain of the transistor 34 is connected to the global The transistors 32, 33, and 34 are connected to the gates of the The conduction state between the source and drain is controlled by the input signals RE, WE, and MUX. The signals RE, WE, and MUX function as switches to switch between a conducting state and a non-conducting state. are used to turn on or off the transistor that acts as a switch, respectively. For example, the signal can be turned on when it is at H level and turned off when it is at L level.

[0051] The transistor 43 is the OS transistor described above. The capacitor 44 has an electrode The electrode is made of a conductor sandwiched between two insulators. In addition to metal, a semiconductor layer that is given conductivity may be used. The position of the transistor 43 will be described in detail later. In addition to the configuration in which a semiconductor layer or an electrode constituting the transistor 43 is disposed as a capacitor, The electrode 44 can be used as one of the electrodes.

[0052] The transistor 31 switches between the logic high and low states depending on the potential of the local bit line LBL. The potential of the gate of the transistor 31 is the potential of the transistor 32. When the threshold voltage of the transistor 31 is exceeded, a current flows between the source and the drain. .

[0053] The correction circuit 35 corrects the current flowing between the source and drain of the transistor 31 through the wiring S L and the global bit line GBL, or It has a function of transmitting the potential of the bit line GBL to the local bit line LBL. The potential of the gate of the transistor 31 is transferred between the source and drain of the transistor 31. It has the function of discharging to the line SL.

[0054] The transistors 31 to 34 included in the transistor layer 30 are also Preferably, the element layer 20 is made up of an OS transistor. The transistor layers 30 and 40 are formed on a silicon substrate having a Si transistor. Since the semiconductor device can be stacked and arranged, integration can be easily achieved.

[0055] FIG. 3A is a diagram for explaining the operation of the semiconductor device 10. As shown in FIG. The operation of the semiconductor device 10 is carried out during a period 11 during which data is written to the memory cells. 0, a period 120 during which a correction operation for reading data is performed, and a period during which a data read operation is performed. It can be broadly divided into 130 sections.

[0056] The operation of the semiconductor device 10 is not limited to the order shown in FIG. By turning off each transistor included in the correction circuit 35, the gate of the transistor 31 The potential held in the transistor 31, for example, the potential corresponding to the threshold voltage of the transistor 31, is maintained. Therefore, for example, as shown in FIG. 3B, the period 120 and the period 130 A period 140 during which the operation is stopped while the threshold voltage is maintained may be provided between the Alternatively, as shown in FIG. 3C, for example, the period 120 can be divided into periods 120_1 and 120_2. By repeating this process multiple times, such as 120_2 and 140, the transition The potential held at the gate of transistor 31 corresponds to the threshold voltage of transistor 31. A potential refresh operation can be achieved.

[0057] 4A and 4B are flowcharts for explaining the period 110, i.e., the data write operation. and a circuit diagram.

[0058] In a data write operation, first, as shown in FIG. 4A, the signals WE and MUX are set to The local bit line WL is set to H level, and the signal WL and the signal RE are set to L level (operation 111). The local bit line LBL is electrically connected to the global bit line GBL. The line LBL is charged by the global bit line GBL. is set to a voltage according to the data to be written in the memory cell 42.

[0059] Next, as shown in FIG. 4A, the signals WL, WE, and MUX are set to the H level, and the signal The signal RE is set to the L level (operation 112). The capacitor 44 is electrically connected to the local bit line LBL. The local bit line LBL is supplied with a voltage according to the data to be written to the memory cell 42. Then, data is written to the memory cell 42 (operation 113). A schematic operation is shown in FIG. 4B. In FIG. 4B, the dashed arrow indicates the writing to the memory cell 42. Voltage V according to the input data DATA In Figure 4B, the crossed transponders represent The crossed transistor symbol represents the off state, and the uncrossed transistor symbol represents the on state. represent.

[0060] Next, as shown in FIG. 4A, the signals WE and MUX are set to the H level, the signals WL and The signal RE is set to the L level (operation 114). The voltage V DATA Then, as shown in FIG. 4A, the signals WE, MUX, and The signal WL and the signal RE are set to the L level (operation 115), and the data write operation is completed. When proceeding to the correction operation, it is possible to omit operation 115.

[0061] 5A, 5B, 6A, 6B, and 7 illustrate period 120, i.e., the correction operation. 1 is a flow chart and circuit diagram for explaining the present invention.

[0062] In the correction operation, first, as shown in FIG. 5A, the signals WE and MUX are set to the H level, The signals WL and RE are set to the L level (operation 121). The local bit line LBL is The local bit line LBL is electrically connected to the global bit line GBL. , are charged by the global bit line GBL. The precharge voltage of the global bit line LBL is Vpre1. GBL and the local bit line LBL are precharged (operation 122: GBL, LB A schematic diagram of operation 122 is shown in FIG. 5B. In the center, the dashed arrow indicates the pre-write operation to the global bit line GBL and the local bit line LBL. The charge voltage Vpre1 ​​is shown. In FIG. 5B, the transistor symbol marked with a cross represents the off state, and an uncrossed transistor symbol represents the on state.

[0063] Next, as shown in FIG. 5A, the signals WE and RE are set to the H level, and the signals WL and The signal MUX is set to the L level (operation 123). The local bit line LBL is connected to the transistor 33, the transistor 31, and the transistor 32 are electrically connected to the wiring SL. The local bit line LBL is connected to the transistor 33, the transistor 31, and the The charge according to the precharge voltage Vpre1 ​​is discharged via the transistor 32. The potential of the local bit line LBL is equal to the threshold voltage (Vth) of the transistor 31. When this happens, the discharge stops and the threshold voltage Vth is held at the gate of transistor 31. (Operation 124: threshold correction). The potential of the wiring SL is discharged when the local bit line LBL is discharged. A schematic operation of operation 124 is shown in FIG. In FIG. 6A, the dashed arrow indicates the discharge from the local bit line LBL to the line SL. In Figure 6A, the transistor symbol with a cross indicates the current that flows through the transistor. A transistor symbol without a cross represents an on state.

[0064] Then, as shown in FIG. 5A, the signals WE, RE, WL, and MUX are connected to the L The local bit line LBL sets the potential of the line SL to V SL ,to If the threshold voltage of the transistor 31 is Vth, the gate-source voltage Vgs is Vth. (Vgs=Vth), that is, (Vth+V SL ) is held. The schematic operation of 125 is illustrated in FIG. 6B. In FIG. 6B, the crossed transistors The crossed transistor symbol represents the off state, and the uncrossed transistor symbol represents the on state. vinegar.

[0065] The operation flow shown in FIG. 5A can be configured differently. For example, the operation flow shown in FIG. The flow shown in FIG. 7 differs from that shown in FIG. 5A in that the wiring SL Specifically, the potential of the operation 121 corresponding to the operation 121 is switched. In operation 125A, which corresponds to operation 125, the line SL is connected to the potential V SL0 Keep it as In operation 123A corresponding to operation 123, the line SL is set to a potential V SL0 Greater than Potential V SL By adopting this configuration, when the potential of the local bit line LBL is small, Even if the voltage Vcc is 0.01 V, a current can flow through the wiring SL.

[0066] 8A and 8B are flow charts for explaining the period 130, i.e., the data read operation. and a circuit diagram.

[0067] In a data read operation, first, as shown in FIG. 8A, the signal WL is set to the H level, and the signal WE Then, the signal MUX and the signal RE are set to the L level (operation 131). The local bit line LBL is connected to the voltage V SL +Vth and capacitor 4 Voltage of 4V DATA and are added together through charge sharing (operation 132). The potential (V DATA +Vth+V SL )

[0068] Next, as shown in FIG. 8A, the signals WL, RE, and MUX are set to the H level, and the signal The signal WE is set to the L level (operation 133). The transistor 31 is turned on by the gate potential (V DAT A +Vth+V SL ) and current (Idata) flows. The precharge line GBL is applied with a precharge voltage Vpre1 ​​and is in an electrically floating state (floating The potential of the global bit line GBL is set to the value Id The voltage varies from Vpre1 ​​depending on the ata (operation 134). The signal is read out by the drive circuit as Vread (operation 135). This is illustrated in FIG. 8B. In FIG. 8B, the crossed transistor symbol represents the off state. ,An uncrossed transistor symbol represents the on state.

[0069] 9A and 9B show the flow and circuit for explaining period 140, i.e., the resting operation. Figure.

[0070] In the sleep mode, first, as shown in FIG. 9A, the signals WL, WE, MUX, and The signal RE is set to the L level (operation 141). Voltage (V SL +Vth) and the voltage V of the capacitor 44 DATA and is maintained (operation 142). A schematic diagram of operation 142 is shown in FIG. 9B. In FIG. 9B, the cross marks indicate The crossed transistor symbol represents the off state, and the uncrossed transistor symbol represents the Indicates the on state.

[0071] In FIG. 10A, the device layers 20_1 to 20_M shown in FIG. 1 are formed on a silicon substrate 50. 10A shows a perspective view of the semiconductor device 10 arranged in the vertical direction (z-axis direction). It represents the depth direction (x-axis direction) and the horizontal direction (y-axis direction).

[0072] In FIG. 10A, the memory cells 42 included in the transistor layers 41_1 and 41_2 are indicated by dotted lines. It shows.

[0073] As shown in FIG. 10A, a semiconductor device 10 according to an embodiment of the present invention includes an OS transistor. Therefore, the same fabrication method can be repeated in the vertical direction. This allows the manufacturing process to be used, thereby reducing the manufacturing cost. In the semiconductor device 10 according to one embodiment, a transistor layer 40 having a memory cell 42 is formed in a planar direction. Instead, they can be stacked vertically to increase memory density, making it possible to miniaturize devices. This can be achieved.

[0074] 10B shows the respective components of the element layers 20_1 to 20_M shown in FIG. 10A. 10B is a diagram showing the circuits provided on the silicon substrate 50. A control logic circuit 6, which is composed of Si transistors on a silicon substrate 50 1, row driver circuit 62, column driver circuit 63 and output circuit 64. The logic circuit 61, row drive circuit 62, column drive circuit 63 and output circuit 64 are implemented as This will be described in detail in the fourth embodiment.

[0075] 11, the transistor layers 30, 41_1 of the semiconductor device 10 shown in FIG. 11 corresponds to a diagram in which the transistor layers 41_1, 41_2 are extracted and illustrated. The memory cell in 41_2 has a transistor 43 and a capacitor 44, a local The bit lines LBL and word lines WL are shown. The LBL is shown by a dashed line to improve visibility. Also shown is a global bit line GBL that penetrates each transistor layer. As mentioned above, the global bit line GBL is made thicker than the other lines to improve visibility. is illustrated in.

[0076] As shown in FIG. 11, in the semiconductor device 10, the transistor 4 3, the local bit line LBL connected to the transistor layer 30, the compensation circuit and the silicon The global bit line GBL connected to the substrate 50 is By adopting this configuration, the local bit lines connected to each memory cell are arranged in the vertical direction. Therefore, the parasitic capacitance of the local bit line LBL can be significantly reduced. Therefore, even if the data signal stored in the memory cell is multi-valued, the potential can be read out. Furthermore, one embodiment of the present invention is a method for reading data stored in a memory cell as a current. Therefore, even if the data is multi-valued, it can be easily read out.

[0077] 12A and 12B show the transistor 31 and the correction circuit 35 shown in FIG. 2B. A circuit diagram for explaining an example is shown in FIG. 2B. In FIG. 2B, each transistor has a back gate. Although the transistors are shown as having a top gate structure or a bottom gate structure without electrodes, The structure of the transistor is not limited to this. For example, as shown in FIG. 12A, The transistor layer 30A may have a back gate electrode connected to the back electrode line BGL. By using the configuration of FIG. 12A, the electrical characteristics such as the threshold voltage of each transistor can be controlled externally. It can be more easily controlled.

[0078] Alternatively, as shown in FIG. 12B, a back gate electrode connected to the gate electrode may be used. By using the configuration of FIG. 12B, each transistor can be The amount of current that flows can be increased.

[0079] Although the semiconductor device 10 of FIG. 1 has been described as having one type of memory cell, it may be possible to use two or more types of memory cells. 13A shows a semiconductor device corresponding to a modification of the semiconductor device 10. 1 shows a block diagram of a semiconductor device 10A.

[0080] The semiconductor device 10A has different circuit structures between the transistor layer 20 and the transistor layer 30. The semiconductor device 10 differs from the semiconductor device 10 in that a transistor layer 90 having memory cells of this structure is provided.

[0081] FIG. 13B is a circuit diagram showing an example of the configuration of a memory cell included in the transistor layer 90. The memory cell 91 includes a transistor 92, a transistor 93, and a capacitor 94. do.

[0082] One of the source and drain of the transistor 92 is connected to the gate of the transistor 93. The gate of the transistor 93 is connected to one electrode of a capacitor 94. The other of the source and drain of the transistor 92 and the source of the transistor 92 One of the source and drain of the transistor 93 is connected to the wiring BL2. The other electrode of the capacitor 94 is connected to the wiring SL2. The source or drain of the transistor 92 is electrically connected to the line CAL. One of the electrodes is connected to the gate of the transistor 93 and one of the electrodes of the capacitor 94. Let the node be node N.

[0083] The wiring CAL is used as a wiring for applying a predetermined potential to the other electrode of the capacitor 94. When data is read from the memory cell 91, the potential of the wiring CAL is set to the When writing data to the cell 91 and while the data is being stored in the memory cell 91, This makes the potential of the line CAL different from that of the line CAL. The apparent threshold voltage of the transistor 93 is set to 0 when writing data to the memory cell 91 and when and the apparent threshold voltage of the transistor 93 while the data is being stored in the memory cell 91. The pressure can be different.

[0084] When the memory cell 91 has the configuration shown in FIG. 13B, data is written to the memory cell 91. When the data is written to the memory cell 91, or while the data is being held in the memory cell 91, Regardless of the data stored, no current flows between the wiring SL2 and the wiring BL2. When reading data from the memory cell 91, the data stored in the memory cell 91 is transferred between the wiring SL2 and the wiring BL2. A current corresponding to the stored data flows.

[0085] The transistors 92 and 93 are preferably OS transistors. The OS transistor has an extremely low off-state current. The charge corresponding to the memory cell 9 can be held at the node N for a long time. In 1, once written data can be retained for a long time. The frequency of refreshing can be reduced, and the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. Cut.

[0086] The memory cell 91 having the configuration shown in FIG. 13B is a NOSR memory using OS transistors. AM (Nonvolatile Oxide Semiconductor RAM) NOSRAM has the advantage of being able to perform non-destructive readout. On the other hand, when reading out the stored data in the DOSRAM, it is read destructively. become.

[0087] The semiconductor device 10A includes a memory cell 91, which stores data that is frequently read out. You can write from SRAM to NOSRAM. As mentioned above, NOSRAM is non-destructive. Since destructive readout is possible, the frequency of data refresh can be reduced. Therefore, the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. Transistor 92 and transistor 93 shown in FIG. 3B have one gate. The transistors shown are illustrative but not limiting. For example, transistor 92 and transistor One or both of the transistors 93 may be a transistor having two gates (floor a transistor having a front gate and a back gate facing the front gate It may also be possible to use the following.

[0088] 14A and 14B are diagrams illustrating modifications of the semiconductor device 10 shown in FIG. The formula is shown below.

[0089] FIG. 14A shows the structure of the element layers 20_1 to 20_M in the semiconductor device 10 shown in FIG. In the semiconductor device 10B, the transistor layer 40 is disposed below the transistor layer 30. The semiconductor device 10B shown in FIG. 14A has a transistor layer 30 below it. The transistor layer 49 includes transistor layers 49_1 to 49_k. Even if the threshold voltage of the read transistor is not changed, the threshold voltage of the read transistor can be corrected.

[0090] FIG. 14B shows the structure of the element layers 20_1 to 20_M in the semiconductor device 10 shown in FIG. In this case, the semiconductor device includes the transistor layer 49 described in FIG. 14A in addition to the transistor layer 40. In this configuration, the threshold voltage of the read transistor is compensated. It is possible to perform a corrective action.

[0091] 15A and 15B are circuit diagrams corresponding to the memory cell 42 described in FIG. 2B and the like. The circuit blocks corresponding to the circuit diagram are shown in FIGS. 15A and 15B. Thus, the memory cells 42 may be represented as blocks in the drawings.

[0092] 15C and 15D show the transistor 31 and the correction circuit 3 described with reference to FIG. 2B etc. 5, a circuit diagram corresponding to the transistor layer 30, and a circuit block corresponding to the circuit diagram. As shown in Figures 15C and 15D, the transistors 31 and The transistor layer 30 having the correction circuit 35 is shown as a block of the circuit 36 ​​in the drawings. It may be expressed as:

[0093] FIG. 16A also shows a silicon substrate 50 with a memory cell formed of a Si transistor. 1 shows an example of the circuit configuration of a control circuit 51 for controlling the writing and reading of data. The control circuit 51 includes a switch circuit 52, a precharge circuit 53, a precharge circuit 54, a sensor a global bit line SA_GBL connected to the control circuit 51; The bit line SA_GBLB, bit lines BL and BLB are shown.

[0094] As shown in FIG. 16A, the switch circuit 52 is, for example, an n-channel transistor. The transistors 52_1 and 52_2 are turned on in response to a signal CSEL. a wiring pair of global bit lines SA_GBL and SA_GBLB; The conduction state of the wiring pair of bit lines BL and BLB is switched.

[0095] As shown in FIG. 16A, the precharge circuit 53 includes an n-channel transistor 5 The precharge circuit 53 is configured with bits 3_1 to 53_3 in response to the signal EQ. The potential between the line BL and the bit line BLB is set to the intermediate potential VPRE, which corresponds to VDD / 2. This is a circuit for charging.

[0096] The precharge circuit 54 includes a p-channel transistor 5 as shown in FIG. The precharge circuit 54 is configured with bits 4_1 to 54_3 in response to the signal EQB. The potential between the output line BL and the bit line BLB is set to the intermediate potential VPRE, which corresponds to VDD / 2. This is a circuit for charging.

[0097] The sense amplifier 55 is connected to the wiring SAP or the wiring SAN as shown in FIG. 16A. p-channel transistors 55_1 and 55_2 and n-channel transistors The wiring SAP or wiring SAN is connected to VDD or V The transistors 55_1 to 55_4 are inverters. The transistor that constitutes the loop.

[0098] FIG. 16B illustrates a circuit block corresponding to the control circuit 51 described in FIG. 16A and other figures. As shown in FIG. 16B, the control circuit 51 is shown as a block in the drawing. It may be expressed as:

[0099] 17 is a circuit diagram for explaining an example of the operation of the semiconductor device 10 of FIG. 15A to 15D, 16A, and 16B. It shows.

[0100] As shown in FIG. 17, the transistor layer 40 including the transistor layer 41_k includes a plurality of The memory cell 42 is connected to a pair of local bit lines LBL and The memory cell connected to the local bit line LBL_pre The local bit 42 is a memory cell to which data is written or read. The line LBL_pre is a local bit line to be precharged. The memory cells connected to LBL_pre continue to hold the data.

[0101] The local bit line LBL is electrically connected to the global bit line GBL via a circuit 36. The local bit line LBL_pre is connected to the global bit line BL_P via the circuit 36_pre. The bit line GBLB is electrically connected to the bit line GBLB.

[0102] The transistor 97 is connected between the global bit line GBL and the global bit line GBLB. The transistor 97 functions as a switch for switching the conduction state of the signal SW 0 turns it on or off.

[0103] The transistor 98 is connected to the global bit line GBL and the global It functions as a switch for switching the conduction state between the bit line SA_GBL. Transistor 98 is switched on or off by signal SW1.

[0104] The transistor 99 is connected to the global bit line GBLB and the global It functions as a switch to switch the conduction state between the bit line SA_GBLB and the Transistor 99 is switched on or off by signal SW2.

[0105] FIG. 18 shows a timing chart for explaining the operation of the circuit diagram shown in FIG. In the timing chart of Figure 18, the global bit line SA_GBL and The wiring pair of the global bit line SA_GBLB, the global bit line GBL, For the GBLB line pair, when the data is at H level (data=H), The diagram is divided into the case of level (data=L).

[0106] In the timing chart shown in FIG. 18, the time from time T11 to time T13 is the time for writing data. This corresponds to the period during which the operation described in FIG. 4A is performed. The period from time T16 to time T16 corresponds to the correction period. In other words, it corresponds to the period during which the operation described with reference to FIG. 5A is performed. The period from time T16 to time T18 corresponds to the data read period. This corresponds to the period during which the above-described operation is performed. , H level.

[0107] At time T11, the signals MUX and WE are set to H level. The signal SW0 is set to L level. Then, the power supply voltage (VDD, V SS), the global bit line SA_GBL or the global bit line SA One of the wiring pairs of _GBLB, the global bit line GBL or the global bit line GBL One of the pair of lines B is charged. The potential of the local bit line LBL rises. The word line W The potential of the local bit line LBL is set to H level (H in the case of FIG. 18). level) is written to memory cell 42.

[0108] At time T12, the potential of the word line WL is set to L level. It will be held.

[0109] At time T13, both the SAP and SAN lines are set to VDD, and the EQ and EQB signals are inverted. In addition, the wiring of the global bit lines SA_GBL and SA_GBLB The wiring pairs of the global bit line GBL and the global bit line GBLB are both set at the H level. The local bit line LBL_pre is precharged to a high level potential. After that, the signal MUX is set to the L level, and the signal WE may also be set to the low level.

[0110] At time T14, the signals RE and WE are set to H level. The potential of the local bit line LBL_pre is discharged through the transistor 31. This discharge occurs when the voltage between the gate and source of transistor 31 drops below the The voltage drops to the threshold voltage of the capacitor 31.

[0111] At time T15, both the signals WE and RE are set to the L level. BL and the local bit line LBL_pre, depending on the threshold voltage of the transistor 31. The signals EQ and EQB are inverted again to stop the precharge. That is, the global bit line SA_GBL and the global bit line SA_GBLB The wiring pair of the global bit line GBL and the wiring pair of the global bit line GBLB are It becomes airborne and floating.

[0112] At time T16, the word line WL is set to H level to perform charge sharing. The potential of the bit line LBL changes depending on the data written in the memory cell 42. When data of the local bit line LBL is written to the memory cell 42, the potential of the local bit line LBL rises. When L-level data is written to the memory cell 42, the potential of the local bit line LBL On the other hand, in the local bit line LBL_pre, the voltage Vcc decreases due to the operation of the word line WL. Since no charge sharing is performed, the potential does not change.

[0113] At time T17, the signals RE and MUX are set to H level, thereby BL and the local bit line LBL_pre, the transistor included in the circuit 36 A current flows through the local bit 31 and the transistor 31 included in the circuit 36_pre. Since the potentials of the line LBL and the local bit line LBL_pre are different, the transistors of the circuit 36 There is a difference in the current flowing through the transistor 31 included in the circuit 36_pre and the transistor 31 included in the circuit 36_pre. This current difference is caused by the local bit line LBL The potential of the memory cell 42 depends on the data read from the memory cell 42. , the data in the memory cell 42 is transmitted to the global bit line SA_GB L, a wiring pair of the global bit line SA_GBLB, a global bit line GBL, a global The amount of change in the potential of the pair of bit lines GBLB can be converted into the amount of change in the potential of the pair of bit lines GBLB.

[0114] At time T18, the signal RE is set to L level. Then, the power supply voltage ( VDD, VSS) to operate the sense amplifier 55. By operating, the global bit lines SA_GBL and SA_GB LB wiring pair, the global bit line GBL and the global bit line GBLB wiring pair The potential is determined.

[0115] At time T19, the signal SW0 is set to L level and the signal SW1 is set to H level, and the global bit The potential of the wiring pair of the global bit line GBL and the global bit line GBLB is changed in response to the read data. Specifically, when the data is at a H level, the global bit line GBL and The potentials of the wiring pair of the global bit line GBLB and the global bit line GBLB are both switched to the H level. When the data is at the L level, the global bit line GBL and the global bit line GBLB In this state, the potentials of the pair of lines are both switched to the L level. By doing so, a voltage corresponding to the logic of the read data is written back to the memory cell 42. This can be done.

[0116] At time T20, the signals MUX, WL, and WE are set to the L level. In this case, the data can be refreshed according to the logic of the read data.

[0117] In the semiconductor device 10 according to one embodiment of the present invention, the transistor layer 4 having the memory cell 42 This configuration makes the local bit lines LBL shorter. On the other hand, the capacitance of the capacitor 44 of the memory cell 42 can be reduced. In the resistor 42, the parasitic capacitance between the gate of the transistor 43 and the source or drain Depending on the amount, there is a risk of potential fluctuations occurring.

[0118] FIG. 19A shows a transistor 43 and a capacitor 44 included in a memory cell 42, and 19A shows a circuit diagram of the transistors 19A and 19B, which are the transistors 19B and 19C, and the local bit line LBL. The parasitic capacitance between the gate and the source or drain of the transistor 43 is defined as Ctd and Ct It is illustrated as s.

[0119] In response to the fluctuation of the potential of the word line WL, the local bit line LBL, which is in an electrically floating state, The potential of the capacitors Ctd and Cts fluctuates depending on the capacitive coupling. The resulting potential change shortens the local bit line LBL and This becomes particularly significant when the capacitance is reduced.

[0120] FIG. 19B shows a schematic diagram of a waveform for explaining the fluctuation of the potential according to the capacitive coupling. In FIG. 19B, the period T16 to T17 in the timing chart shown in FIG. The potential of the local bit line LBL and the local bit line LBL change in response to the change in the potential of the word line WL. 1 illustrates the change in the potential of the local bit line LBL_pre. The operation is such that the data written to the memory cell 42 is at H level (data=H) and L level ( The figures are divided into the cases where data = L and where data = L.

[0121] As described above, according to one aspect of the present invention, the local bit lines LBL are shortened, and the memory cells Since the capacitance of the capacitor 44 of the local bit line LBL Therefore, the parasitic capacitance of the word line WL and the capacitance of the capacitor 44 can be reduced. The fluctuation of the potential of the local bit line LBL is steeper than the fluctuation of the potential of the During charge sharing at time T16, the fluctuation in the potential of the local bit line LBL is The change in potential of the word line WL becomes steeper than the change in potential of the word line WL (time T16_2). During this period, both the local bit line LBL and the capacitor 44 are in an electrically floating state. Therefore, as the potential of the word line WL rises, the potential of the local bit line LBL rises. On the other hand, when the potential of the word line WL does not change, the voltage rises at the H level and the L level. The potential of the bit line LBL_pre does not fluctuate.

[0122] The potential of the local bit line LBL increases with the increase in the potential of the word line WL at time T1 7, the potentials of the local bit line LBL and the local bit line LBL_pre are The magnitude relationship is reversed. For example, when reading out the L level potential of the local bit line LBL, This can cause problems such as the potential of the local bit line LBL_pre rising above the Rub.

[0123] Therefore, the word line WL is switched from H level to L level at time T17. In other words, the transistor 43 is configured to supply a current to the transistor 31. During the period when the transistor 34 is in a conducting state to pass current and perform data reading, 19C shows the potential of the word line WL at time T17. Explain the fluctuation of the potential of the local bit line LBL when the A schematic diagram of the waveform for this purpose is shown.

[0124] In FIG. 19C, the change in the potential of the word line WL after the time T16 to T16_2 and The potential of the local bit line LBL and the potential of the local bit line LBL_pre are changed as shown in FIG. At time T17, the potential of the word line WL is changed from the H level to the L level. At time T17, the local bit line LBL and the capacitor 44 are switched to Since both the word line WL and the local bit line WL are electrically floating, the potential of the word line WL decreases. The potential of the line LBL drops when the data is at both H level and L level. Without a change in the potential of WL, there is no change in the potential of the local bit line LBL_pre. By inverting the potential of the word line WL at time T17, the local bit line This makes it possible to prevent the magnitude relationship between the potentials of the local bit line LBL and the local bit line LBL_pre from being inverted. Cut.

[0125] By applying the operation of the word line WL in FIG. 19C to FIG. 18, the timing chart in FIG. 20 is obtained. This can be the action of the

[0126] In one embodiment of the present invention, a transistor layer having a memory cell and a correction circuit The data can be read out as a signal with the threshold voltage of the readout transistor corrected. By adopting this configuration, data read from the memory cell to the driver circuit Further, in the semiconductor device according to one embodiment of the present invention, By placing multiple switches between the global bit lines, the data read from the memory cells can be The data can be written back to the memory cell using the logic of the data.

[0127] (Embodiment 2) An example of a semiconductor device that functions as a memory device according to one embodiment of the present invention will be described below. Reveal.

[0128] FIG. 21 shows a semiconductor device in which a memory unit is formed on an element layer 411 having a circuit formed on a semiconductor substrate 311. The memory unit 470 (memory unit 470_1 to memory unit 470_m:m) is two or more 21 is a diagram illustrating an example of a semiconductor device in which an element layer 411 is stacked. A plurality of memory units 470 are stacked on the element layer 411. The gates 470 are connected to the corresponding transistor layers 413 (transistor layers 413_1 to up to transistor layer 413_m), and a plurality of memory devices on each transistor layer 413 Layer 415 (memory device layer 415_1 to memory device layer 415_n: n is 2 or more) In each memory unit 470, a transistor is provided. In this embodiment, the memory device layer 415 is provided on the data layer 413. The present invention is not limited to this. Alternatively, memory device layers 415 may be provided above and below the transistor layer 413. .

[0129] The element layer 411 includes a transistor 300 provided on a semiconductor substrate 311. It can function as a circuit for the device (sometimes called a peripheral circuit). , column driver, row driver, column decoder, row decoder, sense amplifier, Charge circuit, amplifier circuit, word line driver circuit, output circuit, control logic circuit Examples include:

[0130] The transistor layer 413 includes a transistor 200T, which controls each memory unit 470. The memory device layer 415 can function as a circuit for controlling the memory device 4. The memory device 420 shown in this embodiment has a transistor 200M and a capacitor 200M. It has a capacitance element 292.

[0131] The value of m is not particularly limited, but is 2 or more and 100 or less, preferably 2 or more. It is preferably 50 or less, and more preferably 2 or more and 10 or less. There is no limitation, but it is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and The product of m and n is 4 or more and 256 or less, preferably 4 or more and 12 or less. It is 8 or less, and more preferably 4 or more and 64 or less.

[0132] FIG. 21 also shows a transistor 200T included in the memory unit and a transistor A cross-sectional view of the 200M channel length direction is shown.

[0133] As shown in FIG. 21, a transistor 300 is provided on a semiconductor substrate 311. On the memory unit 470, a transistor layer 413 and a memory device A layer 415 is provided, and the transistors included in the transistor layer 413 in one memory unit 470 are The transistor 200T and the memory device 420 included in the memory device layer 415 are The transistor 300 and each memory unit 47 are electrically connected by the conductor 424. The transistor 200T included in the transistor layer 413 in FIG. The conductor 426 is electrically connected to the source and drain of the transistor 200T. , and the transistor 200T through a conductor 428 electrically connected to one of the gates. The conductors 424 are preferably electrically connected to each layer of the memory device layer 415. In addition, the conductor 426 is preferably provided between the transistor layer 413 and the memory It is preferable that the light source is provided in each layer of the device layer 415.

[0134] As will be described in detail later, the side surfaces of the conductor 424 and the conductor 426 are not covered with water or It is preferable to provide an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. Examples of such insulators include silicon nitride, aluminum oxide, and silicon nitride oxide. etc. can be used.

[0135] The memory device 420 includes a transistor 200M and a capacitive element 292. The transistor 200M has the same structure as the transistor 200T of the transistor layer 413. In addition, transistor 200T and transistor 200M can be collectively referred to as transistor It is sometimes called Sta 200.

[0136] Here, the transistor 200 has a region where a channel is formed (hereinafter, referred to as a channel forming region A metal oxide (hereinafter referred to as an oxide semiconductor) that functions as an oxide semiconductor is added to a semiconductor containing It is preferable to use a conductive material.

[0137] As an oxide semiconductor, for example, In-M-Zn oxide (element M is aluminum, gallium, Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In addition, as the oxide semiconductor, a metal oxide such as indium oxide or In- Ga oxide and In-Zn oxide may also be used. By using a compound semiconductor, the on-current or field-effect mobility of the transistor can be increased. It is possible.

[0138] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Conductors can be deposited using methods such as sputtering, making them ideal for constructing highly integrated semiconductor devices. The transistor 200 can be used.

[0139] On the other hand, in a transistor using an oxide semiconductor, impurities and oxygen vacancies in the oxide semiconductor (V O The electrical characteristics of the material change depending on the oxygen vacancy. -on characteristics (a channel exists even when no voltage is applied to the gate electrode, and the transistor (characteristic of current flowing through the capacitor)

[0140] Therefore, an oxide semiconductor with a reduced impurity concentration and a reduced density of defect states is preferably used. In this specification and the like, a low impurity concentration and a low defect level density are referred to as a high purity intrinsic or or essentially high purity authentic.

[0141] Therefore, it is preferable that the impurity concentration in the oxide semiconductor be reduced as much as possible. Impurities in the oxide semiconductor include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like. Examples include metals such as iron, nickel, and silicon.

[0142] In particular, hydrogen as an impurity contained in an oxide semiconductor forms oxygen vacancies in the oxide semiconductor. In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V O It may be called H ) may generate electrons that act as carriers. In addition, some of the hydrogen atoms bond with metal atoms. It may react with oxygen to generate electrons that act as carriers.

[0143] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen has a normally-on In addition, hydrogen in the oxide semiconductor is easily degraded by stress such as heat or an electric field. Because hydrogen is easily mobile, the reliability of transistors deteriorates when a large amount of hydrogen is contained in an oxide semiconductor. There is also a risk that this may happen.

[0144] Therefore, the oxide semiconductor used in the transistor 200 does not contain impurities such as hydrogen and oxygen. It is preferable to use a high-purity intrinsic oxide semiconductor with reduced defects.

[0145] <Sealing structure> Therefore, in order to prevent the intrusion of impurities from the outside, materials that suppress the diffusion of impurities (hereinafter referred to as The transistor 200 is preferably sealed using a material having a barrier property against impurities. stomach.

[0146] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "logging."

[0147] For example, aluminum oxide is a material that has the function of suppressing the diffusion of hydrogen and oxygen. aluminum, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride Silicon nitride or silicon oxide nitride is particularly Since it has a high barrier property against hydrogen, it is preferable to use it as a sealing material.

[0148] Furthermore, for example, aluminum oxide is a material having the function of capturing and fixing hydrogen. Metal oxides such as aluminum, hafnium oxide, gallium oxide, and indium gallium zinc oxide There is.

[0149] Between the transistor 300 and the transistor 200, an insulating layer having a barrier property is provided. Preferably, an insulator 211, an insulator 212, and an insulator 214 are provided. 1. The insulator 212 and / or the insulator 214 are not subject to diffusion or permeation of impurities such as hydrogen. By using a material that suppresses over-conversion, the semiconductor substrate 311, the transistor 300, etc. This can prevent impurities such as hydrogen and water from diffusing into the transistor 200. At least one of the insulating material 211, the insulating material 212, and the insulating material 214 is made of a material that inhibits oxygen permeation. By using the material, the channel of the transistor 200 or the material included in the transistor layer 413 This can prevent oxygen from diffusing into the element layer 411. The insulator 212 is made of a material that suppresses the permeation of impurities such as hydrogen and water. It is preferable to use a material that suppresses the permeation of oxygen by using the insulator 214. It is more preferable to use a material that has absorbing and occluding properties. The insulator 212 is made of a nitride such as silicon nitride or silicon nitride oxide. The insulator 214 may be, for example, aluminum oxide, hafnium oxide, or oxide. Metal oxides such as gallium oxide and indium gallium zinc oxide can be used. In particular, it is preferable to use aluminum oxide as the insulator 214 .

[0150] In addition, the side surfaces of the transistor layer 413 and the memory device layer 415, i.e., the memory unit The sides of the unit 470 are preferably provided with an insulator 287, and the memory unit 47 It is preferable that an insulator 282 is provided on the upper surface of the insulating layer 282. It is preferable that the insulator 287 contacts the insulator 211, the insulator 212, and It is preferable that the insulator 287 and the insulator 214 are in contact with each other. It is preferable to use a material that can be used for the insulator 214 as the material 282 .

[0151] Insulators 283 and 287 are disposed so as to cover insulators 282 and 287. 84 is preferably provided, and the insulator 283 is In FIG. 21, the insulator 287 is preferably in contact with at least one of the insulators 214. The side of the insulator 214, the side of the insulator 212, and the top and side of the insulator 211 are in contact with each other. In the example in which the insulator 283 contacts the upper and side surfaces of the insulator 287 and the upper surface of the insulator 211, However, the present embodiment is not limited to this. and the top and side surfaces of the insulator 212, and the insulator 283 contacts the top and side surfaces of the insulator 287. The insulator 282 and the insulator 28 may be in contact with each other. 7, a material that can be used for the insulators 211 and 212 can be used. preferable.

[0152] In the above structure, the insulator 287 and the insulator 282 are made of a material that suppresses oxygen permeation. It is preferable to use a material that can capture hydrogen as the insulator 287 and the insulator 282. It is even more preferable to use a material that has good adhesion properties. By using a material that has the function of capturing and fixing hydrogen on the side close to the The hydrogen in the resistor 200 or the memory unit 470 is insulated by the insulator 214, the insulator 287, and insulator 282, trapping and securing the hydrogen concentration in transistor 200. In addition, hydrogen or water can be used as the insulator 283 and the insulator 284. It is preferable to use a material that inhibits the permeation of any impurities.

[0153] By adopting the above-described structure, the memory unit 470 is 2, insulator 214, insulator 287, insulator 282, insulator 283, and insulator 284 More specifically, the memory unit 470 is surrounded by the insulators 214, 287, and and an insulator 282 (sometimes referred to as a first structure), The first structure includes the insulator 211, the insulator 212, the insulator 283, and the The insulating material 284 (sometimes referred to as the second structure) surrounds the insulating material 284. A structure in which the memory unit 470 is surrounded by two or more layers of structures is called a nested structure. Here, the memory unit 470 being surrounded by multiple structures is called a memory The unit 470 may be described as being sealed by multiple insulators.

[0154] The second structure also seals the transistor 200 via the first structure. The hydrogen existing outside the second structure is absorbed by the second structure into the inside ( The diffusion of the first structure to the second structure (transistor 200 side) is suppressed. It can efficiently capture and fix hydrogen present in the internal structure of the body.

[0155] Specifically, the first structure contains a metal oxide such as aluminum oxide. The second structure may be made of a nitride such as silicon nitride. In the second embodiment, an aluminum oxide film is disposed between the transistor 200 and the silicon nitride film. It is good.

[0156] Furthermore, the material used for the structure can be used to adjust the hydrogen concentration in the film by appropriately setting the film formation conditions. can be reduced.

[0157] Generally, films formed using the CVD method have higher solubility than films formed using the sputtering method. On the other hand, the compound gas used in the CVD method often contains hydrogen, and The film formed by the VD method has a higher hydrogen content than the film formed by the sputtering method. The quantity is large.

[0158] Therefore, for example, a film having a reduced hydrogen concentration in the film adjacent to the transistor 200 may be used. (Specifically, a film formed by sputtering) is preferably used. As a film for suppressing diffusion, a film with high film coverage but a relatively high hydrogen concentration in the film (specifically When using a film formed by CVD, the hydrogen concentration is It has the function of capturing and fixing hydrogen between the highly effective and highly covering film, and also has the function of capturing and fixing hydrogen between the highly effective and highly covering film. It is advisable to provide a film with a reduced element concentration.

[0159] That is, the film disposed adjacent to the transistor 200 has a relatively low hydrogen concentration. On the other hand, a film with a relatively high hydrogen concentration in the film is preferably used at a location far from the transistor 200. It is advisable to place them apart.

[0160] Specifically, the transistor 200 is formed by a nitride film formed by a CVD method. When sealing with silicon, the transistor 200 and a nitride film formed by CVD are An aluminum oxide film formed by sputtering is placed between the silicon film. More preferably, the silicon nitride film is formed by a CVD method and the silicon nitride film is formed by a sputtering method. The aluminum oxide film formed by the sputtering method was placed between the aluminum oxide film formed by the sputtering method. It is preferable to dispose a silicon nitride film.

[0161] When forming a film using the CVD method, the film does not contain hydrogen atoms or the content of hydrogen atoms is By depositing the film using a compound gas with low hydrogen concentration, the hydrogen concentration in the deposited film is reduced. That's fine.

[0162] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device Preferably, an insulator 282 and an insulator 214 are also provided between the insulating layers 415 . In addition, it is preferable that an insulator 296 be provided between the insulator 282 and the insulator 214. The insulator 296 can be made of the same material as the insulators 283 and 284. Alternatively, silicon oxide or silicon oxynitride can be used. Insulating materials may be used. Here, insulator 282, insulator 296, and insulator 214 may be elements that constitute the transistor 200. The insulator 214 also serves as a component of the transistor 200, thereby enabling the semiconductor device to be manufactured. This is preferable because it can reduce the number of steps required.

[0163] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device Insulators 282, 296, and 214 are provided between the insulating layers 415, respectively. The side of the transistor is preferably in contact with the insulator 287. The resistor layer 413 and the memory device layer 415 are covered with the insulator 282 and the insulator 296, respectively. , insulator 214, insulator 287, insulator 283, and insulator 284. will be done.

[0164] In addition, the insulator 274 may be provided around the insulator 284. A conductor 430 is provided so as to be embedded in the insulators 284, 283, and 211. The conductor 430 may be a transistor 300, i.e., a circuit included in the element layer 411. and electrically connect it.

[0165] In the memory device layer 415, the capacitor element 292 is located in the same layer as the transistor 200M. Therefore, the height of the memory device 420 can be made to be approximately the same as that of the transistor 200M. This can prevent the height of each memory device layer 415 from becoming excessively large. This allows the number of memory device layers 415 to be increased relatively easily. For example, a stack of transistor layers 413 and memory device layers 415 is formed in 10 It may be possible to set it to about 0 layers.

[0166] <Transistor 200> 22A, the transistor 200T and the memory The transistor 200M included in the device 420 can be used as the transistor 200. Let me explain about 0.

[0167] As shown in FIG. 22A, the transistor 200 is made up of an insulator 216 and a conductor 205 ( The oxide 23 is made of a conductive material 205a and a conductive material 205b, an insulator 222, an insulator 224, and an oxide 23. 0 (oxide 230a, oxide 230b, and oxide 230c), and conductor 242 (conductive conductor 242a and conductor 242b) and oxide 243 (oxide 243a and oxide 243b), insulator 272, insulator 273, insulator 250, and conductor 260 (conductor 260a, and conductor 260b).

[0168] The insulator 216 and the conductor 205 are provided on the insulator 214, and the insulator 27 3, an insulator 280 and an insulator 282 are provided. , and insulator 282 can be considered to be part of transistor 200. do.

[0169] In addition, in the semiconductor device of one embodiment of the present invention, a plug is electrically connected to the transistor 200. The conductor 240 (conductor 240a and conductor 240b) functions as a The insulator 241 (insulator 241a, In addition, on the insulator 282 and the conductor 240, The conductor 246 (conductor 246a) is electrically connected to the conductor 240 and functions as a wiring. , and conductor 246b).

[0170] The conductors 240a and 240b are made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing rubber as the main component. The body 240b may be a laminated structure.

[0171] In addition, when the conductor 240 has a layered structure, impurities such as water or hydrogen and oxygen It is preferable to use a conductive material that has the function of suppressing transmission. For example, tantalum, nitride tantalum oxide, titanium, titanium nitride, ruthenium, or ruthenium oxide. It is also preferable that the porous membrane has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. The conductive material may be used in a single layer or a multilayer structure. Impurities such as water or hydrogen diffused from the conductor 280 etc. are transferred to the conductor 240a and the conductor 2 40b, the insulator 230 can be further reduced from being mixed into the oxide 230. 280 from being absorbed by the conductors 240a and 240b. This can be done.

[0172] The insulator 241 provided in contact with the side surface of the conductor 240 may be, for example, silicon nitride. Silicon, aluminum oxide, silicon nitride oxide, or the like may be used. are provided in contact with the insulators 272, 273, 280, and 282. Therefore, impurities such as water or hydrogen from the insulator 280 etc. are transferred to the conductor 240a and the conductor It is possible to prevent the silicon nitride from being mixed into the oxide 230 through the body 240b. The insulator 280 is preferably made of polycarbonate because of its high blocking properties against hydrogen. This can prevent oxygen from being absorbed into the conductors 240a and 240b.

[0173] The conductor 246 is made of a conductive material based on tungsten, copper, or aluminum. The conductor may have a laminated structure, for example, titanium or Alternatively, the conductive material may be a laminate of titanium nitride and the conductive material. The insulating film may be formed so as to be embedded in the opening.

[0174] In transistor 200, conductor 260 functions as the first gate of the transistor. The conductor 205 functions as a second gate of the transistor. 2a and the conductor 242b function as a source electrode or a drain electrode.

[0175] The oxide 230 functions as a semiconductor having a channel formation region.

[0176] Insulator 250 serves as the first gate insulator and is connected to insulators 222 and 22 4 acts as the second gate insulator.

[0177] Here, the transistor 200 shown in FIG. 22A includes an insulator 280, an insulator 273, an insulator 272, the conductor 242, etc., in the opening, the conductor 260 is oxide 230c and It is formed in a self-aligned manner via the insulator 250 .

[0178] That is, the conductor 260 is connected to the insulator 280 via the oxide 230c and the insulator 250. Since the conductive material 242 is formed to fill the openings provided in the conductive material 242a and the conductive material 242b, In this region, alignment of the conductor 260 is not required.

[0179] Here, it is preferable to provide an oxide 230c in an opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 are connected to the oxide 230c via the oxide 230c. 0b and the oxide 230a. Since the oxide 230c and the insulator 250 can be formed by successive film formation, Therefore, the interface between the oxide 230 and the insulator 250 can be kept clean. The effect on carrier conduction is reduced, and transistor 200 has a high on-state current and a high Wavenumber characteristics can be obtained.

[0180] In addition, the transistor 200 shown in FIG. 22A has a bottom and side surfaces of the conductor 260 that are insulated. The bottom and side surfaces of the insulator 250 are in contact with the oxide 230c. .

[0181] The transistor 200 also includes an insulator 282 and an oxide 230 as shown in FIG. 22A. c is in direct contact with the insulating material 280. The diffusion of oxygen into the conductor 260 can be suppressed.

[0182] Therefore, the oxygen contained in the insulator 280 is transferred to the oxide 230a and the oxide 230b via the oxide 230c. and oxide 230b, the oxide 230a and the oxide The oxygen vacancies in the layer 230b are reduced, and the electrical characteristics and reliability of the transistor 200 are improved. It can be done.

[0183] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0184] The transistor 200 includes an oxide 230 (oxide 230a, oxide 230b) including a channel forming region. The oxide 230c is provided with a metal oxide (hereinafter referred to as a metal oxide) that functions as an oxide semiconductor. It is preferable to use a semiconductor material other than a metal oxide semiconductor (also referred to as an oxide semiconductor).

[0185] For example, metal oxides that function as oxide semiconductors have an energy gap of 2 eV or more. It is preferable to use an energy gap of 2.5 eV or more. By using a thin metal oxide, the leakage current (on By using such a transistor, low It is possible to provide a semiconductor device with low power consumption.

[0186] Specifically, the oxide 230 is an In-M-Zn oxide (wherein the element M is aluminum, Gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel Kel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from the group consisting of tungsten, tantalum, magnesium, etc. In particular, the element M may be aluminum, gallium, yttrium, or the like. It is preferable to use thorium or tin. In addition, the oxide 230 may be an In-M oxide, an In -Zn oxide or M-Zn oxide may also be used.

[0187] As shown in FIG. 22A, the oxide 230 is formed by an oxide 230a on the insulator 224 and an oxide an oxide 230b on the oxide 230a; and a metal oxide 230b disposed on the oxide 230b, at least a portion of which is formed by the oxide. and an oxide 230c in contact with the upper surface of 230b. The side of 30c is made of oxide 243a, oxide 243b, conductor 242a, conductor 242b, It is preferable that the insulating material 272, the insulating material 273, and the insulating material 280 are provided in contact with each other. stomach.

[0188] That is, the oxide 230 is composed of an oxide 230a, an oxide 230b on the oxide 230a, and The oxide 230c is on the oxide 230b. The oxide 230a is on the oxide 230b. By having the oxide 230a, the structure formed below the oxide 230a can be transferred to the oxide 230b. The diffusion of impurities can be suppressed. By this, impurities from the structure formed above the oxide 230c are transferred to the oxide 230b. It is possible to suppress the spread of substances.

[0189] In the transistor 200, the oxide 23 is formed in the channel formation region and its vicinity. 2 shows a structure in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 230b, oxide 23 a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or For example, the oxide 230c may have a two-layer structure. In this case, a four-layer laminated structure may be provided.

[0190] The oxide 230 has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, it is preferable that the constituent elements The atomic ratio of element M in the metal oxide used for oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is In the oxide 230b, the atomic ratio of element M to In is preferably larger than that of element M. In the metal oxide used for the oxide 230a, the atomic ratio of In to the element M is In the metal oxide, the atomic ratio of In to the element M is preferably larger than that of In. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. Compounds can be used.

[0191] Specifically, the oxide 230a has an atomic ratio of In:Ga:Zn=1:3:4. or a metal with a composition of 1:1:0.5 [atomic ratio] or a composition of 1:1:0.5 ... An oxide may be used.

[0192] The oxide 230b is In:Ga:Zn=4:2:3 [atomic ratio] or or a metal oxide having a composition of 1:1:1 [atomic ratio] or a composition of about 1:1:1. The oxide 230b may have an atomic ratio of In:Ga:Zn=5:1:3. Or a composition close to that, or In:Ga:Zn=10:1:3 [atomic ratio] or Metal oxides with compositions close to those may also be used. Oxides (e.g., In:Zn=2:1 [atomic ratio] or a composition close to that, In:Zn = 5:1 [atomic ratio] or a composition close to that, or In:Zn = 10:1 [atomic ratio] ] or a composition close thereto) may be used as the oxide 230b. may also be used.

[0193] In addition, the oxide 230c is In:Ga:Zn=1:3:4 [atomic ratio or its a composition in the vicinity of Ga:Zn=2:1 [atomic ratio] or a composition in the vicinity of Ga: A metal oxide having a composition of Zn=2:5 [atomic ratio] or a composition close to that may be used. The oxide 230c is formed of a material that can be used for the oxide 230b, and may be formed as a single layer or a multilayer. For example, when the oxide 230c has a laminated structure, a specific example is In :Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and In:Ga:Zn= 1:3:4 [atomic ratio] or a laminated structure with a composition close to that, Ga:Zn=2:1 [atomic ratio] In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that. The composition is a stacked structure with a composition close to it, Ga:Zn=2:5 [atomic ratio] or a combination close to it. and a laminated structure of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto. , gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto Examples include a laminated structure with

[0194] Note that the structure of the OS transistor included in the memory cell 42 shown in Embodiment 1 and the structure of the transistor The structure of the OS transistor in the memory cell layer 30 may be different from that of the OS transistor in the memory cell layer 30. The oxide 230c of the OS transistor provided in the resonator 42 contains In:Ga:Z A metal oxide with a composition of n=4:2:3 [atomic ratio] or close to that is used to fabricate a transistor. The oxide 230c of the OS transistor provided in the layer 30 contains In:Ga:Zn= 5:1:3 [atomic ratio] or a composition close to that, In:Ga:Zn=10:1:3 [atomic ratio] In:Zn=10:1 [atomic ratio] or its vicinity Composition: In:Zn=5:1 [atomic ratio] or a composition close to that, In:Zn=2:1 A metal oxide having a composition of [atomic ratio] or close thereto may be used.

[0195] In addition, in the oxide 230b and the oxide 230c, the ratio of indium in the film is increased. This can increase the on-state current or field-effect mobility of the transistor, The aforementioned "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0196] The oxide 230b may also have crystallinity. For example, the oxide 230b may have crystallinity. S(c-axis aligned crystalline oxide semic It is preferable to use a crystalline oxide such as CAAC-OS. The material has few impurities and defects (such as oxygen vacancies), and has a highly crystalline, dense structure. Therefore, the extraction of oxygen from the oxide 230b by the source or drain electrode In addition, even if a heat treatment is performed, oxygen is not removed from the oxide 230b. Since the transistor 200 can be manufactured at high temperatures ( It is stable against the so-called thermal budget.

[0197] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216 .

[0198] When the conductor 205 functions as a gate electrode, the potential applied to the conductor 205 is By changing the potential applied to the transistor 20 independently of the potential applied to the transistor 260, the In particular, by applying a negative potential to the conductor 205, the threshold voltage (Vth) of By applying the voltage Vth, the Vth of the transistor 200 is increased and the off-current is reduced. Therefore, it is better to apply a negative potential to the conductor 205 than not to apply a negative potential to the conductor 205. The drain current when the potential applied to the conductor 260 is 0 V is smaller than that when the potential applied to the conductor 260 is 0 V. can be done.

[0199] As shown in FIG. 22A, the conductor 205 is a conductor 242a of the oxide 230 and It is preferable that the area is larger than the area that does not overlap with the conductor 242b. However, the conductor 205 is formed between the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. It is preferable that the oxide 230b extends to the outer region. On the outside of the side surface of the channel width direction of the conductor 205, the conductor 260 is It is preferable that the conductor 205 is overlapped with an insulator therebetween. In the plasma processing in the manufacturing process after the formation of the conductor 205, local charge However, one aspect of the present invention is that The conductor 205 is not limited to the above. It is sufficient to overlap with the oxide 230 located between them.

[0200] In addition, with the bottom surface of the insulator 224 as a reference, the oxide 230a and the oxide 230b and the conductive The height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap is It is preferable that the bottom surface of the casing is located at a position lower than the height of the bottom surface of the casing.

[0201] Although not shown, the conductor 260 functioning as a gate in the channel width direction is The side and top surfaces of the oxide 230b in the panel formation region are covered with the oxide 230c and the insulator 250. By using a structure in which the conductor 260 is covered with the oxide 230b, the electric field generated from the conductor 260 is not generated in the oxide 230b. Therefore, the on-state voltage of the transistor 200 is increased. In this specification, the conductor 260 and the electric field of the conductor 205 electrically surrounds the channel forming region. The structure of the data is called the surrounded channel (S-channel) structure. .

[0202] The conductor 205a is a conductive material that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride may be used. The conductor 205b can be made of a material mainly containing tungsten, copper, or aluminum. It is preferable to use a conductive material that has a thickness of 100 μm. A multi-layer structure of more than one layer may also be used.

[0203] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and the oxide The insulating or conductive material located on the upper layer of the oxide semiconductor is formed by a different film without being exposed to the atmosphere. By successively depositing the seeds, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity This is preferable because a highly intrinsic oxide semiconductor film can be formed.

[0204] At least one of the insulator 222, the insulator 272 and the insulator 273 is water or Preventing impurities such as hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 222 preferably functions as a barrier insulating film that suppresses the At least one of the body 272 and the insulator 273 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, or the like. Diffusion of impurities such as atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. It is preferable to use an insulating material that has the function of suppressing diffusion (i.e., the impurities are difficult to penetrate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) can be suppressed. It is preferable to use an insulating material that has the function of preventing oxygen from permeating through the insulating material.

[0205] For example, silicon nitride or silicon nitride oxide is used as the insulator 273. The body 222 and the insulator 272 are made of aluminum oxide or hafnium oxide. It is preferable that

[0206] This allows impurities such as water or hydrogen to pass through the insulator 222 and into the transistor 200 Alternatively, oxygen contained in the insulator 224 can be prevented from diffusing to the other side. Diffusion to the substrate side via the insulator 222 can be suppressed.

[0207] In addition, impurities such as water or hydrogen are arranged via the insulators 272 and 273. This can prevent diffusion from the insulator 280 and the like to the transistor 200 side. In this way, the transistor 200 is protected from impurities such as water or hydrogen, and from the diffusion of oxygen. The structure can be such that the insulator 272 and the insulator 273 surround the insulator 272 and the insulator 273. preferable.

[0208] Here, it is preferable that the insulator 224 in contact with the oxide 230 releases oxygen by heating. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This can improve the reliability of the transistor 200.

[0209] Specifically, the insulator 224 is made of an oxide material from which part of the oxygen is released by heating. It is preferable that the oxides that desorb oxygen by heating are those that are determined by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (TDS) analysis revealed that oxygen The amount of molecules desorbed is 1.0×10 18 molecules / cm 3 More than 1.0x, preferably 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 mole cules / cm 3or more, or 3.0 x 10 20 molecules / cm 3 That's all. The surface temperature of the film during the TDS analysis was 100°C or higher. A temperature of 700°C or lower, or a temperature in the range of 100°C to 400°C, is preferred.

[0210] The insulator 222 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 is , preferably have lower hydrogen permeability than insulator 224. 3, the insulator 224 and the oxide 230 are surrounded, and water or Impurities such as hydrogen can be prevented from entering the transistor 200.

[0211] Furthermore, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). Preferably, the body 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 2. 22, it is preferable because it can reduce the diffusion below. This can prevent the oxide 224 from reacting with the oxygen contained in the oxide 230.

[0212] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The release of impurities and the introduction of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0213] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0214] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST). For example, when the insulator 222 is a laminated layer, the insulating material may be a single layer or a laminated layer. A three-layer stack of zirconium oxide, aluminum oxide, and zirconium oxide formed in this order. layer, zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide The insulator 222 may be a four-layer laminate in which a hard film and a hard film are formed in this order. A compound containing fluorine and zirconium may also be used. As integration progresses, the gate insulator and the dielectric used in the capacitor element become thinner. This can cause problems such as leakage current in transistors and capacitors. and the use of high-k materials for the insulators that function as dielectrics in the capacitor elements. While maintaining the physical film thickness, the gate potential during transistor operation is reduced and the capacitance element is This makes it possible to secure capacity.

[0215] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. good.

[0216] Also, the oxide 230b and the conductor 242 functioning as a source electrode or a drain electrode are (conductor 242a and conductor 242b) and oxide 243 (oxide 243a and The conductor 242 and the oxide 230b may be arranged in a structure where they are not in contact with each other. This structure can prevent the conductor 242 from absorbing oxygen from the oxide 230b. In other words, by preventing oxidation of the conductor 242, the decrease in the conductivity of the conductor 242 can be suppressed. Therefore, the oxide 243 has a function of suppressing oxidation of the conductor 242. is preferred.

[0217] The oxide 230b is formed between the conductor 242, which functions as a source electrode or a drain electrode. By disposing the oxide 243 having the function of suppressing the permeation of the conductor 242, the oxide This is preferable because the electrical resistance between the electrode 230b and the electrode 230a is reduced. The electrical characteristics and reliability of the transistor 200 can be improved. do.

[0218] Oxide 243 includes aluminum, gallium, yttrium, tin, copper, vanadium, Beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium Using a metal oxide containing one or more elements M selected from sodium, etc. In particular, the element M may be aluminum, gallium, yttrium, or tin. It is preferable that the oxide 243 has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. In addition, In Metal oxides such as M-Zn oxide may also be used. In the metal oxide, the atomic ratio of element M to In is In the oxide, the atomic ratio of element M to In is preferably larger than that of element M. The thickness of 43 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. m or less. In addition, it is preferable that the oxide 243 has crystallinity. When the oxide 230 has such a property, the release of oxygen from the oxide 230 can be suitably suppressed. For example, If the oxide 243 has a crystalline structure such as a hexagonal crystal, the release of oxygen from the oxide 230 can be prevented. It may be possible to suppress it.

[0219] The oxide 243 does not necessarily have to be provided. In that case, the conductor 242 (conductor 2 When the oxide 230 comes into contact with the conductive material 42a and the conductive material 242b, the oxide in the oxide 230 The element may diffuse into the conductor 242, causing the conductor 242 to oxidize. As a result, the conductivity of the conductor 242 is likely to decrease. The conductor 242 absorbs oxygen from the oxide 230. This can be rephrased.

[0220] In addition, oxygen in the oxide 230 is converted into conductor 242 (conductor 242a and conductor 242b ) to form a gap between the conductor 242a and the oxide 230b and between the conductor 242b A foreign layer may be formed between the conductive material 242 and the oxide 230b. Since the conductor 24 also contains a large amount of oxygen, it is presumed that the different layer has insulating properties. The three-layer structure of the oxide 230b, the hetero layer 230b, and the oxide 230c is a three-layer structure consisting of a metal, an insulator, and a semiconductor. It can be considered as a MIS (Metal-Insulator-Semiconductor) structure. In some cases, it is called a diode junction structure, or a MIS structure is mainly used. be.

[0221] The different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, a different layer may be formed between the conductor 242 and the oxide 230c, or between the conductor 242 and the oxide 230c. 42 and oxide 230b, and between conductor 242 and oxide 230c. There are cases where this happens.

[0222] On the oxide 243, a conductor 242 ( The conductor 242a and the conductor 242b are provided. The thickness of the conductor 242 is, for example, , 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0223] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, or the like. Tantalum oxide, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing strontium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium The oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0224] The insulator 272 is provided in contact with the upper surface of the conductor 242 and functions as a barrier layer. By adopting this configuration, the conductor 242 can effectively prevent the overcurrent of the insulator 280. Absorption of excess oxygen can be suppressed. In addition, by suppressing oxidation of the conductor 242, It is possible to suppress an increase in the contact resistance between the transistor 200 and the wiring. This can provide the transistor 200 with good electrical characteristics and reliability.

[0225] Therefore, it is preferable that the insulator 272 has a function of suppressing the diffusion of oxygen. Preferably, the insulator 272 has a function of suppressing oxygen diffusion more effectively than the insulator 280. The insulator 272 may be, for example, aluminum or hafnium. It is preferable to form an insulator containing oxide. The insulator 272 may be, for example, aluminum nitride. An insulator containing aluminum may be used.

[0226] As shown in FIG. 22A, the insulator 272 is formed on a portion of the upper surface of the conductor 242b and the Although not shown, the insulator 272 is in contact with the side surface of the conductor 242a. The insulator 272 is in contact with a part of the insulator 273 and the side surface of the conductor 242a. In this way, for example, oxygen added to the insulator 280 can be used to The absorption of the body 242 can be suppressed.

[0227] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide or silicon oxynitride. , silicon oxynitride, silicon nitride, silicon oxide with fluorine addition, carbon-added oxide silicon dioxide, silicon dioxide doped with carbon and nitrogen, and silicon dioxide with vacancies. In particular, silicon oxide and silicon oxynitride are stable against heat, This is preferable.

[0228] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing it in contact with the top surface of the oxide 230c, the channel forming region of the oxide 230b In addition, as with the insulator 224, the insulator 250 can effectively supply oxygen. It is preferable that the concentration of impurities such as water or hydrogen is reduced. , and it is preferable that the thickness is 1 nm or more and 20 nm or less.

[0229] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Moreover, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0230] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant. By making the insulating layer 250 and the metal oxide into a laminated structure, the insulating layer 250 is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0231] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more selected from the above can be used. Aluminum oxide, an insulator containing oxides of either or both aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a laminate.

[0232] Alternatively, the metal oxide may function as a part of the gate. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the conductive material on the channel forming region side, oxygen released from the conductive material can form a channel. It becomes easier to supply the area.

[0233] In particular, the metal oxide in which the channel is formed acts as a conductor that functions as a gate. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing silicon and nitrogen may also be used. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide or silicon-doped indium tin oxide may also be used. The use of such a material allows the channel to be formed. In some cases, hydrogen contained in the metal oxide formed on the surface of the catalyst can be captured. It may be possible to capture hydrogen that has entered from an insulator or the like.

[0234] Although the conductor 260 is shown as a two-layer structure in FIG. 22A, it may be a single-layer structure or a three-layer structure. It may have a laminated structure of more than one layer.

[0235] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least (i).

[0236] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can prevent the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum chloride, ruthenium, or ruthenium oxide.

[0237] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated structure. For example, a laminate of titanium or titanium nitride and the above conductive material may be used.

[0238] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0239] The metal oxide preferably contains at least indium or zinc. In addition to these, gallium, yttrium, and zinc are preferably contained. It is preferable that the alloy contains boron, titanium, iron, nickel, germanium, etc. nium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tungsten It contains one or more selected from the group consisting of thallium, tungsten, magnesium, etc. Good too.

[0240] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. (Element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium Aluminum, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum cerium, neodymium, hafnium, tantalum, tungsten, or magnesium In particular, the element M is aluminum. Preferably, aluminum, gallium, yttrium, or tin is used.

[0241] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0242] <Transistor 300> The transistor 300 will be described with reference to FIG. 22B. The transistor 300 is formed on a semiconductor substrate A conductor 316 is provided on the gate electrode 311 and functions as a gate insulator. The insulator 315, the semiconductor region 313 consisting of a portion of the semiconductor substrate 311, and the source region or and a low resistance region 314b, which functions as a gate or drain region. The transistor 300 may be either a p-channel or an n-channel type.

[0243] Here, the transistor 300 shown in FIG. 22B has a semiconductor region 313 where a channel is formed. The semiconductor region 313 (part of the semiconductor substrate 311) has a convex shape. The surface is covered with a conductor 316 via an insulator 315. 316 may be made of a material that adjusts the work function. Since it utilizes the protruding portion of the substrate 311, it is also called a FIN type transistor. Even if an insulator is provided in contact with the top of the convex portion and functions as a mask for forming the convex portion, In addition, although the case where a part of the semiconductor substrate 311 is processed to form a convex portion has been shown here, Alternatively, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0244] The transistor 300 shown in FIG. 22B is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the configuration and driving method.

[0245] <Memory device 420> Next, a memory device 420 shown in FIG. Regarding the transistor 200M included in the 20, the same explanation as for the transistor 200 will be omitted. do.

[0246] In the memory device 420, the conductor 242a of the transistor 200M is a capacitive element. 292, and the insulators 272 and 273 function as dielectrics. The conductor 242a is overlapped with the insulator 272 and the insulator 273 sandwiched therebetween. The conductor 290 is provided as shown in FIG. 2 and functions as the other electrode of the capacitor 292. 0 is used as the other electrode of the capacitance element 292 of the adjacent memory device 420. Alternatively, the conductor 290 may be the same as the conductor 290 of the adjacent memory device 420. may be electrically connected to

[0247] The conductor 290 is disposed on the upper surface of the conductor 242a with the insulators 272 and 273 sandwiched therebetween. and also disposed on the side surfaces of the conductor 242a. Since a capacitance larger than the capacitance obtained by the overlapping area of ​​a and the conductor 290 can be obtained, I wish.

[0248] The conductor 424 is electrically connected to the conductor 242b and is connected to the lower layer via the conductor 205. The conductor 424 is electrically connected to the conductor 424 located therein.

[0249] The dielectric of the capacitor element 292 may be silicon nitride, silicon nitride oxide, or aluminum oxide. and hafnium oxide. When the dielectric of the capacitance element 292 has a laminated structure, aluminum oxide and nitride A lamination of hafnium oxide and silicon oxide, or a lamination of hafnium oxide and silicon oxide can be used. For example, silicon nitride may be stacked on aluminum oxide. Alternatively, aluminum oxide may be laminated on silicon nitride.

[0250] Furthermore, as the dielectric of the capacitance element 292, zirconium oxide having a higher dielectric constant than the above materials is used. Zirconium oxide may be used as a single layer as the dielectric of the capacitance element 292. For example, zirconium oxide and aluminum oxide may be used as a laminate. The dielectric of the capacitor element 292 can be a three-layer laminate. Zirconium oxide is often used for the first layer and the third layer, and the first layer and the third layer A second layer in between may be aluminum oxide.

[0251] By using zirconium oxide having a high dielectric constant as the dielectric of the capacitance element 292, The area occupied by the capacitor element 292 in the memory device 420 can be reduced. This is preferable because it can reduce the area required for the device 420 and improve the bit cost.

[0252] The conductor 290 includes the conductor 205, the conductor 242, the conductor 260, and the conductor 42. Materials that can be used for 4 etc. can be used.

[0253] In this embodiment, the transistor 200M and the capacitor 200M are connected with the conductor 424 interposed therebetween. 92 are arranged symmetrically. By disposing the capacitor element 292, a conductor electrically connected to the transistor 200M is 424, thereby reducing the area required for the memory device 420. This is preferable because it can improve the bit cost.

[0254] When the insulator 241 is provided on the side of the conductor 424, the conductor 424 is 42b and at least a portion of the upper surface of 42b.

[0255] Conductor 424 and conductor 205 are used to connect transistors in memory unit 470. The star 200T and the memory device 420 can be electrically connected.

[0256] <Modification 1 of Memory Device 420> Next, referring to FIG. 23B, as a modification of the memory device 420, the memory device 42 The memory device 420A includes a transistor 200M and a transistor 200B. The capacitor 292A is electrically connected to the transistor 00M. It is located below the 200M.

[0257] In memory device 420A, conductor 242a is covered with oxide 243a, oxide 230b, The oxide 230a, the insulator 224, and the insulator 222 are disposed in openings therein. The bottom of the opening is electrically connected to the conductor 205. The conductor 205 is electrically connected to the capacitive element 292A. Connect to the target.

[0258] The capacitor 292A includes a conductor 294 that functions as one of the electrodes and a dielectric The conductor 297 has an insulator 295 that functions as the other electrode and a conductor 297 that functions as the other electrode. The conductor 297 overlaps with the conductor 294 with an insulator 295 sandwiched therebetween. 5 and electrically connected.

[0259] The conductor 294 is disposed at the bottom of an opening formed in an insulator 298 provided on an insulator 296. The insulator 295 is provided on the front and side surfaces of the insulator 298 and the conductor 294. The conductor 297 is provided so as to be embedded in a recess of the insulator 295. It can be done.

[0260] In addition, a conductor 299 is provided so as to be embedded in the insulator 296. 9 electrically connects to the conductor 294. The conductor 299 connects to the adjacent memory device 42. 0A conductor 294.

[0261] The conductor 297 is disposed on the upper surface of the conductor 294 and the lower surface of the conductor 294 with the insulator 295 sandwiched therebetween. At this time, the capacitor element 292A is formed by overlapping the conductor 294 and the conductor 297. This is preferable because it provides a larger capacity than that obtainable with a smaller area.

[0262] The insulator 295 that functions as a dielectric of the capacitance element 292A may be silicon nitride, silicon nitride oxide, or the like. Silicon oxide, aluminum oxide, hafnium oxide, etc. can be used. When the insulator 295 has a laminated structure, the oxide The stacked layers of aluminum nitride and silicon nitride, and hafnium oxide and silicon oxide are used. Here, the top and bottom of the stack is not limited. For example, nitride can be stacked on aluminum oxide. Silicon may be laminated, or aluminum oxide may be laminated on silicon nitride. stomach.

[0263] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 295. The insulator 295 may be made of zirconium oxide in a single layer or in a multilayer structure. For example, a laminate of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 295 may be a three-layer laminate, with the first and third layers being The second layer between the first and third layers is made of zirconium oxide. may also be used.

[0264] By using zirconium oxide having a high dielectric constant as the insulator 295, the capacitance element 2 92A can reduce the area occupied by the memory device 420A. This is preferable because it reduces the area required for 420A and improves the bit cost.

[0265] In addition, the conductor 297, the conductor 294, and the conductor 299 include the conductor 205, the conductor The material can be used for the conductive body 242, the conductive body 260, the conductive body 424, etc. Cut.

[0266] The insulator 298 includes the insulator 214, the insulator 216, the insulator 224, and the insulator Any material that can be used for the body 280 or the like can be used.

[0267] <Modification 2 of Memory Device 420> Next, referring to FIG. 23C, as a modification of the memory device 420, the memory device 42 The memory device 420B includes a transistor 200M and a transistor 200M. The capacitance element 292B is electrically connected to the transistor 00M. It is located above the 200M.

[0268] The capacitor 292B has a conductor 276 that functions as one of the electrodes and a dielectric The conductor 278 has an insulator 277 that functions as the other electrode and a conductor 278 that functions as the other electrode. The conductor 276 overlaps with an insulator 277 sandwiched therebetween.

[0269] An insulator 275 is provided on the insulator 282, and a conductor 276 is provided between the insulator 275 and the insulator 282. 82, the insulator 280, the insulator 273, and the bottom of the opening formed in the insulator 272; The insulator 277 is provided to cover the insulator 282 and the conductor 276. The conductor 278 overlaps with the conductor 276 in the recess of the insulator 277. At least a part of the insulating material 275 is provided on the insulating material 277. The conductor 278 is connected to the capacitance element 292B of the adjacent memory device 420B. Alternatively, the conductor 278 may be used as the other pole of the adjacent memory device 420. It may be electrically connected to the conductor 278 of B.

[0270] The conductor 278 is disposed on the upper surface of the conductor 276 and the lower surface of the conductor 276 with the insulator 277 sandwiched therebetween. At this time, the capacitor element 292B is formed by overlapping the conductor 276 and the conductor 278. This is preferable because it provides a larger capacity than that obtainable with a smaller area.

[0271] In addition, an insulator 279 may be provided so as to fill the recessed portion of the conductor 278 .

[0272] The insulator 277 that functions as the dielectric of the capacitance element 292B may be silicon nitride, silicon nitride oxide, or the like. Silicon oxide, aluminum oxide, hafnium oxide, etc. can be used. When the insulator 277 has a laminated structure, the oxide The stacked layers of aluminum nitride and silicon nitride, and hafnium oxide and silicon oxide are used. Here, the top and bottom of the stack is not limited. For example, nitride can be stacked on aluminum oxide. Silicon may be laminated, or aluminum oxide may be laminated on silicon nitride. stomach.

[0273] In addition, zirconium oxide, which has a higher dielectric constant than the above materials, is used as the insulator 277. The insulator 277 may be made of zirconium oxide in a single layer or in a multilayer structure. For example, a laminate of zirconium oxide and aluminum oxide may be used. Alternatively, the insulator 277 may be a three-layer laminate, with the first and third layers being The second layer between the first and third layers is made of zirconium oxide. may also be used.

[0274] By using zirconium oxide having a high dielectric constant as the insulator 277, the capacitance element 2 92B can reduce the area occupied by the memory device 420B. This is preferable because it reduces the area required for 420B and improves the bit cost.

[0275] The conductor 276 and the conductor 278 are the conductors 205, 242, and Materials that can be used for the body 260, the conductor 424, etc. can be used.

[0276] In addition, the insulators 275 and 279 may include the insulators 214, 216, and Materials that can be used for the body 224, the insulator 280, and the like can be used.

[0277] <Connection between memory device 420 and transistor 200T> In the region 422 surrounded by the dashed line in FIG. 21, the memory device 420 has conductors 4 24 and is electrically connected to the gate of transistor 200T via conductor 205. However, the present embodiment is not limited to this.

[0278] FIG. 24 shows a memory device 420 including conductors 424, 205, 246b, and via conductor 240b as one of the source and drain of transistor 200T. 2 shows an example in which the conductor 242b is electrically connected to the conductor 242b.

[0279] In this way, the memory device 420 is configured according to the circuit function of the transistor layer 413. and the connection method of transistor 200T can be determined.

[0280] FIG. 25 shows a memory unit 470 in a transistor layer 41 having a transistor 200T. 3 and four memory device layers 415 (memory device layers 415_1 to 415_2) An example having a layer 415_4) is shown.

[0281] The memory device layers 415_1 to 415_4 each include a plurality of memory The device 420 is also included.

[0282] The memory device 420 is connected to different memory devices via electrical conductors 424 and electrical conductors 205. The memory device 420 in the device layer 415 and the transistor layer 413 Electrically connect to transistor 200T.

[0283] The memory unit 470 includes an insulator 211, an insulator 212, an insulator 214, an insulator 287, and an insulator 288. , and is sealed by insulator 282, insulator 283, and insulator 284. An insulator 274 is provided around the periphery. A conductor 430 is provided in the insulator 211 and is electrically connected to the element layer 411 .

[0284] An insulator 280 is provided inside the sealing structure. The insulator 280 is heated. The insulator 280 has a function of releasing oxygen, or has an excess oxygen region.

[0285] The insulators 211, 283, and 284 are blocking materials for hydrogen. Insulators 214, 282, and 283 are preferably made of a material having high adhesiveness. The insulator 287 is preferably a material having the function of capturing or fixing hydrogen. It is suitable.

[0286] For example, the material having a high blocking property against hydrogen is silicon nitride, Silicon nitride oxide and the like can also be used. Materials that have this function include aluminum oxide, hafnium oxide, and aluminum and Examples include oxides containing hafnium (hafnium aluminate).

[0287] In this specification, the term "barrier property" refers to the function of suppressing the diffusion of a corresponding substance (permeability). Or, the corresponding substance is captured and fixed (gettering). This function is also called "logging."

[0288] In addition, the insulators 211, 212, 214, 287, 282, and The crystal structure of the material used for the insulator 283 and the insulator 284 is not particularly limited. For example, the structure may be amorphous or crystalline. As a material having an adhesive function, an amorphous aluminum oxide film is preferably used. Amorphous aluminum oxide exhibits better hydrogen trapping and The amount of adhesion may be large.

[0289] Here, the excess oxygen in the insulator 280 is converted into hydrogen in the oxide semiconductor in contact with the insulator 280. The following model can be considered for diffusion:

[0290] Hydrogen present in the oxide semiconductor is transferred to other The diffusion of hydrogen occurs when excess oxygen in the insulator 280 is absorbed by the oxide semiconductor. It reacts with hydrogen to form an OH bond, and the hydrogen diffuses through the insulator 280. Hydrogen atoms are trapped in materials that have the function of capturing or fixing hydrogen (typically, insulators). When the hydrogen atom reaches the insulator 282, it reacts with the atoms in the insulator 282 (e.g., metal atoms). The OH bond reacts with the oxygen atom and is captured or fixed in the insulator 282. It is assumed that the oxygen atoms of the excess oxygen remain in the insulator 280 as excess oxygen. In other words, the excess oxygen in the insulator 280 plays a bridging role in the diffusion of the hydrogen. High probability.

[0291] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors. .

[0292] For example, an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulating layer is formed on the oxide semiconductor. After that, a heat treatment is preferably performed. Specifically, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen, The heat treatment is carried out at a temperature of 350°C or higher, preferably 400°C or higher. The heat treatment time is 1 hour or longer. It is preferably 4 hours or more, and more preferably 8 hours or more.

[0293] By the heat treatment, hydrogen in the oxide semiconductor is oxidized into the insulators 280, 282, and and insulator 287. In addition, the absolute amount of hydrogen present in the vicinity of the oxide semiconductor can be reduced.

[0294] After the heat treatment, the insulators 283 and 284 are formed. The insulator 284 is a material having a high blocking property against hydrogen. The hydrogen diffused outward or the hydrogen present on the outside is then transferred to the inside, specifically, the oxide semiconductor. This can prevent the air from penetrating into the body or the insulator 280 side.

[0295] Regarding the above heat treatment, the following is performed after the insulator 282 is formed: For example, after forming the transistor layer 413 or after forming the memory After forming the re-device layer 415_1 to the memory device layer 415_3, the above-mentioned heating In addition, when hydrogen is diffused outward by the heat treatment, Hydrogen is diffused upward or laterally into the transistor layer 413. Similarly, the memory device layer When heat treatment is performed after forming the memory device layers 415_1 to 415_3, The elements are diffused upward or laterally.

[0296] In the above manufacturing process, the insulator 211 and the insulator 283 are bonded to each other. Thus, the above-mentioned sealing structure is formed.

[0297] As described above, the hydrogen concentration is reduced by using the above structure and manufacturing process. Therefore, a semiconductor device using an oxide semiconductor having high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. It is possible to provide a semiconductor device having the above structure.

[0298] 26A to 26C are diagrams showing examples in which the arrangement of the conductors 424 is different from that in FIG. 26A shows a layout diagram of the memory device 420 as seen from above, and FIG. 26B shows a layout diagram of the memory device 420 as seen from above. 26A is a cross-sectional view of the area indicated by the dashed line A1-A2 in FIG. 26A. FIG. 26C is a cross-sectional view of the area indicated by the dashed line A1-A2 in FIG. 26A. 26A is a cross-sectional view of the portion indicated by the dashed line B1-B2. For clarity, the conductor 205 is not shown in the figure. has an overlapping region with the conductor 260 and the conductor 424.

[0299] As shown in FIG. 26A, the opening in which the conductor 424 is provided, i.e., the conductor 424, is The oxide 230a and the oxide 230b are not only overlapped with the oxide 230a, but also with the oxide 230b. In FIG. 26A, the conductor 424 is disposed on the outside of the oxide 230b. 2. In this example, the oxide 230a and the oxide 230b are provided so as to extend to the B2 side. The conductive material 424 is made of oxide 230a and oxide 230b. b) may be provided so as to protrude to the B1 side, or may be provided so as to protrude to both the B1 side and the B2 side. The sensor may be provided as follows.

[0300] 26B and 26C show memory device layer 415_p-1 and memory device layer 415_p-2. 1 shows an example in which a layer 415_p is stacked (p is a natural number between 2 and n). The memory device 420 included in 415_p-1 includes a conductor 424 and a conductor 205. The memory device layer 415_p is electrically connected to the memory device 420 therein via the .

[0301] In FIG. 26B, in the memory device layer 415_p-1, the conductor 424 is Conductor 242 of memory device layer 415_p-1 and conductor 242 of memory device layer 415_p 05. Here, the conductor 424 is connected to the conductor 242 and the oxide 243. , oxide 230b, and memory device layer 415_p on the outer side of oxide 230a on the B2 side. It is also connected to the conductor 205 of -1.

[0302] In FIG. 26C, conductor 424 is formed from conductor 242, oxide 243, oxide 230b, and The oxide 230a is formed along the B2 side of the insulating layer 230a. The insulating layer 230a is made of an insulator 280, an insulator 273, an insulator 272, the insulator 224, and the opening formed in the insulator 222, and the conductor 205 and the electric current Here, the conductor 424 is electrically connected to the conductor 242 and the oxide 24. 3, oxide 230b and oxide 230a are provided along the B2 side of the oxide 230a. 6B, the conductor 242, the oxide 243, the oxide 230b, and the oxide Between the object 230a, the insulator 224, and the B2 side of the insulator 222 and the conductor 424, , an insulator 241 may be formed.

[0303] By providing the conductor 424 in an area where it does not overlap with the conductor 242, etc., 420 is electrically connected to the memory device 420 provided in a different memory device layer 415. The memory device 420 is provided in the transistor layer 413. The transistor 200T can also be electrically connected to the transistor 200T.

[0304] In addition, when the conductor 424 is used as a bit line, if the conductor 424 overlaps with the conductor 242, etc. By providing it in an area where there is no bit line, the bit lines of the memory devices 420 adjacent in the B1-B2 direction As shown in FIG. 26A, the distance between the conductors 4 on the conductor 242 can be increased. The distance between the oxide 230a and the insulating layer 224 is d1. The distance between the conductors 424 located in the openings formed in the insulator 222 is d2. The distance d2 is greater than the distance d1. By setting the distance d2, the parasitic capacitance of the conductor 424 is reduced compared to the case where the distance d2 is set to d1. By reducing the parasitic capacitance of the conductor 424, the capacitance required for the capacitor 292 can be reduced. This is preferable because it can reduce

[0305] In the memory device 420, it acts as a common bit line for two memory cells. A conductor 424 is provided. The dielectric constant of the dielectric used for the capacitance and the parasitic capacitance between the bit lines are By appropriately adjusting the channel length, the cell size of each memory cell can be reduced. Estimated cell size of memory cell when the node size is 30 nm (also called the 30 nm node) The following describes the estimation of bit density and bit cost. 27A to 27D, the conductor 205 is not shown in order to facilitate understanding of the drawings. When the conductor 205 is provided, the conductor 205 is a conductor 260 and a conductor 424.

[0306] Figure 27A shows a capacitor dielectric with a 10 nm thick hafnium oxide layer and a 1 nm thick hafnium oxide layer. The silicon oxide layers are stacked in order, and the conductors 24 of the memory cells of the memory device 420 are formed. 2, a slit is provided between the oxide 243, the oxide 230a, and the oxide 230b. conductor 242 and a conductor 424 functioning as a bit line so as to overlap the slit. The memory cell 432 thus obtained is called cell A.

[0307] The cell size in cell A is 45.25F 2 is.

[0308] FIG. 27B shows a capacitor with a first zirconium oxide layer and an aluminum oxide layer thereon as a dielectric. A second zirconium oxide layer is stacked on top of the first zirconium oxide layer, forming a memory device 420. The conductor 242, oxide 243, oxide 230a, and oxide 230b of each memory cell A slit is provided between the conductor 242 and the bit line so as to overlap the slit. In this example, a conductor 424 is provided to function as a memory cell 4. Let's call 33 cell B.

[0309] Cell B has a higher dielectric constant than cell A, which reduces the area of ​​the capacitor. Therefore, the cell size of cell B can be reduced compared to cell A. The cell size is 25.53F. 2 is.

[0310] Cell A and cell B are the memory cells shown in FIGS. 21, 23A to 23C, and 24. The memory device 420, the memory device 420A, or the memory device 420B Supports resale.

[0311] FIG. 27C shows a capacitor with a first zirconium oxide layer and an aluminum oxide layer thereon as the dielectric. A second zirconium oxide layer is laminated on top of the first zirconium oxide layer, and the conductive layer of the memory device 420 is Each memory cell shares a body 242, an oxide 243, an oxide 230a, and an oxide 230b. The conductor 242 is partially overlapped with the conductor 242 and partially overlapped with the outer surface of the conductor 242. In this example, a conductor 424 is provided to function as a bit line. Recell 434 is referred to as cell C.

[0312] The spacing of the conductors 424 in cell C is higher than that above the oxide 230 compared to above the conductors 242. Therefore, the parasitic capacitance of the conductor 424 can be reduced. In addition, the conductor 242, the oxide 243, the oxide 230a, and The oxide 230b has no slits. In comparison, the cell size can be reduced. The cell size in cell C is 17.20F. 2 Yes do.

[0313] FIG. 27D shows an example in which the conductor 205 and the insulator 216 are not provided in the cell C. Such a memory cell 435 is called cell D.

[0314] By not providing the conductor 205 and the insulator 216 in the cell D, the memory device 4 Therefore, the memory device 20 can be made thinner. The layer 415 can be thinned, and a memory unit in which multiple memory device layers 415 are stacked The height of 470 can be reduced. Conductor 424 and conductor 205 are considered bit lines. When this is done, the bit lines can be shortened in the memory unit 470. This reduces the parasitic loading of the bit lines, further reducing the parasitic capacitance of conductor 424. The area of ​​the capacitor can be reduced. No slits are provided in the oxide 230b and the oxide 230a. The cell size can be reduced compared to cells B and C. Cell size in cell D is 15.12F 2 is.

[0315] Cells C and D are included in the memory device 420 shown in FIGS. 26A to 26C. It corresponds to a memory cell.

[0316] Here, for cells A to D and cell E which has undergone multi-value encoding in cell D, Density and bit cost C bIn addition, the estimates obtained were Compared with the bit density and bit cost estimates for currently available DRAMs .

[0317] The bit cost C in the semiconductor device according to one embodiment of the present invention b was estimated using Eq. .

[0318]

number

[0319] where n is the number of stacked memory device layers, P c The common part is mainly the element layer 411. Number of turns, P s The memory device layer 415 and the transistor layer 413 are The number of patternings, D d is the bit density of the DRAM, D 3d is the memory device layer 415 The bit density of one layer, P d indicates the number of patterning times for the DRAM. d In , including the increase due to scaling.

[0320] Table 1 shows the expected bit densities of commercially available DRAMs and semiconductors according to an embodiment of the present invention. The bit density of commercially available DRAM is estimated based on the process no. The thicknesses of the semiconductor device of one embodiment of the present invention are two types: 18 nm and 1X nm. The process node is set to 30 nm, and the number of stacked memory device layers in cells A to E is set to 5. Bit density estimates were performed for 1, 10, and 20 layers.

[0321] [Table 1]

[0322] Table 2 shows the bit cost of the semiconductor device according to one embodiment of the present invention based on the bit cost of commercially available DRAMs. The results of estimating the relative bit cost are shown below. A DRAM with a code of 1X nm was used. The thickness is set to 30 nm, and the number of stacked memory device layers in cells A to D is set to 5, 10, and , and 20 layers were estimated.

[0323] [Table 2]

[0324] Table 3 also shows bit density estimates for commercially available DRAMs that differ from those in Table 1. 1 shows an expected value of the bit density of the semiconductor device according to one embodiment of the present invention. The process node of commercially available DRAM is 1X nm. The process node of the semiconductor device is set to 30 nm, and in cell C, the memory device layer 41 5 and the number of stacked transistor layers 413 is 5 layers, 10 layers, and 10 layers and 4 bit / The estimation was made assuming that the cell was multi-valued. The relative bit cost of the semiconductor device according to one embodiment of the present invention was estimated from the bit cost of the AM. Similar to the bit density, the process node of the semiconductor device according to one embodiment of the present invention is 30 nm, and the number of stacked layers of the memory device layer 415 and the transistor layer 413 in the cell C The estimated values ​​are 5 layers, 10 layers, and 10 layers with 4 bits / cell multi-value coding. We carried out the survey.

[0325] [Table 3]

[0326] Although there is a limit to miniaturization of DRAM, the semiconductor device of one embodiment of the present invention is, in principle, By achieving the impossible multi-level processing, we can achieve high-resolution images that exceed DRAM without reaching the limits of miniaturization. It is possible to achieve high bit density, low cost, and extremely low power consumption. Approximately 1 / 60,000 of AM (DRAM: once every 64 ms, semiconductor device of one embodiment of the present invention: 1 Therefore, even if the memory capacity increases significantly, it is necessary to use memory that can save power. can be done.

[0327] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0328] (Embodiment 3) In this embodiment, the semiconductor device can be used for the OS transistor described in the above embodiment. CAC-OS (Cloud-Aligned Composite Silicon) is a metal oxide Oxide Semiconductor), and CAAC-OS(c-axis A The composition of the fused crystal oxide semiconductor and explain.

[0329] <Metal oxide composition> CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconducting properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. CAC-OS or CAC-metal oxide is given the function of In CAC-OS or CAC-metal oxide, By separating the functions, the functionality of both can be maximized.

[0330] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0331] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0332] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0333] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0334] <Metal oxide structure> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis oriented crystal-coated oxide semiconductor) igned crystalline oxide semiconductor), Crystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) semiconductor), pseudo-amorphous oxide semiconductor (a-like OS) amorphous-like oxide semiconductors and amorphous oxide semiconductors There is the body.

[0335] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. 28A. FIG. 28A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides.

[0336] As shown in Figure 28A, IGZO can be broadly divided into Amorphous and Crystal They are classified into Amorphous and Crystal. , completely amorphous. Also, Crystallin Among the e, CAAC (c-axis aligned crystalline), n nanocrystalline and Cloud-Aligned Also, some Crystals contain single crystals. Includes crystal, and poly crystal.

[0337] The structure within the bold frame in Figure 28A is a new crystalline phase This structure is located at the boundary between amorphous and crystalline. It is in the energetically unstable Amorphous and Crystal regions. This can be rephrased as a structure that is completely different from a line.

[0338] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using the ion image. XRD of IGZO (also called crystalline IGZO) with a crystal structure classified as line The spectra are shown in Figures 28B and 28C. Figure 28B shows the spectra of quartz glass, and Figure 28C shows the spectra of crystalline silica. 28C shows the XRD spectrum of crystalline IGZO. The composition is In:Ga:Zn=4:2:3 [atomic ratio]. The IGZO has a thickness of 500 nm.

[0339] As shown by the arrows in Figure 28B, the peaks in the XRD spectrum of quartz glass are almost symmetrical. On the other hand, as shown by the arrow in Figure 28C, crystalline IGZO has a peak in the XRD spectrum. The asymmetric peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, it is called Amorphous. It cannot be said to be ous.

[0340] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0341] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is not possible to confirm the presence of grain boundaries (also called grain boundaries). This is because the CAAC-OS has a crystalline structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is because the strain can be tolerated by changing the crystal structure. The crystal structure in which grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, where carriers are captured and This is likely to cause a decrease in the on-state current or a decrease in the field effect mobility of the transistor. The CAAC-OS, in which no clear grain boundaries are observed, is a suitable material for the semiconductor layer of a transistor. It is a crystalline oxide with a crystal structure. For example, In-Zn oxide and In-Ga-Zn oxide are preferable. is preferable because it can suppress the generation of grain boundaries more effectively than In oxide.

[0342] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0343] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries occurs. In addition, the crystallinity of oxide semiconductors can be affected by impurities and defects. Therefore, CAAC-OS is an oxidized material with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is designed to withstand the high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for an OS transistor, This allows for greater freedom.

[0344] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0345] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor. A-like OS has pores or low density areas. e-OS has lower crystallinity than nc-OS and CAAC-OS.

[0346] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductors in The compound may have two or more of the c-OS and CAAC-OS.

[0347] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0348] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0349] In addition, an oxide semiconductor with a low carrier concentration is preferably used for the transistor. When the carrier concentration of the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is In this specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic.

[0350] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Since the density is low, the trap level density may also be low.

[0351] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. This may be the case.

[0352] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, it is effective to reduce It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0353] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0354] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, they are oxidized. Defect levels are formed in semiconductors, which is why defects in silicon and carbon in oxide semiconductors The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0355] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable to use an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0356] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor becomes a semiconductor. Therefore, the transistor used in the oxide semiconductor tends to be normally on. In this case, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The concentration is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3Less than 1×10, more preferably 18 atoms / cm 3 Below, More preferably 5×10 17 atoms / cm 3 The following applies.

[0357] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Less than.

[0358] By using an oxide semiconductor with sufficiently reduced impurities for a channel formation region of a transistor, This makes it possible to impart stable electrical properties.

[0359] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0360] (Fourth embodiment) In this embodiment, the silicon substrate 50 in the semiconductor device 10 described in the first embodiment is A control logic circuit 61, a row driver circuit 62, a column driver circuit 63 and an output The circuit 64 will now be described.

[0361] FIG. 29 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device. The semiconductor device 10E includes a peripheral circuit 80 and a memory cell array 70. includes a control logic circuit 61, a row driving circuit 62, a column driving circuit 63, and an output circuit 64. Has.

[0362] The memory cell array 70 includes a plurality of memory cells 42. The column driver circuit 63 includes a column decoder 71 and a word line driver circuit 72. The circuit has a pre-charge circuit 81, a pre-charge circuit 82, an amplifier circuit 83, and a write circuit 84. The charge circuit 82 connects the global bit line GBL or the local bit line LBL. The amplifier circuit 83 has a function of precharging the global bit line GBL or It has the function of amplifying the data signal read from the local bit line LBL. The data signal is output as a digital data signal RDATA to the semiconductor device via an output circuit 64. The signal is output to the outside of the device 10E.

[0363] The semiconductor device 10E is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 80 A high power supply voltage (VDD) for the memory cell array 70 and a high power supply voltage (VIL) for the memory cell array 70 are supplied. do.

[0364] The semiconductor device 10E also includes control signals (CE, WE, RE), an address signal ADDR, A data signal WDATA is input from the outside. An address signal ADDR is input to the row decoder 7. 1 and the column decoder 81, and WDATA is input to the write circuit 84.

[0365] The control logic circuit 61 processes external input signals (CE, WE, RE). CE generates control signals for the row decoder 71 and the column decoder 81. WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 61 are not limited to these. Instead, other control signals may be input as needed. A control signal is input for the purpose of reading data from a specific memory cell address. They may be identified as good bits.

[0366] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0367] Generally, in semiconductor devices such as computers, various memory devices are used depending on the application. Figure 30 shows various storage devices by layer. The lower the storage device, the larger the storage capacity and the higher the recording speed. In Figure 30, from the top layer, the registers are connected to a processor such as a CPU. Embedded memory, SRAM (Static Random Access Memory) mory), DRAM (Dynamic Random Access Memory) , showing 3D NAND memory.

[0368] The memory embedded as a register in a CPU or other processing unit is used to temporarily store the results of calculations. Therefore, the frequency of access from the processor is high. The registers hold the setting information of the arithmetic processing unit. It also has functions.

[0369] SRAM is used, for example, for caches. Caches are used to store data stored in main memory. It has the function of duplicating and storing some of the information stored in the database. By replicating the data, you can increase the speed at which data can be accessed.

[0370] DRAM is used for main memory, for example. Main memory reads data from storage. DRAM has the function of storing programs and data. The recording density of DRAM is approximately 0.1~0.3Gbit / mm 2 is.

[0371] 3D NAND memory is used for storage, for example. It has the function of storing necessary data and various programs used by the processing unit. Therefore, storage devices require a large memory capacity and high recording density rather than high operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / m m 2 is.

[0372] A semiconductor device that functions as a memory device of one embodiment of the present invention has high operating speed and can be used for a long period of time. The semiconductor device according to one aspect of the present invention is a memory device that stores data in a memory area. Suitable as a semiconductor device located in the boundary area 901 including both the layer where the in-memory is located In addition, the semiconductor device of one embodiment of the present invention can be used for a main memory. As a semiconductor device located in a boundary area 902 including both a layer and a layer where a storage is located, It can be suitably used.

[0373] (Embodiment 5) This embodiment mode will be described with reference to an electronic component incorporating the semiconductor device or the like shown in the above embodiment mode. An example of an electronic device is shown.

[0374] <Electronic components> First, an example of an electronic component incorporating the semiconductor device 10 or the like will be shown with reference to FIGS. 31A and 31B. Explanations will be given.

[0375] FIG. 31A shows electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. 31A shows a perspective view of the electronic component 700. The electronic component 700 shown in FIG. 31A shows a semiconductor device 10 in which an element layer 20 is stacked on an electronic component 70. In order to show the inside of the electronic component 700, some parts are not shown in the figure. The land 712 is electrically connected to an electrode pad 713. The electrode pad 713 is electrically connected to the semiconductor device 10 by a wire 714. The sub-component 700 is mounted on, for example, a printed circuit board 702. The components are combined and electrically connected on the printed circuit board 702 to form the mounting board 7 04 is completed.

[0376] 31B shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) in package) or MCM (Multi Chip Module) The electronic component 730 is mounted on a package substrate 732 (printed circuit board) by an interposer. 731 is provided, and a semiconductor device 735 and a plurality of semiconductor devices are provided on the interposer 731. A station 10 is provided.

[0377] In the electronic component 730, the semiconductor device 10 is a high bandwidth memory (HBM). The semiconductor device 735 is used as a C Integrated circuits (semiconductor devices) such as PU, GPU, and FPGA can be used.

[0378] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be a silicon interposer, a resin interposer, or the like. An oil interposer or the like can be used.

[0379] The interposer 731 has a plurality of wirings and connects a plurality of integrated circuits with different terminal pitches. The wiring has a function of electrically connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 to the package substrate 7 32. The interposer is sometimes called a "rewiring substrate" or "intermediate substrate." 1, a through electrode is provided, and the integrated circuit and the package substrate 732 are electrically connected by the through electrode. In addition, in silicon interposers, TSV ( Through Silicon Via can also be used.

[0380] It is preferable to use a silicon interposer as the interposer 731. Since an interposer does not require active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring, which is difficult to do with resin interposers.

[0381] In HBM, many wires must be connected to achieve a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is recommended to use a silicon interposer for implementing HBM. It is preferable that:

[0382] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to differences in the expansion coefficient between the posers. The surface of the silicon interposer is highly flat, so the integrated circuit mounted on the silicon interposer and the silicon Connection failures between interposers are unlikely to occur. In particular, it is possible to mount multiple integrated circuits on an interposer. In a 2.5D package (2.5-dimensional mounting) where devices are arranged side by side, the silicon interposer It is preferable to use the

[0383] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. When providing the interposer 731, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the semiconductor device 10 and the semiconductor device 73 It is preferable to align the height of 5.

[0384] In order to mount the electronic component 730 on another substrate, electrodes 733 are attached to the bottom of the package substrate 732. FIG. 31B shows an example in which the electrode 733 is formed by a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, a BGA (Ball Array) Grid Array) mounting can be realized. Also, the electrode 733 is formed with a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, ,PGA (Pin Grid Array) implementation can be realized.

[0385] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) , or QFN (Quad Flat Non-leaded package) The implementation method can be used.

[0386] <Electronic equipment> Next, an example of an electronic device equipped with the above electronic component will be described with reference to FIG.

[0387] The robot 7100 is equipped with a light sensor, microphone, camera, speaker, and display. , various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, optical sensors, The electronic component 730 includes a processor, etc. For example, the electronic component 700 may be a sensor. It has the function of storing the acquired data.

[0388] The microphone has the function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The bot 7100 analyzes the audio signal input via the microphone and The audio signal can be emitted from the speaker. It is possible to communicate with the user using a microphone and speaker. is.

[0389] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has the function of moving using a movement mechanism. The robot 7100 uses a camera to capture the surroundings. It can capture images of the vehicle and analyze them to detect whether there are any obstacles when moving around. .

[0390] The flying object 7120 has a propeller, a camera, a battery, etc., and flies autonomously. The electronic component 730 has the function of controlling these peripheral devices.

[0391] For example, image data captured by a camera is stored in the electronic component 700. 0 can analyze image data and detect the presence or absence of obstacles when moving. In addition, the remaining battery capacity can be estimated from the change in the battery storage capacity by the electronic component 730. This can be done.

[0392] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. It has a camera, brushes, operation buttons, various sensors, etc. Although not shown, the cleaning robot The cleaning robot 7300 is equipped with tires, a suction nozzle, etc. It can detect dust and suck it up through a suction port on the bottom.

[0393] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. In addition, image analysis can be used to detect wires and other objects that may be tangled in the brushes. If it detects an object that is likely to move, it can stop the brush from rotating.

[0394] The car 7160 has an engine, tires, brakes, steering, a camera, etc. For example, electronic components 730 may provide navigation information, speed, engine status, gear selection status, etc. Optimize the driving conditions of the car 7160 based on data such as the frequency of braking and other factors. For example, image data captured by a camera is stored in the electronic component 700. .

[0395] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (television receiver). Imaging device), smartphone 7210, PC (personal computer) 7220, 723 0, game console 7240, game console 7260, etc.

[0396] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic component 730 can perform functions such as noise reduction, resolution up-conversion, etc. Image processing such as:

[0397] The smartphone 7210 is an example of a mobile information terminal. It includes a microphone, camera, speaker, various sensors, and a display. Electronic Components 73 0 controls these peripherals.

[0398] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The C7230 is equipped with a keyboard 7232 and a monitor device 7233, which can be connected wirelessly or by wire. The game console 7240 is an example of a portable game console. This is an example of a stationary game console. The game console 7260 can be equipped with a wireless or wired controller. The controller 7262 is connected to the electronic component 700 and / or the power supply. Sub-components 730 can also be incorporated.

[0399] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0400] (Notes regarding the present specification) The following additional notes will be given regarding the above-described embodiments and the respective configurations in the embodiments. .

[0401] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments or examples. In addition, one embodiment may include a plurality of configurations. When examples are shown, the configuration examples can be combined as appropriate.

[0402] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the form, and / or one or more other The contents (or a part of the contents) described in the embodiment of the present invention may be applied, combined, or You can make substitutions etc.

[0403] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0404] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. Another figure (or a part thereof) described in the embodiment, and / or one or more The figures (or a part thereof) described in a plurality of different embodiments may be combined. allows for the construction of even more diagrams.

[0405] In addition, in the block diagrams in this specification, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into functional blocks. It is difficult to separate the functions into separate parts, and there are cases where multiple functions are involved in one circuit, or where a circuit is involved in multiple circuits. Therefore, the blocks in the block diagram may be The present invention is not limited to the components described above, and may be rephrased appropriately depending on the situation.

[0406] In addition, in the drawings, the size, layer thickness, and area are arbitrarily scaled for convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the sake of convenience, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing deviations. This may include variations in signal, voltage, or current due to the

[0407] In addition, the positional relationships of the components shown in the drawings are relative. When describing components by reference, the terms "above" and "below" that indicate positional relationships are used for convenience. The positional relationship of the components is not limited to the contents described in this specification, and may vary depending on the situation. It can be rephrased appropriately depending on the situation.

[0408] In this specification and the like, when describing the connection relationship of a transistor, the term "source or drain" is used. "one of the two" (or first electrode, or first terminal), "the other of the two The term "second electrode" is used to refer to the source and drain of a transistor. This is because the drain varies depending on the structure or operating conditions of the transistor. The names of the source and drain of a transistor are the source (drain) terminal and the source (drain) terminal. In) electrodes, etc., can be rephrased appropriately depending on the situation.

[0409] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0410] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. The potential difference from the reference potential. For example, the reference potential is the ground voltage (earth If we use the term "voltage", we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0411] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. The term "electrode," "conductive layer," "conductor," "impurity region," etc. may also be used. Lines and the like can be called nodes.

[0412] In this specification, "A and B are connected" means that A and B are electrically connected. Here, A and B are electrically connected to each other. Objects (switches, transistor elements, diodes, etc.), or the elements and A connection that allows transmission of electrical signals between A and B when there is a circuit (including wiring, etc.) If A and B are electrically connected, it is considered that A and B are directly connected. Here, A and B being directly connected means that they are connected via the above object. Instead, electrical signals can be transmitted between A and B via wiring (or electrodes) etc. In other words, a direct connection is a connection that can be seen as the same circuit diagram when expressed as an equivalent circuit. This refers to the connection that can be made.

[0413] In this specification, a switch refers to a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It refers to a device that has the function of controlling whether or not current flows by entering a state where it is in a non-operating state. A switch is a device that has the function of selecting and switching a path through which a current flows.

[0414] In this specification and the like, the channel length is, for example, the length of a semiconductor the body (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the region where they overlap or where the channel is formed. It means separation.

[0415] In this specification, the channel width is, for example, the width of a semiconductor (or a transistor) when it is in an on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows in the semiconductor when the gate electrode is in the non-transistor state), or the channel The length of the portion where the source and drain face each other in the region where the capacitor is formed. .

[0416] In this specification, the terms "film" and "layer" are used in some cases or in other situations. For example, the term "conductive layer" can be used interchangeably with " It may be possible to change the term to "conductive film." In some cases, the term "insulating layer" can be changed to the term "insulating layer." [Explanation of symbols]

[0417] :BL2: Wiring, SL2: Wiring, SW0: Signal, SW1: Signal, SW2: Signal, T11: Time, T12:Time, T13:Time, T14:Time, T15:Time, T16:Time, T1 7: Time, T18: Time, T19: Time, 10: Semiconductor device, 10A: Semiconductor device, 10 B: semiconductor device, 10C: semiconductor device, 10E: semiconductor device, 20: element layer, 20_M: Element layer, 20_1: element layer, 30: transistor layer, 30A: transistor layer, 30B: Transistor layer, 31: transistor, 32: transistor, 33: transistor, 34 : transistor, 35: correction circuit, 36: circuit, 36_pre: circuit, 40: transistor 41_k: transistor layer, 41_1: transistor layer, 41_2: transistor Layer 42: Memory cell 43: Transistor 44: Capacitor 49: Transistor layer , 49_k: transistor layer, 49_1: transistor layer, 50: silicon substrate, 51: Control circuit, 52: switch circuit, 52_1: transistor, 52_2: transistor, 5 3: Precharge circuit, 53_1: Transistor, 53_3: Transistor, 54: Pre Charge circuit, 54_1: Transistor, 54_3: Transistor, 55: Sense amplifier , 55_1: Transistor, 55_2: Transistor, 55_3: Transistor, 55_ 4: Transistor, 61: Control logic circuit, 62: Row drive circuit, 63: Column drive circuit, 64: Output circuit, 70: Memory cell array, 71: Row decoder, 72: Word line driver circuit, 80: Peripheral circuit, 81: Column decoder, 82: Precharge circuit, 83 : Amplification circuit, 84: Circuit, 90: Transistor layer, 91: Memory cell, 92: Trans istor, 93: Transistor, 94: Capacitor, 97: Transistor, 98: Transistor , 99: Transistor, 100: Memory device, 110: Period, 111: Operation, 112: Operation , 113: Operation, 114: Operation, 115: Operation, 120: Period, 120_1: Period, 12 0_2: Period, 121: Operation, 121A: Operation, 122: Operation, 123: Operation, 123A : Operation, 124: Operation, 125: Operation, 125A: Operation, 130: Period, 131: Operation, 132: Operation, 133: Operation, 134: Operation, 135: Operation, 140: Period, 141: Mov ement, 142: Operation, 144: Capacitor, 200: Transistor, 200M: Trans istor, 200T: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 211: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 230c: Oxi de, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241 a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor , 243: Oxide, 243a: Oxide, 243b: Oxide, 246: Conductor, 246a: Conductor, 246b: Conductor, 250: Insulator, 260: Conductor, 260a: Conductor, 26 0b: conductor, 272: insulator, 273: insulator, 274: insulator, 275: insulator, 2 76: Conductor, 277: Insulator, 278: Conductor, 279: Insulator, 280: Insulator, 2 82: Insulator, 283: Insulator, 284: Insulator, 287: Insulator, 290: Conductor, 2 92: Capacitance, 292A: Capacitance, 292B: Capacitance, 294: Conductor, 295: Insulator, 29 6: insulator, 297: conductor, 298: insulator, 299: conductor, 300: transistor 311: semiconductor substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance Region, 315: insulator, 316: conductor, 411: element layer, 413: transistor layer, 4 13_m: transistor layer, 413_1: transistor layer, 415: memory device layer, 415_n: memory device layer, 415_p: memory device layer, 415_p-1: memory memory device layer, 415_1: memory device layer, 415_3: memory device layer, 415 _4: Memory device layer, 420: Memory device, 420A: Memory device, 420 B: memory device, 422: area, 424: conductor, 426: conductor, 428: conductor , 430: conductor, 432: memory cell, 433: memory cell, 434: memory cell, 4 35: memory cell, 470: memory unit, 470_m: memory unit, 470_1 : memory unit, 700: electronic components, 702: printed circuit board, 704: mounting board, 71 1: mold, 712: land, 713: electrode pad, 714: wire, 730: electronic part Product, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor Device, 820: Peripheral circuit, 901: Boundary area, 902: Boundary area, 7100: Robot, 7120: Flying object, 7140: Cleaning robot, 7160: Automobile, 7200: TV device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard, 7233: Monitor device, 7240: Game machine, 7260: Game machine, 7262: Controller 7300: Cleaning robot

Claims

1. a first transistor layer; a second transistor layer having a region located on the first transistor layer, the first transistor layer includes memory cells; the second transistor layer includes a first transistor having a gate electrically connected to a local bit line and a correction circuit electrically connected to the first transistor; the memory cell has a second transistor; the second transistor is electrically connected to the local bit line; the second transistor has an oxide semiconductor in a channel formation region; the correction circuit is electrically connected to a global bit line; The correction circuit has a function of holding a voltage corresponding to a threshold voltage of the first transistor at a gate of the first transistor.

2. a first transistor layer; a second transistor layer having a region located on the first transistor layer, the first transistor layer includes memory cells; the second transistor layer includes a first transistor having a gate electrically connected to a local bit line and a correction circuit electrically connected to the first transistor; the memory cell has a second transistor; the second transistor is electrically connected to the local bit line; the second transistor has an oxide semiconductor in a channel formation region; the oxide semiconductor is indium oxide, the correction circuit is electrically connected to a global bit line; The correction circuit has a function of holding a voltage corresponding to a threshold voltage of the first transistor at a gate of the first transistor.

3. In claim 1 or claim 2, the correction circuit includes third to fifth transistors; the third transistor has a function of controlling conduction between a gate of the first transistor and one of a source and a drain of the first transistor; the fourth transistor has a function of controlling conduction between the other of the source and the drain of the first transistor and a wiring to which a potential for causing a current to flow through the first transistor is applied; The fifth transistor has a function of controlling a conduction state between one of a source or a drain of the first transistor and the global bit line.

Images