Method for manufacturing packaging substrate

Abstract

To provide a method of manufacturing a packaging substrate which easily removes a resist pattern film in a patterning process of an insulating layer and suppresses damage to the insulating layer.SOLUTION: The method includes a preparation step of preparing a base substrate 100 including a core substrate 10 and an insulating layer 20 disposed on the core substrate 10, an etching step of selectively etching the insulating layer 20 with an etching mask 30, and a manufacturing step of manufacturing a packaging substrate from the base substrate 100 subjected to the etching step. The etching mask 30 is disposed on the insulating layer 20 and includes a metal pattern film 31 and a resist pattern film 32 disposed on the metal pattern film 31.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The embodiment relates to a method for manufacturing a packaging substrate. [Background technology]

[0002] In the production of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers so that they can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below microns, more than 10 million cells, high-speed operation, and high heat dissipation, but the technology to perfectly package this has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0004] Recently, research into applying ceramic materials to high-end packaging substrates has been progressing. By forming through-holes in ceramic substrates and filling them with conductive materials, the wiring length between the device and the motherboard can be shortened, resulting in excellent electrical characteristics. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Patent Publication No. 10-2022-0135842 [Patent Document 2] Korean Patent Publication No. 10-2014-0085023 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the embodiment is to provide a method for manufacturing a packaging substrate that can easily remove a resist pattern film and prevent damage to the insulating layer during the patterning process of the insulating layer. [Means for solving the problem]

[0007] A method for manufacturing a packaging substrate according to one embodiment of the present specification includes a preparation step of preparing a base substrate including a core substrate and an insulating layer disposed on the core substrate, an etching step of selectively etching the insulating layer using an etching mask, and a manufacturing step of manufacturing a packaging substrate from the base substrate after the etching step.

[0008] The etching mask is disposed on the insulating layer.

[0009] The etching mask includes a metal pattern film and a resist pattern film disposed on the metal pattern film.

[0010] The metal pattern film may include a first metal pattern layer and a second metal pattern layer disposed on the first metal pattern layer.

[0011] The first metal pattern layer may include any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof.

[0012] The second metal pattern layer may include copper.

[0013] The first metal pattern layer may be disposed on an upper surface of the insulating layer.

[0014] The metal pattern film may be disposed in contact with an upper surface of the insulating layer.

[0015] The ratio of the thickness of the resist pattern film to the thickness of the metal pattern film may be 0.15 or less.

[0016] The ratio of the thickness of the second metal pattern film to the thickness of the first metal pattern film may be 0.5-10.

[0017] The thickness of the metal pattern film may be 100 μm or more and 250 μm or less.

[0018] The etching step may include an etching mask forming process of forming the etching mask on the insulating layer, and a plasma etching process of selectively plasma-etching the insulating layer using the etching mask.

[0019] The resist pattern film can be removed during the plasma etching process.

[0020] After the plasma etching process, a cleaning process of ultrasonically cleaning the base substrate may be further included.

[0021] The vibration frequency during the cleaning process may be 20 kHz to 200 kHz.

[0022] After the etching step, the insulating layer may include through holes with a diameter of 3 μm to 50 μm. [Effects of the Invention]

[0023] The method for manufacturing a packaging substrate according to the embodiment can easily remove the resist pattern film during the patterning of the insulating layer and can prevent damage to the insulating layer. [Brief explanation of the drawings]

[0024] [Figure 1] 10A and 10B are conceptual diagrams illustrating a base substrate in a preparation step according to an embodiment; [Figure 2A] 10A and 10B are conceptual diagrams illustrating an etching step according to an embodiment; [Figure 2B] 10A and 10B are conceptual diagrams illustrating an etching step according to an embodiment; [Figure 2C] 10A and 10B are conceptual diagrams illustrating an etching step according to an embodiment; [Figure 3] 1 is a conceptual diagram illustrating a packaging substrate manufactured through manufacturing steps of an embodiment; BEST MODE FOR CARRYING OUT THE INVENTION

[0025] The present invention will now be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0026] Throughout this specification, the term "combinations thereof" contained in a Markush form phrase means a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, and means including one or more selected from the group of elements.

[0027] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish between identical terms, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0028] In this specification, the term "-" may mean that the compound includes a compound corresponding to "-" or a derivative of "-".

[0029] In this specification, the term "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0030] In this specification, the expression "B is linked to A" means that A and B are directly linked or that A and B are linked via another component therebetween, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0031] In this specification, unless otherwise specified, the singular expression is to be construed as including the singular or plural as the context requires.

[0032] In this specification, the shape, relative size, angle, etc. of each component in the drawings are illustrative and may be exaggerated for the purpose of explanation, and the rights should not be interpreted as being limited to the drawings.

[0033] In this specification, "A and B are adjacent" means that A and B are adjacent to each other, or A and B are not adjacent to each other but are located close to each other. In this specification, the expression "A and B are adjacent to each other" is not interpreted as being limited to A and B being adjacent to each other unless otherwise specified.

[0034] In this specification, unless otherwise specified, a fine line means a line having a width of 5 μm or less, and illustratively means a line having a width of 1 to 4 μm or less.

[0035] After forming a resist film with a developed pattern on an insulating layer, the insulating layer can be selectively etched to develop the pattern in the insulating layer. During the process of continuously selectively etching the insulating layer, the ambient temperature may rise above a certain level, which may cause the resist pattern film to deteriorate and burn onto the insulating layer. The deteriorated resist pattern film may cause damage to the insulating layer during the stripping process, and if the resist pattern film is severely deteriorated, stripping itself may be impossible.

[0036] One could consider removing the resist pattern film by ashing, but this method may damage the insulating pattern layer.

[0037] The inventors of the embodiment have experimentally confirmed that by using means such as an etching mask including a metal pattern film and a resist pattern film, the resist pattern film can be easily removed during the patterning process of the insulating layer, and damage to the insulating layer can be more effectively suppressed, and have completed the embodiment.

[0038] An example will be described below.

[0039] The method for manufacturing a packaging substrate of an embodiment includes a preparation step of preparing a base substrate including a core substrate and an insulating layer disposed on the core substrate, an etching step of selectively etching the insulating layer using an etching mask, and a manufacturing step of manufacturing a packaging substrate from the base substrate after the etching step.

[0040] 1 is a conceptual diagram illustrating a preparation step of an embodiment, and a method for manufacturing a packaging substrate according to the embodiment will be described with reference to FIG.

[0041] Preparation Steps In the preparation step, a base substrate 100 including a core substrate 10 and an insulating layer 20 formed on the core substrate 10 can be prepared.

[0042] The core substrate 10 can have the shape of a substrate, and is not limited as long as it is a substrate that can be used as an electronic component.

[0043] The material of the core substrate 10 may be an organic substance, glass, alumina, aluminum nitride, silicon carbide, silicon nitride, or the like.

[0044] The core substrate 10 may be a glass core. For example, the core substrate 10 may be made of an alkali borosilicate plate glass, an alkali-free borosilicate plate glass, an alkali-free alkaline earth borosilicate plate glass, or the like. The core substrate 10 may be a glass substrate for electronic devices, and may be, for example, a glass substrate manufactured by Schott, AGC, Corning, or the like, but is not limited thereto.

[0045] The core substrate 10 may include an upper surface and a side surface connected to the upper surface and formed in a thickness direction of the core substrate 10. The surface of the core substrate 10 may include a lower surface opposite to the upper surface.

[0046] The side surface formed in the thickness direction of the core substrate 10 is interpreted to mean not only that the side surface is perpendicular to the top surface of the core substrate 10, but also that at least a portion of the side surface forms an angle (inclination angle) other than 90° with the top surface.

[0047] The side surface may be flat or curved.

[0048] The core substrate 10 may include a cavity (not shown) that is a space formed by recessing a portion of the core substrate 10 inward.

[0049] The cavity may be formed by recessing a portion of the upper and / or lower surface of core substrate 10 in the thickness direction of core substrate 10, or may penetrate core substrate 10 in the thickness direction.

[0050] The cavity can provide a space in which an element is mounted. The element mounted in the cavity can be electrically connected to other components in the packaging substrate. The element can be a semiconductor element such as a CPU, GPU, or memory chip, as well as a capacitor element, a transistor element, an impedance element, or other module. In other words, any element that can be mounted in a semiconductor device can be used as the element without any restrictions.

[0051] The core substrate 10 may include a through via portion (not shown) that penetrates the core substrate 10 in the thickness direction.

[0052] The through via portion includes a via space where an electrically conductive layer (not shown) is disposed, and a via inner diameter surface surrounding the via space. The via inner diameter surface is the surface of the core substrate 10 formed inside the through via portion.

[0053] The via spaces may have a substantially uniform inner diameter in the thickness direction of the core substrate 10. The via spaces may have an inner diameter that varies in the thickness direction of the core substrate 10.

[0054] In the preparation step, when a glass core is used as the core substrate 10, the glass core can be etched to provide a through-via portion. Specifically, defects can be formed at predetermined positions within the surface of the glass core. Methods for forming the defects include mechanical etching and laser irradiation.

[0055] The defected region may be subjected to physical or chemical etching to form a through-via portion. When chemical etching is used, wet etching using an etching solution may be performed. The etching solution is not limited as long as it is generally applicable to etching glass substrates. For example, the etching solution may be a sulfuric acid solution, a nitric acid solution, a hydrofluoric acid solution, or the like.

[0056] During the etching process, the surface of the glass core remaining except for the region where the defect is formed may be masked, or etching may be performed without masking.

[0057] A core substrate 10 having a through via portion formed therein can be provided by forming a defect at one point on the upper surface of the glass core, forming a defect at another point on the lower surface of the glass core opposite the one point, and then performing etching.

[0058] The base substrate 100 may include an electrically conductive layer (not shown) formed in the via space. The electrically conductive layer may be formed to fill at least a portion of the via space, or may be formed as a thin film on the inner diameter surface of the via. When the electrically conductive layer is formed as a thin film on the inner diameter surface of the via, the remaining space in the via space other than the space occupied by the electrically conductive layer may be filled with an insulating layer 20.

[0059] The electrically conductive layer disposed in the via space can transmit an electrical signal in the thickness direction of the core substrate 10, and can electrically connect the device, the main board, the rewiring layer, etc. to each other.

[0060] The base substrate 100 may further include an insulating layer 20 formed on the core substrate 10. At least a portion of the insulating layer 20 may be formed in contact with the upper surface of the core substrate 10. The base substrate 100 may further include an electrically conductive layer (not shown). At least a portion of the insulating layer 20 may be formed on the electrically conductive layer. At least a portion of the insulating layer 20 may be formed in contact with the upper surface of the electrically conductive layer. The insulating layer 20 may be disposed intermixed with the electrically conductive layer. The insulating layer 20 may be disposed to surround the electrically conductive layer.

[0061] The insulating layer 20 is not limited as long as it can be used as an insulating layer for semiconductor devices and packaging substrates. For example, the insulating layer 20 may include an epoxy resin containing a filler. For example, the insulating layer 20 may be formed using a build-up layer material such as Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Inc., or an undercoat material, but is not limited thereto.

[0062] The electrically conductive layer corresponds to a conductor that transmits an electrical signal. The electrically conductive layer may include an electrically conductive material. For example, the electrically conductive layer may include at least one of copper, nickel, aluminum, gold, and silver. Copper may be used as the material of the electrically conductive layer.

[0063] In the preparation step, a base substrate 100 can be prepared in which an insulating layer 20 is preliminarily formed on a core substrate 10. In the preparation step, a base substrate 100 can be prepared by forming an insulating layer 20 on a core substrate 10.

[0064] The insulating layer 20 can be formed by laminating a film-like insulating resin on the core substrate 10. For example, the film-like insulating layer 20 can be vacuum-laminated on the core substrate 10 to form the base substrate 100. In such a case, the surface of the electrically conductive layer disposed below the insulating layer 20 can be surrounded without voids.

[0065] Etching step 2A, 2B, and 2C are conceptual diagrams illustrating the etching step of an embodiment, respectively. A method for manufacturing a packaging substrate of an embodiment will be described with reference to FIGS. 2A, 2B, and 2C.

[0066] An etching mask 30 may be disposed on the insulating layer 20. In an etching step, the insulating layer 20 may be selectively etched with the etching mask 30. In an etching step, the insulating layer 20 may be selectively plasma etched with the etching mask 30.

[0067] 1. Etching mask formation process The etching step may include an etching mask formation process for forming an etching mask 30 on the insulating layer 20 .

[0068] The etching mask 30 can be applied to develop a pattern of a pre-designed shape in the insulating layer 20 during the etching step. The etching mask 30 can include a pattern of the same shape as the pattern to be developed in the insulating layer 20 during the etching step. The etching mask 30 can include a hole pattern of the same shape as the hole pattern to be formed in the insulating layer 20 during the etching step.

[0069] The etching mask 30 of the present embodiment may include a metal pattern film 31 and a resist pattern film 32 disposed on the metal pattern film 31. The metal pattern film 31 may be disposed between the resist pattern film 32 and a non-etched region (not shown) in the insulating layer 20. In this case, even if the entire resist pattern film 32 is removed in the etching step, the upper surface of the insulating layer 20 is prevented from being exposed, and the metal pattern film 31 can protect the non-etched region in the insulating layer 20 from the etchant.

[0070] The non-etching region is a region in the insulating layer 20 that is not to be etched, and is a region where the upper surface of the insulating layer 20 is not exposed by the etching mask 30. The etching region is a region in the insulating layer 20 that is to be etched, and is a region where the upper surface of the insulating layer 20 is exposed.

[0071] The metal pattern film 31 may be disposed on and in contact with the insulating layer 20. The metal pattern film 31 may have a two-layer structure. In an embodiment, a metal pattern layer that can exhibit a relatively higher adhesive strength to the insulating layer 20 may be disposed on the upper surface of the insulating layer 20. This may help to ensure that the etching mask 30 is strongly attached to the insulating layer 20, and may more stably protect the non-etched areas in the insulating layer.

[0072] The metal pattern film 31 may include a first metal pattern layer (not shown) and a second metal pattern layer (not shown) disposed on the first metal pattern layer.

[0073] The first metal pattern layer can be disposed on and in contact with the insulating layer 20. The second metal pattern layer can be disposed on the top surface of the first metal pattern layer. The second metal pattern layer can be fixed onto the non-etched areas in the insulating layer 20 via the first metal pattern layer.

[0074] The first metal pattern layer may contain any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof. The first metal pattern layer may contain any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof at 50 atomic % or more. The first metal pattern layer may contain any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof at 60 atomic % or more. The first metal pattern layer may contain any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof at 70 atomic % or more. The first metal pattern layer may contain any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof at 80 atomic % or more. The first metal pattern layer may contain 90 atomic % or more of any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof.The first metal pattern layer may contain 100 atomic % or less of any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof.

[0075] The first metal pattern layer may contain titanium. The first metal pattern layer may contain titanium at 50 atomic % or more. The first metal pattern layer may contain titanium at 60 atomic % or more. The first metal pattern layer may contain titanium at 70 atomic % or more. The first metal pattern layer may contain titanium at 80 atomic % or more. The first metal pattern layer may contain titanium at 90 atomic % or more. The first metal pattern layer may contain titanium at 100 atomic % or less.

[0076] In this case, it may be helpful to allow the metal pattern film 31 to adhere more stably onto the insulating layer 20 during the etching step.

[0077] The thickness of the first metal pattern layer may be 20 μm or more. The thickness of the first metal pattern layer may be 30 μm or more. The thickness of the first metal pattern layer may be 35 μm or more. The thickness of the first metal pattern layer may be 100 μm or less. The thickness of the first metal pattern layer may be 80 μm or less. The thickness of the first metal pattern layer may be 70 μm or less. The thickness of the first metal pattern layer may be 65 μm or less. In such cases, the first metal pattern layer may help ensure that the etching mask 30 adheres to the insulating layer 20 with uniform force throughout.

[0078] The second metal pattern layer may contain copper. The second metal pattern layer may contain copper at 50 atomic % or more. The second metal pattern layer may contain copper at 60 atomic % or more. The second metal pattern layer may contain copper at 70 atomic % or more. The second metal pattern layer may contain copper at 100 atomic % or less. In such a case, even if the resist pattern film 32 is completely removed in the etching step, the non-etched areas in the insulating layer 20 can be stably protected from the etchant.

[0079] The thickness of the second metal pattern layer may be 50 μm or more. The thickness of the second metal pattern layer may be 60 μm or more. The thickness of the second metal pattern layer may be 70 μm or more. The thickness of the second metal pattern layer may be 80 μm or more. The thickness of the second metal pattern layer may be 200 μm or less. The thickness of the second metal pattern layer may be 180 μm or less. The thickness of the second metal pattern layer may be 160 μm or less. In such cases, it may be useful to maintain the metal pattern film 31 stably until the plasma etching is completed and to enable the metal pattern film 31 to be removed relatively quickly by chemical etching.

[0080] The thickness of the metal pattern film 31 may be 100 μm or more. The thickness of the metal pattern film 31 may be 110 μm or more. The thickness of the metal pattern film 31 may be 120 μm or more. The thickness of the metal pattern film 31 may be 130 μm or more. The thickness of the metal pattern film 31 may be 250 μm or less. The thickness of the metal pattern film 31 may be 230 μm or less. The thickness of the metal pattern film 31 may be 220 μm or less. The thickness of the metal pattern film 31 may be 200 μm or less. In such cases, it can help prevent damage to the insulating layer 20 during the process of etching the insulating layer 20 and the process of removing the metal pattern film 31.

[0081] The ratio of the thickness of the second metal pattern film to the thickness of the first metal pattern film may be 0.5 to 10. The thickness ratio may be 0.7 or more. The thickness ratio may be 1 or more. The thickness ratio may be 1.3 or more. The thickness ratio may be 1.6 or more. The thickness ratio may be 8 or less. The thickness ratio may be 6 or less. The thickness ratio may be 4 or less. In such cases, stable adhesion to the surface of the insulating layer can be imparted to the metal pattern film 31, and the patterned insulating layer can be effectively protected from the etchant.

[0082] In the etching step, the resist pattern film 32 is etched together with the insulating layer 20 during patterning, and can be substantially completely removed when the plasma etching is completed. This prevents a portion of the resist pattern film 32 from remaining on the insulating layer 20, thereby preventing defects from being generated in the redistribution layer including the insulating layer 20. Furthermore, since there is no need to introduce a separate process for removing the remaining resist pattern film 32, the process can be made more efficient.

[0083] The resist applied to the resist pattern film 32 is not limited as long as it is one commonly used in the field of packaging substrates. The resist may be an amine-based resist. The resist may be a positive resist. The resist may be a negative resist.

[0084] The resist pattern film 32 can be disposed on the metal pattern film 31. The resist pattern film 32 can be disposed on and in contact with the metal pattern film 31. The resist pattern film 32 can be disposed on a second metal pattern film. The resist pattern film 32 can be disposed on and in contact with the second metal pattern film.

[0085] The ratio of the thickness of the resist pattern film 32 to the thickness of the metal pattern film 31 can be controlled within a predetermined range depending on the embodiment. This allows the resist pattern film 32 to be substantially removed when the plasma etching process is completed, thereby improving process efficiency. Additionally, the resist pattern film 32 can have a thickness sufficient to protect the patterned insulating layer 20.

[0086] The ratio of the thickness of the resist pattern film 32 to the thickness of the metal pattern film 31 may be 0.15 or less. The thickness ratio may be 0.13 or less. The thickness ratio may be 0.08 or more. In such cases, there is no need to introduce a separate process for stripping or ashing the resist pattern film 32, thereby improving process efficiency.

[0087] The thickness of the resist pattern film 32 may be 11 μm or more. The thickness may be 13 μm or more. The thickness may be 15 μm or more. The thickness may be 24 μm or less. The thickness may be 22 μm or less. In such cases, the resist pattern film 32 can stably protect the insulating layer being patterned from the etchant in the plasma etching process.

[0088] The etching mask 30 can be manufactured by the following steps.

[0089] A metal film (not shown) can be formed on the insulating layer 20. Specifically, a first metal film (not shown) can be formed on the insulating layer 20 by sputtering, and a second metal film (not shown) can be formed on the first metal film.

[0090] The metal film may be formed in contact with the upper surface of the insulating layer 20. The first metal film may be formed in contact with the upper surface of the insulating layer 20.

[0091] The first metal film may be formed of the same material as the first metal pattern film and may be formed to substantially the same thickness as the first metal pattern film.

[0092] The second metal film may be formed of the same material as the second metal pattern film and may be formed to substantially the same thickness as the second metal pattern film.

[0093] The composition and thickness of the first metal film and the composition and thickness of the second metal film are omitted here since they are the same as those described above.

[0094] A resist film (not shown) may be formed on the metal film. To improve the adhesion of the resist film to the surface of the metal film, an adhesive may be applied to the entire metal film. The adhesive is not limited as long as it is commonly used in the field of resist films. For example, hexamethyldisilazane may be applied as the adhesive.

[0095] The resist film can be formed by applying a resist composition onto the metal film and curing the composition. The description of the resist composition is omitted here as it overlaps with the above description.

[0096] The resist composition may be applied so as to cover the entire insulating layer 20. The method for applying and curing the resist composition is not limited as long as it is a method commonly used in the field of packaging substrates. The thickness of the resist film formed by applying and curing the resist composition may be substantially the same as the thickness of the resist pattern film 32.

[0097] The resist film can be patterned to form a resist pattern film 32. The resist film can be selectively irradiated with light so as to correspond to the shape of the pattern to be developed in the insulating layer 20. The light source used to irradiate the resist film may be an electron beam. After the light irradiation, the resist film can be developed with a developer to form the resist pattern film 32.

[0098] After the resist pattern film 32 is formed on the metal film, the metal film can be patterned through the resist pattern film 32 to form the metal pattern film 31. The metal pattern film 31 may be formed by dry etching or wet etching. To prevent excessive deterioration of the resist pattern film 32 during the patterning of the metal film, it is preferable to pattern the metal film by wet etching.

[0099] The etching mask 30 may include a through-hole pattern having a diameter of 3 μm to 50 μm. The diameter may be 5 μm or more. The diameter may be 7 μm or more. The diameter may be 40 μm or less. The diameter may be 30 μm or less. The diameter may be 20 μm or less. The diameter may be 15 μm or less. In this case, a fine wiring layer with a high degree of integration can be precisely formed on the insulating layer 20.

[0100] 2. Plasma etching process The etching step may include an etching mask forming process and a plasma etching process for selectively plasma etching the insulating layer 20 using the etching mask 30 .

[0101] After placing the base substrate 100 with the etching mask 30 formed thereon in an etching chamber, etching gas is introduced into the chamber and plasma power is applied to selectively etch the region of the insulating layer 20 where the upper surface is exposed, i.e., the etching region.

[0102] During the plasma etching process, the resist pattern film 32 disposed on the insulating layer 20 may also be etched by the etchant. When the plasma etching process is completed, the entire resist pattern film 32 may be substantially removed. In this case, there is no need to introduce a separate process for removing the resist pattern film 32, and the possibility of damage to the patterned insulating layer 20 during the process of removing the resist pattern film 32 may be reduced.

[0103] Even if the resist pattern film 32 is completely removed during the plasma etching process, the metal pattern film 31 can be maintained. The metal pattern film 31 can contribute to the formation of an elaborate redistribution layer by preventing the etchant from etching the non-etched areas in the insulating layer 20.

[0104] The plasma etching process may be performed in an atmosphere containing an etching gas, which may include a first etching gas and a second etching gas.

[0105] The first etching gas is a fluorine-based gas. The first etching gas may be any one selected from the group consisting of a carbon fluoride, a nitrogen fluoride, a sulfur fluoride, and a combination thereof. The carbon fluoride may be any one selected from the group consisting of CF4, CHF3, CH2F2, CH3F, and a combination thereof. The nitrogen fluoride may be NF3. The sulfur fluoride may be SF6.

[0106] The first etching gas may include nitrogen fluoride.The first etching gas may be nitrogen fluoride.

[0107] The second etching gas may be oxygen gas.

[0108] In the embodiment, the first etching gas and the second etching gas are both introduced as atmospheric gases during the plasma etching process, thereby further improving the etching rate of the insulating layer 20 and the resist pattern film 32.

[0109] The plasma power applied to the plasma etching process may be 1.2 kW or more and 3 kW or less. The plasma power may be 1.5 kW or more. The plasma power may be 2.7 kW or less. The plasma power may be 2.5 kW or less. In this case, an etching rate above a certain level for the insulating layer 20 and the resist pattern film 32 can be ensured, and excessive damage to the insulating layer 20 during patterning by plasma etching can be prevented.

[0110] The maximum value of the ambient temperature in the etching step may be 120° C. or more. The maximum value of the ambient temperature in the plasma etching process may be 120° C. or more.

[0111] If the resist pattern film 32 deteriorates due to the ambient temperature in the chamber, it may be difficult to remove the resist pattern film 32 by a stripping process, and the patterned insulating layer 20 may be damaged during the process of removing the pattern film.

[0112] In consideration of the convenience of the stripping process, if a separate cooling means or stabilization process is introduced to prevent the ambient temperature from rising above a certain level during the plasma etching process, production costs and time may increase.

[0113] In the embodiment, since the resist pattern film 32 can be substantially removed by the etchant when the plasma etching process is completed, the embodiment can effectively reduce the time required to manufacture the packaging substrate by continuously patterning the insulating layer 20 without considering deterioration of the resist pattern film 32 due to the ambient temperature.

[0114] In the etching step, the maximum value of the ambient temperature may be 120° C. or more, 140° C. or more, or 200° C. or less.

[0115] In the plasma etching process, the maximum value of the ambient temperature may be 120° C. or more, 140° C. or more, or 200° C. or less.

[0116] In this case, the time required to complete the patterning of the insulating layer 20 can be effectively reduced.

[0117] 3. Cleaning process The etching step may further include a cleaning process of ultrasonically cleaning the base substrate 100 after the plasma etching process.

[0118] During the process of plasma etching the insulating layer 20, particles may be generated due to the insulating layer 20 or the resist pattern film 32. The particles may remain on or be adsorbed onto the surface of the insulating layer 20 on which the pattern is formed, and may cause a decrease in the electrical reliability of the resulting packaging substrate.

[0119] In the cleaning process, the base substrate 100 is immersed in a water bath and ultrasonic vibrations are applied to the water bath to generate a cavitation phenomenon, which allows particles adsorbed on the surface of the insulating layer 20, which has a complex and fine structure, to be easily removed without excessively damaging the base substrate 100.

[0120] In the cleaning process, the vibration frequency may be 20 kHz to 200 kHz. The vibration frequency may be 30 kHz or more. The vibration frequency may be 50 kHz or more. The vibration frequency may be 70 kHz or more. The vibration frequency may be 150 kHz or less. In such cases, even if the insulating layer 20 has a fine and complex pattern structure, particles can be effectively removed without inducing significant deformation of the insulating layer 20.

[0121] 4.Metal pattern film removal process The etching step may include a metal pattern film removal process for removing the metal pattern film 31 after completing the plasma etching process. The metal pattern film 31 may be removed by wet etching to prevent damage and deformation of the patterned insulating layer 20. The wet etching of the metal pattern film 31 is not limited as long as it is a method commonly used in the etching field.

[0122] After the etching step, the insulating layer 20 may include through holes with a diameter of 3 μm to 50 μm. The diameter may be 5 μm or more. The diameter may be 7 μm or more. The diameter may be 40 μm or less. The diameter may be 30 μm or less. The diameter may be 20 μm or less. The diameter may be 15 μm or less. In this case, it may be possible to realize a highly integrated multi-layered redistribution layer on a packaging substrate.

[0123] Manufacturing Steps 3 is a conceptual diagram illustrating a packaging substrate manufactured by a manufacturing method according to an embodiment. The manufacturing method of the packaging substrate according to the embodiment will be described with reference to FIG.

[0124] In the manufacturing step, the packaging substrate 200 can be manufactured from the base substrate 100 on which the patterned insulating layer 20 is formed.

[0125] In the manufacturing step, an electrical conductive layer 21 can be formed in the area where the insulating layer 20 is etched away by plasma etching, particularly in the through holes, to manufacture a redistribution layer.

[0126] The electrically conductive layer 21 may be formed by a dry method or a wet method.

[0127] The dry method involves forming a seed layer by sputtering in an area where the electrically conductive layer 21 will be disposed, and then plating the area on which the seed layer has been formed to form the electrically conductive layer 21. When forming the seed layer, metals such as titanium, chromium, nickel, etc. may be sputtered, or these metals may be sputtered together with copper. Sputtering creates an anchor effect in which the surface on which the electrically conductive layer 21 will be disposed interacts with the deposited metal particles, thereby improving the adhesion of the electrically conductive layer 21.

[0128] The wet method involves applying a primer to the area where the electrically conductive layer 21 needs to be formed, followed by metal plating. The primer may contain a compound having a functional group such as an amine. Depending on the desired level of adhesion, the primer may contain both a compound having a functional group such as an amine and a silane coupling agent. When using a silane coupling agent, the surface to be primed is pretreated with the silane coupling agent, and then a compound having an amine group is applied to the pretreated area to form a primer layer.

[0129] After forming the seed layer or primer layer, the electrically conductive layer 21 can be formed by plating with a metal. Copper plating may be applied when forming the electrically conductive layer 21, but is not limited to this. Prior to metal plating, portions of the seed layer or primer layer that do not require the formation of the electrically conductive layer 21 can be passivated, or portions that require the formation of the electrically conductive layer 21 can be activated, and then plating can be performed. The activation or passivation treatment may be a light irradiation treatment using a laser of a specific wavelength, a chemical treatment, or the like. However, after metal plating without applying the activation or passivation treatment, the electrically conductive layer 21 can be etched and patterned according to a pre-designed shape.

[0130] When the patterned insulating layer 20 includes a hole pattern, an electrically conductive layer 21 may be formed in the through-holes in the insulating layer 20. The electrically conductive layer 21 may electrically connect an electrically conductive layer (not shown) located above the electrically conductive layer 21 to an electrically conductive layer (not shown) located below the electrically conductive layer 21.

[0131] When the pre-designed structure of the first redistribution layer 25 is a multi-layer structure, another patterned insulating layer 20 and another patterned electrically conductive layer 21 can be formed on the patterned insulating layer 20 and another patterned electrically conductive layer 21. The other patterned insulating layer 20 and another patterned electrically conductive layer 21 disposed on the patterned insulating layer 20 and another patterned electrically conductive layer 21 can be formed by the method described above.

[0132] When the first redistribution layer 25 has a multi-layer structure, the electrically conductive layer 21 may have a smaller width disposed at an upper portion of the first redistribution layer 25. The electrically conductive layer 21 may have a smaller thickness disposed at an upper portion of the first redistribution layer 25. The electrically conductive layer 21 may have a smaller pitch disposed at an upper portion of the first redistribution layer 25. This allows the first redistribution layer 25 to form a stable electrical connection with a semiconductor device having a fine pattern.

[0133] The manufacturing steps may further include, if necessary, a process of forming a second redistribution layer (not shown) disposed under the core substrate 10. The second redistribution layer may have a single-layer structure or a multi-layer structure. The redistribution layer formed under the core substrate 10 may be formed by the same method as described above.

[0134] The second redistribution layer may have a single-layer structure or a multi-layer structure.

[0135] When the second redistribution layer has a multi-layer structure, the electrical conductive layer may be arranged with a wider width as it goes down in the second redistribution layer. The electrical conductive layer may be arranged with a thicker thickness as it goes down in the second redistribution layer. The electrical conductive layer may have a larger pitch as it goes down in the second redistribution layer. This allows the second redistribution layer to form a stable electrical connection with a main board on which a wider or thicker electrical conductive layer is formed.

[0136] In the manufacturing process, a redistribution layer having a pre-designed structure may be formed on the upper and / or lower sides of the core substrate 10 to provide a packaging substrate 200 .

[0137] If necessary, upper terminals or the like may be additionally formed on the upper and / or lower sides of the packaging substrate 200 during the manufacturing process, and bumps may be additionally formed on the lower side of the packaging substrate 200. The bumps may be arranged in a predetermined shape under a redistribution layer arranged under the core substrate 10. For example, the bumps may be arranged on a portion of the lower surface of the packaging substrate 200 so as to contact a main board or the like.

[0138] Manufactured packaging substrate The packaging substrate 200 manufactured by the packaging substrate manufacturing method of the embodiment may include the core substrate and the patterned insulating layer 20 disposed on the core substrate.

[0139] The packaging substrate 200 may further include an electrically conductive layer 21 surrounded by a patterned insulating layer 20 .

[0140] The materials and structures of the core substrate 10, insulating layer 20 and electrically conductive layer 21 are the same as those described above, so a description thereof will be omitted here.

[0141] The patterned insulating layer 20 may include through holes formed in the thickness direction of the insulating layer 20. An electrical conductive layer 21 may be formed in the through holes.

[0142] The electrically conductive layer 21 surrounded by the patterned insulating layer 20 may be formed on the patterned insulating layer 20 by the dry method or the wet method described above.

[0143] The insulating layer 20 may include a through-hole pattern. The diameter of the through-holes included in the insulating layer 20 may be 3 μm to 50 μm. The diameter may be 5 μm or more. The diameter may be 7 μm or more. The diameter may be 40 μm or less. The diameter may be 30 μm or less. The diameter may be 20 μm or less. The diameter may be 15 μm or less. In this case, a through-hole pattern with a higher pattern density can be stably implemented in the insulating layer 20.

[0144] The following examples are provided for illustrative purposes only and are not intended to limit the scope of the present invention.

[0145] Manufacturing example: Packaging substrate manufacturing Example 1: An insulating layer was formed on the upper surface of a Corning glass plate SG7.8 by vacuum laminating an Ajinomoto Build-up Film (ABF), and a base substrate was then provided.

[0146] A metal film was formed on the insulating layer. Specifically, a first metal layer having a thickness of 50 μm was formed on the upper surface of the insulating layer by a sputtering process using a titanium target, and a second metal layer having a thickness of 100 μm was formed on the upper surface of the first metal layer by a sputtering process using a copper target.

[0147] A resist composition, RESONAC's DRY FILM PHOTEC (RY series), was applied to the metal film and cured to form a 15 μm thick resist film. The resist film was exposed to an electron beam and developed to form a resist pattern film with numerous hole patterns with diameters of 7 to 10 μm. The metal film was then patterned using an etching solution to form a metal pattern film including a first metal pattern film formed from the first metal layer and a second metal pattern film formed from the second metal layer, completing an etching mask with a thickness of 165 μm.

[0148] The base substrate with the etching mask formed thereon was placed in an etching chamber, and plasma etching was performed to form a hole pattern in the insulating layer. During plasma etching, a plasma power of 1.5 kW or more was applied, and 150 sccm of NF3 was supplied as the first etching gas and 150 sccm of O2 was supplied as the second etching gas into the chamber.

[0149] After completing the patterning of the insulating layer, the base substrate was subjected to a cleaning process. Specifically, the base substrate was immersed in a water tank and then subjected to ultrasonic cleaning for 300 seconds using a vibration frequency of 20 kHz to 130 kHz.

[0150] After cleaning, it was confirmed that no resist pattern film remained on the metal pattern film, and the metal pattern film was then removed with an etching solution to complete the packaging substrate.

[0151] Example 2: A packaging substrate was produced under the same conditions as in Example 1, except that the thickness of the resist pattern film was 20 μm.

[0152] Comparative Example 1: A packaging substrate was manufactured under the same conditions as in Example 1, except that only a second metal pattern layer having a thickness of 150 μm was used as the metal pattern film and a vibration frequency of 100 kHz was used in the cleaning process.

[0153] Comparative Example 2: An insulating layer was patterned under the same conditions as in Example 1, except that the thickness of the resist pattern film was 25 μm. After patterning, it was confirmed that the resist pattern film remained on the metal pattern film, and the resist pattern film was stripped and removed. After removing the resist pattern film, the base substrate was immersed in a water tank and then subjected to ultrasonic cleaning for 300 seconds at a vibration frequency of 100 kHz. After cleaning, the metal pattern film was removed with an etching solution, completing a packaging substrate.

[0154] Comparative Example 3: A packaging substrate was manufactured under the same conditions as in Example 1, except that the thickness of the resist pattern film was 10 μm and the vibration frequency in the cleaning process was 100 kHz.

[0155] Comparative Example 4: A packaging substrate was manufactured under the same conditions as in Example 1, except that only a second metal pattern layer having a thickness of 100 μm was used as the metal pattern film and a vibration frequency of 100 kHz was used in the cleaning process.

[0156] The thicknesses of the metal pattern film and resist pattern film for each example and comparative example are shown in Table 1 below, and whether or not the resist pattern film remained after plasma etching for each example and comparative example is shown in Table 2 below.

[0157] Evaluation example: Evaluation of the presence or absence of damage to a patterned insulating layer In the packaging substrates manufactured for each example and comparative example, the patterned insulating layer was observed with an optical microscope to check whether or not there was any damage to the patterned insulating layer. If no damage was observed, it was evaluated as Pass, and if damage was observed, it was evaluated as Fail.

[0158] The evaluation results for each of the examples and comparative examples are shown in Table 2 below.

[0159] [Table 1]

[0160] [Table 2]

[0161] After completing the patterning of the insulating layer, in Example and Comparative Examples 1, 3, and 4, no resist pattern film remained on the metal pattern film, whereas in Comparative Example 2, the resist pattern film remained.

[0162] In the evaluation of the presence or absence of damage to the insulating layer, the Example and Comparative Example 2 were rated as Pass, whereas Comparative Examples 1, 3, and 4 were rated as Fail.

[0163] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also fall within the scope of the present invention. [Explanation of symbols]

[0164] 100 Base board 10 Core Board 20 insulating layer 21 Electrically Conductive Layer 25 1st redistribution layer 30 Etching Mask 31 Metal pattern film 32 Resist pattern film 200 Packaging Substrate

Claims

1. a preparation step of preparing a base substrate including a core substrate and an insulating layer disposed on the core substrate; an etching step of selectively etching the insulating layer using an etching mask; and manufacturing a packaging substrate from the base substrate after the etching step, The etching mask is disposed on the insulating layer and includes a metal pattern film and a resist pattern film disposed on the metal pattern film.

2. the metal pattern film includes a first metal pattern layer and a second metal pattern layer disposed on the first metal pattern layer; The method of claim 1 , wherein the first metal pattern layer includes any one selected from the group consisting of titanium, nickel, chromium, molybdenum, tungsten, aluminum, and combinations thereof.

3. The method for manufacturing a packaging substrate according to claim 2 , wherein the second metal pattern layer comprises copper.

4. The method of manufacturing a packaging substrate according to claim 2 , wherein the first metal pattern layer is disposed in contact with an upper surface of the insulating layer.

5. The method for manufacturing a packaging substrate according to claim 1 , wherein a ratio of a thickness of the resist pattern film to a thickness of the metal pattern film is 0.15 or less.

6. 3. The method of claim 2, wherein a ratio of the thickness of the second metal pattern layer to the thickness of the first metal pattern layer is 0.5-10.

7. The method for manufacturing a packaging substrate according to claim 1 , wherein the thickness of the metal pattern film is 100 μm or more and 250 μm or less.

8. the etching step includes an etching mask forming process of forming the etching mask on the insulating layer, and a plasma etching process of selectively plasma-etching the insulating layer using the etching mask; The method for manufacturing a packaging substrate according to claim 1 , wherein the resist pattern film is removed in the plasma etching process.

9. The method further includes a cleaning step of ultrasonically cleaning the base substrate after the plasma etching step. The method for manufacturing a packaging substrate according to claim 8, wherein the vibration frequency in the cleaning process is 20 kHz to 200 kHz.

10. The method for manufacturing a packaging substrate according to claim 1 , wherein the insulating layer after the etching step includes through holes having a diameter of 3 μm to 50 μm.

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