Gate driver circuit, power supply control circuit, and power supply device

Abstract

The gate driver circuit has room for further consideration regarding generation of the drive signal voltage.SOLUTION: The gate driver circuit includes a drive control circuit configured to generate a drive signal for pulse-driving between an upper voltage and a lower voltage in a cycle corresponding to a pulse signal, and input the drive signal to a gate of a switch element to be driven to control driving of the switch element, a reference voltage generation circuit configured to generate a reference voltage, and an upper voltage generation circuit configured to generate the upper voltage based on the reference voltage with reference to a source voltage generated at a source of the switch element according to a drain current of the switch element.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a gate driver circuit, a power supply control circuit, and a power supply device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there are power supply devices that generate an output voltage by switching operations using switch elements. Such power supply devices include a gate driver circuit that generates a drive signal for driving the switch elements.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-171290

[0005] [overview] The gate driver circuit disclosed in Patent Document 1 leaves room for further consideration regarding the generation of drive signal voltages.

[0006] The gate driver circuit disclosed in this specification includes a drive control circuit, a reference voltage generation circuit, and an upper voltage generation circuit. The drive control circuit is configured to receive a pulse signal, an upper voltage, and a lower voltage, generate a drive signal that pulses between the upper voltage and the lower voltage at a period corresponding to the pulse signal, and input the drive signal to the gate of the switch element to drive and control the switch element. The reference voltage generation circuit is configured to generate a reference voltage. The upper voltage generation circuit is configured to generate an upper voltage based on the reference voltage, with reference to a source voltage generated at the source of the switch element in accordance with the drain current of the switch element. The drive control circuit sets the drive signal to the upper voltage to turn the switch element to the ON state and sets the drive signal to the lower voltage to turn the switch element to the OFF state.

[0007] The power supply control device disclosed in this specification includes a gate driver circuit configured as described above and a switch element.

[0008] The power supply device disclosed in this specification includes a power supply control device having the above-described configuration and a current-voltage conversion circuit connected to the drain of the switch element and configured to generate an output voltage according to the drain current. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a power supply device 200Y. The power supply device 200Y is a so-called DC / DC converter. [Figure 2] FIG. 2 is a diagram showing the internal configuration of the high-side regulator 1y. [Figure 3] FIG. 3 is a graph showing waveforms of each voltage of the power supply control device 100Y. [Figure 4] FIG. 4 is a graph showing the drain-source current Ids and the drain-source voltage Vds of the switch element SW1. [Figure 5] 5 is a diagram showing the power supply device 200X. The power supply device 200X is a so-called DC / DC converter. [Figure 6] FIG. 6 is a diagram showing the internal configuration of the high-side regulator 1x. [Figure 7] FIG. 7 is a graph showing waveforms of each voltage of the power supply control device 100X.

[0010] [Detailed explanation] <Regarding the power supply device 200Y of the comparative example> First, power supply device 200Y will be described as a comparative example of power supply device 200X of the present disclosure. Next, the problems with the comparative example will be described, followed by a description of power supply device 200X of the present disclosure.

[0011] FIG. 1 is a diagram showing a power supply device 200Y. The power supply device 200Y is a so-called DC / DC converter. It receives an input of a power supply voltage Vcc, generates an output voltage Vo, and supplies the output voltage Vo to a load (not shown). As shown in FIG. 1, the power supply device 200Y includes a power supply control device 100Y and various discrete components (e.g., an inductor L and a capacitor Co).

[0012] The power supply control device 100Y has a plurality of external terminals (external terminals T1 to T3 in accordance with FIG. 1) as means for establishing electrical connection with the outside. The external terminal T1 is connected to an application terminal of a power supply voltage Vcc. The external terminal T2 is connected to a ground terminal GND. The external terminal T3 is connected to a first terminal of an inductor L.

[0013] A second terminal of the inductor L is connected to a first terminal of the capacitor C1. A second terminal of the capacitor C1 is connected to the ground terminal. A DC output voltage Vo is generated at the connection node between the inductor L and the capacitor C1. The output voltage Vo is obtained by smoothing the voltage converted from current to voltage by the inductor L using the capacitor C1.

[0014] The power supply control device 100Y includes a gate driver circuit 50y, a switch element SW1, and a sense resistor R1.

[0015] The gate driver circuit 50y is configured to generate a drive signal G1. The gate driver circuit 50y includes a high-side regulator 1y, a pulse signal generating circuit 2, and a drive control circuit 3.

[0016] The high-side regulator 1y is connected to the external terminals T1 and T2. The high-side regulator 1y receives the power supply voltage Vcc and the ground voltage GND as inputs and generates an upper voltage Vreg1 based on the ground voltage GND. In this specification, the ground voltage generated at the ground terminal GND is also referred to as the ground voltage GND using the same reference symbol. The detailed configuration of the high-side regulator 1y will be described later.

[0017] The pulse signal generating circuit 2 generates a pulse signal PWM that drives the device with a predetermined frequency.

[0018] The drive control circuit 3 has an input terminal TI, an output terminal TO, an upper power supply terminal TH, and a lower power supply terminal TL. The input terminal TI is connected to the pulse signal generating circuit 2. The input terminal TI receives a pulse signal PWM from the pulse signal generating circuit 2. The output terminal TO is connected to the gate terminal of a switch element SW1, which will be described later. The output terminal TO is a terminal from which a drive signal G1, which will be described later, is generated.

[0019] The upper power supply terminal TH is connected to the high-side regulator 1y. The upper power supply terminal TH receives the upper voltage Vreg1 from the high-side regulator 1y. The lower power supply terminal TL is connected to the external terminal T2. The ground voltage GND is received by the lower power supply terminal TL.

[0020] The drive control circuit 3 receives the pulse signal PWM, the upper voltage Vreg1, and the ground voltage to generate the drive signal G1. More specifically, the drive control circuit 3 generates the drive signal G1 that pulses between a high level (corresponding to the upper voltage Vreg1) and a low level (corresponding to the ground voltage GND) in synchronization with the pulse period of the pulse signal PWM.

[0021] The switch element SW1 is an enhancement type Ga-HEMT (High Electron Mobility Transistor). The gate terminal of the switch element SW1 is connected to the output terminal of the drive control circuit 3. The drain terminal of the switch element SW1 is connected to an external terminal T3. The source terminal of the switch element SW1 is connected to a first terminal of a sense resistor R1. The second terminal of the sense resistor R1 is connected to an external terminal T2.

[0022] The switch element SW1 is controlled to be turned on / off by the drive signal G1. Specifically, when the drive signal G1 is at a high level, the switch element SW1 is turned on. When the drive signal G1 is at a low level, the switch element SW1 is turned off. More specifically, this is as follows.

[0023] In the switch element SW1, the channel between the source terminal and the drain is inverted according to the gate-source voltage difference, forming an inversion layer (not shown). When the gate-source voltage difference exceeds a certain threshold voltage, the formed inversion layer becomes a current path, and the source terminal and drain terminal are in a conductive state (ON state). Conversely, when the gate-source voltage difference is less than the certain threshold voltage, the source terminal and drain terminal are in a non-conductive state (OFF state).

[0024] In the conductive state, the on-resistance of the switch element SW1 decreases as the gate-source voltage difference increases. In other words, as the gate-source voltage difference increases, the ratio of the drain current Id to the source voltage Vs increases. Here, the ratio of the drain current Id to the source voltage Vs is also referred to as the current capability of the switch element SW1.

[0025] When the switch element SW1 is in a conductive state, a drain current Id flows between the source and drain of the switch element SW1. Current-to-voltage conversion occurs when the drain current Id flows through the inductor L. The voltage converted from the drain current Id by the inductor L is smoothed by the capacitor Co, generating the output voltage Vo, which is a DC voltage.

[0026] When the switch element SW1 is in a conductive state, a source voltage Vs corresponding to the drain current Id is generated across the switch element SW1. More specifically, the source voltage Vs is determined by the current value of the drain current Id and the resistance value of the sense resistor R1. When the switch element SW1 is in a non-conductive state, the drain current Id does not flow (the current value of the drain current Id is set to 0), and the source voltage Vs is 0V.

[0027] As described above, the sense resistor R1 generates a voltage across itself due to the drain current Id. By detecting the voltage across the sense resistor R1, it is possible to sense (detect) the value of the drain current Id. For this reason, the sense resistor R1 can be considered to be arranged for current sensing of the drain current Id.

[0028] <Detailed configuration of the high-side regulator 1y> 2 shows the internal configuration of the high-side regulator 1y, which includes an internal power supply circuit 4, a reference voltage generating circuit 5, an operational amplifier OP1, transistors Q1 and Q2, variable resistors VR1 and VR2, a resistor R2, and capacitors C1 and C2.

[0029] The internal power supply circuit 4 has a first terminal connected to the external terminal T1, a second terminal connected to the upper power supply terminal of the operational amplifier OP1, and a third terminal connected to the reference voltage generation circuit 5. The internal power supply circuit 4 receives a power supply voltage Vcc via the external terminal T1 and generates a predetermined internal voltage Vi. The internal power supply circuit 4 also supplies the internal voltage Vi to both the reference voltage generation circuit 5 and the operational amplifier OP1.

[0030] The reference voltage generation circuit 5 is a bandgap power supply circuit. The reference voltage generation circuit 5 is connected to the internal power supply circuit 4, the ground terminal GND, and the non-inverting input terminal (+) of the operational amplifier OP1. The reference voltage generation circuit 5 receives the internal voltage Vi as an input and generates a first reference voltage Vref1 referenced to the ground voltage GND. The reference voltage generation circuit 5 supplies the first reference voltage Vref1 to the non-inverting input terminal (+) of the operational amplifier OP1.

[0031] The output terminal of the operational amplifier OP1 is fed back to the inverting input terminal (-) via a variable resistor VR1. Specifically, the output terminal of the operational amplifier OP1 is connected to a first terminal of the variable resistor VR1. The second terminal of the variable resistor VR1 is connected to a first terminal of the variable resistor VR2. The second terminal of the variable resistor VR2 is connected to the ground terminal GND.

[0032] The variable resistors VR1 and VR2 are connected in series to form a voltage divider circuit. A feedback voltage Vf corresponding to the voltage division ratio of the variable resistors VR1 and VR2 is generated at the connection node between the variable resistors VR1 and VR2.

[0033] The operational amplifier OP1 controls the output of the second reference voltage Vref2 so that the first reference voltage Vref1 and the feedback voltage Vf coincide (so that the non-inverting input terminal (+) and the inverting input terminal (-) are imaginarily shorted).

[0034] Transistors Q1 and Q2 are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Transistor Q1 is diode-connected, with its gate connected to its drain. The drain of transistor Q1 is connected to the gate of transistor Q2 as well as to the first terminal of resistor R2. The source of transistor Q1 is connected to the output of operational amplifier OP1 as well as to the first terminal of capacitor C1.

[0035] The drain terminal of the transistor Q2 is connected to the output terminal of the power supply voltage Vcc together with the first terminal of the resistor R2, and the source terminal of the transistor Q2 is connected to the upper power supply terminal of the drive control circuit 3 as the output terminal of the upper voltage Vreg1.

[0036] The second terminal of the capacitor C1 is connected to the ground terminal GND together with the second terminal of the sense resistor R1. The first terminal of the capacitor C2 is connected to the gate terminal of the transistor Q2. The second terminal of the capacitor C2 is connected to the ground terminal GND together with the second terminal of the sense resistor R1.

[0037] Basically, transistors Q1 and Q2 are always on. As mentioned above, transistor Q1 is diode-connected. Therefore, the gate voltage and drain voltage of transistor Q1 are equal to the gate voltage of transistor Q2.

[0038] Here, the gate voltage of transistor Q1 is the gate-source voltage Vgs1 of transistor Q1 minus the second reference voltage Vref2. The gate voltage of transistor Q2 is the gate-source voltage Vgs2 of transistor Q2 minus the upper voltage Vreg1. Since these two values ​​are equal, the upper voltage Vreg1 is the sum of the second reference voltage Vref2 and the gate-source voltage Vgs1 minus the gate-source voltage Vgs2.

[0039] Figure 3 is a graph showing the waveforms of each voltage of the power supply control device 100Y. From top to bottom, Figure 3 shows the pulse signal PWM, drive signal G1, drain current Id, source voltage Vs, and gate-source voltage Vgs3. In Figure 3, the voltage waveform has its voltage value on the vertical axis, the current waveform has its current on the vertical axis, and both the voltage waveform and the current waveform have their time axes on the horizontal axis.

[0040] As shown in Figure 3, the pulse signal PWM is a digital signal that changes between two values, high and low, at a predetermined period and a predetermined duty ratio. When the pulse signal PWM is at a high level, the drive control circuit 3 takes in an upper voltage Vreg1 and outputs it as a drive signal G1. When the pulse signal PWM is at a low level, the drive control circuit 3 takes in a ground voltage GND and outputs it as a drive signal G1. Therefore, the drive signal G1 changes between two values, high (= a voltage value corresponding to the upper voltage Vreg1) and low (= a voltage value corresponding to the ground voltage GND), in synchronization with the pulse signal PWM.

[0041] When the drive signal G1 rises to high level, the gate-source voltage Vgs3 also rises in conjunction with it. This turns on the switch element SW1, and the drain current Id begins to flow. As mentioned above, the drain current Id is smoothed by the inductor L and capacitor Co. Therefore, the value of the drain current Id gradually increases at a predetermined slew rate while the switch element SW1 is on.

[0042] When the drive signal G1 falls to low level, the gate-source voltage Vgs3 also falls in conjunction with it, turning off the switch element SW1 and preventing the drain current Id from flowing.

[0043] As described above, the source voltage Vs is determined based on the value of the drain current Id and the resistance value of the sense resistor R1. Therefore, as the value of the drain current Id gradually increases, the source voltage Vs also gradually increases at the same slew rate as the drain current Id.

[0044] <Considerations regarding the current capacity of the switch element SW1> The upper voltage Vreg1 is maintained at a constant voltage value. Therefore, the gate-source voltage Vgs3 decreases as the source voltage Vs increases. Specifically, if the source voltage Vs rises from 0V to a predetermined voltage Va during the on-period of the switch element SW1, the gate-source voltage Vgs3 during the same period gradually decreases by the voltage Va from the upper voltage Vreg1.

[0045] As described above, the gate-source voltage Vgs3 affects the current-carrying capacity of the switch element SW1. Therefore, when the gate-source voltage Vgs3 decreases, the current-carrying capacity of the switch element SW1 decreases. Furthermore, when a Gan-HEMT is adopted as the switch element SW1, there are problems as described below.

[0046] <Consideration of the Current-Carrying Capacity of Gan-HEMT> As general characteristics of Gan-HEMT, there are the following. To increase the current-carrying capacity of Gan-HEMT, the high-level drive signal input to the gate of Gan-HEMT must be set within a predetermined voltage range (hereinafter also referred to as the "high-efficiency range").

[0047] This will be described with a specific example. For example, assume that the high-efficiency range of the switch element SW1 is 5.5V or more and less than 6.0V. The upper limit value of the high-efficiency range is the rated voltage (= gate breakdown voltage) of the switch element SW1. In this case, when the voltage value of the high-level drive signal G1 is lower than 5.5V, the current-carrying capacity of the switch element SW1 significantly decreases. Also, when the drive signal G1 exceeds 6.0V, it exceeds the rated voltage of the switch element SW1, and there is a risk that the switch element SW1 will be damaged. More specifically, it is as follows.

[0048] Figure 4 is a graph showing the drain-source current Ids and drain-source voltage Vds of the switch element SW1. In Figure 4, the dashed line indicates the state where the gate-source voltage Vgs3 of the switch element SW1 is 5.0V (= the state where the drive signal G1 is outside the high-efficiency range). In Figure 4, the solid line indicates the state where the gate-source voltage Vgs3 of the switch element SW1 is 5.7V (= the state where the drive signal G1 is within the high-efficiency range). Note that in this case, the on-threshold voltage of the switch element SW1 is less than 5.0V.

[0049] 4, for example, when the drain-source voltage Vds is a predetermined voltage Vb, the value of the drain-source current Ids is larger when the gate-source voltage Vgs3 is 5.7 V than when the gate-source voltage Vgs3 is 5.0 V. In this way, when the gate-source voltage Vgs3 of the switch element SW1 is set to a value within the high efficiency range (in this example, equal to or greater than 5.5 V and less than 6.0 V), the current capability of the switch element SW1 is optimally exhibited.

[0050] Therefore, the gate driver circuit 50y controls the voltage value of the high-level drive signal G1 (= the voltage value of the upper voltage Vreg1) to be within the high-efficiency range. At this time, the gate driver circuit 50y generates the upper voltage Vreg1 as a constant voltage referenced to the ground terminal GND. Then, as described above, if the gate-source voltage Vgs3 decreases as the drain current Id increases, there is a risk that the voltage value of the gate-source voltage Vgs3 will fall outside the high-efficiency range.

[0051] To address this problem, the gate driver circuit 50x of the present disclosure is capable of suppressing a decrease in the current capability of the switch element SW1. The gate driver circuit 50x, power supply control device 100X, and power supply device 200X according to embodiments of the present disclosure will be described in detail below. The configurations of the gate driver circuit 50x, power supply control device 100X, and power supply device 200X according to embodiments of the present disclosure include components common to the gate driver circuit 50y, power supply control device 100Y, and power supply control device 100Y described above. Therefore, the common components are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0052] <Regarding the power supply device 200X of the embodiment according to the present disclosure> FIG. 5 is a diagram showing a power supply device 200X. The power supply device 200X is a so-called DC / DC converter. It receives an input of a power supply voltage Vcc, generates an output voltage Vo, and supplies the output voltage Vo to a load (not shown). As shown in FIG. 5, the power supply device 200X includes a power supply control device 100X and various discrete components (e.g., an inductor L and a capacitor Co).

[0053] The power supply control device 100X has a plurality of external terminals (external terminals T1 to T3 in accordance with FIG. 1) as means for establishing electrical connection with the outside. The external terminal T1 is connected to an application terminal of a power supply voltage Vcc. The external terminal T2 is connected to a ground terminal GND. The external terminal T3 is connected to a first terminal of an inductor L.

[0054] The power supply control device 100X includes a switch element SW1 and a sense resistor R1 similar to those described above, and also includes a gate driver circuit 50x.

[0055] The gate driver circuit 50x is configured to generate a drive signal G1. The gate driver circuit 50x includes a pulse signal generation circuit 2 and a drive control circuit 3 similar to those described above. In addition, the gate driver circuit 50x includes a high-side regulator 1x.

[0056] The high-side regulator 1x is connected to an external terminal T1, an external terminal T2, an output terminal TO, and the source terminal of the switch element SW1.

[0057] The high-side regulator 1x receives the power supply voltage Vcc, the source voltage Vs, and the drive signal G1, generates an upper voltage Vreg2 based on the source voltage Vs, and inputs this voltage to the upper power supply terminal TH. That is, as described above, when the source voltage Vs rises, the upper voltage Vreg2 also rises accordingly. The rate of rise (slew rate) of the upper voltage Vreg2 at this time corresponds to the rate of rise (slew rate) of the source voltage Vs.

[0058] Therefore, even if the source voltage Vs rises while the switch element SW1 is on, the drive signal G1 (= upper voltage Vreg2) also rises at the same time. As a result, the gate-source voltage Vgs3 is maintained constant while the switch element SW1 is on. This prevents a decrease in the current capability of the switch element SW1. The detailed configuration of the high-side regulator 1x is described below.

[0059] <Detailed configuration of high-side regulator 1x> 6 is a diagram showing the internal configuration of high-side regulator 1x. As shown in Fig. 6, high-side regulator 1x includes an internal power supply circuit 4, a reference voltage generation circuit 5, an operational amplifier OP1, transistors Q1 and Q2, variable resistors VR1 and VR2, a resistor R2, and capacitors C1 and C2, which are similar to those described above. The lower power supply terminal of operational amplifier OP1, the second terminal of variable resistor VR2, and the second terminals of capacitors C1 and C2 are connected to ground terminal GND.

[0060] In addition, the high-side regulator 1x includes an inverter 10 and a sample-and-hold circuit 11.

[0061] The input terminal of the inverter 10 is connected to the output terminal TO, and the output terminal of the inverter 10 is connected to the sample-and-hold circuit 11 (more specifically, the gate terminal of a transistor Q3, which will be described later).

[0062] Inverter 10 receives drive signal G1 as input and supplies drive signal G2, which is the inverse of the logic of drive signal G1, to sample-and-hold circuit 11 (more specifically, to the gate terminal of transistor Q3). Specifically, when drive signal G1 is at a high level, drive signal G2 is at a low level. Conversely, when drive signal G1 is at a low level, drive signal G2 is at a high level.

[0063] The sample-and-hold circuit 11 is connected to the reference voltage generating circuit 5, the inverter 10, the operational amplifier OP1, and the source terminal of the switch element SW1. The sample-and-hold circuit 11 receives the first reference voltage Vref1 and the drive signal G2, generates a hold voltage Vh, and inputs it to the non-inverting input terminal (+) of the operational amplifier OP1. Specifically, this is as follows.

[0064] The sample-and-hold circuit 11 includes a transistor Q3 and a capacitor C3. The transistor Q3 is an N-channel MOSFET. The drain terminal of the transistor Q3 is connected to the reference voltage generating circuit 5. The source terminal of the transistor Q3, together with the first terminal of the capacitor C3, is connected to the inverting input terminal of the operational amplifier OP1. The gate terminal of the transistor Q3 is connected to the output terminal of the inverter 10, as described above. The second terminal of the capacitor C3 is connected to the source terminal of the switch element SW1.

[0065] Transistor Q3 is controlled to turn on and off by drive signal G2. Specifically, when drive signal G2 is at a high level, a channel inversion layer is formed between the source and drain terminals, and this inversion layer becomes a current path, turning the transistor Q3 conductive (on). Conversely, when drive signal G2 is at a low level, the channel inversion layer disappears between the source and drain terminals, turning the transistor Q3 non-conductive (off).

[0066] The sample-and-hold circuit 11 samples (acquires) the first reference voltage Vref1 when the drive signal G1 is at a low level, and holds (retains) the sampled first reference voltage Vref1 when the drive signal G1 is at a high level. Specifically, this is as follows.

[0067] When the drive signal G1 is at a low level, the drive signal G2 is at a high level. At this time, the transistor Q3 is turned on, and the first reference voltage Vref1 is supplied to the non-inverting input terminal (+) of the operational amplifier OP1 and the first terminal of the capacitor C3. Then, a charge corresponding to the potential difference between the source voltage Vs and the first reference voltage Vref1 is accumulated in the capacitor C3. In other words, the capacitor C3 samples the first reference voltage Vref1.

[0068] When the drive signal G1 is at a high level, the drive signal G2 is at a low level. At this time, the transistor Q3 is turned off. At this time, a charge corresponding to the potential difference between the source voltage Vs and the first reference voltage Vref1 is accumulated in the capacitor C3 due to the sampling operation. Therefore, the hold voltage Vh is held at a voltage value equivalent to the first reference voltage Vref1, which is based on the source voltage Vs.

[0069] During the on-period of the switch element SW1 (=when the drive signal G1 is at a high level), the second reference voltage Vref2 is generated by the operational amplifier OP1 and the variable resistors VR1 and VR2 based on the first reference voltage Vref1 held with the source voltage Vs as the reference. That is, the second reference voltage Vref2 is a voltage based on the source voltage Vs.

[0070] As described above, the second terminals of the capacitors C1 and C2 are connected to the source terminal of the switch element SW1, so that the gate-source voltages Vgs1 and Vgs2 are each voltages referenced to the source voltage Vs.

[0071] The upper voltage Vreg2 is the sum of the second reference voltage Vref2 and the gate-source voltage Vgs1 minus the gate-source voltage Vgs2. Because the second reference voltage Vref2, the gate-source voltage Vgs1, and the gate-source voltage Vgs2 are voltages referenced to the source voltage Vs, the upper voltage Vreg2 is also a voltage referenced to the source.

[0072] Figure 7 is a graph showing the waveforms of each voltage of the power supply control device 100X. From top to bottom, Figure 7 shows the pulse signal PWM, drive signal G1, drain current Id, source voltage Vs, and gate-source voltage Vgs3. In Figure 7, the voltage waveform has its voltage value on the vertical axis, the current waveform has its current on the vertical axis, and both the voltage waveform and the current waveform have their time axes on the horizontal axis.

[0073] 7, when the pulse signal PWM is at a high level, the drive control circuit 3 receives the upper voltage Vreg2 and outputs it as the drive signal G1, and when the pulse signal PWM is at a low level, the drive control circuit 3 receives the ground voltage GND and outputs it as the drive signal G1.

[0074] When the drive signal G1 rises to a high level, the drain current Id flows so as to gradually increase at a predetermined slew rate as described above, and in response, the source voltage Vs also gradually increases at the same slew rate.

[0075] Here, the upper voltage Vreg2 is a voltage based on the source voltage Vs. More specifically, the upper voltage Vreg2 is generated by the high-side regulator 1x based on the power supply voltage Vcc with the source voltage Vs as the reference. Therefore, when the source voltage Vs rises, the upper voltage Vreg2 also rises in accordance with the rise in the source voltage Vs. The amount of rise in the upper voltage Vreg2 at this time corresponds to the amount of rise in the source voltage Vs.

[0076] During the on-period of switch element SW1, drive signal G1 corresponds to upper voltage Vreg2, so both source voltage Vs and drive signal G1 rise equally. For example, as shown in Figure 7, if source voltage Vs rises by a predetermined voltage Va during the on-period of switch element SW1, drive signal G1 also rises by the predetermined voltage Va during the same period. Therefore, during the on-period of switch element SW1, even if source voltage Vs rises, gate-source voltage Vgs3 does not fall but remains constant.

[0077] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure. For example, although the switching element SW1 is an enhancement-type GaAs-HEMT, this is not limiting. For example, the switching element SW1 may be a depletion-type GaAs-HEMT.

[0078] The switch element SW1 may also be a general MOSFET. Even in this case, there is the advantage that the reduction in the current capability of the switch element SW1 can be suppressed, as described above. Since it is preferable to generate the drive signal G1 in the high-efficiency range described above for a GaN-HEMT, adopting the configuration of the present disclosure can more effectively suppress the reduction in current capability.

[0079] Furthermore, although the power supply control device 100X has been described as including a sense resistor R1, it need not necessarily be included. For example, the sense resistor R1 may be externally connected between the switch element SW1 and the ground terminal GND by being externally attached to the external terminal T2 of the power supply control device 100X. In this case, the effect of suppressing the decrease in the current capability of the switch element SW1 described above can be obtained.

[0080] The sense resistor R1 may be a resistor, or may be a semiconductor element that has a predetermined resistance value when both ends are in a conductive state, such as a MOSFET in a diode-connected state.

[0081] <Additional Notes> The gate driver (50x) disclosed in the specification includes a drive control circuit (3) configured to receive a pulse signal (PWM), an upper voltage (Vreg2), and a lower voltage (GND), generate a drive signal (G1) that pulses between the upper voltage (Vreg2) and the lower voltage (GND) at a period corresponding to the pulse signal (PWM), and input the drive signal (G1) to the gate of the switch element (SW1) to be driven to drive and control the switch element (SW1); and a reference voltage generation circuit (5, O) configured to generate reference voltages (Vref1, Vref2). and an upper voltage generating circuit (1x) configured to generate an upper voltage (Vreg2) based on reference voltages (Vref1, Vref2) with reference to a source voltage (Vs) generated at the source of the switch element (SW1) according to a drain current (Id) of the switch element (SW1), and a drive control circuit (3) sets a drive signal (G1) to the upper voltage (Vreg2) to turn on the switch element (SW1) to be driven, and sets the drive signal (G1) to the lower voltage (GND) to turn off the switch element (SW1) (first configuration).

[0082] The gate driver (50x) according to the first configuration includes a sample-and-hold circuit (11) configured to sample reference voltages (Vref1, Vref2) based on the source voltage (Vs) when the drive signal (G1) is the lower voltage (GND) and to hold the sampled reference voltages (Vref1, Vref2) when the drive signal (G1) is the upper voltage (Vreg2), and the upper voltage generation circuit (1x) generates the upper voltage (Vreg2) based on the sampled reference voltages (Vref1, Vref2) based on the source voltage (Vs) (second configuration).

[0083] The power supply control device (100X) disclosed in the specification includes a gate driver (50x) according to the first or second configuration, and a switch element (SW1) (third configuration).

[0084] In the power supply control device (100X) according to the third configuration, the switch element (SW1) is a GaN-HEMT (fourth configuration).

[0085] A power supply control device (100X) according to the third or fourth configuration includes a semiconductor element (R1) having a resistance whose first terminal is connected to the source of a switch element (SW1) and whose second terminal is connected to the application terminal of a lower voltage (GND), and through which a current flows to generate a source voltage (Vs) between both ends of the first terminal and the second terminal (fifth configuration).

[0086] The power supply device (200X) disclosed in the specification comprises a power supply control device (100X) according to any one of the third to fifth configurations, and a current-voltage conversion circuit (L, Co) connected to the drain of the switch element (SW1) and configured to generate an output voltage (Vo) according to the drain current (Id) (sixth configuration). [Explanation of symbols]

[0087] 1x High-side regulator 1y High-side regulator 2 Pulse signal generation circuit 3. Drive control circuit 4 Internal power circuit 5 Reference voltage generation circuit 10 Inverter 11 Sample and hold circuit 50x gate driver circuits 50y gate driver circuit 100X Power Control Unit 100Y Power Control Device 200X power supply 200Y power supply C1, C2, C3 capacitors Co capacitor G1 drive signal G2 drive signal GND Ground terminal, ground voltage (lower voltage) Id Drain current Ids Drain-source current L Inductor (current-voltage conversion circuit) OP1 operational amplifier PWM pulse signal Q1, Q2, Q3 transistors R1 Sense resistor (semiconductor element) R2 resistance SW1 Switch element T1~T3 external terminals TH Upper power supply end TI input terminal TL Lower power supply end TO output terminal VR1, VR2 variable resistors Va specified voltage Vb Specific voltage Vcc power supply voltage Vds Drain-source voltage Vf Feedback voltage Vgs1 Source voltage Vgs2 Source voltage Vgs3 Source voltage Vh Hold voltage Vi internal voltage Vo output voltage Vref1 First reference voltage Vref2 Second reference voltage Vreg1 upper voltage Vreg2 upper voltage Vs Source voltage

Claims

1. a drive control circuit configured to receive a pulse signal, an upper voltage, and a lower voltage, generate a drive signal for pulse driving between the upper voltage and the lower voltage at a period corresponding to the pulse signal, and input the drive signal to a gate of a switch element to be driven to drive and control the switch element; a reference voltage generating circuit configured to generate a reference voltage; an upper voltage generating circuit configured to generate the upper voltage based on a reference voltage, with a source voltage generated at the source of the switch element in accordance with a drain current of the switch element as a reference; Equipped with The drive control circuit is a gate driver circuit that sets the drive signal to the upper voltage to turn on the switch element to be driven, and sets the drive signal to the lower voltage to turn off the switch element.

2. a sample-and-hold circuit configured to sample the reference voltage with respect to the source voltage when the drive signal is at the lower voltage, and to hold the sampled reference voltage when the drive signal is at the upper voltage; 2. The gate driver circuit according to claim 1, wherein the high-side voltage generating circuit generates the high-side voltage based on the sampled reference voltage, with the source voltage as a reference.

3. a gate driver circuit according to claim 1; The switch element; A power supply control device comprising:

4. 4. The power supply control device according to claim 3, wherein the switching element is a GaN-HEMT.

5. 4. The power supply control device according to claim 3, further comprising a semiconductor element having a resistance, a first terminal of which is connected to the source of the switch element, a second terminal of which is connected to the terminal to which the lower voltage is applied, and a resistance through which a current flows to generate the source voltage between both ends of the first terminal and the second terminal.

6. The power supply control device according to claim 3; a current-voltage conversion circuit connected to the drain of the switch element and configured to generate an output voltage according to the drain current; A power supply device comprising:

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