Plasma processing apparatus

Abstract

To prevent the damage of a sample and the positional deviation of a wafer at the time of removing the wafer after destaticization by eliminating the defective destaticization.SOLUTION: The plasma processing apparatus includes a processing chamber which is disposed in a vacuum container and in which plasma is formed, the processing chamber being depressurized, a sample stage which is disposed at a lower side in the processing chamber and has an upper surface having a function of an electrostatic chuck and on which a wafer to be processed by the plasma is placed, a plurality of pins which are disposed inside the sample stage and are driven in a vertical direction to come into contact with a back surface of the wafer to raise and lower the wafer above the upper surface of the sample stage, and a plurality of openings which are disposed in the sample stage and in which the plurality of pins move inside. When the plurality of pins are driven upward to raise the back surface of the wafer above the upper surface of the sample stage, the tip of one of the plurality of pins is different in height from the tips of the other pins.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a plasma processing apparatus. [Background technology]

[0002] A plasma processing apparatus equipped with pusher pins and an operating method thereof are described in Patent Document 1. Patent Document 1 states that "Pusher pins 260 are arranged inside a through-passage that penetrates metal block 251, dielectric film 255, the insulating member, and plate member that constitute sample stage 250, with their axes parallel to the axial direction of this passage, and are arranged in positions axially symmetrical about the center of wafer 220 and at positions 60% to 80% of the radius of wafer 220 so as to prevent the application of uneven external force to wafer 220, which may cause cracks, damage, etc." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-153678 Summary of the Invention [Problem to be solved by the invention]

[0004] One method for removing a wafer held in a plasma processing system is to release the charge accumulated on the wafer via plasma. However, this method alone cannot completely remove the residual charge between the electrostatic chuck (ESC) on the sample stage and the backside of the wafer, resulting in the backside of the wafer remaining attached to the top surface of the sample stage equipped with the ESC. If an attempt is made to forcibly remove the wafer from the top surface of the sample stage in this state, the force of the wafer's release from the sample stage can cause it to bounce and shift from its center position on the sample stage. It is necessary to resolve this problem of incomplete removal of the residual charge between the top surface of the sample stage equipped with the ESC and the backside of the wafer, thereby preventing damage to the sample (wafer) and subsequent misalignment when the wafer is removed from the sample stage after charge removal.

[0005] The present disclosure aims to provide a technology that eliminates the problem of poor discharge of residual charges between the top surface of a sample stage having an electrostatic chuck and the back surface of a wafer, and prevents the wafer from shifting position when it is removed from the sample stage after discharge.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows.

[0008] A plasma processing apparatus according to one embodiment includes: a processing chamber disposed within the vacuum vessel and having a reduced pressure therein in which plasma is formed; a sample stage disposed at a lower portion within the processing chamber, the sample stage having an upper surface that functions as an electrostatic chuck, on which a wafer to be processed by the plasma is placed; a plurality of pins disposed inside the sample stage and driven in the vertical direction to contact the back surface of the wafer and raise and lower the wafer above the upper surface of the sample stage; a plurality of openings disposed on the upper surface of the sample stage, through which each of the plurality of pins moves; When removing residual charge between the upper surface of the sample stage and the back surface of the wafer, when the multiple pins are driven upward to raise the back surface of the wafer above the upper surface of the sample stage, one of the multiple pins is at a different height than the other pins. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to prevent damage to the wafer, which is a sample, due to insufficient neutralization, and to prevent the wafer from being displaced when removed after neutralization. [Brief explanation of the drawings]

[0010] [Figure 1]10A to 10C are cross-sectional views showing a wafer peeling process according to a comparative example. [Figure 2] 10A to 10C are cross-sectional views illustrating a wafer peeling process according to an embodiment. [Figure 3] 10A and 10B are explanatory diagrams of distributions of wafer misalignment locations according to a comparative example and an example. [Figure 4] 1 is a longitudinal sectional view schematically showing an example of the configuration of a plasma processing apparatus according to an embodiment; [Figure 5] FIG. 2 is an explanatory diagram schematically illustrating an example of the configuration of a sample stage and a plurality of pins according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the present disclosure are described below.

[0012] The plasma processing apparatus (106) according to the embodiment is a plasma processing apparatus having a sample stage (250) equipped with an electrostatic chuck (ESC) that electrostatically holds a sample (wafer) (220) using an electrostatic adsorption method, and has a plurality of pins (260) that raise and lower the wafer (220) on an upper surface (2501) of the sample stage (250). When removing residual charge between the upper surface of the sample stage and the back surface of the wafer, the plurality of pins (260) protrude from the upper surface (2501) of the sample stage (250) by different lengths.

[0013] That is, when the upper surface of the sample stage and the back surface of the wafer are spaced apart to remove residual charge between them, the length of protrusion of the pins 260 from the upper surface 2501 of the sample stage 250 varies when the wafer 220 is raised on the upper surface 2501 of the sample stage 250. For example, it is preferable that one of the pins 2601 has a height difference of, for example, 0.5 mm to 1.0 mm relative to the other pins 2602. In other words, the length (L31) of one pin 2601 protruding from the upper surface 2501 of the sample stage 250 is A mm + (0.5 mm to 1.0 mm), and the length (L32) of the other pin 2602 protruding from the upper surface 2501 of the sample stage 250 is A mm. At this time, for example, the angle of the wafer 220 with respect to the upper surface (2501) of the sample stage (250) is preferably in the range of 0.22 degrees to 0.45 degrees.

[0014] This makes it possible to prevent damage to the sample due to improper neutralization and misalignment when removing the wafer after neutralization.

[0015] Hereinafter, an embodiment will be described with reference to the drawings. [Example]

[0016] Fig. 1 is a cross-sectional view of a wafer peeling process according to a comparative example, Fig. 2 is a cross-sectional view of a wafer peeling process according to an example, and Fig. 3 is an explanatory diagram of the distribution of wafer misalignment locations according to the comparative example and the example.

[0017] The process of peeling off the wafer 220 according to the comparative example will be described with reference to FIG.

[0018] Initially, the wafer 220, which is a sample, is placed on the upper surface 2501 of the sample stage 250, i.e., the mounting surface 2501 of the wafer 220. The sample stage 250 has the upper surface 2501, which functions as an adsorption surface of an electrostatic chuck (ESC: Electric Static Chuck) that fixes the wafer 220 using an electrostatic adsorption method. The sample stage 250 has a plurality of pusher pins 260 for peeling the wafer 220 from the upper surface 2501.

[0019] Next, as a method of peeling the wafer 220 from the upper surface 2501, there is a method of dissipating the charge accumulated on the wafer 220 via plasma. After the charge accumulated on the wafer 220 has been completely dissipated, the multiple pusher pins 260 are raised to peel the back surface 2201 of the wafer 220 from the upper surface 2501 of the sample stage 250. At this time, the distance L11 on the left side between the upper surface 2501 of the sample stage 250 and the back surface 2201 of the wafer 220 and the distance L12 on the right side of the back surface 2201 of the wafer 220 are set to the same length (L11 = L12). In other words, the upper surface 2501 of the sample stage 250 and the back surface of the wafer 220 are ideally parallel to each other.

[0020] However, it was found that the above-mentioned method of dissipating the electric charge alone is not enough to completely dissipate the residual electric charge between the electrostatic chuck ESC provided on the sample stage 250 and the back surface 2201 of the wafer 220, and a phenomenon may occur in which the back surface 2201 of the wafer 220 continues to be adsorbed to the upper surface 2501 of the sample stage 250.

[0021] If, with this residual charge remaining, the pusher pins 260 are raised to forcibly separate the wafer 220 from the upper surface 2501 of the sample stage 250, the force of the wafer 220 separating from the sample stage 250 may cause the wafer 220 to bounce and deviate from the center position of the sample stage 250.

[0022] It is necessary to eliminate the failure to discharge the residual charge between the upper surface 2501 of the sample stage 250 having the electrostatic chuck ESC and the back surface 2201 of the wafer 220, and to prevent the resulting damage to the wafer 220 and the displacement of the wafer when it is removed from the sample stage 250 after discharge.

[0023] Next, the process of peeling the wafer 220 according to the embodiment will be described with reference to FIG.

[0024] Initially, the wafer 220 is placed on the upper surface 2501 of the sample stage 250. The upper surface 2501 of the sample stage 250 constitutes the attraction surface of the electrostatic chuck ESC.

[0025] Next, a method for peeling the wafer 220 from the upper surface 2501 is performed in which the charge accumulated on the wafer 220 is released via plasma. Here, the upper surface of the sample stage and the back surface of the wafer are separated to remove any residual charge between the upper surface of the sample stage and the back surface of the wafer. At this time, the back surface 2201 of the wafer 220 is detached or peeled obliquely from the upper surface 2501 of the sample stage 250. For this purpose, the height L21 of the upper tip of one pusher pin (first pin) 2601 is set to a height different from the height L22 of the upper tip of another pusher pin (second pin) 2602 (L21 > L22), and the multiple pusher pins 260 are raised. In other words, the height balance of the pusher pins 260 is changed from an equal state (see FIG. 1) to an uneven state (see FIG. 2). At this time, for example, the angle θ of the wafer 220 with respect to the upper surface (2501) of the sample stage (250) is preferably in the range of 0.22 degrees to 0.45 degrees. This allows a portion of the wafer 220 to be detached from the upper surface 2501 of the sample stage 250 without the wafer 220 bouncing. That is, in FIG. 2, with the left end of the backside of the wafer 220 in contact with the upper surface 2501, the backside on the right side of the wafer 220 can be peeled off from the upper surface 2501 from the left end of the backside.

[0026] At this time, plasma enters the gap between the upper surface 2501 of the sample stage 250 and the back surface 2201 of the wafer 220, and the charge accumulated on the back surface 2201 of the wafer 220 and the surface of the electrostatic chuck ESC (i.e., the upper surface 2501 of the sample stage 250) can be released via the plasma.

[0027] Thereafter, the multiple pusher pins 260 are raised again. This causes the wafer 220, some of which are in contact with the upper surface 2501 of the sample stage 250, to be completely detached or peeled off from the upper surface 2501. In other words, the distance between the left end of the back surface of the wafer 220 and the upper surface 2501 is set to be L33. This prevents the wafer 220 from being misaligned. At this time, for example, the height L31 of the upper tip of the first pin 2601 is set to a different height from the height L32 of the upper tip of the second pin 2602 (L31>L32>L33). At this time, for example, the angle θ of the wafer 220 with respect to the upper surface (2501) of the sample stage (250) is in the range of 0.22 degrees to 0.45 degrees.

[0028] Although not particularly limited, the height L31 of the upper tip of the first pin 2601 and the height L32 of the upper tip of the second pin 2602 can be changed to the same value (L32 = L31 = L34) thereafter. This allows the wafer 220 to be picked up reliably in the same manner as before. Also, the heights L21 and L22 can be changed directly to height L34 without changing them to heights L31 and L32. In this way, the steps for changing the multiple pusher pins 260 can be shortened.

[0029] Fig. 3 shows the results of investigating the amount of deviation of the center point of the wafer 220 from the center position of the sample stage 250 when removing the wafer after neutralization in the configuration examples of Fig. 1 and Fig. 2. As shown in Fig. 3, it can be seen that the amount of deviation in the configuration example of Fig. 2 is smaller than the amount of deviation in the configuration example of Fig. 1.

[0030] Next, an example of the configuration of a plasma processing apparatus having the sample stage 250 of Fig. 2 will be described with reference to Fig. 4. Fig. 4 is a vertical cross-sectional view showing the outline of the configuration of the plasma processing apparatus according to the embodiment.

[0031] In particular, this figure shows the configuration of an etching processing unit, which is one of the plasma processing devices 106.

[0032] The plasma processing apparatus 106 is roughly divided into upper and lower sections, with an upper processing vessel section equipped with a vacuum vessel, an electric field or magnetic field generator, and an exhaust device, and a lower rectangular parallelepiped bed section accommodating a control device for adjusting the supply of electric power, gas, and fluids such as a cooling refrigerant to the processing vessel section.

[0033] 4 is an enlarged view of the upper vessel section of the plasma processing apparatus 106, showing an outline of the configuration of its main components. In this figure, a processing chamber 200 is arranged inside a vacuum vessel 210 that constitutes the vessel section, and a disk-shaped antenna 201 that radiates radio waves into the processing chamber 200 to supply an electric field is provided at the top of the processing chamber 200, and a sample stage 250 on the bottom on which a substrate-shaped sample to be processed, such as a wafer 220, is placed.

[0034] The vacuum vessel 210 has a lid member 215 for the vacuum vessel 210 arranged above the antenna 201 at its top, a sidewall 211 having a substantially cylindrical shape that covers the outer periphery of the processing chamber 200, and a lower vessel 212 arranged below the sidewall 211. The sidewall 211 and the lower vessel 212 are arranged to surround the outer periphery with a space therebetween. The space between them is a space where gas, plasma, and reaction products in the processing chamber 200 move downward and are exhausted from an opening arranged below the lower vessel 212 by operation of an exhaust pump 203, which is an exhaust device connected to the lower vessel below.

[0035] A magnetic field generating device 202, which is made up of, for example, an electromagnetic coil and a yoke, is installed around the sidewall 211 and the lid member 215 that surround the outer periphery of the processing chamber 200. A magnetic field supplied from the magnetic field generating device 202 and an electric field supplied from the antenna 201 into the processing chamber 200 form a plasma in the processing chamber 200.

[0036] Above the sample stage 250 of the processing chamber 200, a shower plate 205 having a disk shape constituting the ceiling surface of the processing chamber 200 is disposed facing the upper surface of the sample stage 250. Above the shower plate 205 and between it and the cover member 215, a disk-shaped window member 205a made of a dielectric material such as quartz is disposed, connected to the upper end of the side wall 211 and attached to hermetically seal the inside and outside of the processing chamber 200.

[0037] A gap is formed between the shower plate 205 and the window member 205a, forming a space. A process gas, which is a mixture of multiple substances, is supplied from a gas supply means (not shown) at a predetermined flow rate and mixture ratio to fill the space. A plurality of through-holes, each with a small diameter and communicating with the space, are arranged in parallel with and opposite to the upper surface of the shower plate 205, on which a sample is placed on the sample stage 250. The process gas filling the space enters the space above the sample stage 250 in the process chamber 200 through the through-holes and is supplied thereto during sample processing. A vacuum exhaust valve 204, which has a plurality of rotatable flaps that can open and close communication, is arranged below an opening in the bottom of the vacuum vessel 210 and between the opening and the inlet of the exhaust pump 203. During processing, sample transport, or other periods when the interior of the vacuum vessel 200 is not open to the atmosphere and a vacuum pressure is maintained, the pressure in the process chamber 200 is controlled by the coordinated operation of the vacuum exhaust valve 204 and the exhaust pump 203.

[0038] During sample processing, high-frequency power is applied to the antenna 201 via a high-frequency power supply 221 and a matching box 222 installed outside the vacuum vessel 210 and a coaxial cable 201a connected thereto, and a high-frequency electric field is introduced into the processing chamber 200 through the antenna 201. At the same time, a magnetic field formed by a magnetic field forming device 202 is supplied into the processing chamber 200, and the interaction between these excites atoms and molecules of the processing gas material to form plasma, which is used to etch the wafer 220.

[0039] The sample stage 250 includes a substantially cylindrical metal block 251 with a disk-shaped interior and high thermal conductivity, a dielectric film 255 made of a dielectric material composed primarily of alumina and yttria and disposed above the upper surface of the circular block to cover it, and a film-like electrode 257 disposed within the dielectric film 255 and electrically connected to the DC power supply 206 via a filter circuit 256. In this example, the dielectric film 255, filter circuit 256, and DC power supply 206 constitute an electrostatic chuck (ESC). A ceramic cover 253 is installed on the outer periphery of the circular mounting surface on which the wafer 220 is mounted and on the sidewall of the metal block 251 to electrically insulate them from plasma and to protect them from wear due to sputtering and etching by the plasma.

[0040] Furthermore, a concentric or spiral flow path 254 is arranged inside the metal block 251 that constitutes the sample stage 250, and a coolant whose temperature or flow rate (speed) is adjusted by a temperature adjustment unit 209 installed outside the vacuum vessel 210 is introduced into the metal block 251, thereby adjusting the temperature of the metal block 251 and ultimately the sample stage 250. The wafer 220 receives heat from the plasma during processing while placed on the top surface of the sample stage 250, but the temperature of the wafer 220 placed thereon can be adjusted by adjusting the temperature of the sample stage 250.

[0041] In order to improve thermal conduction between the wafer 220 and the sample stage 250 or the metal block 251, a plurality of openings are arranged on the upper surface of the dielectric film 255, which are connected to a gas source 213 of a heat-conductive gas, such as He gas, via a gas supply adjustment valve 214, and with the wafer 220 placed on the placement surface, He gas is supplied to the space between the back surface of the wafer 220 and the dielectric film 255. This He gas transfers heat supplied to the wafer 220 through the dielectric film 255 and the metal block 251, thereby cooling the wafer 220.

[0042] A metal plate member is disposed below the metal block 251 via an insulating member, thereby hermetically sealing and separating the interior and exterior of the processing chamber 200. Further below this, an actuator 258, an arm 259 connected to the actuator 258, and a plurality of rod-shaped pusher pins 260 (e.g., three in this embodiment) connected to the end of the arm 259 and extending in the vertical direction are disposed. The pusher pins 260 are disposed inside a through passage (also referred to as a through hole) (310: see FIG. 5) that penetrates the metal block 251, the dielectric film 255, the insulating member, and the plate member that constitute the sample stage 250, so that their axes are parallel to the axial direction of the passage. Furthermore, the pusher pins 260 are disposed axially symmetrically about the center of the wafer 220 and at a position between 60% and 80% of the radius of the wafer 220 to prevent the application of uneven external force to the wafer 220, which may cause cracks, damage, etc. Here, the multiple through passages provided in the sample stage 250 can be rephrased as multiple openings (310) inside which multiple pusher pins (also referred to as multiple pins) 260 move up and down. The multiple pusher pins 260 include a first pin 2601 and a second pin 2602 (see FIG. 5).

[0043] The vertical direction driven by the actuator 258 is arranged parallel to the axis or substantially parallel to it, and the pusher pin 260 connected to the arm 259 is moved up and down in conjunction with the operation of the actuator 258. Such an operation is performed when the wafer 220 is transferred in and out of the processing chamber 200 before and after processing.

[0044] In this example, a single arm 259 connected to a single actuator 258 can operate multiple pusher pins 260 in synchronization. In this case, the vertical length of the first pin 2601 is made longer than the vertical length of the second pin 2602. Although it is necessary to prepare pusher pins of different lengths, the actuator 258 and arm 259 that reliably drive the multiple pusher pins 260 can be installed in the area below the sample stage 250.

[0045] If there is sufficient space below the sample stage 250, one arm 259 connected to one actuator 258 may drive one first pin 2601, and one arm 259 connected to another actuator 258 may drive multiple second pins 2602. Alternatively, one arm 259 connected to one actuator 258 may be provided for each of the pusher pins 260 (first pin 2601, multiple second pins 2602). In this case, the vertical length of the first pin 2601 can be set to the same length as the vertical length of the second pin 2602. The length (height) of the tip of the first pin 2601 protruding from the upper surface (mounting surface 2501: see Figure 5) of the sample stage (250) can be controlled relatively freely, so it can be adjusted to an optimal length (height). Furthermore, since the upward movement speed and downward movement speed of the first pin 2601 can be controlled relatively freely, it is possible to appropriately set a movement speed that can prevent damage to the wafer 220. Note that there are other configuration examples for the drive method of the multiple pusher pins 260, and it is not limited to the actuator 258 and arm 259 shown in FIG.

[0046] Next, referring to FIG. 5, a configuration example of the sample stage 250 and the multiple pusher pins 260 will be described using a plan view and a cross-sectional view of the sample stage 250. FIG. 5 is an explanatory diagram that schematically shows a configuration example of the sample stage and the multiple pins according to the embodiment. FIG. 5 also shows a schematic diagram of a state when the upper surface 2501 of the sample stage 250 and the back surface of the wafer 220 are spaced apart to remove residual charge between the upper surface 2501 of the sample stage 250 and the back surface of the wafer 220. Although the wafer 220 is not shown in FIG. 5, the configuration during removal of charge can be seen in FIG. 2.

[0047] At this time, the wafer 220 is detached or peeled off with the back surface 2201 of the wafer 220 obliquely relative to the upper surface 2501 of the sample stage 250 .

[0048] 5, the sample stage 250 has a circular mounting surface 2501 when viewed from above. In this example, three pusher pins 260 (2601, 2602, 2602) are provided on the mounting surface 2501 so as to be arranged, for example, at the vertices of an equilateral triangle. Each of the three pusher pins 260 is provided inside an opening 310 provided in the sample stage 250 so as to be movable in the up and down direction.

[0049] The three pusher pins 260 have one first pin 2601 and two second pins 2602, 2602. The first pin 2601 is connected to a first drive circuit DR1 that allows movement in the up and down direction. One of the second pins 2602 is connected to a second drive circuit DR2 that allows movement in the up and down direction. The other second pin 2602 is connected to a third drive circuit DR3 that allows movement in the up and down direction.

[0050] The drive circuits DR1, DR2, and DR3 are connected to a control device CNT, and are configured so that the first pin 2601 moves up and down, and the second pins 2602, 2602 move up and down under the control of the control device CNT.

[0051] The cross-sectional view shown in FIG. 5 schematically illustrates the state of the first pin 2601 and the two second pins 2602, 2602 when the wafer 220 is raised on the upper surface (mounting surface 2501) of the sample stage 250 by the control device CNT.

[0052] When the wafer 220 is raised on the upper surface of the sample stage 250, the length L21 by which the upper tip T1 of the first pin 2601 protrudes from the upper surface of the sample stage (250) and the length L22 by which the upper tip T2 of the second pin 2602 protrudes from the upper surface of the sample stage (250) are different, and the length L21 is set to be longer than the length L22. That is, L21-L22 is set to a value of, for example, 0.5 mm or more and 1.0 mm or less. In other words, the length by which the upper tip of the first pin 2601 protrudes from the upper surface 2501 of the sample stage 250 is set to A mm(L22)+(0.5 mm or more and 1.0 mm or less: L21-L22), and the length by which the upper tip of the second pin 2602 protrudes from the upper surface of the sample stage 250 is set to A mm(L22).

[0053] The control device CNT can control the lengths L21 and L22 by controlling the drive circuits DR1, DR2, and DR3. In addition, the control device CNT can control the lengths L31, L32, and L34 described in FIG. 2 by controlling the drive circuits DR1, DR2, and DR3.

[0054] The present disclosure is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0055] 106: Plasma processing equipment 200: Processing room 201: Antenna 201a: Coaxial cable 202: Magnetic field forming device 203: Exhaust pump 204: Vacuum exhaust valve 205: Shower plate 206:DC power supply 210: Vacuum container 213: Gas source 214: Gas supply adjusting valve 215: Lid member 220: Wafer (sample) 221: High frequency power supply 250: Sample stage 259: Arm 260: Pusher pin 310:Aperture 2201: Back side 2501: Top surface (mounting surface) 2601: 1st pin 2602: 2nd pin CNT: Control device ESC: Electrostatic chuck.

Claims

1. a processing chamber disposed within the vacuum vessel and having a reduced pressure therein in which plasma is formed; a sample stage disposed at a lower portion within the processing chamber, the sample stage having an upper surface that functions as an electrostatic chuck, on which a wafer to be processed by the plasma is placed; a plurality of pins disposed inside the sample stage and driven in the vertical direction to abut against the back surface of the wafer and raise and lower the wafer above the upper surface of the sample stage; a plurality of openings disposed on the sample stage, through which each of the plurality of pins moves; a plasma processing apparatus, wherein when the plurality of pins are driven upward to raise the back surface of the wafer above the upper surface of the sample stage, a tip of one of the plurality of pins is at a different height relative to tips of the other pins.

2. In claim 1, The plasma processing apparatus, wherein the plurality of pins are three pins.

3. In claim 2, A plasma processing apparatus, wherein the height of the tip of the one pin has a difference in height of 0.5 mm to 1.0 mm from the height of the tips of the other pins.

4. In claim 1, When the plurality of pins are driven upward to raise the back surface of the wafer above the upper surface of the sample stage, the angle of the back surface of the wafer with respect to the upper surface of the sample stage is in the range of 0.22 degrees to 0.45 degrees.

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