Method for producing a semiconductor component using a low-temperature plasma etching process

Abstract

To provide a method of manufacturing a semiconductor device.SOLUTION: The method includes forming a first mold structure and a second mold structure spaced apart from the first mold structure in a horizontal direction on a semiconductor structure, wherein the first mold structure includes a first insulating layer and a second insulating layer alternately stacked one by one, and the second mold structure includes a third insulating layer including the same material as that of the first insulating layer, forming a mask pattern on the first mold structure and the second mold structure, and performing an etching process on the first mold structure and the second mold structure using a first etching gas including an oxygen-containingfluorocarbon.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing semiconductor devices using a low-temperature plasma etching process. [Background technology]

[0002] As the geometrical features of structures on semiconductor substrates continue to shrink and the types of structures evolve, etching processes present numerous challenges. Particularly when fabricating semiconductor devices containing high-aspect-ratio components, problems arise due to different etch rates for two different insulating materials. For example, when simultaneously etching a first mold structure, which is made up of two different insulating materials stacked alternately, and a second mold structure, which is made up of only one insulating material, the etching depths of the first and second mold structures may differ even if the etching times are the same. This can increase the difficulty of simultaneously forming patterns on the first and second mold structures. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a method for manufacturing a semiconductor device having improved electrical characteristics and reliability.

[0004] An object of the present invention is to provide a method for manufacturing a semiconductor device, which reduces the difficulty and cost of the manufacturing process.

[0005] The problem to be solved by the present invention is not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] To achieve the above object, a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention includes the steps of: forming a first mold structure on a semiconductor structure and a second mold structure horizontally spaced from the first mold structure, the first mold structure having a structure in which a first insulating film and a second insulating film different from the first insulating film are alternately stacked one by one; and the second mold structure including a third insulating film including the same material as that of the first insulating film; forming a mask pattern on the first mold structure and the second mold structure; and performing an etching process on the first mold structure and the second mold structure using a first etching gas using the mask pattern as an etching mask, the first etching gas including an oxygen-containing fluorocarbon.

[0007] A method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention includes the steps of: forming an insulating pattern on a substrate; forming conductive contacts in the insulating pattern; forming an etch stop layer on the insulating pattern and the conductive contacts; and forming a mold structure on the etch stop layer, the mold structure including a first mold film, a lower support film, a second mold film, and an upper support film stacked in sequence, the first mold film and the second mold film including a first material, the lower support film and the upper support film including a second material, the first material and the second material having etch selectivity with respect to each other; forming a mask pattern on the mold structure; and performing an etching process on the mold structure using a first etching gas using the mask pattern as an etching mask, wherein a via hole penetrating the mold structure and the etch stop layer is formed by the etching process, the first etching gas including an oxygen-containing fluorocarbon.

[0008] A method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention includes the steps of: preparing a first substrate including a cell array region and a contact region adjacent to the cell array region; forming a peripheral circuit structure including peripheral circuit transistors on the first substrate; and forming a mold structure on the peripheral circuit structure, the mold structure including an interlayer insulating film and a sacrificial film alternately stacked one on the other, the interlayer insulating film including a first material and the sacrificial film including a second material, the first material and the second material having etching selectivity with respect to each other; and trimming the mold structure so that the mold structure has a staircase structure in the contact region. forming a planarization insulating film covering the staircase structure; and simultaneously forming a vertical channel hole penetrating the mold structure in the cell array region, a first penetrating structure hole penetrating the planarization insulating film and the mold structure in the contact region, and a second penetrating structure hole penetrating the planarization insulating film in the contact region, wherein the forming of the vertical channel hole, the first penetrating structure hole, and the second penetrating structure hole includes performing an etching process of the mold structure and the planarization insulating film using a first etching gas, and the first etching gas includes a fluorocarbon containing oxygen. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a flow chart that schematically illustrates a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention. [Figure 2A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention. [Figure 2B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention. [Figure 2C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention. [Figure 2D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention. [Figure 3] FIG. 10 is a diagram showing the etching rate as a function of the CF4 gas flow rate for an SiO2 film, a SiN film, a Si film, and an ACL (Amorphous Carbon Layer) film in a comparative example. [Figure 4] FIG. 10 is a diagram showing the etching rate as a function of the CF3OCFCF2 gas flow rate for an SiO2 film, a SiN film, a Si film, and an ACL film in an experimental example. [Figure 5] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 6] FIG. 6 is a cross-sectional view taken along line AA' in FIG. 5. [Figure 7] 7A to 7C are plan views illustrating a method for manufacturing the semiconductor element of FIG. 6. [Figure 8] 7A to 7C are cross-sectional views showing a method for manufacturing the semiconductor element of FIG. 6. [Figure 9] 7A to 7C are cross-sectional views showing a method for manufacturing the semiconductor element of FIG. 6. [Figure 10] 7A to 7C are cross-sectional views showing a method for manufacturing the semiconductor element of FIG. 6. [Figure 11] 7A to 7C are cross-sectional views showing a method for manufacturing the semiconductor element of FIG. 6. [Figure 12] 7A to 7C are plan views illustrating a method for manufacturing the semiconductor element of FIG. 6. [Figure 13] 7A to 7C are cross-sectional views showing a method for manufacturing the semiconductor element of FIG. 6. [Figure 14] 7A to 7C are cross-sectional views showing a method for manufacturing the semiconductor element of FIG. 6. [Figure 15] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 16A] FIG. 16 is a cross-sectional view taken along the line BB′ in FIG. [Figure 16B] FIG. 16 is a cross-sectional view taken along the line CC' in FIG. [Figure 17A] 16A to 16C are cross-sectional views taken along the line BB' of FIG. 15, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17B]16A to 16C are cross-sectional views taken along the line CC' in FIG. 15, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18A] 16A to 16C are cross-sectional views taken along the line BB' of FIG. 15, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18B] 16A to 16C are cross-sectional views taken along the line CC' in FIG. 15, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19A] 16A to 16C are cross-sectional views taken along the line BB' of FIG. 15, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19B] 16A to 16C are cross-sectional views taken along the line CC' in FIG. 15, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0011] 1 is a flow chart illustrating a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device using a low-temperature plasma etching process according to an embodiment of the present invention.

[0012] 1 and 2A, a method for manufacturing a semiconductor device using a low-temperature plasma etching process includes a step S1 of forming a first mold structure MO1 and a second mold structure MO2 on a semiconductor structure SST, and forming a first state semiconductor device WF-1 by performing the step S1 of forming the first mold structure MO1 and the second mold structure MO2 on the semiconductor structure SST.

[0013] The semiconductor structure SST includes a substrate containing a semiconductor material. The semiconductor material includes silicon (Si) or germanium (Ge). Alternatively, the semiconductor structure SST includes a compound semiconductor such as silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), or indium phosphide (InP). Alternatively, the semiconductor structure SST has a silicon-on-insulator (SOI) structure. For example, the semiconductor structure SST includes a buried oxide layer (BOX layer).

[0014] The semiconductor structure SST is a device having a specific circuit structure, such as a dynamic random access memory (DRAM), a NAND flash memory (NAND flash), a ferroelectric random access memory (FRAM), a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), an application processor (AP), or an application specific integrated circuit (ASIC).

[0015] The semiconductor structure SST includes a first region R1 and a second region R2 adjacent to the first region R1. The first region R1 and the second region R2 are horizontally spaced apart. A first mold structure MO1 is disposed on the semiconductor structure SST in the first region R1. A second mold structure MO2 is disposed on the semiconductor structure SST in the second region R2.

[0016] The first mold structure MO1 includes a first insulating film DI1 and a second insulating film DI2, which are different from each other. The first insulating film DI1 and the second insulating film DI2 are alternately stacked one after another on the semiconductor structure SST. The first insulating film DI1 and the second insulating film DI2 include insulating materials. For example, the first insulating film DI1 and the second insulating film DI2 include materials having etching selectivity with each other. For example, the first insulating film DI1 includes silicon oxide, and the second insulating film DI2 includes silicon nitride.

[0017] The second mold structure MO2 includes a third insulating film DI3. The third insulating film DI3 is stacked on the semiconductor structure SST. The third insulating film DI3 includes an insulating material. For example, the third insulating film DI3 includes the same material as the first insulating film DI1. For example, the third insulating film DI3 includes silicon oxide.

[0018] Referring to Figures 1 and 2B, for a semiconductor element in a first state (WF-1 in Figure 2A), a step (S2) of forming a first mask pattern PM on a first mold structure MO1 and a second mold structure MO2 can be performed to form a semiconductor element in a second state WF-2.

[0019] Forming the first mask pattern PM includes forming a mask film (not shown) on the first mold structure MO1 and the second mold structure MO2, and performing an exposure and development process for the mask film. The first mask pattern PM includes a first opening OP1 and a second opening OP2. The first opening OP1 exposes a portion of the top surface of the first mold structure MO1. The second opening OP2 exposes a portion of the top surface of the second mold structure MO2.

[0020] The first mask pattern PM includes a silicon-based or carbon-based material. For example, the first mask pattern PM includes an Amorphous Carbon Layer (ACL). For example, the first mask pattern PM includes single crystal or polycrystalline silicon. The first mask pattern PM includes single crystal or polycrystalline silicon that is not doped with other elements. Alternatively, the first mask pattern PM may include single crystal or polycrystalline silicon doped with carbon (C), boron (B), phosphorus (P), or a metal. Alternatively, the first mask pattern PM may include a photoresist material.

[0021] Referring to Figures 1 and 2C, a third-state semiconductor element WF-3 can be formed by performing step S3 of etching the first mold structure and the second mold structure using a first etching gas and using the first mask pattern PM as an etching mask on the second-state semiconductor element (WF-2 in Figure 2B).

[0022] An etching process using a first etching gas forms a first via hole HARV1 in the first mold structure MO1 and a second via hole HARV2 in the second mold structure MO2. The first via hole HARV1 overlaps vertically with the first opening OP1. The first via hole HARV1 penetrates the first mold structure MO1. A portion of the top surface of the semiconductor structure SST is exposed through the first via hole HARV1. The second via hole HARV2 overlaps vertically with the second opening OP2. The second via hole HARV2 penetrates the second mold structure MO2. A portion of the top surface of the semiconductor structure SST is exposed through the second via hole HARV2. The first via hole HARV1 and the second via hole HARV2 are formed simultaneously.

[0023] The first via hole HARV1 and the second via hole HARV2 have a high aspect ratio. For example, the ratio of the horizontal width to the vertical height of the first via hole HARV1 is 15 or more, but it is not limited thereto. For example, the ratio of the horizontal width to the vertical height of the second via hole HARV2 is 15 or more, but it is not limited thereto.

[0024] The first etching gas contains an oxygen-containing fluorocarbon. For example, the first etching gas contains a substance having a chemical formula of CxFyOz (1 ≤ x ≤ 5, 2x - 2 ≤ y ≤ 2x + 2, 1 ≤ z < x, where x, y, and z are natural numbers). For example, the first etching gas contains a substance having an ether structure such as trifluoromethyl R(1)-O-CR(2)=CR(3)R(4) (R(1), R(2), R(3), R(4)=CaFb, 0 ≤ a ≤ 3, b = 2a + 1, where a and b are natural numbers), for example, trifluorovinyl ether (CF3OCFCF2), pentafluoroethyl trifluorovinyl ether (C4F8O), and decafluoropropyl vinyl ether (C5F 10 O), and includes at least one of them.

[0025] The etching process using the first etching gas is a low-temperature plasma etching process. The etching process using the first etching gas is performed at 0°C or lower and -100°C or higher. The etching process using the first etching gas uses inductively coupled plasma (ICP), capacitively coupled plasma (CCP), helicon wave plasma, or electron cyclotron resonance plasma (ECR), etc.

[0026] In addition to the first etching gas, a second etching gas may be further included in the etching process. The second etching gas may include a single type of molecule or two or more types of molecules. For example, the second etching gas may include at least one of hydrogen (H), hydrogen fluoride (HF), nitrogen fluoride, phosphorous fluoride, sulfur fluoride, fluorocarbon, hydrofluorocarbon, and / or a gas containing a halogen element.

[0027] For example, nitrogen fluorides include nitrogen trifluoride (NF3). For example, phosphorus fluorides include phosphorus trifluoride (PF3) or phosphorus pentafluoride (PF5). For example, sulfur fluorides include sulfur hexafluoride (SF6) or sulfur tetrafluoride (SF4). Carbon fluorides include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), or octafluoropropane (C3F8). For example, hydrofluorocarbons include monofluoromethane (CHF3), difluoromethane (CH2F2), etc. For example, gases containing halogen elements include hydrogen bromide (HBr) and / or chlorine (Cl2).

[0028] When forming the high-aspect-ratio first via hole HARV1 and the second via hole HARV2 using a fluorocarbon or hydrofluorocarbon, the etching rate of the first insulating film DI1 may differ from the etching rate of the second insulating film DI2. For example, when the first insulating film DI1 and the third insulating film DI3 contain silicon oxide and the second insulating film DI2 contains silicon nitride, the etching rate of the first insulating film DI1 and the third insulating film DI3 may be lower than the etching rate of the second insulating film DI2. Therefore, when simultaneously forming the first via hole HARV1 and the second via hole HARV2 using an etching process, the second via hole HARV2 may not yet be formed in the second mold structure MO2 when the first via hole HARV1 is formed in the first mold structure MO1. This is because the first mold structure MO1 has a structure in which the first insulating film DI1 and the second insulating film DI2, which have different etching rates with fluorocarbon and hydrofluorocarbon, are alternately stacked, and the second mold structure MO2 includes only a single third insulating film DI3. The third insulating film DI3 contains the same material as the first insulating film DI1. For these reasons, it is difficult to simultaneously form the first via hole HARV1 and the second via hole HARV2, increasing the difficulty and cost of the manufacturing process. Furthermore, because the second via hole HARV2 may not be completely formed when the first via hole HARV1 is formed, the electrical connection of components formed in subsequent processes becomes unstable. This can degrade the electrical characteristics and reliability of the semiconductor device.

[0029] The manufacturing method of a semiconductor device using a low-temperature plasma etching process according to the present invention includes a first etching gas during the etching process. The first etching gas includes a fluorocarbon containing oxygen. For example, the first etching gas includes a substance having a chemical formula of CxFyOz (1≦x≦5, 2x - 2≦y≦2x + 2, 1≦z<x, where x, y, and z are natural numbers). For example, the first etching gas includes a substance having an ether structure such as trifluoromethyl R(1)-O-CR(2)=CR(3)R(4) (R(1), R(2), R(3), R(4)=CaFb, 0≦a≦3, b = 2a + 1, where a and b are natural numbers), for example, trifluorovinyl ether (CF3OCFCF2), pentafluoroethyl trifluorovinyl ether (C4F8O), and decafluoropropyl vinyl ether (C5F 10 O), and includes at least one of them.

[0030] During the etching process, the flow rate of the first etching gas supplied to the first mold structure MO1 and the second mold structure MO2 is adjusted fluidly. As an example, when the sum of the flow rates of the gases excluding the first etching gas is 100, the flow rate ratio of the first etching gas is 100:20 to 100:40. As will be described later, when the sum of the flow rates of the gases excluding the first etching gas is 100 and the flow rate of the first etching gas is in the flow rate ratio of 100:20 to 100:40, the effects of the present invention are most significantly achieved.

[0031] When the first etching gas is used to form the high-aspect-ratio first via hole HARV1 and the second via hole HARV2, the difference in etching rate between the first insulating film DI1 and the second insulating film DI2 is reduced. When the first etching gas is used to form the high-aspect-ratio first via hole HARV1 and the second via hole HARV2, the difference in etching rate between the third insulating film DI3 and the second insulating film DI2 is reduced. For example, when the first insulating film DI1 and the third insulating film DI3 contain silicon oxide and the second insulating film DI2 contains silicon nitride, the difference in etching rate between the first insulating film DI1 and the third insulating film DI3 and the second insulating film DI2 is reduced. Therefore, when the first via hole HARV1 and the second via hole HARV2 are simultaneously formed by an etching process, the second via hole HARV2 can also be formed in the second mold structure MO2 at the same time as the first via hole HARV1 is formed in the first mold structure MO1. For these reasons, the difficulty and cost of the semiconductor device manufacturing process are reduced. Furthermore, since the second via hole HARV2 is completely formed when the first via hole HARV1 is formed, electrical connections between components formed in subsequent processes are stabilized, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0032] If the difference between the etching rates of the first insulating film DI1 and the second insulating film DI2 is large, it is difficult to form the first via hole HARV1 by etching the first mold structure MO1. This is because even a slight change in the process conditions can result in the etching depth being deeper or shallower than the target depth. In contrast, according to the present invention, the difference between the etching rates of the first insulating film DI1 and the third insulating film DI3 and the second insulating film DI2 is reduced. This reduces the difficulty of the manufacturing method for forming the first via hole HARV1 in a structure in which different insulating films are alternately stacked, such as the first mold structure MO1.

[0033] In addition, when the first mask pattern PM includes a silicon-based or carbon-based material and a fluorocarbon containing oxygen is used as the first etching gas, the etching rate of the first mask pattern PM decreases, thereby improving the etching selectivity of the first mask pattern PM compared to the first through third insulating films DI1, DI2, and DI3.

[0034] In the method for manufacturing a semiconductor device using a low-temperature plasma etching process according to the present invention, the etching process is performed at a temperature range of 0°C or below and -100°C or above. This reduces the surface temperature of the component undergoing the etching process, thereby increasing the adsorption rate of the etching gas (e.g., the first etching gas) present as a gas, thereby increasing the etching rate. Furthermore, the low temperature reduces unwanted surface chemical reactions. For these reasons, the selectivity between the etching target and the etching mask can be improved, and horizontal etching can be prevented.

[0035] When hydrogen is used as the second etching gas, the etching rate is significantly improved. When a gas containing a fluorocarbon, hydrofluorocarbon, or halogen element is used as the second etching gas, the inner surface of the component to be etched can be protected during the etching process.

[0036] 1 and 2D, a step (S4) of removing the first mask pattern PM is performed in the semiconductor device in a third state (WF-3 in FIG. 2C). Next, a first via VIA1 filling the first via hole (HARV1 in FIG. 2C) and a second via VIA2 filling the second via hole (HARV2 in FIG. 2C) are formed. The first via VIA1 and the second via VIA2 have a high aspect ratio. The first via VIA1 and the second via VIA2 include, but are not limited to, a conductive material.

[0037] The flow rate conditions for the etching gas types in the comparative examples and experimental examples are as shown in Table 1 below.

[0038] [Table 1]

[0039] Both the comparative example and the experimental example were performed at a temperature of -30°C. In both the comparative example and the experimental example, a SiO2 film, SiN film, Si film, or ACL film was deposited on a wafer substrate, and then a low-temperature plasma etching process was performed on the wafer substrate. The gases used in the etching process were supplied to the wafer substrate. A silicon substrate was used as the wafer substrate. An inductively coupled plasma was used as the plasma source. The comparative example used CF4 as the etching gas, and the experimental example used CF3OCFCF2 as the etching gas, except that all other conditions were the same. In the comparative example and the experimental example, H2, CH2F2, and Cl2 were all supplied to the wafer in common, and the flow rates of each gas were the same in both the comparative example and the experimental example. The flow rates were measured in sccm.

[0040] The etching rates of SiO2, SiN, Si, and ACL in the comparative examples and experimental examples are shown in Table 2 below.

[0041] [Table 2]

[0042] The results of the ratio of the etching rate of the SiO2 film to the etching rate of the SiN film and the ratio of the etching rate of the SiO2 film to the etching rate of the Si film in the comparative example and the experimental example are as shown in Table 3. In other words, the etching rate ratio may also be called the etching selectivity ratio.

[0043] [Table 3]

[0044] Referring to Table 2, the etching rates of both the SiO2 film and the SiN film were lower in the experimental example than in the comparative example. However, the decrease in the etching rate of the SiN film was greater than the decrease in the etching rate of the SiO2 film. Referring to Table 3, the ratio of the etching rate of the SiO2 film to the etching rate of the SiN film was higher in the experimental example than in the comparative example. From the above results, it can be seen that the difference between the etching rates of the SiO2 film and the SiN film was smaller in the experimental example than in the comparative example.

[0045] Fig. 3 is a diagram showing the etching rates of a SiO2 film, a SiN film, a Si film, and an ACL (Amorphous Carbon Layer) film as a function of the CF4 gas flow rate in a comparative example. Fig. 4 is a diagram showing the etching rates of a SiO2 film, a SiN film, a Si film, and an ACL film as a function of the CF3OCFCF2 gas flow rate in an experimental example.

[0046] Referring to Figure 3, the etch rates of the SiO2 film, SiN film, Si film, and ACL film in the comparative example are plotted against the CF4 gas flow rate. The experimental conditions for the comparative example were the same as those in Table 1, except that the CF4 gas flow rate was changed to 0, 10, 20, 30, or 60 sccm. Figure 3 shows that as the CF4 gas flow rate increased, the etch rates (Å / min) of both the SiO2 film and the SiN film increased. Therefore, the difference between the etch rates of the SiO2 film and the SiN film did not change significantly with the CF4 gas flow rate.

[0047] FIG. 4 shows the etch rates of SiO2, SiN, Si, and ACL films as a function of the CF3OCFCF2 gas flow rate in an experimental example. The experimental conditions in the experimental example were the same as those in Table 1, except that the CF3OCFCF2 gas flow rate was changed to 0, 10, 20, 30, or 60 sccm. FIG. 4 shows that the difference between the etch rates of SiO2 and SiN films decreases when the CF3OCFCF2 gas flow rate is 20, 30, or 40 sccm. These experimental results show that when the sum of the flow rates of the gases excluding CF3OCFCF2 (CF4, H2, CH2F2, and Cl2) is 100, and the CF3OCFCF2 flow rate is 100:20 to 100:40, the effect of reducing the difference between the etch rates of SiO2 and SiN films is significant.

[0048] 5 is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line AA' in FIG.

[0049] 5 and 6, a semiconductor device 1000 includes a second substrate 100, a first insulating pattern 12, a conductive contact 14, an etch stop pattern 16, a capacitor CA, a lower support pattern LS, and an upper support pattern US. The capacitor CA includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE.

[0050] A second substrate 100 is provided. The second substrate 100 corresponds to the semiconductor structure SST in FIGS. 2A to 2D. The second substrate 100 is a semiconductor substrate. Alternatively, the second substrate 100 may have a DRAM device structure. Thus, the semiconductor device 1000 may be a DRAM device.

[0051] The first insulating pattern 12 is disposed on the second substrate 100. The first insulating pattern 12 covers at least a portion of the top surface of the second substrate 100. For example, the first insulating pattern 12 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride. For another example, the first insulating pattern 12 includes an empty region.

[0052] It should be understood that the terms "first," "second," and "third" used in this specification are merely names used to distinguish between components, and do not indicate a manufacturing order or positional characteristics between the components.

[0053] The conductive contacts 14 are disposed on the second substrate 100. There may be a plurality of conductive contacts 14, and the plurality of conductive contacts 14 are spaced apart from one another in a first horizontal direction D1 and a second horizontal direction D2. The plurality of conductive contacts 14 are spaced apart from one another via a first insulating pattern 12. In FIGS. 5 to 14, the first horizontal direction D1 and the second horizontal direction D2 are parallel to the top surface of the second substrate 100 and intersect with each other (for example, perpendicular to each other). The vertical direction D3 is perpendicular to the top surface of the second substrate 100.

[0054] The conductive contacts 14 include at least one of an impurity-doped semiconductor material (e.g., polycrystalline silicon), a metal-semiconductor compound (e.g., tungsten silicide), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), or a metal (e.g., titanium, tungsten, or tantalum). The conductive contacts 14 are electrically connected to impurity regions (e.g., source / drain terminals) formed in the second substrate 100.

[0055] The etch stop pattern 16 is disposed on the first insulating pattern 12. The etch stop pattern 16 covers the first insulating pattern 12 and exposes the conductive contact 14. The etch stop pattern 16 includes at least one of silicon oxide, SiCN, or SiBN.

[0056] The bottom electrode BE is disposed on the conductive contact 14. The bottom electrode BE is connected to the conductive contact 14. The bottom electrode BE extends in a vertical direction Z. The vertical direction Z is a direction perpendicular to the upper surface of the second substrate 100. The bottom electrode BE has a pillar shape. There may be a plurality of bottom electrodes BE, and the plurality of bottom electrodes BE are spaced apart from each other in a first horizontal direction D1 and a second horizontal direction D2. In a plan view, as an example, the bottom electrodes BE are arranged in a honeycomb shape. In particular, six bottom electrodes BE are arranged to surround one bottom electrode BE in a hexagonal shape, with one bottom electrode BE at the center.

[0057] The bottom electrode BE includes a conductive material, such as silicon (Si), a metal material (e.g., cobalt, titanium, nickel, tungsten, and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN, TaAlN), and tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SrO (SrRuO3), SrO ((Ba,Sr)RuO3), CaRuO (CaRuO3), and LsCo), or a metal silicide.

[0058] The upper support pattern US and the lower support pattern LS are provided on the second substrate 100. The upper support pattern US and the lower support pattern LS are spaced apart from each other in the vertical direction D3. The upper support pattern US is located higher than the lower support pattern LS. Although not shown, additional support patterns spaced apart from each other in the vertical direction D3 may be provided, with the uppermost support pattern being referred to as the upper support pattern US. As an example, three support patterns spaced apart from each other in the vertical direction D3 may be provided, with the uppermost support pattern being referred to as the upper support pattern US. The upper support pattern US and the lower support pattern LS are provided between adjacent lower electrodes BE. The upper support pattern US and the lower support pattern LS contact the side surfaces of the lower electrode BE and surround the side surfaces of the lower electrode BE. The upper support pattern US and the lower support pattern LS physically support the lower electrode BE. The thickness of the upper support pattern US along the vertical direction D3 is different from the thickness of the lower support pattern LS along the vertical direction D3. Each of the upper support pattern US and the lower support pattern LS includes, for example, at least one of silicon nitride, SiBN, and SiCN.

[0059] Through holes PH are arranged between adjacent bottom electrodes BE. For example, the through holes PH are arranged in a circular shape between three adjacent bottom electrodes BE, exposing a portion of a side surface of each of the three bottom electrodes BE. However, the present invention is not limited thereto, and the through holes PH may be arranged between the plurality of bottom electrodes BE in various shapes. The through holes PH penetrate the upper support pattern US and the lower support pattern LS. The through holes PH expose the etch stop pattern 16. There may be a plurality of through holes PH, and the plurality of through holes PH are spaced apart from each other in the first horizontal direction D1 and the second horizontal direction D2.

[0060] A dielectric film DL is provided on the upper support pattern US, the lower support pattern LS, the bottom electrode BE, and the etch stop pattern 16. The dielectric film DL conformally covers the upper support pattern US, the lower support pattern LS, the bottom electrode BE, and the etch stop pattern 16. The dielectric film DL contacts the top surface of the bottom electrode BE. The dielectric film DL fills a portion of the through-hole PH. The dielectric film DL in contact with the bottom electrode BE has the same crystalline structure as the bottom electrode BE. For example, the dielectric film DL has a tetragonal structure. The dielectric film DL is formed of a single film or a combination of films selected from a combination of metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, and perovskite-structured dielectric materials such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT.

[0061] An upper electrode TE is provided on the dielectric film DL. The upper electrode TE covers the lower electrode BE, the upper support pattern US, and the lower support pattern LS. The upper electrode TE fills the remainder of the through-hole PH, the gap between the upper support pattern US and the lower support pattern LS, and the gap between the lower support pattern LS and the etch stop pattern 16. The dielectric film DL is interposed between the lower electrode BE and the upper electrode TE, between the upper support pattern US and the upper electrode TE, and between the lower support pattern LS and the upper electrode TE. The dielectric film DL is interposed between the top surface of the lower electrode BE and the upper electrode TE.

[0062] The top electrode TE includes at least one of titanium nitride, impurity-doped polysilicon, and impurity-doped silicon germanium. The top electrode TE may be a single layer or a multi-layer. The bottom electrode BE, the dielectric layer DL, and the top electrode TE constitute a capacitor CA. For example, the capacitor CA may function as an information storage element so that the semiconductor device 1000 according to the present invention operates as a memory device.

[0063] 7 and 12 are plan views showing a method for manufacturing the semiconductor device of Fig. 6, and Figs. 8 to 11 and Figs. 13 and 14 are cross-sectional views showing a method for manufacturing the semiconductor device of Fig. 6. Hereinafter, a method for manufacturing the semiconductor device 1000 according to Fig. 6 will be described with reference to Figs. 7 to 14. For the sake of simplicity, a description of the same content as above will be omitted.

[0064] 7 and 8, a second substrate 100 is provided. A first insulating pattern 12 is formed on the second substrate 100. A conductive contact 14 is formed in the first insulating pattern 12. An etch stop layer 16L is formed on the second substrate 100. The etch stop layer 16L is formed to cover the top surfaces of the first insulating pattern 12 and the conductive contact 14.

[0065] A third mold structure MO3 is formed on the etch stop layer 16L. The third mold structure MO3 is formed by alternately stacking various insulating materials. For example, the third mold structure MO3 is formed by sequentially stacking a first mold film 20, a lower support film 22, a second mold film 24, and an upper support film 26. The lower support film 22 includes a material that has etching selectivity with respect to the first mold film 20. The upper support film 26 includes a material that has etching selectivity with respect to the second mold film 24. The first mold film 20 and the second mold film 24 include the same material. For example, the first mold film 20 and the second mold film 24 include silicon oxide. The lower support film 22 and the upper support film 26 include the same material. For example, the lower support film 22 and the upper support film 26 include at least one of silicon nitride, SiBN, and SiCN.

[0066] A first mask film 40 and a second mask pattern 42 are sequentially formed on the third mold structure MO3. The first mask film 40 covers the upper support film 26. The first mask film 40 includes, for example, at least one of polysilicon, silicon nitride, and silicon oxynitride. The second mask pattern 42 is formed on the first mask film 40 and has third openings OP3. There may be multiple third openings OP3, and portions of the upper surface of the first mask film 40 are exposed through the third openings OP3. The multiple third openings OP3 vertically overlap the conductive contacts 14. The second mask pattern 42 includes, for example, at least one of a spin-on hard mask (SOH), an amorphous carbon layer (ACL), and polycrystalline silicon.

[0067] Referring to FIG. 9, an etching process can be performed on the first mask film 40, the third mold structure MO3, and the etch stop film 16L using the second mask pattern 42 as an etching mask. The etching process uses a low-temperature plasma etching process. The method for performing the etching process is the same as the etching process using the low-temperature plasma etching process described with reference to FIGS. 1 to 2D. For example, the first etching gas used in the etching process includes CF3OCFCF2. For simplicity, a description of the etching process using the low-temperature plasma etching process described with reference to FIGS. 1 to 2D will be omitted.

[0068] As a result, a third via hole HARV3 having a shape similar to the third opening OP3 in a plan view may be formed. A plurality of third via holes HARV3 may be formed according to the third opening OP3. The third via holes HARV3 penetrate the third mold structure MO3 and the etching stop layer 16L in the vertical direction D3 to expose the top surfaces of the conductive contacts 14. After the etching process, the remaining unetched portions of the etching stop layer 16L constitute the etching stop pattern 16. For example, the first mask film 40 and the second mask pattern 42 are removed by a separate removal process after the etching process.

[0069] A method for manufacturing a semiconductor device according to the present invention includes forming a third mold structure MO3 including a first mold film 20, a lower support film 22, a second mold film 24, and an upper support film 26 on a second substrate 100, forming a second mask pattern 42 on the third mold structure MO3, and performing a low-temperature plasma etching process using the second mask pattern 42 as an etching mask. The first mold film 20 and the second mold film 24 are made of the same material, and the lower support film 22 and the upper support film 26 are made of the same material. For example, the first mold film 20 and the second mold film 24 are made of silicon oxide, and the lower support film 22 and the upper support film 26 are made of silicon nitride. That is, the third mold structure MO3 has a structure in which different insulating materials are alternately stacked, similar to the first mold structure MO1 in FIGS. 1 through 2D. The first etching gas described with reference to FIGS. 1 through 2D may be used in the low-temperature plasma etching process. Therefore, the difference between the etching rate of the first mold film 20 and the second mold film 24 and the etching rate of the lower support film 22 and the upper support film 26 can be reduced, thereby reducing the difficulty and cost of the manufacturing method for forming the third via hole HARV3. As a result, the difficulty and cost of the manufacturing method for the semiconductor device 1000 can be reduced.

[0070] 10, a first bottom electrode film 50 is formed on the third mold structure MO3 and fills the third via hole HARV3. The first bottom electrode film 50 covers the exposed upper surfaces of the conductive contacts 14 and the upper support film 26. For example, the first bottom electrode film 50 is formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

[0071] The first lower electrode film 50 includes at least one of silicon (Si), a metal material (e.g., cobalt, titanium, nickel, tungsten, and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN, TaAlN), and tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), or a metal silicide.

[0072] 11, a portion of the upper portion of the first lower electrode film 50 is removed. A lower electrode BE is formed from the first lower electrode film 50. Removing the upper portion of the first lower electrode film 50 may, for example, include performing an etch-back process. The lower electrode BE penetrates the third mold structure MO3 in the vertical direction D3 and is electrically connected to the conductive contact 14. For example, the lower electrode BE is formed to have a pillar shape. The upper portion of the third via hole HARV3 may not be filled with the lower electrode BE.

[0073] 12 and 13, a second mask film 60 and a third mask pattern 62 are sequentially formed on the third mold structure MO3 and the lower electrode BE. The second mask film 60 covers the upper support film 26 and the lower electrode BE. The third mask pattern 62 is formed on the second mask film 60 and has a fourth opening OP4. There may be multiple fourth openings OP4. A portion of the upper surface of the second mask film 60 is exposed through the fourth opening OP4. The second mask film 60 includes, for example, polysilicon. The third mask pattern 62 includes, for example, photoresist.

[0074] 14, the second mask film 60 and the upper support film 26 are anisotropically etched using the third mask pattern 62 as an etching mask. This removes a portion of the second mask film 60 and a portion of the upper support film 26 that vertically overlap the fourth opening OP4. The remaining portion of the upper support film 26 forms the upper support pattern US. Through holes PH are formed through the upper support pattern US. The through holes PH may be multiple and vertically overlap the fourth opening OP4. A portion of the upper surface of the second mold film 24 is exposed through the through holes PH.

[0075] Next, the second mold film 24 is removed. This may expose the bottom surfaces of the upper support patterns US, portions of the side surfaces of the lower electrodes BE, and the top surface of the lower support film 22. The removal process of the second mold film 24 includes an isotropic etching process. Phosphoric acid (H3PO4) may be used to perform the isotropic etching process. As an example, but not limited to, the remaining portions of the second mask film 60 are removed before removing the second mold film 24. After the second mold film 24 is removed, the through holes PH extend to the top surface of the lower support film 22.

[0076] A portion of lower support film 22 that vertically overlaps with through-hole PH is etched to expose a portion of the upper surface of first mold film 20. The remaining portion of lower support film 22 constitutes lower support pattern LS. Through-hole PH extends into lower support pattern LS and further penetrates lower support pattern LS.

[0077] Next, the first mold film 20 is removed, thereby exposing the bottom surfaces of the lower support patterns LS, the remaining side surfaces of the lower electrodes BE, and the top surfaces of the etch stop patterns 16. The removal process of the first mold film 20 includes an isotropic etching process. Phosphoric acid (H3PO4) may be used to perform the isotropic etching process.

[0078] 6, a dielectric layer DL is formed on the upper support pattern US, the lower support pattern LS, the bottom electrode BE, and the etch stop pattern 16. The dielectric layer DL conformally covers the upper support pattern US, the lower support pattern LS, the bottom electrode BE, and the etch stop pattern 16. The dielectric layer DL fills a portion of the through hole PH.

[0079] The dielectric film DL in contact with the bottom electrode BE may be formed to have the same crystal structure as the bottom electrode BE. For example, the dielectric film DL may be formed to have a tetragonal structure. The dielectric film DL may be formed by a deposition technique with excellent step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0080] An upper electrode TE is formed on the dielectric film DL. The upper electrode TE fills the remaining portion of the through-hole PH and covers the lower electrode BE. The upper electrode TE may fill between the lower electrode BE and an adjacent lower electrode BE, between the upper support pattern US and the lower support pattern LS, and between the lower support pattern LS and the etching stop pattern 16. By forming the upper electrode TE, the dielectric film DL may be interposed between the lower electrode BE and the upper electrode TE. The lower electrode BE, the dielectric film DL, and the upper electrode TE constitute a capacitor CA.

[0081] Fig. 15 is a plan view showing a semiconductor device according to an embodiment of the present invention, Fig. 16A is a cross-sectional view taken along line BB' in Fig. 15, and Fig. 16B is a cross-sectional view taken along line CC' in Fig. 15.

[0082] 15, 16A and 16B, a semiconductor device 2000 according to the present invention includes a second substrate 100, a peripheral circuit structure PS on the second substrate 100, and a cell array structure CS on the peripheral circuit structure PS.

[0083] 15 to 16B, a first horizontal direction X is defined as a direction parallel to the top surface of the second substrate 100, a second horizontal direction Y is defined as a direction parallel to the top surface of the second substrate 100 and perpendicular to the first horizontal direction X, and a vertical direction Z is defined as a direction perpendicular to the top surface of the second substrate 100.

[0084] The second substrate 100 extends in a first horizontal direction X and a second horizontal direction Y from the cell array region CAR toward the contact region CCR. In a plan view, the contact region CCR extends from the cell array region CAR in the first horizontal direction X (or in the direction opposite to the first horizontal direction X). Contrary to what is shown, the contact region CCR may extend from the cell array region CAR in the second horizontal direction Y (or in the direction opposite to the second horizontal direction Y).

[0085] The second substrate 100 is, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. An isolation layer 110 is provided in the second substrate 100. The isolation layer 110 defines an active region of the second substrate 100. The isolation layer 110 includes, for example, silicon oxide.

[0086] A peripheral circuit structure PS is provided on the second substrate 100. The peripheral circuit structure PS includes a peripheral circuit transistor PTR on an active region of the second substrate 100, a peripheral contact plug 190, a peripheral circuit wiring 195 electrically connected to the peripheral circuit transistor PTR via the peripheral contact plug 190, and a peripheral circuit insulating film 130 surrounding these.

[0087] The peripheral circuit transistors PTR, the peripheral contact plugs 190, and the peripheral circuit wiring 195 constitute a peripheral circuit. The peripheral circuit transistors PTR function to facilitate the operation of the semiconductor device 2000. More specifically, each of the peripheral circuit transistors PTR includes a peripheral gate insulating film 140, a peripheral gate electrode 150, a peripheral capping pattern 160, a peripheral gate spacer 170, and a peripheral source / drain region 180.

[0088] The peripheral gate insulating film 140 is provided between the peripheral gate electrode 150 and the second substrate 100. The peripheral capping pattern 160 is provided on the peripheral gate electrode 150. The peripheral gate spacers 170 cover the sidewalls of the peripheral gate insulating film 140, the peripheral gate electrode 150, and the peripheral capping pattern 160. Peripheral source / drain regions 180 are provided within the second substrate 100 adjacent to both sides of the peripheral gate electrode 150.

[0089] The peripheral circuit wiring 195 is electrically connected to the peripheral circuit transistors PTR via the peripheral contact plugs 190. Each of the peripheral circuit transistors PTR may be, for example, an NMOS transistor or a PMOS transistor. Each of the peripheral circuit transistors PTR may be a planar transistor or a gate-all-around transistor. For example, the width of the peripheral contact plugs 190 in the first horizontal direction X or the second horizontal direction Y increases as the peripheral contact plugs 190 move farther away from the second substrate 100 in the vertical direction Z. The peripheral contact plugs 190 and the peripheral circuit wiring 195 include a conductive material such as a metal.

[0090] The peripheral circuit insulating film 130 is provided on the upper surface of the second substrate 100. The peripheral circuit insulating film 130 covers the peripheral circuit transistor PTR, the peripheral contact plug 190, and the peripheral circuit wiring 195 on the second substrate 100. The peripheral circuit insulating film 130 includes a plurality of insulating films having a multi-layer structure. For example, the peripheral circuit insulating film 130 includes silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material.

[0091] A cell array structure CS including a third substrate 200 and a stack structure ST on the third substrate 200 is provided on the peripheral circuit insulating film 130. The third substrate 200 extends in a first horizontal direction X and a second horizontal direction Y. The third substrate 200 may not be provided on a portion of the contact region CCR. The third substrate 200 is a semiconductor substrate including a semiconductor material. The third substrate 200 includes at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0092] A stacked structure ST is provided on the third substrate 200. The stacked structure ST extends from the cell array region CAR to the contact region CCR. A plurality of stacked structures ST are provided, and the stacked structures ST are arranged along the second horizontal direction Y and spaced apart from each other in the second horizontal direction Y by isolation structures 350. For convenience of explanation, only one stacked structure ST will be described below, but the following description may be applied to other stacked structures ST as well.

[0093] The stacked structure ST includes interlayer insulating films ILD and gate electrodes EL, which are stacked alternately. The vertical thickness of each gate electrode EL is substantially the same. Hereinafter, the thickness refers to the thickness in the vertical direction Z.

[0094] The length of the gate electrodes EL in the first horizontal direction X decreases as the gate electrodes EL become farther from the third substrate 200 in the vertical direction Z. In other words, the length of each gate electrode EL in the first horizontal direction X is greater than the length in the first horizontal direction X of the electrode located immediately above it. The lowermost gate electrodes EL of the stacked structure ST have the longest length in the first horizontal direction X, and the uppermost gate electrodes EL have the shortest length in the first horizontal direction X.

[0095] The gate electrodes EL have pad portions ELp on the contact regions CCR. The pad portions ELp of the gate electrodes EL are arranged at different positions in the horizontal and vertical directions. The pad portions ELp form a stepped structure along the first horizontal direction X. The thickness of the pad portions ELp is greater than the thickness of other portions of the gate electrodes EL.

[0096] Due to the stepped structure, the thickness of the stacked structure ST decreases as it moves away from the outermost one of the first vertical channel structures VS1 in the first horizontal direction X, and the sidewalls of the gate electrode EL are spaced apart at regular intervals along the first horizontal direction X in a plan view.

[0097] The gate electrode EL includes at least one of a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, aluminum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), and a transition metal (e.g., titanium, tantalum). More preferably, the gate electrode EL includes tungsten.

[0098] The interlayer insulating film ILD is provided between the gate electrodes EL. That is, like the gate electrodes EL, the length of the interlayer insulating film ILD in the first horizontal direction X decreases as it moves away from the third substrate 200 in the vertical direction Z.

[0099] For example, the thickness of each interlayer insulating film ILD is smaller than the thickness of each gate electrode EL. For example, the thickness of the uppermost interlayer insulating film ILD is larger than the thickness of each of the other interlayer insulating films ILD. For example, the thickness of the lowermost interlayer insulating film ILD is smaller than the thickness of each of the other interlayer insulating films ILD.

[0100] Except for the bottom and top interlayer dielectric layers ILD, the other interlayer dielectric layers ILD have substantially the same thickness, although this is merely an example and the thickness of the interlayer dielectric layers ILD may vary depending on the characteristics of the semiconductor device 2000.

[0101] The interlayer dielectric film ILD may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material, such as high-density plasma oxide (HDP oxide) or tetra ethyl orthosilicate (TEOS).

[0102] A source structure SC may be provided in the cell array region CAR between the third substrate 200 and the lowermost one of the interlayer dielectric films ILD, and extend from the cell array region CAR to the contact region CCR.

[0103] The source structure SC includes a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on the third substrate 200. The second source conductive pattern SCP2 may be provided between the first source conductive pattern SCP1 and the lowest one of the interlayer dielectric films ILD. The thickness of the first source conductive pattern SCP1 is greater than the thickness of the second source conductive pattern SCP2.

[0104] The first and second source conductive patterns SCP1 and SCP2 include a semiconductor material such as silicon or a semiconductor material doped with impurities. When the first and second source conductive patterns SCP1 and SCP2 include a semiconductor material doped with impurities, the impurity concentration of the first source conductive pattern SCP1 may be greater than the impurity concentration of the second source conductive pattern SCP2.

[0105] A plurality of first vertical channel structures VS1 may be provided on the cell array region CAR, penetrating the stack structure ST and the source structures SC. The first vertical channel structures VS1 may penetrate at least a portion of the third substrate 200, and the lower surface of each first vertical channel structure VS1 may be located at a lower level than the upper surface of the third substrate 200 and the lower surfaces of the source structures SC. That is, the first vertical channel structures VS1 may be in direct contact with the third substrate 200.

[0106] 15, the first vertical channel structures VS1 are arranged in a zigzag pattern along the first horizontal direction X or the second horizontal direction Y. The first vertical channel structures VS1 may not be provided on the contact regions CCR.

[0107] The first vertical channel structure VS1 is provided in a vertical channel hole CH penetrating the stack structure ST. As the first vertical channel structure VS1 extends in the vertical direction Z, its width in the first horizontal direction X or the second horizontal direction Y is constant. Alternatively, as the first vertical channel structure VS1 extends in the vertical direction Z, its width in the first horizontal direction X or the second horizontal direction Y increases.

[0108] Each first vertical channel structure VS1 includes a data storage pattern DSP and a vertical semiconductor pattern VSP sequentially provided on the inner wall of the vertical channel hole CH, a buried insulating pattern VI filling the inner space surrounded by the vertical semiconductor pattern VSP, and a conductive pad PAD on the buried insulating pattern VI. The conductive pad PAD is provided in the space surrounded by the buried insulating pattern VI and the data storage pattern DSP (or the vertical semiconductor pattern VSP). The top surface of each first vertical channel structure VS1 has, for example, a circular, elliptical, or bar shape. The data storage pattern DSP is adjacent to the sidewalls of the interlayer dielectric layer ILD and the sidewalls of the gate electrode EL. Although not shown, a barrier layer is interposed between the data storage pattern DSP and the gate electrode EL. The barrier layer includes a metal oxide (e.g., aluminum oxide (Al2O3)). The vertical semiconductor pattern VSP conformally covers the inner wall of the data storage pattern DSP.

[0109] The vertical semiconductor pattern VSP is provided between the data storage pattern DSP and the buried insulating pattern VI. The vertical semiconductor pattern VSP has a pipe shape or a macaroni shape with a closed bottom. The data storage pattern DSP has a pipe shape or a macaroni shape with an open bottom.

[0110] The vertical semiconductor pattern VSP includes, for example, a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. The vertical semiconductor pattern VSP contacts a portion of the source structure SC. Specifically, the vertical semiconductor pattern VSP contacts the first source conductive pattern SCP1 of the source structure SC. The conductive pad PAD includes, for example, a semiconductor material doped with impurities or a conductive material.

[0111] Although not shown in FIGS. 16A and 16B , a plurality of second vertical channel structures VS2 are provided on the contact region CCR, penetrating the planarization insulating film 250, the stack structure ST, and the source structure SC. More specifically, the second vertical channel structures VS2 penetrate the pad portion ELp of the gate electrode EL. The second vertical channel structures VS2 are provided around the first through structures C1. The second vertical channel structures VS2 may not be provided on the cell array region CAR. The second vertical channel structures VS2 are formed simultaneously with the first vertical channel structures VS1 and have substantially the same structure. However, depending on the embodiment, the second vertical channel structures VS2 may not be provided.

[0112] A planarization insulating film 250 is provided on the contact region CCR, covering the stacked structure ST and a portion of the peripheral circuit insulating film 130. More specifically, the planarization insulating film 250 is provided on the pad portion ELp of the gate electrode EL while covering the stepped structure of the stacked structure ST. The planarization insulating film 250 has a substantially flat upper surface. The upper surface of the planarization insulating film 250 is substantially coplanar with the uppermost surface of the stacked structure ST. More specifically, the upper surface of the planarization insulating film 250 is substantially coplanar with the uppermost surface of the interlayer insulating film ILD of the stacked structure ST.

[0113] The planarization insulating film 250 may include a single insulating film or multiple stacked insulating films. The planarization insulating film 250 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material. The planarization insulating film 250 may include an insulating material different from that of the interlayer dielectric film ILD of the stacked structure ST. For example, if the interlayer dielectric film ILD of the stacked structure ST includes high-density plasma oxide, the planarization insulating film 250 may include TEOS.

[0114] First through structures C1 are provided in first through structure holes C1H that penetrate the planarization insulating film 250, the stack structure ST, the source structure SC, and the third substrate 200. Each of the first through structures C1 is in direct contact with one of the pad portions ELp of the gate electrode EL. Each of the first through structures C1 has a protrusion portion PTS at the same vertical level as one of the pad portions ELp of the gate electrode EL. The protrusion portion PTS is a portion that protrudes from the center of the first through structure C1 in the first horizontal direction X or the second horizontal direction Y.

[0115] Each of the first through structures C1 is connected to a peripheral circuit wiring 195 of the peripheral circuit structure PS. Each of the first through structures C1 is electrically connected to a peripheral circuit transistor PTR via the peripheral circuit wiring 195 and the peripheral contact plug 190.

[0116] Each of the first through structures C1 is adjacent to a plurality of second vertical channel structures VS2 and is spaced apart from each other in the horizontal direction (i.e., the first horizontal direction X or the second horizontal direction Y). The first through structures C1 are spaced apart from the isolation structures 350 in the second horizontal direction Y.

[0117] A first sidewall insulating pattern 202 is interposed between each of the first through structures C1 and the second substrate 100. The first sidewall insulating pattern 202 electrically insulates each of the first through structures C1 from the second substrate 100. The first sidewall insulating pattern 202 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0118] Except for one gate electrode EL that directly contacts the first through structure C1, second sidewall insulating patterns CID are disposed between each of the remaining gate electrodes EL and the first through structure C1. The second sidewall insulating patterns CID can electrically insulate the first through structure C1 from each of the remaining gate electrodes EL. The second sidewall insulating patterns CID can also be disposed between the source structures SC and the first through structure C1. The second sidewall insulating patterns CID can electrically insulate the source structures SC from the first through structure C1. The second sidewall insulating patterns CID include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0119] A second through structure C2 is provided in a second through structure hole C2H that penetrates at least a portion of the planarization insulating film 250 and the peripheral circuit insulating film 130. The second through structure C2 is electrically connected to the peripheral circuit transistor PTR of the peripheral circuit structure PS. Unlike the illustration, a plurality of second through structures C2 may be provided. The second through structure C2 is spaced apart from the third substrate 200, the source structure SC, and the stack structure ST in the first horizontal direction X. The second through structure C2 may be spaced apart from the isolation structure 350.

[0120] The top surfaces of the first vertical channel structure VS1, the second vertical channel structure VS2, the first through structure C1, and the second through structure C2 are all coplanar with one another.

[0121] An upper insulating film 260 is provided on the planarizing insulating film 250 and the stack structure ST. The upper insulating film 260 covers an upper surface of the planarizing insulating film 250, an upper surface of the uppermost layer of the interlayer insulating film ILD of the stack structure ST, and upper surfaces of the first and second vertical channel structures VS1 and VS2.

[0122] The upper insulating film 260 may include one insulating film or multiple stacked insulating films. The upper insulating film 260 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k material. The upper insulating film 260 may include, for example, substantially the same insulating material as the planarizing insulating film 250, but may include a different insulating material from the interlayer insulating film ILD of the stack structure ST.

[0123] Bit line contact plugs BLCP are provided to be connected to corresponding first vertical channel structures VS1 through the upper insulating film 260. First contact plugs C1CP are provided to be connected to corresponding first through structures C1 through the upper insulating film 260. Second contact plugs C2CP are provided to be connected to corresponding second through structures C2 through the upper insulating film 260.

[0124] A bit line BL connected to a corresponding bit line contact plug BLCP is provided on the upper insulating layer 260. A first conductive line CL1 connected to a corresponding first through structure C1 and a second conductive line CL2 connected to a corresponding second through structure C2 are provided on the upper insulating layer 260.

[0125] The bit line contact plug BLCP, the first through structure C1, the second through structure C2, the bit line BL, the first contact plug C1CP, the second contact plug C2CP, and the first and second conductive lines CL1 and CL2 may include a conductive material such as a metal. Although not shown, additional wiring and additional vias electrically connected to the bit line BL and the first and second conductive lines CL1 and CL2 may be provided on the upper insulating film 260.

[0126] When a plurality of stack structures ST are provided, an isolation structure 350 may be provided in an isolation trench TR that crosses between the plurality of stack structures ST in the first horizontal direction X. The isolation structure 350 is spaced apart from the first and second vertical channel structures VS1 and VS2 in the second horizontal direction Y.

[0127] The isolation structure 350 penetrates the stack structure ST and the second source conductive pattern SCP2. The height level of the upper surface of the isolation structure 350 is substantially the same as the height levels of the upper surfaces of the first and second vertical channel structures VS1 and VS2 and the first and second through structures C1 and C2. The lower surface of the isolation structure 350 may, for example, be substantially coplanar with the lower surface of the second source conductive pattern SCP2 and is located at a higher level than the upper surface of the third substrate 200.

[0128] A plurality of the isolation structures 350 are provided, and the isolation structures 350 are spaced apart from each other in the second horizontal direction Y via the stack structure ST.

[0129] The isolation structure 350 conformally covers the interlayer dielectric film ILD and the sidewall of the gate electrode EL. The isolation structure 350 includes, for example, silicon oxide.

[0130] 17A to 19B are views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which FIGS. 17A, 18A, and 19A are cross-sectional views taken along line B-B' in FIG. 15, and FIGS. 17B, 18B, and 19B are cross-sectional views taken along line CC' in FIG. 15.

[0131] 17A and 17B, a second substrate 100 including a cell array region CAR and a contact region CCR is provided. An isolation layer 110 defining an active region is formed in the second substrate 100. The isolation layer 110 is formed by forming a trench (not shown) in the upper portion of the second substrate 100 and filling the trench with silicon oxide.

[0132] A peripheral circuit transistor PTR is formed on an active region defined by the device isolation film 110. A peripheral contact plug 190 and a peripheral circuit wiring 195 are formed, the peripheral contact plug 190 being connected to a peripheral source / drain region 180 of the peripheral circuit transistor PTR. A peripheral circuit insulating film 130 is formed to cover the peripheral circuit transistor PTR, the peripheral contact plug 190, and the peripheral circuit wiring 195.

[0133] 18A and 18B, a third substrate 200 is formed on the peripheral circuit insulating film 130. The third substrate 200 extends from the cell array region CAR toward the contact region CCR.

[0134] A portion of the third substrate 200 above the contact region CCR is removed. The purpose of removing the portion of the third substrate 200 is to create a space in which the second penetrating structure C2 is provided.

[0135] A first sidewall insulating pattern 202 is formed in the third substrate 200. The first sidewall insulating pattern 202 defines a space in which a first through structure C1, which will be described later, will be formed.

[0136] A fourth mold structure MO4 is formed on the third substrate 200. Forming the fourth mold structure MO4 includes sequentially stacking a first buffer insulating film 351, a first semiconductor film 352, a second buffer insulating film 353, and a second semiconductor film 354 on the third substrate 200. The first and second buffer insulating films 351 and 353 are formed of, for example, silicon oxide. The first and second semiconductor films 352 and 354 are formed of, for example, a semiconductor material such as silicon.

[0137] A fifth mold structure MO5 is formed on the fourth mold structure MO4. Forming the fifth mold structure MO5 includes alternately stacking interlayer insulating films ILD and sacrificial films SL on the third substrate 200 one by one.

[0138] The third substrate 200 is exposed to the outside through the vertical channel hole CH. The bottom surface of the vertical channel hole CH is located at a level lower than the top surface of the third substrate 200.

[0139] The sacrificial layer SL is formed of an insulating material different from the interlayer dielectric layer ILD. The sacrificial layer SL is formed of a material having etching selectivity with respect to the interlayer dielectric layer ILD. For example, the sacrificial layer SL is formed of silicon nitride, and the interlayer dielectric layer ILD is formed of silicon oxide. The sacrificial layers SL are formed to substantially the same thickness, and the interlayer dielectric layer ILD may have a thickness that varies in some regions. The fifth mold structure MO5 is similar to the first mold structure MO1 described with reference to FIGS. 1 to 2D in that it has a structure in which different insulating layers (i.e., interlayer dielectric layers ILD and sacrificial layers SL) are alternately stacked one by one.

[0140] A trimming process is performed on the fifth mold structure MO5 on the contact region CCR. The trimming process includes forming a mask pattern (not shown) covering a portion of the top surface of the fifth mold structure MO5 in the cell array region CAR and the contact region CCR, patterning the fifth mold structure MO5 with the mask pattern, reducing the area of ​​the mask pattern, and patterning the fifth mold structure MO5 with the mask pattern having the reduced area. The process of reducing the area of ​​the mask pattern and patterning the fifth mold structure MO5 with the mask pattern is repeated alternately. As a result of the trimming process, the fifth mold structure MO5 has a stepped structure.

[0141] After the trimming process, preliminary pad portions SLp are formed, which are thicker than other portions of the sacrificial layers SL. The preliminary pad portions SLp are parts of the sacrificial layers SL and are formed at the ends of the sacrificial layers SL. The preliminary pad portions SLp are formed by removing parts of the interlayer dielectric layer ILD exposed to the outside in a stepped structure, depositing an additional material identical to the sacrificial layer SL, and etching the additional material so that it remains only on the interlayer dielectric layer ILD. As a result, the top surfaces of the preliminary pad portions SLp may be positioned at a higher level than the top surfaces of the other portions of the sacrificial layers SL connected to the preliminary pad portions SLp.

[0142] A planarization insulating film 250 is formed on the fifth mold structure MO5. The planarization insulating film 250 surrounds the fifth mold structure MO5. The planarization insulating film 250 covers the side surfaces of the fourth mold structure MO4, part of the upper surface and side surfaces of the third substrate 200, and part of the upper surface of the peripheral circuit insulating film 130. The planarization insulating film 250 covers the spare pad portions SLp of the fifth mold structure MO5.

[0143] 19A and 19B, the vertical channel holes CH, the first through structure holes C1H, the second through structure holes C2H, and the isolation trenches TR are simultaneously formed. The vertical channel holes CH, the first through structure holes C1H, the second through structure holes C2H, and the isolation trenches TR are formed by performing an etching process on the fifth mold structure MO5, the planarization insulating film 250, the fourth mold structure MO4, and the third substrate 200. The etching process corresponds to a low-temperature plasma etching process.

[0144] Each vertical channel hole CH penetrates the fifth mold structure MO5 and the fourth mold structure MO4. Each vertical channel hole CH may also penetrate a portion of the third substrate 300. The vertical channel holes CH expose a portion of the top surface of the third substrate 300 to the outside.

[0145] The first through structure holes C1H penetrate the planarization insulating film 250, the fifth mold structure MO5, the fourth mold structure MO4, and the third substrate 200. The first through structure holes C1H may further penetrate a portion of the peripheral circuit insulating film 130. The first through structure holes C1H expose a portion of the peripheral circuit wiring 195 to the outside.

[0146] The second through structure holes C2H penetrate the planarization insulating film 250. The second through structure holes C2H can further penetrate a portion of the peripheral circuit insulating film 130. A portion of the peripheral circuit wiring 195 is exposed to the outside through the second through structure holes C2H.

[0147] In the cell array region CAR, the isolation trenches TR penetrate the fifth mold structure MO5. The isolation trenches TR may further penetrate the second semiconductor film 354. A portion of the top surface of the second buffer insulating film 353 is exposed by the isolation trenches TR.

[0148] A low-temperature plasma etching process can be used to form the vertical channel hole CH, the first through-structure hole C1H, the second through-structure hole C2H, and the isolation trench TR. The etching process is performed in the same manner as the low-temperature plasma etching process described with reference to FIGS. 1 to 2D. For example, the first etching gas used in the etching process includes CF3OCFCF2. For simplicity, a description of the low-temperature plasma etching process described with reference to FIGS. 1 to 2D will be omitted.

[0149] The vertical channel hole CH, the first through-structure hole C1H, the second through-structure hole C2H, and the isolation trench TR penetrate different components, for example, the vertical channel hole CH penetrates a structure in which interlayer insulating films ILD and sacrificial films SL are alternately stacked, while the second through-structure hole C2H penetrates only the planarization insulating film 250, which is a single component.

[0150] The interlayer dielectric film ILD and the sacrificial film SL may include different insulating materials. For example, the interlayer dielectric film ILD may include silicon oxide, and the sacrificial film SL may include silicon nitride. The planarization insulating film 250 may include the same material as the interlayer dielectric film ILD.

[0151] If fluorocarbon or hydrofluorocarbon is used in the etching process for forming the vertical channel hole CH and the second through structure hole C2H, the etching rate of silicon oxide differs from that of silicon nitride. Specifically, the etching rate of silicon nitride is higher than that of silicon oxide. Therefore, when the vertical channel hole CH is formed during the etching process, the second through structure hole C2H may not yet be formed. For this reason, it is difficult to simultaneously form the vertical channel hole CH and the second through structure hole C2H.

[0152] The method for manufacturing a semiconductor device 2000 according to the present invention includes simultaneously forming the vertical channel hole CH, the first through-structure hole C1H, the second through-structure hole C2H, and the isolation trench TR. A low-temperature plasma etching process can be used to form the vertical channel hole CH, the first through-structure hole C1H, the second through-structure hole C2H, and the isolation trench TR. The low-temperature plasma etching process can use the first etching gas described with reference to FIGS. 1 to 2D. This reduces the difference between the etching rate of the interlayer dielectric film ILD and the planarization insulating film 250 and the etching rate of the sacrificial film SL. This reduces the difficulty and cost of the manufacturing method for forming the vertical channel hole CH, the first through-structure hole C1H, the second through-structure hole C2H, and the isolation trench TR. Consequently, the difficulty and cost of the manufacturing method for the semiconductor device 2000 are reduced.

[0153] 16A and 16B, first and second vertical channel structures VS1 and VS2 are formed in the vertical channel hole CH, a first through structure C1 is formed in the first through structure hole C1H, and a second through structure C2 is formed in the second through structure hole C2H.

[0154] After the first and second vertical channel structures VS1 and VS2 are formed, the first buffer insulating film 351, the first semiconductor film 352, and the second buffer insulating film 353 of the fourth mold structure MO4 are removed. Removing the first buffer insulating film 351, the first semiconductor film 352, and the second buffer insulating film 353 includes performing a wet etching process through the isolation trench TR. During the wet etching process, a portion of the data storage pattern DSP may be removed. Next, a first source conductive pattern SCP1 is formed, filling the space vacated by the first buffer insulating film 351, the first semiconductor film 352, and the second buffer insulating film 353. The remaining second semiconductor film 354 is referred to as a second source conductive pattern SCP2. Thus, a source structure SC including the first source conductive pattern SCP1 and the second source conductive pattern SCP2 may be formed.

[0155] In the process of forming the first through structure C1, the protrusion portion PTS and the second sidewall insulating pattern CID are also formed, as described with reference to FIGS. 15 to 16B.

[0156] Next, the sacrificial film SL is selectively removed by the isolation trench TR. The selective removal of the sacrificial film SL includes wet etching using phosphoric acid (H2PO4). The gate electrode EL is formed in the space where the sacrificial film SL is removed.

[0157] An isolation structure 350 is formed in the isolation trench TR. Then, an upper insulating film 260 is formed on the stack structure ST and the planarization insulating film 250. Bit line contact plugs BLCP are formed through the upper insulating film 260 and connected to the corresponding first vertical channel structures VS1. First contact plugs C1CP are formed through the upper insulating film 260 and connected to the corresponding first through structures C1. Second contact plugs C2CP are formed through the upper insulating film 260 and connected to the second through structures C2.

[0158] A bit line BL connected to a corresponding bit line contact plug BLCP is formed on the upper insulating film 260. A first conductive line CL1 connected to a corresponding first contact plug C1CP is formed on the upper insulating film 260. A second conductive line CL2 connected to a second contact plug C2CP is formed on the upper insulating film 260. Thus, the semiconductor device 2000 is manufactured.

[0159] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that all the above-described embodiments are illustrative and not limiting.

Claims

1. forming a first mold structure on a semiconductor structure and a second mold structure spaced apart from the first mold structure in a horizontal direction, the first mold structure having a structure in which first insulating films and second insulating films different from the first insulating films are alternately stacked one by one, and the second mold structure including a third insulating film including the same material as that included in the first insulating film; forming a mask pattern on the first mold structure and the second mold structure; performing an etching process on the first mold structure and the second mold structure using a first etching gas by using the mask pattern as an etching mask; The first etching gas includes oxygen-containing fluorocarbon.

2. 2. The method of claim 1, wherein the first etching gas includes a substance having a chemical formula of CxFyOz (1≦x≦5, 2x-2≦y≦2x+2, 1≦z<x, and x, y, and z are natural numbers).

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching gas contains trifluoromethyl R(1)-O-CR(2)=CR(3)R(4) (R(1), R(2), R(3), R(4)=CaFb, 0≦a≦3, b=2a+1, and a and b are natural numbers).

4. 2. The method of claim 1, wherein the etching process using the first etching gas is performed at a temperature of 0° C. or less and −100° C. or more.

5. The method of claim 1 , wherein the mask pattern comprises a silicon-based or carbon-based material.

6. forming an insulating pattern on a substrate; forming a conductive contact in the insulating pattern; forming an etch stop layer on the insulating pattern and the conductive contact; forming a mold structure on the etch stop layer, the mold structure including a first mold film, a lower support film, a second mold film, and an upper support film stacked in order, the first mold film and the second mold film including a first material, the lower support film and the upper support film including a second material, and the first material and the second material having etch selectivity with respect to each other; forming a mask pattern on the mold structure; and performing an etching process on the mold structure using a first etching gas by using the mask pattern as an etching mask; the etching process forms a via hole through the mold structure and the etch stop layer; The method for manufacturing a semiconductor device, wherein the first etching gas includes a fluorocarbon containing oxygen.

7. 7. The method of claim 6, wherein the first etching gas includes a substance having a chemical formula of CxFyOz (1≦x≦5, 2x-2≦y≦2x+2, 1≦z<x, and x, y, and z are natural numbers).

8. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the first etching gas contains trifluoromethyl R(1)-O-CR(2)=CR(3)R(4) (R(1), R(2), R(3), R(4)=CaFb, 0≦a≦3, b=2a+1, and a and b are natural numbers).

9. providing a first substrate including a cell array region and a contact region adjacent to the cell array region; forming a peripheral circuit structure including a peripheral circuit transistor on the first substrate; forming a mold structure on the peripheral circuit structure, the mold structure including an interlayer insulating film and a sacrificial film alternately stacked one on the other, the interlayer insulating film including a first material, the sacrificial film including a second material, and the first material and the second material having etching selectivity with respect to each other; trimming the mold structure so that the mold structure has a staircase structure in the contact region; forming a planarization insulating film covering the staircase structure; simultaneously forming a vertical channel hole penetrating the mold structure in the cell array region, a first penetrating structure hole penetrating the planarization insulating layer and the mold structure in the contact region, and a second penetrating structure hole penetrating the planarization insulating layer in the contact region; forming the vertical channel hole, the first through structure hole, and the second through structure hole includes performing an etching process of the mold structure and the planarization insulating film using a first etching gas; The method for manufacturing a semiconductor device, wherein the first etching gas includes a fluorocarbon containing oxygen.

10. 10. The method of claim 9, wherein the first etching gas includes a substance having a chemical formula of CxFyOz (1≦x≦5, 2x-2≦y≦2x+2, 1≦z<x, and x, y, and z are natural numbers).

Images