Low voltage signal level conversion circuit

Abstract

To provide a level conversion circuit for outputting a signal without delay or distortion even when a low voltage signal is inputted.SOLUTION: A first PMOS (transistor) inserted between a power supply for supplying a second signal level and a drain of the first NMOS, a second PMOS (transistor) inserted between a second power supply voltage and a drain of the second NMOS, a first capacitor inserted between a gate of the first PMOS and a gate of the first NMOS, and a second capacitor inserted between a gate of the second PMOS and a gate of the second NMOS. The signal level conversion circuit comprises a first resistor inserted between the gate of a first PMOS and the drain of a second NMOS, and a second resistor inserted between the gate of the second PMOS and the drain of the first NMOS, and outputs the drain voltage of the first NMOS or the second NMOS.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a level conversion circuit that operates with a low-voltage clock signal. [Background technology]

[0002] In recent years, in LSIs that have internal circuits and system circuits, the CMOS circuits that make up the internal circuits have become increasingly miniaturized, with the maximum operating voltage of these miniaturized CMOS circuits falling to 1V or less. On the other hand, the operating voltage of the system circuit side is often a normal voltage (3.3V to 5.5V). This means that the signal level from the miniaturized CMOS circuit needs to be converted to match the voltage on the system circuit side, and various level conversion circuits are used to convert from low voltage to high voltage.

[0003] Figure 5 is a diagram showing a conventional level conversion circuit. The level conversion circuit 41 shown in Figure 5 is composed of two PMOS transistors 45 (MP1) and 46 (MP2) and two NMOS transistors 47 (MN1) and 48 (MN2). A signal CKi is input from a signal generation source 42 to the gate of the NMOS transistor 47, and an inverted signal CKZi of the signal CKi is input from a signal generation source 43 to the gate of the NMOS transistor 48. The drains of the PMOS transistor (MP1) 45 and the NMOS transistor (MN1) 47 are connected to output a signal CKOZ, which is also input to the gate of the PMOS transistor (MP2) 46. The drains of the PMOS transistor (MP2) 46 and the NMOS transistor (MN2) 48 are connected to output a signal CKO, which is also input to the gate of the PMOS transistor (MP1) 45.

[0004] Immediately after signal CKi changes from 0V to Vdd1 (V), the gate voltage of PMOS transistor (MP1) 45, which is the load on NMOS transistor (MN1) 47, remains at 0V (i.e., Vgp1=VDD), so PMOS transistor (MP1) 45 is in the ON state and attempts to maintain the CKOZ voltage at the VDD voltage. At this time, the operation of the level conversion circuit can be divided into the following three cases depending on the value of Vdd1 input from signal CKi. <case1>When the NMOS transistor (MN1) 47, to whose gate Vdd1 is input, is able to drop the output CKOZ to near low voltage (approximately 0V), the input voltage Vdd1 quickly turns on the NMOS transistor (MN1) 47, and the output CKOZ quickly drops to the ground voltage (Vss=0V) level. When the K value of the NMOS transistors (MN1) 47 and (MN2) 48 is Kn, and the K value of the PMOS transistor (MP1) 45 and NMOS transistor (MP2) 46 is Kp, then Kn(Vdd1-Vn) 2 >Kp(VDD-Vp) 2 holds true.

[0005] <case2>When the NMOS transistor (MN1) 47, to whose gate Vdd1 is input, is able to drop the CKOZ voltage until the PMOS transistor (PM2) 46 turns on. In other words, even though the NMOS transistor (MN1) 47 can be turned on by the input of Vdd1, its drivability is low, so the CKOZ voltage only drops slightly (ΔV1 in Figure 7). If this ΔV1 is just above the threshold of the PMOS transistor (PM2) 46, the PMOS transistor (PM2) 46 will only be turned on weakly. This causes the CKO voltage to rise slowly, but as the CKO voltage rises, the pull-up current of the PMOS transistor (MP1) 45 decreases, causing the CKOZ voltage to drop further. This causes the PMOS transistor (MP2) to turn on more strongly, accelerating the rise in the CKO voltage. The output inversion characteristic due to this positive feedback operation is shown by ΔV2 in Figure 7. As can be seen from Figure 7, the initial inversion of the output due to positive feedback operation is slow, and subsequent operation is also left to the level conversion circuit, so the inversion operation takes a certain amount of time. <case2>In the case of Kn(Vdd1-Vtn) 2 <Kp(Vdd1-Vtp) 2 holds true. <case3>When the NMOS transistor (MN1) 47, to whose gate Vdd1 is input, cannot drop the CKOZ voltage until the PMOS transistor (PM2) 46 turns on, Kn (Vdd1-Vtn) 2 < <Kp(Vdd1-Vtp) 2 In this case, the inversion operation of the level conversion circuit does not occur, and the operation is stopped.

[0006] <case1>In this case, the operation is as follows. In the level conversion circuit 41, when a high-level signal CKi from the signal generation source 42 is input to the gate of the NMOS transistor 47, the NMOS transistor 47 turns on and the source-side ground voltage Vss (low level, i.e., 0 V) ​​is input to the gate of the PMOS transistor 46, turning the PMOS transistor 46 on. Meanwhile, the output CKZi from the signal generation source 43 is an inverted signal of CKi and is therefore low level. When this low-level signal CKZi is input to the gate of the NMOS transistor 48, the NMOS transistor 48 turns off. As a result, a high-level voltage (VDD) is output as the signal CKO from the connection point between the drain of the PMOS transistor 46 and the drain of the NMOS transistor 48. Furthermore, since the connection point between the drain of the PMOS transistor 46 and the drain of the NMOS transistor 48 is connected to the gate of the PMOS transistor 45, the PMOS transistor 45 is turned off by the high-level signal CKO. Therefore, the voltage on the ground side of the NMOS transistor 47 in the ON state (ground voltage, ie, 0V) is input to the gate of the PMOS transistor 46, and the PMOS transistor 46 is reliably turned ON.

[0007] When signal CKi is at a low level, the opposite occurs. That is, in level conversion circuit 41, when a low-level signal CKi from signal generator 42 is input to the gate of NMOS transistor 47, NMOS transistor 47 turns OFF. On the other hand, output CKZi from signal generator 43 is an inverted signal of CKi and is therefore at a high level. When this high-level signal CKZi is input to the gate of NMOS transistor 48, NMOS transistor 48 turns ON, and the ground voltage (low level, Vss = 0V) on the source side is input to the gate of PMOS transistor 45, turning PMOS transistor 45 ON. When PMOS transistor 45 turns ON, a high-level voltage (VDD) on the source side of PMOS transistor 45 is input to the gate of PMOS transistor 46, turning PMOS transistor 46 OFF. As a result, a low-level voltage (Vss: ground voltage 0V) is output as signal CKO from the connection point between the drain of PMOS transistor 46 and the drain of NMOS transistor 48. It is also possible to output an inverted signal CKOZ of the signal CKO from the connection point between the drain of the PMOS transistor 45 and the drain of the NMOS transistor 47.

[0008] Figure 6 shows <case1>This shows the input / output characteristics of a conventional level conversion circuit in the case of the input signal (CK). It shows that the output (inverted) signal (CKOZ) follows the input signal (CK) without delay. <case1>In this case, the inversion of the level shifter (conversion) circuit output proceeds smoothly as shown in Figure 6. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent Publication No. 2013-187712 Summary of the Invention [Problem to be solved by the invention]

[0010] next, <case2>The operation in this case will be explained. <case2>10 is a diagram showing input / output characteristics of a conventional level conversion circuit in the case of FIG. <case2>In this case, the inverted output (CKOZ) of the level conversion circuit exhibits complex behavior with respect to the input signal (CKi), as shown in Figure 7. If the NMOS transistor (MN1) 47, to whose gate the Vdd1 voltage is input, can lower the output CKOZ voltage beyond the threshold voltage of the PMOS transistor (MP2) 46 (ΔV1 in Figure 7), the PMOS transistor (MP2) 46 to which the CKOZ voltage is input turns ON. Since the NMOS transistor (MN2) 48, to which 0V is input as the input signal CKZi, is OFF, the output CKO voltage rises toward the VDD voltage (the behavior of the output CKO voltage at this time is the same as the behavior of CKOZ when CKi changes from Vdd1 to 0V in Figure 7). As a result, the PMOS transistor (MP1) 45 to which the output signal CKO is input turns OFF, and the output signal CKOZ voltage drops to 0V (ΔV2 in Figure 7).

[0011] In other words, even though the NMOS transistor (MN1) 47 can be turned on by the input of Vdd1, its drivability is low, so the CKOZ voltage only drops slightly (ΔV1 in Figure 7). If this ΔV1 is just above the threshold of the PMOS transistor (PM2) 46, the PMOS transistor (PM2) 46 will only be turned on weakly. This causes the CKO voltage to rise slowly, but as the CKO voltage rises, the pull-up current of the PMOS transistor (MP1) 45 decreases, causing the CKOZ voltage to drop further. This causes the PMOS transistor (MP2) to turn on more strongly, accelerating the rise in the CKO voltage. The output inversion characteristic due to this positive feedback operation is shown by ΔV2 in Figure 7. As can be seen from Figure 7, the initial inversion of the output due to positive feedback operation is slow, and subsequent operation is also left to the level conversion circuit, so the inversion operation takes a certain amount of time. In this way, the output inversion operation is dependent on the positive feedback operation between the two inverters that make up the level conversion circuit, which causes problems of delay and distortion in the output signal when the output is inverted, as shown in Figure 7. The present invention provides a level conversion circuit that does not cause problems of delay and distortion in the output signal when the output is inverted. [Means for solving the problem]

[0012] The present invention provides a level conversion circuit that operates on a low-voltage signal with a small circuit configuration, and specifically has the following features. (1) The present invention provides a signal level conversion circuit for converting a signal of a first signal level to a second signal level, the signal level conversion circuit comprising: a first NMOS transistor receiving a signal of the first signal level at its gate input; a second NMOS transistor receiving an inverted signal of the first signal at its gate input; a first PMOS transistor inserted between a power supply for supplying a second signal level and the drain of the first NMOS transistor; a second PMOS transistor inserted between a second power supply voltage and the drain of the second NMOS transistor; a first capacitance inserted between the gate of the first PMOS transistor and the gate of the first NMOS transistor; a second capacitance inserted between the gate of the second PMOS transistor and the gate of the second NMOS transistor; a first resistor inserted between the gate of the first PMOS transistor and the drain of the second NMOS transistor; and a second resistor inserted between the gate of the second PMOS transistor and the drain of the first NMOS transistor, and the drain voltage of the first NMOS transistor or the second NMOS transistor is an output of the signal level conversion circuit.

[0013] (2) The present invention provides a signal level conversion circuit for converting a signal of a first signal level to a second signal level, the signal level conversion circuit comprising: a first PMOS transistor receiving a signal of the first signal level at its gate input; a second PMOS transistor receiving an inverted signal of the first signal at its gate input; a first NMOS transistor inserted between a power supply for supplying a second signal level and the drain of the first PMOS transistor; a second NMOS transistor inserted between a second power supply voltage and the drain of the second PMOS transistor; a first capacitance inserted between the gate of the first NMOS transistor and the gate of the first PMOS transistor; a second capacitance inserted between the gate of the second NMOS transistor and the gate of the second PMOS transistor; a first resistor inserted between the gate of the first NMOS transistor and the drain of the second PMOS transistor; and a second resistor inserted between the gate of the second NMOS transistor and the drain of the first PMOS transistor, the signal level conversion circuit outputting a drain voltage of the first PMOS transistor or the second PMOS transistor. (3) In addition to (1) or (2), the present invention is a signal level conversion circuit characterized in that the drivability of the first NMOS transistor and the first PMOS transistor is different from the drivability of the second NMOS transistor and the second PMOS transistor, respectively. [Effects of the Invention]

[0014] In a conventional level shifter (conversion) circuit consisting of two PMOS transistors and two NMOS transistors, problems such as delay and distortion in the output signal occur when the input signal voltage becomes small. However, by simply adding two capacitances and two resistances, the output characteristics of the level shifter (conversion) circuit of the present invention have little or no delay or distortion. Furthermore, since the drivability of the NMOS transistor (MN2) 18 and PMOS transistor (MP2) 16 on the output side in Figure 1 can be made smaller than the drivability of the NMOS transistor (MN1) 17 and PMOS transistor (MP1) 15 on the input side, the level shifter circuit can be made smaller and the current consumption of the circuit can be reduced. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing a first embodiment of a level conversion circuit according to the present invention. [Figure 2] FIG. 2 is a diagram showing an example of the level conversion characteristics of the first embodiment of the level conversion circuit of the present invention when high-frequency clock signals are input from CKi and CKZi. [Figure 3] FIG. 3 is a table showing the voltage values ​​of each node before and after clock inversion when a low-voltage clock with a duty of 50% is input to the conventional circuit and the new circuit (first embodiment). [Figure 4] FIG. 4 is a diagram showing a second embodiment of the level conversion circuit of the present invention. [Figure 5] FIG. 5 is a diagram showing a conventional level conversion circuit. [Figure 6] Figure 6 shows <case1>10 is a diagram showing input / output characteristics of a conventional level conversion circuit in the case of FIG. [Figure 7] Figure 7 shows <case2>10 is a diagram showing input / output characteristics of a conventional level conversion circuit in the case of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0016] 1 is a diagram showing a first embodiment of a level conversion circuit of the present invention. The level conversion circuit 11 converts a signal of a first signal level to a signal of a second signal level and is composed of two PMOS transistors 15 (MP1) and 16 (MP2), two NMOS transistors 17 (MN1) and 18 (MN2), two capacitances 21 and 22, and two resistors 23 and 24. A signal CKi of a first signal level is input from a signal generation source (first signal generation source) 12 to the gate of the NMOS transistor 17, and an inverted signal CKZi of the signal CKi is input from a signal generation source 13 to the gate of the NMOS transistor 18. The signal generation source 13 may be formed by inputting the signal CKi of the signal generation source (first signal generation source) 12 to an inverter and inverting it. The source of the NMOS transistor 17 (referred to as the first NMOS transistor) is grounded (Vss=0V), and its drain is connected to the drain of the PMOS transistor 15 (referred to as the first PMOS transistor), the source of which is connected to a power supply (VDD), which is a power supply for supplying a second signal level.

[0017] The source of NMOS transistor 18 (referred to as a second NMOS transistor) is grounded (Vss), and its drain is connected to the drain of PMOS transistor 16 (referred to as a second PMOS transistor), the source of which is connected to a power supply (VDD). A capacitance 21 (referred to as a first capacitance) is inserted between the gate of PMOS transistor 15 and the gate of NMOS transistor 17, and a capacitance 22 (referred to as a second capacitance) is inserted between the gate of PMOS transistor 16 and the gate of NMOS transistor 18. Furthermore, a resistor 23 (referred to as a first resistor) is inserted between the gate of PMOS transistor 15 and the drain of NMOS transistor 18, and a resistor (referred to as a second resistor) is inserted between the gate of PMOS transistor 16 and the drain of NMOS transistor 17. The output of the level conversion circuit 11 of the present invention is a signal CKOZ (second signal) of the drain voltage of the PMOS transistor 15 and the drain voltage of the NMOS transistor 17, and a signal CKO (second signal) of the drain voltage of the PMOS transistor 16 and the drain voltage of the NMOS transistor 18.

[0018] The operation of the level conversion circuit of the present invention will now be described. <case1>In this case, the level conversion circuit of the present invention operates in the same manner as a conventional circuit. In the initial state of level conversion circuit 11, the signal CKi output from signal generator 12 is 0V, and the signal CKZi output from signal generator 13 is Vdd1. Suppose NMOS transistor 17 is OFF, NMOS transistor 18 is ON, PMOS transistor 15 is ON, and PMOS transistor 16 is OFF. Therefore, CKOZ and CKZp are at VDD voltage, and CKO and CKp are at 0V. In this state, when signal CKi pulses up from 0V to Vdd1 voltage, NMOS transistor 17 turns ON, and at the same time, the gate voltage CKp of PMOS transistor 15 rises from 0V to Vdd1 due to the effect of capacitor 21, and the drain current of PMOS transistor 15 decreases. This facilitates the inversion of CKOZ from VDD voltage to 0V.

[0019] Meanwhile, the output CKZi of the signal generator 13 is an inverted signal of CKi, and therefore changes from Vdd1 to 0V. Therefore, the NMOS transistor 18 turns OFF. At the same time, the gate voltage CKZp of the PMOS transistor 15 drops from VDD by Vdd1 due to the effect of the capacitor 22. When Vdd1 is greater than the threshold voltage of the PMOS transistor 16, the PMOS transistor 16 turns ON. This facilitates the inversion of CKO from 0V to the VDD voltage. After the inversion is complete, if there is no change in the input signals CKi and CKZi, CKp converges to the CKO voltage, and CKZp converges to the CKOZ voltage, further stabilizing this circuit inversion. When this LOW-level signal CKZi is input to the gate of the NMOS transistor 18, the NMOS transistor 18 turns OFF. As a result, a HIGH-level voltage (VDD) is output as the signal CKO from the junction of the drains of the PMOS transistor 16 and NMOS transistor 18. Furthermore, since the connection point between the drain of the PMOS transistor 16 and the drain of the NMOS transistor 18 is connected to the gate of the PMOS transistor 15, the HIGH level signal CKO turns off the PMOS transistor 15. Therefore, the voltage on the ground side of the ON-state NMOS transistor 17 (ground voltage, i.e., 0 V) ​​is input to the gate of the PMOS transistor 16, and the PMOS transistor 16 is reliably turned on.

[0020] When the signal CKi is at the LOW level, the situation is reversed from the above. That is, in the level conversion circuit 11, when the LOW-level signal CKi from the signal source 12 is input to the gate of the NMOS transistor 17, the NMOS transistor 17 turns OFF. On the other hand, since the output CKZi of the signal source 13 is the inverted signal of CKi, it is at the HIGH level. When this HIGH-level signal CKZi is input to the gate of the NMOS transistor 18, the NMOS transistor 18 turns ON, and the ground voltage (Vss, LOW level) on the source side is input to the gate of the PMOS transistor 15, causing the PMOS transistor 15 to turn ON. When the PMOS transistor 15 turns ON, the HIGH-level voltage (VDD) on the source side of the PMOS transistor 15 is input to the gate of the PMOS transistor 16, so the PMOS transistor 16 turns OFF. As a result, a LOW-level voltage (Vss: ground voltage 0V) is output as the signal CKO from the connection point between the drain of the PMOS transistor 16 and the drain of the NMOS transistor 18. Incidentally, an inverted signal CKOZ of the signal CKO can also be output from the connection point between the drain of the PMOS transistor 15 and the drain of the NMOS transistor 17.

[0021] <In the case of Case 2>. Immediately after the signal CKi changes from 0V to Vdd1 (V), the gate voltage CKp of the PMOS transistor (MP1) 15 rises to Vdd1 by the capacitor 21, so the Vgp1 voltage becomes VDD - Vdd1, and the ability to pull up the CKOZ voltage is significantly reduced compared to the conventional circuit. Therefore, since the pull-down ability of the NMOS transistor (MN1) 17 to which the gate input Vdd1 is input can be easily made larger than the pull-up ability of the PMOS transistor (MP1) 15, it becomes possible to pull down the output signal CKOZ voltage close to 0V. That is, even under conditions where Vdd1 is small and the operation of Case 1 cannot be expected in the conventional circuit, the new circuit can achieve the operation of Case 1.

[0022] On the one hand, when the signal CKi changes from Vdd1 to 0V, the NMOS transistor (MN1) 17 turns off, and the PMOS transistor (MP1) 15 turns on because the CKp voltage drops from VDD to about Vdd1, and the output signal CKOZ is pulled up to the VDD voltage. In this circuit, since the output signal can be inverted without depending on the positive feedback operation of the two inverters constituting the level conversion circuit, a stable high-speed operation with a small inversion delay time can be realized.

[0023] When the signal CKi voltage changes from 0V to Vdd1, the signal CKZi changes from Vdd1 to 0V, so the CKZp voltage drops from VDD to about Vdd1, and the PMOS transistor (MP2) 16 turns on, so the voltage of the output signal CKO is pulled up to VDD. After the voltages of this output signal CKOZ and CKO are inverted, as time passes, the CKp voltage is pulled up to the VDD voltage by the output signal CKO voltage, and the CKZp voltage is pulled down to 0V by the output signal CKOZ voltage. This is due to the positive feedback operation between the two inverters with the CR delay time intervening after the output inversion, and the node voltages of the MOS transistors finally converge to the same values as those of the conventional circuit. When the CKi voltage changes from Vdd1 to 0V and CKZi changes from 0V to the Vdd1 voltage, the node voltages of the MOS transistors also converge to the same values as those of the conventional circuit after the output inversion.

[0024] In the new circuit, when the period when the input clock CKi to the level conversion circuit is high-frequency is sufficiently shorter than the time constant of the above CR (period: T << CR), the voltages of each node are shown in the right column of the table in FIG. 3. From this table, it can be seen that in the high-frequency clock, the Vgp1 voltage immediately after the clock rise fluctuates in the direction of turning off the PMOS transistor (MP1) 15, and the Vgp1 voltage immediately after the clock fall fluctuates in the direction of turning on the PMOS transistor (MP1) 15 more strongly. That is, this level conversion circuit operates faster as the clock frequency increases.

[0025] Figure 2 shows an example of the level conversion characteristics of the new circuit when high-frequency clock signals are input from CKi and CKZi. Even though the input voltage to CKi is the same as in Figure 7, the delay in the CKOZ output voltage in Figure 2 is extremely small compared to Figure 7, and no distortion of the waveform is observed. This is because CKp changes in conjunction with the input voltage to CKi, controlling the drive capacity of the PMOS transistor so that the CKOZ output is more likely to invert. In this way, by adding two capacitors and two resistors to the conventional circuit as shown in Figure 1, this level conversion circuit is able to achieve excellent level conversion characteristics.

[0026] FIG. 3 is a table showing the voltage values ​​of each node before and after clock inversion when a low-voltage clock with a duty cycle of 50% is input to the conventional circuit and the new circuit (first embodiment). The new circuit is shown separately for when a low-frequency clock is input and when a high-frequency clock is input. From the operational analysis of the new circuit described above, it can be seen that the level conversion output, which uses the CKOZ voltage as the output, is determined solely by the operating currents of the NMOS transistor (MN1) 17 and the PMOS transistor (MP1) 15 immediately after the rising and falling edges of CKi, while the NMOS transistor (MN2) 18 and the PMOS transistor (MP2) 16 merely serve to maintain the state after the rising and falling edges have finished. Therefore, the drivability of the NMOS transistor (MN2) 18 and the PMOS transistor (MP2) 16 can be made smaller than that of the NMOS transistor (MN1) 17 and the PMOS transistor (MP1) 15, enabling the level conversion circuit to be miniaturized and the current consumption of the circuit to be reduced.

[0027] The level conversion circuits described so far are for cases where the input signal level and output signal are positive voltages with respect to the ground voltage, but of course there are also cases where the input signal level and output signal are negative voltages with respect to the ground voltage. Figure 4 is a diagram showing a second embodiment of the level conversion circuit of the present invention. The second embodiment of the level conversion circuit of the present invention is a signal level converter for cases where the input signal level is negative voltage with respect to the ground voltage. The power supply that supplies the second signal level is a negative power supply (-VSS), and the roles of the PMOS transistor and NMOS transistor in the first embodiment of the level conversion circuit of the present invention are reversed.

[0028] The level conversion circuit in the second embodiment of the present invention converts a signal of a first signal level into a signal of a second signal level, and is composed of two PMOS transistors 35 (MP1) and 36 (MP2), two NMOS transistors 37 (MN1) and 38 (MN2), two capacitances 51 and 52, and two resistors 53 and 54. A signal CKi of a first signal level is input from a signal generation source (first signal generation source) 32 to the gate of the PMOS transistor 35, and an inverted signal CKZi of the signal CKi is input from a signal generation source 33 to the gate of the PMOS transistor 36. The signal generation source 33 may be obtained by inputting the signal CKi of the signal generation source (first signal generation source) 32 to an inverter and inverting it.

[0029] The source of PMOS transistor 35 (referred to as the first PMOS transistor) is grounded (VDD, 0V), its drain is connected to the drain of NMOS transistor 37 (referred to as the first NMOS transistor), and the source of NMOS transistor 35 is connected to a power supply (-VSS). This -VSS is a power supply for supplying a second signal level. The source of PMOS transistor 36 (referred to as the second PMOS transistor) is grounded (VDD = 0V), and its drain is connected to the drain of NMOS transistor 38 (referred to as the second NMOS transistor), and the source of NMOS transistor 38 is connected to a power supply (-VSS). A capacitance 51 (referred to as the first capacitance) is inserted between the gate of PMOS transistor 35 and the gate of NMOS transistor 37, and a capacitance 52 (referred to as the second capacitance) is inserted between the gate of PMOS transistor 36 and the gate of NMOS transistor 38. Furthermore, a resistor 54 (called a first resistor) is inserted between the gate of the PMOS transistor 35 and the drain of the NMOS transistor 38, and a resistor (called a second resistor) 53 is inserted between the gate of the PMOS transistor 36 and the drain of the NMOS transistor 37.

[0030] The output of the level conversion circuit 31 in the second embodiment of the present invention is a signal CKOZ (second signal) which is the drain voltage of the PMOS transistor 35 and the NMOS transistor 37, and a signal CKO (second signal) which is the drain voltage of the PMOS transistor 36 and the NMOS transistor 38. The signals CKOZ and CKO are second signals. In this way, the power supply that supplies the second signal level is the negative power supply (-VSS), and the roles of the PMOS transistor and the NMOS transistor are reversed. The circuit operation in the second embodiment behaves similarly to the circuit shown in the first embodiment.

[0031] As described above in detail, the level shifter (conversion) circuit of the present invention has a simple circuit configuration in which two capacitances and two resistances are added to a conventional level conversion circuit, and can obtain an output signal without delay or distortion even when the input voltage is small. It goes without saying that, in this specification, when the content described and explained in a certain part of the specification can be consistently applied to other parts not described, the content can also be applied to the other parts. Furthermore, the above embodiment is merely an example, and various modifications can be made within the scope of the present invention, and it goes without saying that the scope of the present invention is not limited to the above embodiment. [Explanation of symbols]

[0032] 11 level conversion circuit, 12 (clock) signal generation source, 13 (clock) signal generation source, 15 PMOS transistor, 16 PMOS transistor, 17 NMOS transistor, 18 NMOS transistor, 21 capacitance (capacitance), 22 capacitance (capacitance), 23 resistor, 24 resistor, 31 level conversion circuit, 32 (clock) signal generation source, 33 (clock) signal generation source, 35 PMOS transistor, 36 PMOS transistor, 37 NMOS transistor, 38 NMOS transistor, 42 (clock) signal generation source, 43 (clock) signal generation source, 45 PMOS transistor, 46 PMOS transistor, 47 NMOS transistor, 48 NMOS transistor, 51 capacitance (capacitance), 52 capacitance (capacitance), 53 resistor, 54 resistor,

Claims

1. a first NMOS transistor receiving a signal of the first signal level as a gate input; a second NMOS transistor having an inverted signal of the first signal as a gate input; a first PMOS transistor interposed between a power supply for supplying a second signal level and the drain of the first NMOS transistor; a second PMOS transistor inserted between a second power supply voltage and the drain of the second NMOS transistor; a first capacitance inserted between the gate of the first PMOS transistor and the gate of the first NMOS transistor; a second capacitance inserted between the gate of the second PMOS transistor and the gate of the second NMOS transistor; a first resistor inserted between the gate of the first PMOS transistor and the drain of the second NMOS transistor; a second resistor inserted between the gate of the second PMOS transistor and the drain of the first NMOS transistor; It consists of a signal level conversion circuit having a drain voltage of the first NMOS transistor or the second NMOS transistor as an output;

2. a first PMOS transistor receiving a signal of the first signal level as a gate input; a second PMOS transistor having an inverted signal of the first signal as a gate input; a first NMOS transistor interposed between a power supply for supplying a second signal level and the drain of the first PMOS transistor; a second NMOS transistor inserted between a second power supply voltage and the drain of the second PMOS transistor; a first capacitance inserted between the gate of the first NMOS transistor and the gate of the first PMOS transistor; a second capacitance inserted between the gate of the second NMOS transistor and the gate of the second PMOS transistor; a first resistor inserted between the gate of the first NMOS transistor and the drain of the second PMOS transistor; a second resistor inserted between the gate of the second NMOS transistor and the drain of the first PMOS transistor; It consists of a signal level conversion circuit having a drain voltage of the first PMOS transistor or the second PMOS transistor as an output;

3. 3. The signal level conversion circuit according to claim 1, wherein: A signal level conversion circuit characterized in that the drivability of a first NMOS transistor and a first PMOS transistor is different from the drivability of a second NMOS transistor and a second PMOS transistor, respectively.

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