Semiconductor memory device

Abstract

If a stacked nonvolatile GAA (gate-all-around transistor) stacked in the vertical direction having high-speed and low-cost characteristics is used for one bit, the planar pattern area can be significantly reduced as compared with the conventional HBM, the cost can be significantly reduced, the length of the output of the memory can be extremely shortened as compared with the conventional HBM, and high-speed (about 1 / 10000) and low-power (about 1 / 100) output can be realized.SOLUTION: In a plurality of horizontal FETs having the same conductivity type in channel portions vertically stacked at the same position on the same plane, a ferroelectric insulating film capable of storing information in a nonvolatile manner is used as a gate insulating film 144 in the plurality of horizontal FETs, one horizontal FET is used as a memory for storing 1-bit information, and a source 142 and a drain 141 of the memory formed by the vertically stacked horizontal FETs are connected in the vertical direction to realize a memory cell array.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This relates to a semiconductor memory using gate-all-around transistors. [Background technology]

[0002] Ultra-low-cost, high-capacity, high-speed semiconductor memory is essential in a wide range of fields, including generative AI, HPC, and cloud computing. Generative AI currently uses HBM (Reference 1), which consists of approximately 12 layers of DRAM, each of which stores one bit using planar transistors and storage capacitors. In this conventional HBM, the storage capacitor requires a pattern area adjacent to the planar transistor, and the manufacturing process is different.

[0003] In conventional HBM, after manufacturing the planar DRAM, it is diced and stacked in multiple layers (currently up to about 12 layers), and the output is realized by penetrating the DRAM. In generative AI, a widely used method is to place the generative AI logic LSI and the conventional HBM adjacent to each other on a semiconductor transposer, and connect the output of the HBM to the AI ​​logic LSI via wiring that passes through the semiconductor transposer.

[0004] In generative AI, it is known that, due to scaling laws, achieving as large a number of parameters as possible at low cost is important for improving the accuracy of the AI. Increasing the amount of calculations used for learning is also important, and in order to perform a large amount of calculations in a limited time, it is important to increase the data transfer speed between the conventional HBM that stores information and the AI ​​logic LSI.

[0005] The conventional HBM technology uses DRAM with planar transistors, which results in a large pattern area and high manufacturing costs. Furthermore, because the DRAM is multi-layered after dicing, the distance between the upper and lower DRAMs is determined by the thickness of the silicon substrate (currently at a minimum of 4 microns). This means that the vertically extending DRAM output length is very long. To further improve AI accuracy, however, it is necessary to further increase the number of stacked DRAM layers. However, increasing the number of stacked layers increases the vertical output length, making it difficult to achieve higher speeds. (Reference 1) K. Kim et al, “Present and challenges of High Bandwidth Memory,” IMW Proceedings of tech Papers.1.1, 2024. Summary of the Invention The problem that the invention is trying to solve

[0006] The conventional HBM used in conventional AI applications, etc., uses DRAM with planar transistors, which increases manufacturing costs. In addition, because the DRAM is multi-layered after dicing, the distance between DRAMs is limited by the thickness of the silicon substrate, and the length of the DRAM output running vertically is very long, making it impossible to achieve high-speed output.

[0007] In a plurality of lateral FETs having the same conductivity type in the channel portion vertically stacked at the same position on the same plane, an insulating film capable of storing information non-volatilely is used as the gate insulating film of the plurality of lateral FETs, and one of the lateral FETs is used as a memory for storing 1 bit of information, and a memory cell array is realized by vertically connecting the sources and drains of the memory made of the vertically stacked lateral FETs, and using the memory cell array as a semiconductor memory.

[0008] According to the present invention, by using a vertically stacked non-volatile GAA (gate all around) transistor, such as an MBCFET, which has high speed and low cost characteristics, for one bit, the planar pattern area can be significantly reduced compared to the conventional HBM, thereby enabling a significant reduction in cost (for example, when 1024 layers are stacked, the cost can be reduced to 1 / 50 or less).

[0009] Furthermore, the distance between the upper and lower non-volatile GAAs is approximately 40 nm (approximately twice the minimum processing dimension) using cutting-edge microfabrication technology, which is extremely short compared to the thickness of the silicon substrate of the conventional HBM. This allows the memory output length to be extremely short, enabling faster output (approximately 1 / 10,000).

[0010] In other words, the present invention has the effect of realizing a large-capacity, high-speed semiconductor memory at an ultra-low cost compared to the conventional HBM. Its range of application is not limited to the above-mentioned generative AI applications, but can also be applied in a wide range of fields such as cloud computing and edge computing. BEST MODE FOR CARRYING OUT THE INVENTION

[0011] A first embodiment of an integrated circuit according to the present invention will be described below with reference to the drawings. [First embodiment] (Configuration of the first embodiment)

[0012] A first embodiment of the present invention will now be described. Figure 1 shows a top view (top left), cross-sectional circuit diagram (top right), and two cross-sectional views (bottom two) of the proposed 4-bit stacked memory. As shown in the upper left figure, when viewed from above, two-bit memory cells 123 and 124 are visible. The boundaries between them are indicated by dashed lines. The area of ​​one-bit memory cell is 2F*4F=8F 2 This allows for extremely fine processing (F is the design rule).

[0013] As shown in the upper right figure, which is a cross-sectional circuit diagram in the 109, 110 direction of the upper left figure, two FeFET (Ferroelectric FET) type GAA transistors 123 and 125, or 124 and 126, are stacked vertically, and the source electrodes 103, 105 and the drain electrodes 104, 106 are shared vertically. By stacking, the pattern area can be significantly reduced compared to a planar type in which the GAA is arranged in a plane direction (half in the case of the pattern diagram in Figure 1).

[0014] In addition, a diagonal word line pattern is realized by shifting the WLs 101 and 102 running in the adjacent BL direction by one layer between adjacent stacked GAAs 123 and 124, or 125 and 126. This is to solve the problem that when programming 123, incorrect writing occurs in GAA 124, which occurs in the conventional type where the shift is not by one layer, and a large program current flows in GAA 125 connected to 104.

[0015] The cross section in the directions 107 and 108 is shown at the bottom left. The source is shared by a vertical wiring 142 embedded in the source part, and the drain is shared by a vertical wiring 141 embedded in the drain part. The two stacked GAAs 123 and 125 are insulated by an inter-gate insulating film 145.

[0016] The cross section in the 109,110 direction is shown at the bottom right.,As mentioned above, in the adjacent BL direction, the WLs 101 and 102 are,shifted by one layer by adjacent stacked GAAs 123 and 124, or,125 and 126, to realize a diagonal word line,pattern.

[0017] FIG. 2 shows a circuit diagram (left) of a row decoder for selecting a word line, and a cross-sectional view (right) of a stacked transfer gate therein. The NOR section 210 is placed at the top of the stacked cell array. Multiple row addresses 201 are input to the gate, and a read / program combined power supply 200 is used as the power source. Its output 202 is connected to the source electrodes of the next-stage transfer gates 205 and 206. Partially decoded row address signals 207 and 208 are input to the gate. The transfer gate section is stacked in the same way as the memory cells 120, 209, and its drain output is directly connected to the WLs 101 and 102 from the sidewall 147. The output 202 of the NOR section is also input to the gate of the GAA 204, which connects the vertically running bit line 104 and the GBL 203 running horizontally across the top of the stacked section, perpendicular to the WL.

[0018] Figure 3 shows the overall configuration of the proposed memory chip. For simplicity, we have assumed a cell array 302 with four stacked layers and 4 * 4 = 16 memory cells arranged on a plane, for a total of 64 bits. The cell array section 302 and the row decoder transfer gate 303 are stacked, with the row decoder NOR sections 303 and 305, column decoder 309, address buffer 310, and peripheral circuitry 311 that drives them configured above them. If the cell array is large, it can be divided into rows and columns, just like conventional memories.

[0019] As described above, this invention uses the diagonal WL method, so row decoders are placed on the left and right of the cell array 302. By stacking the transfer gate section, which has the largest pattern area in the row decoder circuit, the plane pattern area can be significantly reduced.

[0020] The GBLs running horizontally above the cell array 302 are connected vertically 306 and connected to output lines (shared with input lines) 312 by an upper column decoder 309. By attaching a logic LSI 313 for generation AI or the like manufactured by a separate process above this and connecting the I / O lines above and below, it is possible to achieve faster operation than the conventional HBM. In addition, since the semiconductor transposer used in the past is no longer necessary, the delay time in wiring the HBM output through the semiconductor transposer is eliminated, enabling high-speed operation. Further improvement in speed can be achieved by dividing the I / O lines into multiple parts. For example, by dividing them into N parts, the data transfer speed can be improved by N times.

[0021] As a first modification of the first embodiment of the present invention, it is also possible to realize a method in which the WLs 101 and 102 running in the adjacent BL direction are not shifted by the adjacent stacked GAAs 123 and 124, or 125 and 126. This method can significantly reduce the number of manufacturing steps compared to the first embodiment (can be reduced to about half), and is therefore suitable for applications requiring large capacity and low cost rather than reliability of the memory cells.

[0022] As a second modification of the first embodiment of the present invention, a method can be considered in which not only the transfer gates of the row decoder but also part or all of the NOR section of the row decoder, the column decoder section, the peripheral circuits, etc. are stacked in the same manner as the stacked memory cell array 302. The total number of processes can be reduced with a slight increase in the plane pattern area, and since the reduction in the total number of processes is more expensive than the increase in the pattern area, it is possible to achieve lower costs than in the first embodiment.

[0023] As a second embodiment of the present invention, instead of stacking a logic LSI on top of the memory array used in the first embodiment by pasting or the like, it is also possible to consider a method of realizing it by arranging it horizontally within the same chip. This is particularly effective when using a stacked GAA to realize logic LSI to achieve low-cost, high-speed, and low-power consumption performance. Effects of the embodiment

[0024] The present invention has the effect of realizing a semiconductor memory that is ultra-low cost, large capacity, high speed, and low power consumption compared to the conventional HBM. Specific numerical values ​​will be explained below. Figure 4 shows the dependency of the manufacturing cost 402 per bit of the stacked cell array portion 302 of the first embodiment on the number of layers 401 (for process technologies assuming 256 layers and 1024 layers). The manufacturing cost of a conventional single-layer GAA is taken as 1. If stacking is performed after the pre-processing step, such as dicing and bonding, as with HBM, the manufacturing cost will be even higher than 1. Equation (1) was used for the estimation. BIT COST=(1+A+BC(N-1)) / (N-1) / Y (1+A+BC(N-1)) (1) N is the number of layers, A is the increase rate of 0.2 that is independent of the number of layers among the increase in processes compared to the conventional single-layer type, B is the percentage of one process (based on the conventional single-layer GAA), C is the additional number of processes of 6 when adding one layer, and Y is the yield of the conventional single-layer type, which is 98%.It can be seen that costs can be reduced to 1 / 12.5 using process technology assuming 256 layers (Reference 2) (B=0.01, dashed line in the figure), and to 1 / 50 using process technology assuming 1024 layers (Reference 3) (B=0.0025, solid line in the figure).

[0025] Next, we will explain the effects of increasing speed and reducing power consumption. Generally, memory access time is classified into random access time and serial access time, and the latter is important for high-speed applications such as generation AI. Figure 5 shows simulation values ​​for the dependency of the delay time 500 of the I / O line portion (corresponding to 312) of the first embodiment on the number of stacks 401. 501 shows the simulation value for the conventional HBM type, and 502 shows the simulation value for the first embodiment.

[0026] Although delay time is basically proportional to the square of the length of the I / O line (because delay time is proportional to resistance and parasitic capacitance), this proposal has the potential to reduce delay time to approximately 1 / 10,000 compared to the conventional HBM method (assuming the thickness of each HBM layer is 4 um, and the proposed vertical design rule is the cutting-edge 20 nm). Power consumption during high-speed operation, which is proportional to the length of the I / O line, can be reduced to approximately 1 / 100. (Reference 2) M.Sako et al,VLSI Symp.Dig.of tech.Papers,C2-1,2023. (Reference 3) Hidefumi Miyajima, 71st Spring Meeting of the Japan Society of Applied Physics, 23a-71A-1, 2024. Other Examples: Industrial Applicability

[0027] The present invention is not limited to this embodiment. Instead of the GAA FeFET, a spin transistor, PCM (Phase Change Memory), or the like can also be used as the lateral transistor. The scope of application is applicable to all currently commercialized integrated circuits, such as logic LSIs, AI-dedicated LSIs, and FPGAs. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 shows a top view (upper left) of a proposed 4-bit stacked memory of a first embodiment of a semiconductor memory using gate-all-around transistors according to the present invention, a cross-sectional circuit diagram (upper right), and cross-sectional views in two directions (bottom two). [Figure 2] FIG. 1 is a circuit diagram (left) of a row decoder for selecting a word line in a first embodiment of a semiconductor memory using gate-all-around transistors according to the present invention, and a cross-sectional view (right) of a stacked transfer gate therein. [Figure 3] 1 shows the overall configuration of a memory chip of a first embodiment of a semiconductor memory using gate-all-around transistors according to the present invention. [Figure 4] This shows the dependency of the manufacturing cost per bit of the stacked cell array portion of a first embodiment of a semiconductor memory using gate-all-around transistors according to the present invention on the number of stacked layers. [Figure 5] 10 shows simulation values ​​of the dependency of the number of stacked layers of the delay time of the I / O line portion of the first embodiment of the semiconductor memory using the gate-all-around type transistor according to the present invention. [Explanation of symbols]

[0029] 101, 102—WL word lines, 103, 105—SL source lines, 104, 106—BL bit lines, 107, 108—drain current flow direction, 109, 110—direction of adjacent bit line word lines, 120, 121—stacked GAA, 123 to 126—GAA transistor, 140—GAA transistor, 141—vertical bit lines embedded in the drain of the GAA, 142—vertical source lines embedded in the source of the GAA, 143—gate electrode, 144—ferroelectric gate insulating film, 145—gate-to-gate insulating film, 146—insulating film, 147—GAA source / drain sidewall epitaxial layer, 200--Power supply for read / program of the NOR circuit portion of the row decoder, 201--Multiple row address signals, 202--Output signal of the NOR circuit portion of the row decoder, 203--Global bit line, 204--GAA transistor connecting the vertical bit line and the global bit line, 205, 206--Stacked GAA transistor constituting the transfer gate of the row decoder, 207, 208--Stacked GAA transistor input to the gate of the transfer gate, 209--Stacked GAA of the transfer gate, 210--NOR circuit portion of the row decoder, 300, 301--word lines, 302--memory cell array section, 303--row decoder transfer gate, 304, 305--vertical wiring of left and right row decoder NOR sections, 306--horizontal and vertical wiring of global bit lines, 307, 308--left and right row decoder NOR sections, 309--column decoder, 310--row column address buffer, 311--peripheral circuits for driving address buffers and decoders, etc., 312--output line (also serves as input), 313--logic LSI for generation AI, etc., 401--Number of stacks, 402--Bit cost, which is the cost per bit of semiconductor memory, 500 shows the delay time of the output line, 501 shows the dependency of the delay time of the output line on the number of stacking layers (in the case of a conventional HBM), and 502 shows the dependency of the delay time of the output line on the number of stacking layers (in the case of the first embodiment of the present invention).

Claims

1. A semiconductor memory comprising a plurality of lateral FETs having the same conductivity type in their channel portions stacked vertically at the same position on the same plane, wherein gate signal electrodes of the lateral FETs are stacked vertically via an insulating film, drain electrodes and source electrodes of the vertically stacked lateral FETs are connected vertically to each other, and the lateral FETs have a function of storing information, and wherein a large number of the lateral FETs are integrated.

2. 2. The semiconductor memory according to claim 1, wherein the lateral FET is a gate-around type that uses four sides as a channel, and the resistance value of the lateral FET is made variable by programming the lateral FET.

3. 3. The semiconductor memory according to claim 1, wherein the lateral FET uses a ferroelectric material, a ferromagnetic material, a phase change material, or the like.

4. In the semiconductor memory according to claims 1, 2, and 3, the lateral FETs adjacent in the direction in which the gate electrodes run are offset by one lateral FET.

5. In the semiconductor memory according to claims 1, 2, and 3, in the lateral FET adjacent to the direction in which the gate electrode runs, the gate electrode runs parallel to the lateral FET.

6. In the semiconductor memory of claims 1 to 5, in a row decoder circuit that selects a word line connected to the gate of the lateral FET, the lateral FET connected to the word line from the sidewall of its drain electrode is stacked in the same manner as the lateral FET that stores information stacked in the vertical direction.

7. The semiconductor memory of claims 1 to 6, characterized in that a column decoder, an address buffer, and peripheral circuits for driving these are arranged above the integrated lateral FET for storing the information.

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