Semiconductor device

Abstract

To provide a storage device capable of increasing storage capacity per unit area without complicating a process.SOLUTION: The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, wherein each of the plurality of memory cells includes a switching element and a capacitive element having a first electrode and a second electrode, and in at least one of the plurality of memory cells, the switching element controls connection between the first electrode and one bit line of the plurality of bit lines in accordance with a potential applied to one word line of the plurality of word lines, and the second electrode is connected to the one word line different from the one word line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory device and a semiconductor device using the memory device. [Background technology]

[0002] DRAM (Dynamic Random Access Memory), a type of semiconductor memory device (hereinafter simply referred to as a memory device), Random Access Memory (RAM) is a memory that uses transistors and capacitors (hereafter referred to as It has a simple structure that consists of memory cells with a single quantum well (also called a quantum element). (Static Random Access Memory) Since the number of semiconductor elements required to configure a memory cell is small, the memory capacity per unit area is This can increase the cost and reduce the manufacturing cost.

[0003] However, although DRAM has the advantage of being able to increase capacity compared to other memory devices, it is becoming increasingly difficult to increase the chip size. In order to increase the integration density of LSI while suppressing the size, the To achieve this, it is necessary to reduce the area of ​​the memory cell. However, when the capacitance value becomes smaller due to the reduction in the area of ​​the capacitive element, each digital value As the difference in charge between them becomes smaller, the frequency of refresh operations must be increased. Therefore, when increasing the memory capacity per unit area of ​​DRAM, It is necessary to reduce the area of ​​the memory cell while ensuring a certain level of capacitance in the capacitive element. There is.

[0004] In the following Patent Document 1, a transistor of a different conductivity type is provided in a first memory cell and a second memory cell. By using a register, the bit line and word line are shared, reducing the area of ​​the memory cell. The RAM configuration is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 7-312392 Summary of the Invention [Problem to be solved by the invention]

[0006] The DRAM described in Patent Document 1 requires the use of transistors of different conductivity types. Therefore, the number of manufacturing processes increases compared to DRAM using single-conductivity transistors. In addition, transistors of different conductivity types have different characteristics such as on-current and threshold voltage. It is difficult to align the transistor characteristics. Therefore, the data retention time and writing time are In this case, the voltage to be applied to the transistor tends to differ between memory cells. To align transistor characteristics, process conditions and transistor layouts must be carefully considered. Therefore, the manufacturing process becomes complicated.

[0007] In view of the above-mentioned problems, the present invention provides a method for increasing the memory capacity per unit area without complicating the process. One of the objects of the present invention is to propose a storage device that can increase the capacity. By increasing the storage capacity per unit area of ​​the storage device without complicating the process, A semiconductor device using a memory device that can be made smaller or more functional while keeping costs low. One of the objectives is to propose a semiconductor device. [Means for solving the problem]

[0008] Each memory cell of the DRAM has a switching element for controlling the switching of the switching element. A word line supplies a signal to the memory cell, and a data write / read circuit is connected to the memory cell. In addition to the bit line for performing the read / write, a common potential is supplied to one of a pair of electrodes of the capacitor element. The present inventors have proposed a method for providing the function of the capacitance line to the word line. By doing so, we thought we could reduce the number of wires in the cell array.

[0009] In view of this, in a memory device according to one embodiment of the present invention, a switching element is switched using a word line. The memory cell is configured to control the switching and supply a potential to the capacitor element. When focusing on the memory cell, the switching of the switching element in the memory cell is controlled. a word line for supplying a potential to a capacitor element in the memory cell; That is, in a memory device according to one embodiment of the present invention, one word line are connected to the switching elements in the memory cells of one row, and The recell has a structure that is connected to a capacitance element.

[0010] Specifically, a memory device according to one embodiment of the present invention includes a plurality of memory cells and a plurality of word lines. Each of the plurality of memory cells has a switching element and a The word lines are connected to the capacitors, and the charge inflow, retention, and outflow are controlled by the capacitors. One of the two is connected to the switching element, and the other is connected to a part of the capacitance element. It is connected to one of the pair of electrodes.

[0011] In addition, in a memory device according to one embodiment of the present invention, a transistor used as the switching element The transistor has a wider band gap than silicon and a lower intrinsic carrier density than silicon. The channel forming region may contain a semiconductor such as , oxide semiconductors, silicon carbide, which have a band gap more than twice that of silicon, gallium nitride, etc. Transistors using the above semiconductors are not the same as ordinary silicon or Compared to transistors made of semiconductors such as germanium, the off-state current is extremely low. Therefore, the transistor having the above structure can be used to discharge the charge flowing into the capacitor. By using it as a switching element to hold the charge, it is possible to prevent leakage of charge from the capacitance element. You can do this. [Effects of the Invention]

[0012] In a memory device according to one embodiment of the present invention, a word line is allowed to function as a capacitance line, The number of wirings in the cell array can be reduced. Since there is no need to change the polarity of the electrodes, the process can be simplified and the number of electrodes per unit area can be increased. It is possible to realize a storage device that can increase the storage capacity.

[0013] In addition, in one embodiment of the present invention, it is possible to obtain a memory cell having a capacity of 10 ... By increasing the storage capacity, it is possible to reduce the size and increase the functionality while keeping costs low. A semiconductor device using the memory device can be realized. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a circuit diagram showing the configuration of a cell array. [Figure 2] FIG. 2 is a diagram schematically showing the operation of a memory cell. [Figure 3]FIG. 2 is a diagram schematically showing the operation of a memory cell. [Figure 4] 10 is a timing chart of the potential applied to the cell array. [Figure 5] 3A and 3B are an enlarged top view and cross-sectional view of a part of the cell array. [Figure 6] 3A and 3B are an enlarged top view and cross-sectional view of a part of the cell array. [Figure 7] 3A and 3B are an enlarged top view and cross-sectional view of a part of the cell array. [Figure 8] 3A and 3B are an enlarged top view and cross-sectional view of a part of the cell array. [Figure 9] FIG. 2 is a circuit diagram showing the configuration of a cell array. [Figure 10] 3A and 3B are an enlarged top view and cross-sectional view of a part of the cell array. [Figure 11] 3A and 3B are an enlarged top view and cross-sectional view of a part of the cell array. [Figure 12] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 13] FIG. 1 is a block diagram showing the configuration of a storage device. [Figure 14] FIG. [Figure 15] 1A to 1C illustrate a structure of an oxide semiconductor. [Figure 16] 1A to 1C illustrate a structure of an oxide semiconductor. [Figure 17] 1A to 1C illustrate a structure of an oxide semiconductor. [Figure 18] FIG. 10 is a graph illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 19] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 20] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 21] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 22] 1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculations. [Figure 23] 10 is a graph showing characteristics of a transistor including an oxide semiconductor film. [Figure 24] FIG. 10 shows Vg-Id characteristics of the transistor of Sample 1 after a BT test. [Figure 25] FIG. 10 shows Vg-Id characteristics of a transistor of Sample 2 after a BT test. [Figure 26] FIG. 1 shows the Vg dependence of Id and mobility. [Figure 27] 1A and 1B are graphs showing the relationship between substrate temperature and threshold voltage, and the relationship between substrate temperature and mobility. [Figure 28] FIG. 1 shows XRD spectra of sample A and sample B. [Figure 29] FIG. 10 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Figure 30] 1A to 1C illustrate a structure of a transistor. [Figure 31] 1A to 1C illustrate a structure of a transistor. [Figure 32] Electronic equipment illustration. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0016] In addition, the microprocessor, image processing circuit, DSP (Digital Signal Processor) processor), integrated circuits such as microcontrollers, RF tags, memory cards Various semiconductor devices that can use the storage device, such as storage media, semiconductor display devices, etc., The semiconductor display device is included in the scope of the present invention. Light-emitting devices with light-emitting elements, such as LEDs, in each pixel, electronic paper, DMDs (Di digital Micromirror Device), PDP (Plasma Dis) play panel), FED (Field Emission Display), etc. and other semiconductor display devices having circuit elements using semiconductor films in their driving circuits. Included in the category.

[0017] (Embodiment 1) FIG. 1 is a circuit diagram showing an example of the configuration of a cell array 100 of a memory device according to one embodiment of the present invention. The cell array 100 shown in FIG. 1 is made up of a plurality of memory cells 1 arranged in a matrix. 01, a plurality of word lines WL, and a plurality of bit lines BL. The signal from the driving circuit is , are supplied to each memory cell 101 via a plurality of word lines WL and a plurality of bit lines BL.

[0018] The number of word lines WL and bit lines BL is determined by the number and arrangement of memory cells 101. The cell array 100 shown in FIG. 1 has memory cells arranged in x rows and y columns (x and y are both natural numbers). The circuit has a filter 101, word lines WL1 to WLy, and bit lines BL1 to BLx.

[0019] Each memory cell 101 has a transistor 102 that functions as a switching element. , and a capacitor element 103. The memory cell 101 may include a transistor, a die, etc., as needed. The circuit may further include circuit elements such as electrodes, resistors, capacitors, and inductors. The switching element using the transistor 102 is a switching element that controls the flow of charge into the capacitor 103, The amount of charge held in the capacitor 103 is controlled by the following equation: The digital value of the stored data can be identified.

[0020] The transistor 102 functioning as a switching element has a gate electrode and a gate electrode functioning as an active layer. a gate insulating film located between the gate electrode and the semiconductor film; a gate electrode of the transistor 102; and a source electrode and a drain electrode connected to the gate electrode of the transistor 102. The operation of the memory device can be controlled by applying a potential to the source electrode and drain electrode. .

[0021] Note that the semiconductor film of the transistor 102 is formed using a wide-gap semiconductor such as an oxide semiconductor. Silicon, germanium, which may be amorphous, microcrystalline, polycrystalline or single crystalline, may also be used. or silicon germanium, or single crystal silicon carbide, or other semiconductors. For example, when silicon is used for the semiconductor film, a silicon single crystal semiconductor substrate, SO Silicon thin films produced by the I method, silicon thin films produced by the vapor phase epitaxy method, etc. The semiconductor film can be used.

[0022] A semiconductor with a wider band gap than silicon semiconductors and a lower intrinsic carrier density than silicon. Examples of conductors include oxide semiconductors, silicon carbide (SiC), gallium nitride (Ga Examples of oxide semiconductors include silicon carbide and nitride semiconductors. Unlike compound semiconductors such as thorium, they are produced by sputtering or wet methods (printing, etc.). It has the advantage of being easy to manufacture and suitable for mass production. The process temperature for GaN is about 1500°C, and that for oxide semiconductors is about 1100°C. Therefore, oxide semiconductors can be formed on glass substrates, which are inexpensive and readily available. It is possible to form a film on the surface and it is resistant to heat treatment at high temperatures of 1500℃ to 2000℃. A semiconductor element made of an oxide semiconductor is stacked on an integrated circuit made of a non-functional semiconductor. It is also possible to accommodate larger substrates. Compared to silicon or gallium nitride, oxide semiconductors have the advantage of being more suitable for mass production. In addition, crystalline oxide semiconductors are used to improve transistor performance (e.g., mobility). Even when trying to obtain a conductor, crystalline oxide can be easily obtained by heat treatment at 250 to 800°C. A compound semiconductor can be obtained.

[0023] In addition, impurities such as water or hydrogen, which act as electron donors (donors), are reduced, and oxygen is By reducing defects, the oxide semiconductor is highly purified (Purified Oxide Semiconductors are i-type (intrinsic semiconductors) or very close to i-type. Therefore, a transistor including the oxide semiconductor has a characteristic of having an extremely low off-state current. Specifically, the highly purified oxide semiconductor is analyzed by secondary ion mass spectrometry (SIMS). Measurement of hydrogen concentration by Condary Ion Mass Spectrometry The value is 5 x 10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 The following is more preferable: is 5 x 10 17 / cm 3 The following applies: In addition, oxide semiconductors that can be measured by Hall effect measurement The carrier density of the membrane is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Not yet less than 1×10 11 / cm 3 In addition, the band gap of the oxide semiconductor is The gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. The concentration of impurities such as carbon and hydrogen is sufficiently reduced, and oxygen vacancies are also reduced, resulting in high The off-state current of a transistor can be reduced by using a purified oxide semiconductor film. can be done.

[0024] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The measurement is performed using SIMS. SIMS, by its principle, is not suitable for measuring the area near the sample surface or the area where a film made of a different material is formed. It is known that it is difficult to obtain accurate data on the vicinity of the laminated interface. When analyzing the distribution of hydrogen concentration in the thickness direction of a film by SIMS, The average value in the range where there are no extreme fluctuations and the value is almost constant. is used as the hydrogen concentration. Due to the influence of the hydrogen concentration in the film, it may be difficult to find a region where a nearly constant value is obtained. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is determined as the hydrogen concentration in the film. Furthermore, in the region where the film exists, a peak having a maximum value is used as the hydrogen concentration. If there is no peak or valley-shaped peak with a minimum value, the value at the inflection point is taken as the hydrogen concentration. To hire.

[0025] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer For example, when the channel width is 1×10 6 μm Even in a device with a channel length of 10 μm, the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the detection limit, i.e., 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-current density, which corresponds to the value obtained by dividing the off-current by the channel width of the transistor, is 100 It can be seen that the capacitance is less than zA / μm. A circuit that controls the charge flowing into or out of a capacitor element using the transistor is used. The off-state current density was measured. A semiconductor film is used in the channel forming region, and the charge amount per unit time of the capacitance element is calculated. The off-state current density of the transistor was measured. As a result, the source electrode and drain electrode of the transistor When the voltage between the gate electrodes is 3 V, an even lower off-state current density of several tens of yA / μm is obtained. Therefore, it was found that the transistor using the highly purified oxide semiconductor film as the active layer The off-state current of the transistor is significantly lower than that of a transistor using crystalline silicon. stomach.

[0026] Unless otherwise specified, the off-state current in this specification refers to the off-state current in an n-channel transistor. In this case, the drain electrode is set to a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and gate electrode. When the potential of the gate electrode is set to a reference potential, the potential of the gate electrode is set to 0 or less. This refers to the current that flows between the source and drain electrodes when the gate is on.

[0027] The oxide semiconductor used is at least indium (In) or zinc (Zn ) is preferably contained. In particular, it is preferably contained In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to these, it is preferable to have gallium (Ga). It is preferable to use hafnium (Hf) as a stabilizer. It is preferable that the stabilizer contains aluminum (Al). is preferred.

[0028] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0029] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0030] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0031] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In3SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0032] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that.

[0033] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0034] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0035] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), a, b, c are in the vicinity of the oxide composition (a-A) 2 +(b-B) 2 + (c-C) 2 ≦r 2 The above expression means that r satisfies the above condition, and r can be set to, for example, 0.05. The same is true for monsters.

[0036] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0037] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0038] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface of 0.1 nm or less.

[0039] For Ra, the centerline average roughness defined in JIS B0601 can be applied to the surface. It is a three-dimensional extension of the method, which is based on the averaging of the absolute values ​​of the deviations from the reference surface to the specified surface. This can be expressed as the "value obtained" and is defined by the following formula 1.

[0040]

number

[0041] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 ) (the rectangular region bounded by the four points represented by (x2, y2)), and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0042] Also, the c-axis is oriented and the ab-plane, surface or interface is triangular or hexagonal when viewed from the direction of the interface. When viewed from the direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are The a-axis and b-axis are arranged in layers, and the orientation of the a-axis and b-axis is different on the ab plane (centered on the c-axis). C-Axis Aligned Crystal (CAAC) This article describes oxides containing .

[0043] In a broad sense, oxides containing CAAC are non-single crystals that are not single crystals and are not uniform in size when viewed from the direction perpendicular to the ab plane. The atomic arrangement is triangular, hexagonal, equilateral triangular or equilateral hexagonal, and perpendicular to the c-axis direction. From the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0044] CAAC is not a single crystal, but it is not made up of only amorphous material. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it's impossible to tell for sure.

[0045] When the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. The c-axis of each crystalline part that composes the CAAC is aligned in a certain direction (for example, the substrate surface supporting the CAAC, C Or, the individual CAACs may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate surface supporting the CAAC, It may be oriented in a direction perpendicular to the surface of the

[0046] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, the material may or may not be transparent to visible light. Sometimes they're not there.

[0047] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0048] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 15 to 17, the upward direction is the c-axis direction, and the direction perpendicular to the c-axis direction is the The plane where the two points are located is called the ab plane. When we simply refer to the upper half and the lower half, we are referring to the plane ab as the boundary. The upper half and the lower half.

[0049] Figure 15(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as 4) adjacent to the In atom. The structure shown has a metal atom and a nearby oxygen atom. The structure shown in Figure 15(A) is an octahedral structure, but it can be easily For simplicity, the structure is shown in a plan view. There are three O atoms in each group, each with four coordinates. The small group shown in Figure 15(A) has a zero charge.

[0050] Figure 15(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom. The structure shown has a tetracoordinated O atom and two tetracoordinated O atoms adjacent to Ga. Both exist on the ab plane. There is one each in the upper and lower halves of Figure 15(B). In addition, since In also has a five-coordinate structure, it can take the structure shown in Figure 15(B). The small group shown in FIG. 15(B) has a charge of 0.

[0051] FIG. 15(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 15(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in Figure 15(C), there are three 4-coordinate O atoms in the upper half and one 4-coordinate O atom in the lower half. There may be four-coordinated O. The small group shown in Figure 15(C) has a zero charge.

[0052] FIG. 15(D) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 15(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 15(D) has a charge of +1.

[0053] Figure 15(E) shows a small group containing two Zn atoms. The upper half of Figure 15(E) shows one Zn atom. The small group shown in Figure 15(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0054] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0055] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In atom have three neighboring In atoms in the downward direction, and the lower half Each of the three O atoms has three neighboring In atoms in the upward direction. One O atom in the upper half of the five-coordinate Ga atom has one neighboring Ga in the downward direction, and one O in the lower half has one neighboring Ga in the upward direction. One O atom in the upper half of the tetrahedral Zn has one neighboring Zn atom in the downward direction, and the three O atoms in the lower half Each O has three neighboring Zn atoms in the upward direction. The number of O atoms is equal to the number of adjacent metal atoms below the O atoms. The number of tetrahedral O atoms is equal to the number of neighboring metal atoms above the O atoms. The sum of the number of neighboring metal atoms in the downward direction and the number of neighboring metal atoms in the upward direction is 4. Therefore, the number of tetrahedral O atoms above a metal atom and the number of tetrahedral O atoms below another metal atom are When the sum of the number of O and the number of metal atoms is 4, two small groups containing metal atoms can bond together. For example, a hexacoordinated metal atom (In or Sn) is bonded via a tetracoordinated O atom in the lower half. In this case, since there are three tetrahedral O atoms, a pentahedral metal atom (Ga or In) or It will bond to one of the four-coordinate metal atoms (Zn).

[0056] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0057] Figure 16(A) shows a model diagram of the middle group that constitutes the layer structure of the In-Sn-Zn oxide. FIG. 16(B) shows a large group consisting of three medium groups. (C) shows the atomic arrangement when the layer structure of FIG. 16(B) is observed from the c-axis direction.

[0058] In FIG. 16(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 16(A), the upper and lower halves of In are There is one tetracoordinate O in each of them, which is shown as a circled 1. Similarly, in Figure 16 In (A), there is one tetracoordinate O in the bottom half and three tetracoordinate O in the top half. Zn with one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. This shows that:

[0059] In FIG. 16(A), the middle group, which constitutes the layer structure of In-Sn-Zn oxide, is Sn has three tetrahedral O atoms in the upper half and one in the lower half, and It bonds to In in the upper and lower halves, and the In has three tetracoordinate O atoms in the upper half. It bonds to Zn, and three tetracoordinate O atoms are attached to the upper half of the Zn via one tetracoordinate O atom in the lower half. In is bonded to a Zn atom with one tetracoordinate O atom in the upper half. It bonds to a small group of two atoms via a tetracoordinate O atom in the lower half of this small group. The structure is such that three tetracoordinate O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple groups combine to form a larger group.

[0060] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6 67, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. 5(E), there is a small group containing two Zn atoms. For example, there are Sn-containing If there is one small group containing two Zn atoms for every small group, the charges are canceled out. Therefore, the total charge of the layer structure can be set to zero.

[0061] Specifically, the large group shown in Figure 16(B) is repeated to form In-Sn-Zn The resulting In-S system oxide crystals (In2SnZn3O8) can be obtained. The layer structure of n-Zn oxide is In2SnZn2O7(ZnO) m (m is 0 or a natural number It can be expressed by the formula:

[0062] In addition, there are oxides of quaternary metals such as In-Sn-Ga-Zn oxides and ternary In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0063] For example, in Figure 17(A), a middle group model consisting of a layer structure of In-Ga-Zn oxide is shown. A diagram is shown.

[0064] In FIG. 17(A), the middle group, which constitutes the layer structure of In-Ga-Zn oxide, is In the upper half and lower half, there are three tetrahedral O atoms, and in the lower half, there is one tetrahedral O atom. It bonds to the Zn in the molecule, and through the three tetracoordinate O atoms in the lower half of the Zn, the tetracoordinate O atoms Each bond to a Ga atom in the upper half and the lower half, and one tetracoordinate O atom in the lower half of the Ga atom Three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the Several of these medium groups combine to form large groups.

[0065] Figure 17(B) shows a large group consisting of three medium groups. 17(B) shows the atomic arrangement when the layer structure of FIG. 17(B) is observed from the c-axis direction.

[0066] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are Since the valence numbers are +3, +2, and +3 respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge is always 0.

[0067] The middle group, which is composed of the layer structure of In-Ga-Zn oxide, is shown in FIG. The combination of different middle groups, In, Ga, and Zn, is not limited to the same middle group. Large groups are also possible.

[0068] The source terminal and the drain terminal of the transistor are connected to the polarity and the voltage of the transistor. The name changes depending on the level of the potential applied to the electrode. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source terminal, and the electrode to which a high potential is applied is called the The electrode connected to the drain terminal is called the drain terminal. The electrode to which the high potential is applied is called the drain terminal, and the electrode to which the high potential is applied is called the source terminal. In the following, either the source terminal or the drain terminal will be referred to as the first terminal, and the other will be referred to as the second terminal. 1, the connection relationship between the transistor 102 and the capacitor 103 included in the memory cell 101 will be described. .

[0069] The source terminal of a transistor is a source region that is a part of the active layer, or a region that is in the active layer. Similarly, the drain terminal of a transistor refers to the connected source electrode of the active layer. The term "drain electrode" refers to the drain region that is a part of the active layer, or the drain electrode that is connected to the active layer.

[0070] In this specification, connection means electrical connection, and the current, voltage, or potential is This corresponds to a state where the signal can be supplied or transmitted. Therefore, the connected state is a direct connection. does not necessarily refer to the state in which a current, voltage, or potential is available or transferable. To enable transmission, the signal is transmitted through elements such as wiring, conductive films, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via a direct connection.

[0071] Also, even if components that are independent on the circuit diagram are connected, For example, when a part of a wiring functions as an electrode, one conductive film is used for connecting a plurality of components. In this specification, the term "connection" refers to such a single conductive film. However, if a product combines the functions of multiple components, it is also included in this category.

[0072] In the memory cell 101 shown in FIG. 1, the gate electrode of the transistor 102 is connected to the word line W The first terminal of the transistor 102 is connected to one of the bit lines BL. The first terminal is connected to one electrode of the capacitor 103. The other electrode of the capacitor element 103 is connected to another word line WL different from one of the word lines. are connected to one another.

[0073] Specifically, in the cell array 100 shown in FIG. 1, in the memory cell 101 in the first row and first column, The gate electrode of the transistor 102 is connected to the word line WL1. The first terminal of the capacitor 102 is connected to the bit line BL1, and the second terminal of the capacitor 102 is connected to one of the bit lines BL1 and BL2. The other electrode of the capacitor 103 is connected to the word line WL2. is connected.

[0074] In the cell array 100 shown in FIG. 1, each memory cell 101 in the y-th row has a capacitance element. The other electrode of the terminal 103 is connected to a capacitance line CL.

[0075] In the cell array shown in FIG. 1, any memory cell 101 is connected to two adjacent word lines. However, one aspect of the present invention is not limited to this configuration. The two word lines connected to any one memory cell 101 may be spaced apart and not adjacent to each other. stomach.

[0076] In addition, in FIG. 1, the memory cell 101 includes a transistor 10 that functions as a switching element. Although the present invention is not limited to this configuration, In this embodiment, at least one transistor that functions as a switching element is provided in each memory cell. The number of the transistors may be plural. In the case where the switching element is made up of a plurality of transistors, The transistors may be connected in parallel, in series, or in a combination of series and parallel. may be connected in combination.

[0077] In this specification, the state in which transistors are connected in series means, for example, Only one of the first terminal and the second terminal of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the terminals. The state in which transistors are connected in parallel is when the first terminal of the first transistor is connected to the second transistor. the second terminal of the first transistor is connected to the second terminal of the second transistor; It means that it is connected to a child.

[0078] Next, the cell array 100 shown in FIG. 1 will be used as an example to explain the structure of a memory device according to one embodiment of the present invention. The operation of the cell array shown in FIG. A write period Ta, a data retention period Ts, and a read period Ts. The potentials applied to the cell array 100 during the above periods are different from each other. A timing chart is shown as an example.

[0079] In FIG. 4, the memory cell 101 in the i-th row and j-th column and the memory cell 101 in the i-th row and j+1-th column are and the memory cell 101 in the i+1th row and jth column, and the memory cell 101 in the i+1th row and j+1th column. These four cases are used as examples of writing, storing, and reading data. The memory cell 101 is assumed to be included in the memory cell 101 at x row and y column.

[0080] First, the operation of the cell array 100 during the write period Ta will be described. In FIG. 4, the memory cell 101 in the i-th row and the j-th column and the memory cell 102 in the i-th row and the j+1 The data is written to the memory cell 101 in the i+1th row and jth column first, and then Data is written to the memory cell 101 and the memory cell 101 in the (i+1)th row and the (j+1)th column. This example illustrates a case where:

[0081] First, the word line WLi connected to the memory cell 101 in the i-th row to be written is selected. Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi, and the word line The ground potential GND is applied to the word lines other than the word line WLi including WLi+1. Only the transistor 102 whose gate electrode is connected to the word line WLi is selectively turned on. It becomes like this.

[0082] During the period when the word line WLi is selected, the bit lines BLj and BL The potential of a signal containing data is applied to bit line BLj, bit line BLj+1. The level of the potential applied to the bit line B naturally differs depending on the data content. A high-level potential VDD is applied to Lj, and a ground potential GND is applied to the bit line BLj+1. The potential applied to the bit lines BLj and BLj+1 is The voltage is applied to one of the electrodes of the capacitor 103 via the transistor 102 .

[0083] The potential VH is equal to or higher than the potential VDD. The potential difference of the potential VDD is equal to or greater than the threshold voltage of the transistor 102. do.

[0084] FIG. 2A shows the state of each memory cell 101 when data is written to the memory cell 101 in the i-th row. 2A, the operation of the second terminal of the transistor 102 is shown. and one of the electrodes of the capacitor 103 are connected to a node FG. According to the above potential, the potential of the node FG is V The potential becomes DD, and the potential becomes ground potential GND in the memory cell 101 in the i-th row and j+1-th column. The amount of charge flowing into the capacitor 103 is controlled in accordance with the potential of the node FG. Write data to the memory cell 101 in the jth column and the memory cell 101 in the ith row and j+1th column will be carried out.

[0085] Next, the ground potential GND is applied to the word line WLi. The transistor 102 to which the output electrode is connected is turned off, and a charge is transferred to the capacitor 103. is maintained.

[0086] When an oxide semiconductor is used for the semiconductor film of the transistor 102, has the characteristic of having an extremely low off-state current. The charge is less likely to leak, and compared to when a semiconductor such as silicon is used for the transistor 102, , data can be retained for a long period of time.

[0087] Next, the word line WLi+ connected to the memory cell 101 in the (i+1)th row to be written Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi+1. The word lines other than the word line WLi+1 including the word line WLi are supplied with the ground potential GND. Therefore, the transistor 10 whose gate electrode is connected to the word line WLi+1 Only 2 is selectively turned on.

[0088] During the period when the word line WLi+1 is selected, the bit line BLj, the bit line The potential of a signal containing data is applied to bit line BLj+1. The level of the potential given to +1 naturally differs depending on the data content. The line BLj is applied with a ground potential GND, and the bit line BLj+1 is applied with a high-level potential VDD. The potential applied to the bit lines BLj and BLj+1 is The voltage is applied to one of the electrodes of the capacitor 103 through the transistor 102. (B) shows the state of each memory cell when writing data to the memory cell 101 in the i+1th row. 2B, the operation of the node FG The potential of the memory cell 101 in the (i+1)th row and the jth column is the ground potential GND, and the potential of the memory cell 101 in the (i+1)th row and the jth column is the ground potential GND. The potential of the memory cell 101 in the j+1th column is VDD. Therefore, by controlling the amount of charge flowing into the capacitor element 103, the memory cell in the (i+1)th row and the jth column Data is written to the memory cell 101 in the (i+1)th row and the memory cell 101 in the (j+1)th column.

[0089] In the cell array 100 shown in FIG. 1, the word line WLi+1 corresponds to the memory cell in the i+1th row. 101, and is also connected to the memory cell 101 in the i-th row. WLi+1 is connected to the other electrode of the capacitor 103 of the memory cell 101 in the i-th row. The other electrode of the capacitor 103 is connected to a potential Vcc during the period when the word line WLi is selected. The ground potential GND is applied to the word line WLi+ as shown in FIG. The potential VH is applied during the period when the capacitor 103 is selected. Since the potential difference between the pair of electrodes is maintained by the law of conservation of charge, the word line WLi+1 is selected. During this period, the potential difference between the potential VH and the ground potential GND is As a result, the voltage in the memory cell 101 in the i-th row and j-th column is The node FG is at a potential VDD+VH, and the memory cell 101 in the i-th row and j+1-th column The node FG is at the potential VH.

[0090] Next, the ground potential GND is applied to the word line WLi+1. The transistor 102 having a gate electrode connected to the capacitor 103 is turned off. Note that the potential difference between the pair of electrodes of the capacitor 103 satisfies the law of conservation of charge. Therefore, when the ground potential GND is applied to the word line WLi+1, the jth row The node FG in the memory cell 101 in the i-th row and j+1-th column is at the potential VDD. The node FG in the memory cell 101 is at the ground potential GND.

[0091] In order to prevent erroneous data from being written to the memory cell 101, each word line WL After the selection of the bit line BL is completed, it is desirable to stop the supply of the potential including the data to the bit line BL. I wish.

[0092] Next, the operation of the cell array 100 during the data retention period Ts will be described.

[0093] During the retention period Ts, all the word lines WL are charged to a level at which the transistors 102 are turned off. The potential of the memory cell in the i-th row, specifically the ground potential GND, is applied. When data is stored in the memory cell 101 of the i+1th row and the memory cell 101 of the i+1th row, 3A, the charge flowing into the capacitor 103 is While it is being held, the data is held.

[0094] Next, the operation of the cell array 100 during the data read period Tr will be described.

[0095] First, during the read period Tr, the bit line B connected to the memory cell 101 to be read is A high-level potential VR is applied to the memory cell 10 in the j-th column in FIG. 1 and the bit line BLj connected to the memory cell 101 in the j+1th column. A high-level potential VR is applied to the potentials VDD and BLj+1. The potential is the same as or lower than the potential VDD and higher than the ground potential GND. After the potential VR is applied, both the bit line BLj and the bit line BLj+1 are The system is in a charging state.

[0096] Next, the word line WLi connected to the memory cell 101 in the i-th row to be read is selected. Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi, and the word The other word lines including the line WLi+1 are supplied with the ground potential GND. Only the transistor 102 whose gate electrode is connected to the gate line WLi is selectively turned on. .

[0097] When the transistor 102 is turned on, the charge held in the capacitor 103 is read out. The charge flows to the bit line BL where the data is read, or the charge flows from the bit line BL where the data is read. The charge flows into the capacitance element 103. The above operation is determined by the potential of the node FG during the retention period. .

[0098] FIG. 3B shows the state of each memory cell 101 when data is read from the memory cell 101 in the i-th row. 4. Specifically, in the case of the timing chart shown in FIG. During the retention period, the node FG in the memory cell 101 in the ith row and jth column is at the potential VDD. Therefore, as shown in FIG. 3B, the transistor 102 is turned on during the read period. Then, a current flows from the capacitor 103 in the memory cell 101 in the i-th row and j-th column to the bit line BLj. Since the charge flows out, the potential of the bit line BLj rises to a potential VR+α. During the retention period, the node FG in the memory cell 101 in the i-th row and j+1-th column is set to the ground potential GND Therefore, when the transistor 102 is turned on during the readout period, the j+ Charge flows from the bit line BLj+1 to the capacitor element 103 in the memory cell 101 in the first column. As a result, the potential of the bit line BLj+1 drops to a potential VR-β.

[0099] Therefore, the potentials of the bit lines BLj and BLj+1 are the same as those of the memory cell 101 in the i-th row and j-th column and the A height corresponding to the amount of charge held in the capacitor 103 of the memory cell 101 in the j+1th column Then, by reading the difference in the amount of charge from the above potential, the memory in the i-th row and j-th column Data can be read from cell 101 and memory cell 101 in the i-th row and j+1-th column. .

[0100] Next, the data from the memory cell 101 in the i-th row and j-th column and the memory cell 101 in the i-th row and j+1-th column are When the data readout is completed, the bit line BLj and the bit line BLj+1 are set to a high level again. After applying the potential VR to the bit line BLj, the bit line BLj+1 is set to a floating state. To be in a certain state.

[0101] Then, the word line WLi+1 connected to the memory cell 101 in the i-th row to be read is Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi+1. The other word lines including the word line WLi are supplied with the ground potential GND. Only the transistor 102 whose gate electrode is connected to the word line WLi+1 is selectively turned on. It becomes like this.

[0102] When the transistor 102 is turned on, the charge held in the capacitor 103 is read out. The charge flows to the bit line BL where the data is read, or the charge flows from the bit line BL where the data is read. The charge flows into the capacitance element 103. The above operation is determined by the potential of the node FG during the retention period. .

[0103] Specifically, in the case of the timing chart shown in FIG. 4, in the immediately preceding retention period, The node FG in the memory cell 101 is at the ground potential GND. When the transistor 102 is turned on, the memory cell 101 in the (i+1)th row and the jth column Since charges flow from the bit line BLj into the capacitance element 103 in the bit line BLj, the potential of the bit line BLj The potential drops to VR-β. Also, during the immediately preceding hold period, the memory cell in the i+1th row and j+1th column The node FG in the memory cell 101 is at the potential VDD. When the transistor 102 is turned on, the memory cell 101 in the (i+1)th row and the (j+1)th column Since the charge flows from the capacitor 103 to the bit line BLj+1, the charge on the bit line BLj+1 The potential rises to VR+α.

[0104] Therefore, the potentials of the bit lines BLj and BLj+1 are the same as those of the memory cell 101 in the (i+1)th row and the jth column. Depending on the amount of charge stored in the capacitor 103 of the memory cell 101 in the (i+1)th row and the (j+1)th column, Then, by reading the difference in the amount of charge from the potential, the height of the jth row in the i+1th row is Data is read from the memory cell 101 in the i+1th row and j+1th column and the memory cell 101 in the i+1th row and j+1th column. You can put it out.

[0105] A read circuit is connected to the tip of each bit line BL, and the output signal of the read circuit is includes the data read from the cell array 100.

[0106] In this embodiment, four adjacent memory cells 101 are taken as an example, and write, hold, and read operations are performed. Although the operations of the specified readout have been described, one aspect of the present invention is not limited to this configuration. The above operation can be performed on the memory cell 101 at any address that has been set.

[0107] The capacitance line CL is maintained at a fixed potential such as the ground potential GND throughout the entire period. .

[0108] In a memory device according to one embodiment of the present invention, one word line is connected to memory cells in one row. are connected to the switching elements, and are connected to the capacitance elements in the memory cells of another row. Therefore, the number of wirings connected to the memory cells can be reduced. However, as described above, when a word line connected to a capacitance element is selected, The potential of the node FG increases as the potential of the word line increases. For example, Before writing the data, a high-level potential VDD has already been applied to the node FG. In this case, as shown in FIG. 2B, as the potential of the word line WLi+1 rises, In the i-th memory cell 101, the node FG becomes high to the potential VDD+VH. The transistor 102 in the j-th column memory cell 101 has a source terminal and a drain terminal The potential difference between the transistors increases, which tends to increase the off-state current. Wide-gap semiconductors such as oxide semiconductors are used to significantly reduce the off-state current of 02. It is preferable to use the above for the semiconductor film of the transistor 102. By significantly reducing the current, the memory This prevents the charge from leaking from the recell 101 and ensures a data retention period.

[0109] Next, an example of a specific structure of each memory cell 101 will be described.

[0110] FIG. 5A shows an enlarged top view of a part of the cell array 100 shown in FIG. 5(B) shows a cross-sectional view taken along dashed line A1-A2 in FIG. 5(A). In the example, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. It has been done.

[0111] The transistor 102 includes a semiconductor film 105 and a gate insulating film 106 formed on a substrate 104 having an insulating surface. The conductive film 106 and the conductive film 108 functioning as a source electrode or a drain electrode on the semiconductor film 105 are The insulating film 107, the semiconductor film 105, the conductive film 106, and the insulating film 108 on the conductive film 107, The gate electrode 104 is provided at a position overlapping the semiconductor film 105 with the film 108 sandwiched therebetween. The transistor 102 further includes a conductive film 109 covering the conductive film 109. The insulating film 110 may be included as a component. The transistor 102 has a top-gate, top-contact structure.

[0112] The capacitor 103 includes a conductive film 107 formed on a substrate 104 having an insulating surface, The insulating film 108 on the conductive film 107 and the conductive film 107 overlapping the insulating film 108 are sandwiched between the insulating film 108 and the conductive film 107. The conductive film 107, the insulating film 108, and the conductive film 111 overlap each other. functions as the capacitor element 103.

[0113] Note that the conductive film 106 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 109 also functions as a bit line. The conductive film 107 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 111 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0114] FIG. 6A shows another example of an enlarged top view of a part of the cell array 100 shown in FIG. FIG. 6(B) shows a cross-sectional view taken along the dashed line B1-B2 in FIG. 6(A). In FIG. 6B, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. 03 is formed.

[0115] The transistor 102 has a source electrode or a drain electrode formed on a substrate 104 having an insulating surface. Conductive films 116 and 117 function as drain electrodes, and conductive films 116 and 117 17, and the insulating film on the conductive film 116, the conductive film 117, and the semiconductor film 115. 118 and a gate electrode provided at a position overlapping the semiconductor film 115 with the insulating film 118 sandwiched therebetween. The transistor 102 further includes a conductive film 119 that functions as a conductive electrode. The insulating film 120 covering the film 119 may be included as a component. The transistor 102 shown in B) has a top-gate bottom-contact structure. .

[0116] The capacitor 103 includes a conductive film 117 formed on a substrate 104 having an insulating surface, The insulating film 118 on the conductive film 117 and the conductive film 117 overlapping the insulating film 118 are sandwiched between the insulating film 118 and the conductive film 117. The conductive film 117, the insulating film 118, and the conductive film 121 overlap each other. functions as the capacitor element 103.

[0117] Note that the conductive film 116 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 119 also functions as a bit line. The conductive film 117 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 121 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0118] FIG. 7A shows another example of an enlarged top view of a part of the cell array 100 shown in FIG. FIG. 7B shows a cross-sectional view taken along the dashed line C1-C2 in FIG. 7A. 7B, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. 03 is formed.

[0119] The transistor 102 is formed on a substrate 104 having an insulating surface. The conductive film 129 is a functional conductive film, the insulating film 128 is on the conductive film 129, and the insulating film 128 is sandwiched between the conductive film 129 and the insulating film 128. A semiconductor film 125 provided at a position overlapping the conductive film 129, and a source electrode on the semiconductor film 125. Alternatively, the conductive film 126 and the conductive film 127 function as drain electrodes. Furthermore, the transistor 102 includes a semiconductor film 125, a conductive film 126, and a conductive film 127. The insulating film 130 may be included as a component. The transistor 102 has a bottom-gate, top-contact structure.

[0120] In addition, the transistor 102 has a semiconductor film 125 between the conductive film 126 and the conductive film 127. The present invention provides a channel etch structure in which the insulating film 130 is exposed. The transistor 102 is not limited to the above structure. A channel protection film formed of an insulating film may be provided on the semiconductor film 125. By providing the protective film, when the conductive film 126 and the conductive film 127 are formed, etching is prevented. Damage such as film reduction caused by plasma or etching agent during etching may cause damage to the channel of the semiconductor film 125. Therefore, the transistor 102 can be prevented from being applied to the region where the transistor 102 is to be formed. Reliability can be improved.

[0121] The capacitor 103 includes a conductive film 131 formed on a substrate 104 having an insulating surface, The insulating film 128 on the conductive film 131 and the conductive film 131 overlapping the insulating film 128 are sandwiched between the insulating film 128 and the conductive film 131. The conductive film 131, the insulating film 128, and the conductive film 127 overlap each other. functions as the capacitor element 103.

[0122] Note that the conductive film 126 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 129 also functions as a bit line. The conductive film 127 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 131 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0123] FIG. 8A shows another example of an enlarged top view of a part of the cell array 100 shown in FIG. FIG. 8(B) shows a cross-sectional view taken along dashed line D1-D2 in FIG. 8(A). In FIG. 8B, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. 03 is formed.

[0124] The transistor 102 is formed on a substrate 104 having an insulating surface. a conductive film 139 that functions as a gate electrode; an insulating film 138 on the conductive film 139; and a source electrode on the insulating film 138. Alternatively, the conductive films 136 and 137 function as drain electrodes, and the conductive films 136 and The insulating film 138 is provided over the conductive film 137 so as to overlap with the conductive film 139 with the insulating film 138 interposed therebetween. The transistor 102 further includes a semiconductor film 135. The insulating film 140 covering the conductive film 136 and the conductive film 137 may be included as a component. The transistor 102 shown in FIGS. 8A and 8B is a bottom-gate type. It has a tact structure.

[0125] The capacitor 103 includes a conductive film 141 formed over a substrate 104 having an insulating surface, The insulating film 138 on the conductive film 141 and the conductive film 141 overlapping the insulating film 138 are sandwiched between the insulating film 138 and the conductive film 141. The conductive film 141, the insulating film 138, and the conductive film 137 overlap each other. functions as the capacitor element 103.

[0126] Note that the conductive film 136 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 139 also functions as a bit line. The conductive film 137 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 141 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0127] 5 to 8 illustrate the case where the transistor 102 has a single-gate structure. However, the transistor 102 has multiple gate electrodes electrically connected to each other. Alternatively, the semiconductor device may have a multi-gate structure having a plurality of channel forming regions.

[0128] 5 to 8, the transistor 102 has a gate electrode that is located only on one side of the active layer. The transistor 102 has an active layer and a A back gate electrode may be provided on the opposite side of the gate electrode. The gate electrode may be in a floating state where it is electrically insulated, or may be in a state where a potential is applied. In the latter case, the back gate electrode may have the same height as the gate electrode. A low potential may be applied, or a fixed potential such as ground may be applied. By controlling the potential applied to the back gate electrode, the threshold voltage of the transistor 102 can be adjusted. The pressure can be controlled.

[0129] As described in this embodiment, in a memory device according to one embodiment of the present invention, By providing the function as a capacitance line, the number of wires in the cell array can be reduced. Therefore, it is possible to increase the storage capacity per unit area without complicating the process. It is possible to realize a storage device that can do this.

[0130] (Embodiment 2) In this embodiment, a storage device according to one embodiment of the present invention having a configuration different from that shown in FIG. 1 will be described. The configuration of the channel array 200 will be described.

[0131] 9 is a circuit diagram showing an example of the configuration of the cell array 200 of this embodiment. In the cell array 200, a plurality of memory cells 201 are arranged in a first block 290 and a second block 291. The first block 290 is divided into blocks 291. The memory cells 201 included in the first block 290 are On the top, memory cells 201 included in the second block 291 are provided. The cell array 200 shown in this embodiment has a structure in which memory cells 201 are stacked. do.

[0132] In FIG. 9, the plurality of memory cells 201 are divided into a first block 290 and a second block 291. Although the example shows a case where the signal is divided into two blocks, one aspect of the present invention is that the signal is divided into two blocks. However, the present invention is not limited to the above. It's okay to have it.

[0133] Each of the plurality of blocks includes a plurality of memory cells 201 arranged in a matrix and a plurality of word lines. Each block has a plurality of active lines WL and a plurality of bit lines BL. The number of word lines WL and bit lines BL to be connected is determined by the number and arrangement of memory cells 201. The signal from the driving circuit is transmitted to the plurality of word lines WL and the plurality of bit lines B. L to each memory cell 201.

[0134] Specifically, in FIG. 9, a first block 290 has memory cells 201 arranged in x rows and y columns, and In addition, when the first word lines WLa1 to WLay and the first bit lines BLa1 to BLax are provided, 9, the second block 291 is composed of memory cells 292 arranged in rows x and columns y. 01, and the second word lines WLb1 to WLby and the second bit lines BLb1 to BL This shows an example where bx is present.

[0135] Each memory cell 201 is connected to a switch in the same manner as in the cell array 100 shown in FIG. The semiconductor device includes a transistor 202 that functions as a switching element and a capacitor 203. The gate electrode of the transistor 202 is connected to one of the word lines WL. The first terminal of the transistor 202 is connected to one of the bit lines BL, and the second terminal is connected to a capacitance element 9. However, in the cell array 200 shown in FIG. The other electrode of the element 203 is formed on one of the word lines of a different block or on a different layer. The capacitor is connected to one of the capacitor lines.

[0136] Specifically, in the cell array 200 shown in FIG. 9, for example, one of the second blocks 291 has In the memory cell 201 in the first column of the row, the gate electrode of the transistor 202 is connected to the second word line The first terminal of the transistor 202 is connected to the second bit line BLb1. 1, and the second terminal is connected to one electrode of the capacitor 203. The other electrode of the capacitor element 203 is connected to the first word line WLa1 of the first block 290. is connected to.

[0137] In the cell array 200 shown in FIG. 9, a capacitance line CL is provided below the first block 290. Specifically, in the cell array 200 shown in FIG. 10 shows an example in which the capacitance lines CL1 to CLy are provided below the first block 290. For example, in the memory cell 201 in the first row and first column of the first block 290, The gate electrode of the transistor 202 is connected to the first word line WLa1. The first terminal of the transistor 202 is connected to the first bit line BLa1, and the second terminal is The capacitor 203 is connected to one electrode of the capacitor 203. The other electrode of the capacitor 203 is , and is connected to a capacitance line CL1 provided below the first block 290.

[0138] In the cell array 200 shown in FIG. 9, in addition to the capacitance element 203 included in any one block, One electrode of the block is connected to a word line or a capacitance line of a block below the block. However, one embodiment of the present invention is not limited to this configuration. The other electrode of the capacitor 203 is connected to a word line or a capacitor of a block above the block. It may be connected to a line.

[0139] The memory cell 201 may include transistors, diodes, resistors, capacitors, etc., as needed. The transistor 202 may further include circuit elements such as a transistor, an inductor, etc. The switching element controls the inflow, retention, and outflow of charges in the capacitance element 203 . The difference in the amount of charge held in the capacitor element 203 determines the digital value of the stored data. The tal value can be identified.

[0140] Next, an example of a specific structure of each memory cell 201 will be described.

[0141] 10(A) to 10(C) are enlarged views of parts of each layer of the cell array 200 shown in FIG. An example of a top view is shown. The top views of each layer overlap at the dashed line E1-E2. 10(D) shows a cross-sectional view taken along dashed line E1-E2 in FIGS. 10(A) to 10(C).

[0142] The first layer of the cell array 200 is formed on a substrate 204 having an insulating surface. In the first layer of the cell array 200, a conductive film 231 that functions as a capacitance line is formed. .

[0143] The second layer of the cell array 200 is formed on an insulating film 232 that covers the conductive film 231. The second layer of the cell array 200 includes a transistor of the first block 290. A transistor 202a and a transistor 202b are formed.

[0144] The transistor 202a has a semiconductor film 205a and a semiconductor film 205b formed on the insulating film 232. The conductive film 206a and the conductive film 205a functioning as a source electrode or a drain electrode are 7a, the insulating film 208 on the semiconductor film 205a, the conductive film 206a and the conductive film 207a, and the insulating film The insulating film 208 is sandwiched between the gate electrode 204 and the semiconductor film 205a. The transistor 202b has a semiconductor layer over an insulating film 232. a semiconductor film 205b and a conductive film serving as a source electrode or a drain electrode on the semiconductor film 205b. The conductive film 206b and the conductive film 207b, the semiconductor film 205b, the conductive film 206b and the conductive film 20 The insulating film 208 on the semiconductor film 205b is placed at a position overlapping the insulating film 208 on the semiconductor film 205b with the insulating film 208 sandwiched therebetween. The transistor has a conductive film 209 that functions as a gate electrode. The transistor 202a and the transistor 202b form an insulating film 230 that covers the conductive film 209. The transistor 202a and the transistor 202b shown in FIGS. The transistor 202b has a top-gate, top-contact structure.

[0145] The overlapping portion of the conductive film 207a, the insulating film 232, and the conductive film 231 forms a capacitance element. The conductive film 207b, the insulating film 232, and the conductive film 231 function as the insulating film 203a. The overlapping portion functions as the capacitor 203b. is contained in the first block 290.

[0146] The conductive film 206a serves as a source electrode or a drain electrode of the transistor 202a. The conductive film 206b serves as a source electrode or a drain electrode of the transistor 202b. The conductive film 209 functions as a first bit line. 2a and transistor 202b, and also serves as the gate electrode of the first word line. The conductive film 207a functions as a source electrode or a drain electrode of the transistor 202a. The conductive layer 203 functions as an electrode of the capacitor 203a as described above. The film 207b functions as a source electrode or a drain electrode of the transistor 202b. In addition, as described above, it functions as an electrode of the capacitor 203b.

[0147] The third layer of the cell array 200 is formed on the insulating film 240 that covers the insulating film 230. The third layer of the cell array 200 includes a transistor of the second block 291. A transistor 202c and a transistor 202d are formed.

[0148] The transistor 202c has a semiconductor film 205c and a semiconductor film 205d formed on the insulating film 240. The conductive film 206c functioning as a source electrode or a drain electrode and the conductive film 205c are 7c, the insulating film 241 on the semiconductor film 205c, the conductive film 206c, and the conductive film 207c, The insulating film 241 is sandwiched between the gate electrode 205 and the semiconductor film 205c. The transistor 202d has a semiconductor layer formed on the insulating film 240 and a conductive film 242 that functions as a gate insulating film. a semiconductor film 205d and a conductive film serving as a source electrode or a drain electrode on the semiconductor film 205d. The conductive film 206d and the conductive film 207d, the semiconductor film 205d, the conductive film 206d and the conductive film 20 The insulating film 241 is provided on the semiconductor film 205d, and the insulating film 241 is provided in a position overlapping the semiconductor film 205d with the insulating film 241 interposed therebetween. The transistor has a conductive film 242 that functions as a gate electrode. The insulating film 243 covering the conductive film 242 is formed between the transistor 202c and the transistor 202d. The transistor 202c shown in FIG. 10(A) and FIG. 10(D) may be included in the element. The transistor 202d is a top-type transistor, similar to the transistors 202a and 202b. It has a gate-type top contact structure.

[0149] The conductive film 207c, the insulating film 230, the insulating film 240, and the conductive film 209 overlap each other. The conductive film 207d, the insulating film 230, and the insulating film 230 function as the capacitor 203c. The portion where the insulating film 240 and the conductive film 209 overlap functions as a capacitor 203d. The capacitance element 203c and the capacitance element 203d are included in the second block 291.

[0150] The conductive films 206c and 206d are connected to the transistors 202c and 202 d and also functions as a second bit line. The conductive film 242 serves as the gate electrodes of the transistor 202c and the transistor 202d. The conductive film 207c functions as a second word line. 2c as a source or drain electrode, and as described above, The conductive film 207d functions as an electrode of the transistor 203d. The gate electrode functions as a gate electrode or a drain electrode of the capacitor 203d, as described above. It functions as a pole.

[0151] In FIG. 10, a parasitic capacitance formed between the first word line and the second word line is reduced. Therefore, the conductive film 209 and the conductive film 242 are spaced apart from each other, in other words, the conductive film 209 of the substrate 204 is The conductive film 209 and the conductive film 242 are arranged so as not to overlap in the vertical direction. However, one aspect of the present invention is not limited to this configuration, and the conductive layer 204 may be formed in a direction perpendicular to the substrate 204. The film 209 and the conductive film 242 may be disposed so as to overlap each other.

[0152] 10, the top surface of the insulating film 232 is the surface of the transistor 2 formed thereon. It is desirable that the transistors 202a and 202b are planarized to match the characteristics of the transistors 202a and 202b. Therefore, after forming the insulating film 232, the transistors 202a and 202b are formed. Before forming the insulating film 232, it is desirable to flatten the surface of the insulating film 232 by a CMP method or the like. Similarly, in FIG. 10, the top surface of insulating film 240 is the surface of the transistor to be formed thereon. 202c, and it is desirable that the transistor 202d be planarized to match the characteristics of the transistor 202c. Therefore, after forming the insulating film 240, the transistors 202c and 202d are Before forming the insulating film 240, it is desirable to flatten the surface of the insulating film 240 by a CMP method or the like. .

[0153] Next, a specific example of each memory cell 201 when the transistor structure is different from that shown in FIG. 10 will be described. An example of the structure will be described.

[0154] 11(A) to 11(C) are enlarged views of parts of each layer of the cell array 200 shown in FIG. An example of a top view is shown. The top views of each layer overlap at the dashed line F1-F2. 11(D) shows a cross-sectional view taken along dashed line F1-F2 in FIGS. 11(A) to 11(C).

[0155] The cell array 200 shown in FIGS. 11(A) to 11(D) includes a transistor 202a, a transistor 202b, a transistor 202c, a transistor 202d, a transistor 202e, a transistor 202f, a transistor 202g, a transistor 202h ... The structures of the transistors 202b, 202c, and 202d are different from those in FIG. do.

[0156] In the cell array 200 shown in FIGS. 11(A) to 11(D), the first layer of the cell array 200 is The cell array 200 is formed on a substrate 204 having an insulating surface. A conductive film 236 that functions as a capacitance line is formed on the first insulating film 232 .

[0157] The second layer of the cell array 200 is formed on the insulating film 234 that covers the conductive film 236. The second layer of the cell array 200 includes a transistor of the first block 290. A transistor 202a and a transistor 202b are formed.

[0158] Specifically, the transistors 202a and 202b have a source and a drain on the insulating film 234. The conductive film 216a and the conductive film 217a function as an electrode or a drain electrode, and the conductive film 21 6b and conductive film 217b, conductive film 216a and conductive film 217a, conductive film 216b and conductive film The semiconductor film 215a and the semiconductor film 215b on the conductive film 217b, the conductive film 216a and the conductive film 217b 17a, the conductive film 216b, the conductive film 217b, the semiconductor film 215a, and the semiconductor film 215b The insulating film 218 is sandwiched between the semiconductor film 215a and the semiconductor film 215b. The conductive film 219 functions as a gate electrode and is provided at a position corresponding to the gate electrode. The transistor 202a and the transistor 202b are formed by insulating film 235 covering the conductive film 219. In the cell array 200 shown in FIGS. 11(A) to 11(D), The transistor 202a and the transistor 202b are top-gate bottom-contact transistors. It has a hexagonal structure.

[0159] 10, the conductive film 217a, the insulating film 234, and the conductive film 236 are The overlapping portion functions as a capacitor 203a. The portion where the conductive film 236 overlaps with the capacitor 203b functions as the capacitor 203b. 3a and the capacitive element 203b are included in the first block 290.

[0160] Specifically, the transistors 202c and 202d are provided over the insulating film 244 as follows: The conductive films 216c and 217c function as source and drain electrodes. The conductive film 216d and the conductive film 217d, and the conductive film 216c and the conductive film 217c and the conductive film 216d The semiconductor film 215c on the conductive film 217d, the semiconductor film 215d, the conductive film 216c and the conductive film 216d The conductive film 217c, the conductive film 216d and the conductive film 217d, the semiconductor film 215c, the semiconductor film 215 The insulating film 245 on the semiconductor film 215c and the semiconductor film 215d are sandwiched between the insulating film 245. and a conductive film 246 which functions as a gate electrode and is provided in a position overlapping with the conductive film 246. The transistors 202c and 202d are formed by insulating films covering the conductive film 246. 11(A) to 11(D) may include the cell array 247 as a component. In 00, transistor 202c and transistor 202d are connected to transistor 202a and transistor 202b. Like the transistor 202b, it has a top-gate, bottom-contact structure.

[0161] 10, the conductive film 216c, the insulating film 235, and the insulating film 244 are formed. The portion overlapping with the conductive film 219 functions as a capacitor 203c. d, and the insulating film 235, the insulating film 244, and the conductive film 219 overlap each other. The capacitive element 203c and the capacitive element 203d are connected to the second block 291. Included.

[0162] In FIG. 11, in order to reduce the parasitic capacitance formed between the first word line and the second word line, Therefore, the conductive film 219 and the conductive film 246 are spaced apart from each other, in other words, the vertical direction of the substrate 204 is The conductive film 219 and the conductive film 246 are arranged so as not to overlap in the perpendicular direction. However, one embodiment of the present invention is not limited to this structure. The conductive film 219 and the conductive film 246 may be disposed so as to overlap each other.

[0163] 11, the top surface of the insulating film 234 is the surface of the transistor 2 formed thereon. It is desirable that the transistors 202a and 202b are planarized to match the characteristics of the transistors 202a and 202b. Therefore, after forming the insulating film 234, the transistors 202a and 202b are formed. Before forming the insulating film 234, it is desirable to flatten the surface of the insulating film 234 by a CMP method or the like. Similarly, in FIG. 11, the top surface of insulating film 244 is the surface of the transistor formed thereon. 202c, and it is desirable that the transistor 202d be planarized to match the characteristics of the transistor 202c. Therefore, after forming the insulating film 244, the transistors 202c and 202d are Before forming the insulating film 244, it is desirable to flatten the surface of the insulating film 244 by a CMP method or the like. .

[0164] In addition, in FIG. 10, all the transistors have a top-gate top-contact structure. In Figure 11, all the transistors have a top-gate bottom-contact structure. However, the present invention is not limited to this configuration, and the transistor may be a bottom gate type. That's fine.

[0165] This embodiment mode can be implemented in combination with the above embodiment modes.

[0166] (Embodiment 3) In this embodiment, a method for manufacturing a transistor included in a cell array will be described. In this embodiment, a transistor including an oxide semiconductor will be described as an example.

[0167] First, as shown in FIG. 12(A), an insulating film 701 is formed on a substrate 700. A conductive film 702 and a conductive film 703 are formed on the transistor 712. It functions as the gate electrode of the transistor 713 and also as a word line. The conductive film 703 functions as a word line different from the above-mentioned word line.

[0168] There is no significant limitation on the material that can be used for the substrate 700, but at least it is necessary to use a material that can be used for subsequent processing. The substrate 700 must have heat resistance sufficient to withstand the heat treatment. Glass substrates manufactured by the fusion method or float method, quartz substrates, semiconductor substrates, ceramic A glass substrate can be used when the temperature of the subsequent heat treatment is high. For this purpose, it is advisable to use a material with a strain point of 730°C or higher. Generally, substrates made of synthetic resin tend to have a lower heat resistance temperature compared to the above substrates. Any material can be used as long as it can withstand the processing temperature in the process.

[0169] The insulating film 701 is made of a material that can withstand the temperature of a heat treatment in a later manufacturing process. The insulating film 701 is made of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or aluminum nitride. It is preferable to use aluminum, aluminum oxide, etc.

[0170] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means substance.

[0171] The thickness of the conductive film 702 and the conductive film 703 is 10 nm to 400 nm, preferably 100 nm to 400 nm. In this embodiment, the thickness is set to 200 nm by sputtering using a tungsten target. After forming a 150 nm conductive film, the conductive film is etched to form the desired shape. The conductive films 702 and 703 are patterned. When the conductive films 702 and 703 have tapered edges, the gate insulating film stacked thereon can be easily formed. This is preferable because it improves the film coverage. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0172] Next, as shown in FIG. 12(B), a gate insulating film 70 is formed on the conductive film 702 and the conductive film 703. After forming the conductive film 702, an oxide semiconductor film is formed on the gate insulating film 704 at a position where the oxide semiconductor film 702 overlaps the conductive film 702. Then, a dielectric film 705 and an oxide semiconductor film 706 are formed.

[0173] The gate insulating film 704 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. Silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x >0, y>0), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y>0), nitrogen-doped hafnium aluminate (HfAl x Oy (x>0, y> 0)) or the like, can be formed by laminating a single film or a plurality of films.

[0174] It is desirable that the gate insulating film 704 contains as little impurities as possible, such as moisture and hydrogen. When forming a silicon oxide film by sputtering, a silicon target is used. A quartz target or a quartz target is used, and oxygen or a mixture of oxygen and argon is used as the sputtering gas. A mixed gas is used.

[0175] By removing impurities and reducing oxygen defects, the i-type or substantially i-type structure is obtained. The oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to the interface state. Therefore, the oxide semiconductor films 705 and 706 are purified in a later step. As a result, oxide semiconductor films 705 and 706 are formed at the interfaces between the oxide semiconductor film 705 and the gate insulating film 704. Therefore, it is important to reduce the interface state at the gate insulating film 704. For example, high density plastics using microwaves (frequency 2.45 GHz) are required. Zuma CVD is preferred because it can form dense, high-quality insulating films with high dielectric strength. The close contact between the oxide semiconductor and the high-quality gate insulating film reduces the interface state. As a result, the interface characteristics can be improved.

[0176] Of course, if a high-quality insulating film can be formed as the gate insulating film 704, the sputtering method can be used. Other film formation methods such as tarring and plasma CVD can be applied. The insulating film may be one whose film quality and interface characteristics with the oxide semiconductor are improved by the heat treatment. In any case, it goes without saying that the gate insulating film must be of high quality, and the gate insulating film and oxide Any material may be used as long as it can reduce the interface state with the compound semiconductor and form a good interface.

[0177] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 704 having a structure in which an insulating film such as a silicon dioxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are classified into insulating films with high barrier properties and oxide semi-insulating films. The insulating film is formed between the conductive film 705 and the oxide semiconductor film 706. , for example, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. By using an insulating film with high barrier properties, it is possible to prevent moisture or hydrogen from entering the atmosphere. Impurities in the substrate 700, such as alkali metals and heavy metals, are oxidized. In the oxide semiconductor film 705, the oxide semiconductor film 706, the gate insulating film 704, or the oxide semiconductor Preventing penetration into the interfaces between the conductor film 705, the oxide semiconductor film 706, and other insulating films and their vicinity In addition, a nitrogen oxide film can be formed in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low content of The insulating film having high thermal conductivity is prevented from being in direct contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. can be done.

[0178] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0)), and a second gate insulating film is formed on the first gate insulating film. As the insulating film, a silicon oxide film (SiO x (x>0) The gate insulating film 704 may be formed by layering the gate insulating film 704 with a thickness of 100 nm. may be set appropriately depending on the characteristics required of the transistor.

[0179] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 70 having a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 4.

[0180] The gate insulating film 704 is formed on the oxide semiconductor film 705 and the oxide semiconductor film 70 When hydrogen is contained in the oxide semiconductor film 705 and the oxide semiconductor film 706, the oxide semiconductor film 705 and the oxide semiconductor film 706 are in contact with each other. The gate insulating film 704 is preferably free of hydrogen, hydroxyl groups, and water, since these have a negative effect on the electrical properties of the transistor. It is desirable that the gate insulating film 704 does not contain hydrogen, hydroxyl groups, and moisture. In order to prevent this, the preheating chamber of the sputtering equipment is used as a pretreatment for film formation. The substrate 700 on which the conductive films 702 and 703 are formed is preheated, and the conductive films 702 and 703 are adsorbed to the substrate 700. It is preferable to desorb and exhaust impurities such as moisture or hydrogen that have been absorbed. The temperature is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means provided in the preheating chamber is preferably a cryopump. It can also be omitted.

[0181] The oxide semiconductor films 705 and 706 are formed by an oxide semiconductor film formed on the gate insulating film 704. The oxide semiconductor film can be formed by processing the oxide semiconductor film into a desired shape. The film thickness is 2 nm or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably The oxide semiconductor film is formed by using an oxide semiconductor as a target. The oxide semiconductor film is formed by sputtering using a rare gas (e.g., argon). ) atmosphere, oxygen atmosphere, or a mixture of rare gas (e.g., argon) and oxygen atmosphere. The film can be formed by sputtering.

[0182] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating film 704 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. The treatment may be carried out in an atmosphere containing argon to which chlorine, carbon tetrafluoride, etc. have been added.

[0183] The oxide semiconductor film is made of the above-mentioned quaternary metal oxide In-Sn-Ga-Z. n-type oxide semiconductors, In-Ga-Zn-type oxide semiconductors, which are oxides of ternary metals, In -Sn-Zn oxide semiconductor, In-Al-Zn oxide semiconductor, Sn-Ga-Zn oxide oxide semiconductors, Al-Ga-Zn oxide semiconductors, Sn-Al-Zn oxide semiconductors, and In-Zn oxide semiconductors, Sn-Zn oxide semiconductors, and Al- Zn-based oxide semiconductor, Zn-Mg-based oxide semiconductor, Sn-Mg-based oxide semiconductor, In-M In-based oxide semiconductors, In-Ga-based oxide semiconductors, In-based oxide semiconductors, Sn-based oxide semiconductors Conductors, Zn-based oxide semiconductors, etc. can be used.

[0184] In this embodiment, a tantalum containing In (indium), Ga (gallium), and Zn (zinc) is used. In-Ga-Zn oxide semiconductor with a thickness of 30 nm obtained by sputtering using a Zn target The conductive thin film is used as an oxide semiconductor film. When forming the film by the quartz crystal deposition method, the atomic ratio of In:Ga:Zn is preferably 1:1:1, In-, denoted as 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 A Ga-Zn oxide target is used. In-Ga-Zn oxide with the above atomic ratio is used. By depositing an oxide semiconductor film using an oxide target, polycrystalline or CAAC can be obtained. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more. The filling rate is preferably 95% or more and less than 100%. By using the oxide semiconductor film, the formed oxide semiconductor film becomes a dense film.

[0185] When an In-Zn oxide material is used as the oxide semiconductor, the target to be used is The composition ratio is In:Zn=50:1 to 1:2 in atomic ratio (InO 3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn= 1.5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO = 3:4 to 15:2) For example, the target used to form an oxide semiconductor film made of In-Zn oxide is When the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn By keeping it within the above range, it is possible to realize an improvement in mobility.

[0186] In addition, when forming an In-Sn-Zn oxide, the composition ratio of the target to be used is set to In :Sn:Zn atomic ratio is 1:2:2, 2:1:3, 1:1:1, or 20:45: Let's say it's 35.

[0187] In this embodiment, the substrate is held in a processing chamber maintained in a reduced pressure state, and the remaining moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. During the deposition, the substrate temperature is set to 100° C. or higher and 600° C. or lower, preferably The temperature may be 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump. As an exhaust means, a turbo pump with a A cryopump may be used to evacuate the deposition chamber. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms Since the exhaust gas contains the oxide semiconductor film formed in the deposition chamber, The concentration of impurities can be reduced.

[0188] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, and the film This is preferable because the thickness distribution is uniform.

[0189] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, up to the gate insulating film 704 is formed in the pre-heating chamber of the sputtering device. The substrate 700 is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 700. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. A pump is preferred. However, this preheating step can be omitted.

[0190] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m 3 / second or less By doing so, it is possible to prevent alkali from being added to the oxide semiconductor film during the film formation by sputtering. It is possible to reduce the inclusion of impurities such as metals and hydrides. By using an adsorption type vacuum pump, alkali metals, hydrogen atoms, hydrogen molecules, Backflow of impurities such as water, hydroxyl radicals, or hydrides can be reduced.

[0191] In addition, by setting the purity of the target to 99.99% or more, it is possible to prevent the target from being mixed into the oxide semiconductor film. It is possible to reduce alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, etc. In addition, by using the target, lithium, sodium, and the like can be easily formed in the oxide semiconductor film. The concentration of alkali metals such as sodium and potassium can be reduced.

[0192] Note that etching for forming the oxide semiconductor films 705 and 706 was performed by Dry etching or wet etching may be used, or both may be used. The etching gas used in this process is a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2 ), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc. ) is preferable. Also, a gas containing fluorine (a fluorine-based gas, for example, carbon tetrafluoride (CF4), Sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc. , hydrogen bromide (HBr), oxygen (O2), and these gases are mixed with helium (He) and argon (A r), or a gas to which a rare gas such as argon is added.

[0193] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0194] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Organic acids such as phosphoric acid and oxalic acid can be used. (manufactured by Kanto Chemical Co., Ltd.) is used.

[0195] Resist masks for forming the oxide semiconductor films 705 and 706 are formed by ink jet printing. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0196] Note that reverse sputtering is performed before forming a conductive film in the next step. Resist residues adhering to the surfaces of the semiconductor film 706 and the gate insulating film 704 are removed. It is preferable that

[0197] Note that the oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen (water) as impurities. It may contain a large amount of water or hydrogen, which easily forms donor levels. Therefore, in one embodiment of the present invention, In order to reduce impurities such as water or hydrogen in the conductive film (dehydration or dehydrogenation), In an atmosphere, in an inert gas atmosphere such as nitrogen or rare gas, in an oxygen gas atmosphere, or in ultra-dry air (When measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter In this case, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, The oxide semiconductor film 705 and the oxide semiconductor film 706 are The product is then subjected to heat treatment.

[0198] The oxide semiconductor films 705 and 706 are subjected to heat treatment. Moisture or hydrogen can be released from the oxide semiconductor film 705 and the oxide semiconductor film 706. The substrate is heated at a temperature of 250° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. For example, the heat treatment can be performed at 500°C for 3 to 6 minutes. If the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so the strain point of the glass substrate can be reduced. It can be processed at temperatures above this.

[0199] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0200] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gases such as rare gases like argon or nitrogen that do not react with the material to be treated by heat treatment. The body is used.

[0201] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is mixed with water or water. It is preferable that the nitrogen or helium introduced into the heat treatment device is not included. The purity of rare gases such as neon and argon is 6N (99.9999%) or more, preferably 7N (99.9999%) or more. N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm) pm or less).

[0202] Note that oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. There is no problem even if it is used in a low-cost sodalite, which contains a large amount of alkali metals such as sodium. It has been pointed out that ash glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current Status of Physical Properties and Device Development," Solid State Physics, September 2009, Vol. 44, pp. 62 1-633.) However, this is not an appropriate indication. Alkali metals do not form oxide semiconductors. Alkaline earth metals are not constituent elements of oxide semiconductors, so they are considered impurities. In particular, Na, among alkali metals, is an impurity when it is not an element that is present in the alloy. When the insulating film in contact with the semiconductor film is an oxide, Na diffuses into the insulating film. + It becomes. In addition, Na breaks the bond between the metal and oxygen that constitute the oxide semiconductor in the oxide semiconductor film. As a result, for example, the threshold voltage may change in the negative direction. This shift leads to deterioration of transistor characteristics, such as normally-on and reduced mobility. This impurity causes transistor characteristics to vary. The deterioration and variation of the characteristics occur when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, the hydrogen concentration in the oxide semiconductor film is 1×10 18 / cm 3 below, More preferably 1×10 17 / cm 3 If it is less than 100%, reduce the concentration of the impurities. Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5 × 10 16 / cm 3 Less than 1 × 10 16 / cm 3 or less, more preferably 1 × 10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 below, Preferably 1 x 10 15 / cm 3 Similarly, the measured value of the K concentration should be 5 x 1 0 15 / cm 3 Less than 1 × 10 15 / cm 3 The following would be appropriate.

[0203] Through the above steps, the hydrogen concentrations in the oxide semiconductor films 705 and 706 were reduced. This allows the oxide semiconductor film to be highly purified, thereby stabilizing the oxide semiconductor film. In addition, the carrier density caused by hydrogen defects is extremely low when the material is heated below the glass transition temperature. Therefore, it is possible to form an oxide semiconductor film having a wide band gap. The plate can be used to fabricate transistors, which can improve mass productivity. The treatment can be performed at any time after the oxide semiconductor film is formed.

[0204] Note that the oxide semiconductor films 705 and 706 may be amorphous or crystalline. The crystalline oxide semiconductor film may have a crystalline structure having a c-axis orientation. Oxide semiconductor (also called C-Axis Aligned Crystal: CAAC) Even if the oxide semiconductor film contains This is preferable because it is possible.

[0205] An oxide semiconductor film composed of CAAC can also be fabricated by a sputtering method. To obtain CAAC by sputtering, the oxide semiconductor film must be deposited at the initial stage. The crystals are grown using the hexagonal crystals as seeds. To achieve this, it is important to keep the distance between the target and the substrate as large as possible (for example, For example, about 150 mm to 200 mm), and the substrate heating temperature is set to 100°C to 500°C, preferably 20 The temperature is preferably 0 to 400°C, more preferably 250 to 300°C. In addition, the deposited oxide semiconductor film is heat-treated at a temperature higher than the substrate heating temperature during film formation. This makes it possible to repair micro defects contained in the film and defects at the interface of the stacked layers.

[0206] Specifically, CAAC has a hexagonal lattice structure in the ab plane parallel to the insulating film surface. and a zinc-containing crystal having a hexagonal structure and a c-axis orientation that is approximately perpendicular to the ab plane. It's Akira.

[0207] Compared to amorphous oxide semiconductors, CAAC has an ordered structure of metal-oxygen bonds. In other words, when the oxide semiconductor is amorphous, the coordination number may differ depending on the individual metal atom. It is possible, but in CAAC, the coordination number of the metal atom is almost constant. The deficiency of hydrogen atoms (including hydrogen ions) and alkali metal atoms is reduced, resulting in the release and bonding of hydrogen atoms. It has the effect of reducing charge transfer and instability.

[0208] Therefore, by manufacturing a transistor using an oxide semiconductor film including CAAC, Occurs after applying light or bias-thermal stress (BT) to a transistor Therefore, the amount of change in the threshold voltage of the transistor can be reduced. It is possible to fabricate transistors with dielectric properties.

[0209] Next, as shown in FIG. 12C, a source electrode or a drain electrode is formed over the oxide semiconductor film 705. The conductive films 707 and 708 functioning as gate electrodes were formed over the oxide semiconductor film 706. A conductive film 709 and a conductive film 710 functioning as a source electrode and a drain electrode are formed.

[0210] Specifically, the conductive films 707 to 710 are formed by the oxide semiconductor film 705 and the oxide semiconductor film 706. After forming a conductive film on the substrate 706 by sputtering or vacuum deposition, the conductive film is molded into a predetermined shape. The film can be formed by patterning.

[0211] The conductive films 707 to 710 can be formed using aluminum, chromium, copper, tantalum, An element selected from titanium, molybdenum, and tungsten, or a composite containing the above elements Examples of the metal include gold and alloy films made of the above elements. chromium, tantalum, titanium, molybdenum, tungsten, etc. on the underside or on the top of the metal film Any high melting point metal film may be laminated. Aluminum or copper has a heat resistance. To avoid problems with corrosion, it is recommended to use it in combination with high melting point metal materials. Metal materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Scandium, yttrium, etc. can be used.

[0212] The conductive films 707 to 710 may each be formed from a single conductive film. For example, the conductive film may be formed by laminating a plurality of conductive films. A single layer structure of aluminum film, a two-layer structure with titanium film laminated on aluminum film, and titanium film. An aluminum film is layered on top of the titanium film, and a titanium film is then formed on top of that, creating a three-layer structure. Structure, etc.

[0213] The conductive films 707 to 710 are formed using a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium oxide. Indium tin oxide mixture, indium oxide zinc oxide mixture or the above metal oxide materials with silicon A material containing silicon or silicon oxide can be used.

[0214] When heat treatment is performed after the conductive films 707 to 710 are formed, the conductive films 707 to 710 must be made of a material that can withstand the heat treatment. It is preferable that the conductive films 707 to 710 have heat resistance.

[0215] Note that the oxide semiconductor films 705 and 706 are formed during etching of the conductive film. The materials and etching conditions are adjusted appropriately so that the etching is not removed as much as possible. Depending on the conditions, exposed portions of the oxide semiconductor films 705 and 706 may be partially etched. By etching, grooves (recesses) may be formed.

[0216] In this embodiment, a titanium film is used as the conductive films 707 to 710. Therefore, a solution containing ammonia and hydrogen peroxide (ammonia hydrogen peroxide solution) is used to selectively induce The oxide semiconductor film 705 and the oxide semiconductor film 706 can be wet-etched. 706 may also be partially etched. Specifically, the solution containing ammonia hydrogen peroxide is 31% by weight of hydrogen peroxide solution, 28% by weight of ammonia solution, and water were mixed in a volume ratio of 5:2:2. A mixed aqueous solution is used. Alternatively, a solution containing chlorine (Cl2), boron trichloride (BCl3), etc. The conductive film may be dry-etched using a gas.

[0217] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the applied light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be formed by etching a plurality of resist masks. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A resist that corresponds to at least two different patterns using a single multi-tone mask Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0218] In addition, the oxide semiconductor film 705 and the conductive film 707 functioning as a source electrode or a drain electrode and the conductive film 708, or between the oxide semiconductor film 706 and the source or drain electrode The conductive film 709 and the conductive film 710 functioning as a source region and a drain region are formed between the conductive film 709 and the conductive film 710. As a material for the oxide conductive film, an oxide conductive film may be provided. It is preferable that the material contains zinc as a component, and it is preferable that the material does not contain indium oxide. Such oxide conductive films include zinc oxide, zinc aluminum oxide, and zinc aluminum oxynitride. Aluminum, etc. can be applied.

[0219] For example, in the case of forming an oxide conductive film, patterning for forming the oxide conductive film, The conductive films 707 to 710 are patterned together. is also good.

[0220] By providing an oxide conductive film that functions as a source region and a drain region, Resistance between the oxide semiconductor film 705 and the conductive film 707 and the conductive film 708, and resistance between the oxide semiconductor film 706 and the conductive film Since the resistance between the conductive film 709 and the conductive film 710 can be reduced, high-speed operation of the transistor can be achieved. In addition, the oxide layer that functions as the source and drain regions can be formed. By providing the conductive film, the withstand voltage of the transistor can be increased.

[0221] Next, a plasma treatment using a gas such as N2O, N2, or Ar may be performed. This plasma treatment removes water and the like attached to the exposed surface of the oxide semiconductor film. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0222] After the plasma treatment, the conductive films 707 to 709 are removed as shown in FIG. 10, the oxide semiconductor film 705, and the oxide semiconductor film 706. Form.

[0223] The insulating film 711 is formed using the same material and the same stacked structure as the gate insulating film 704. The insulating film 711, like the gate insulating film 704, is resistant to moisture and hydrogen. It is desirable to minimize the amount of impurities such as hydrogen contained in the insulating film 711. The atoms penetrate into the oxide semiconductor film 705 and the oxide semiconductor film 706. Oxygen in the oxide semiconductor film 706 is extracted, and the oxide semiconductor film 705 and the oxide semiconductor film 70 6 becomes low resistance (n-type), which may result in the formation of a parasitic channel. Therefore, the insulating film 711 is formed without using hydrogen so that the insulating film 711 contains as little hydrogen as possible. It is desirable to use a material with high barrier properties for the insulating film 711. For example, insulating films with high barrier properties include silicon nitride films, silicon nitride oxide films, and aluminum nitride films. A laminated insulating film, an aluminum nitride oxide film, or the like can be used. When using an insulating film such as a silicon oxide film or a silicon oxynitride film having a low nitrogen content, The insulating film having a high barrier property is formed on the side closer to the oxide semiconductor film 705 and the oxide semiconductor film 706. Then, the conductive films 707 to 709 are formed with an insulating film having a low nitrogen content sandwiched therebetween. The oxide semiconductor film 710 and the oxide semiconductor film 705 and the oxide semiconductor film 706 are overlapped with each other. By using an insulating film with high barrier properties, the oxide semiconductor film 705 and the oxide semiconductor film 706 can be formed. In the oxide semiconductor film 706, in the insulating film 711, or in the oxide semiconductor film 705, the oxide semiconductor The film 706 is formed by a method for preventing impurities such as moisture or hydrogen from entering the interface between the film 706 and other insulating films and the vicinity thereof. In addition, a nitride film can be formed in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low ratio of silicon, The insulating film made of a high-quality material is in direct contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. This can be prevented.

[0224] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 711 has a structure in which a silicon nitride film having a film thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. Set the temperature to 100°C.

[0225] Note that heat treatment may be performed after the insulating film 711 is formed. In an atmosphere of dry air or a rare gas (argon, helium, etc.), preferably 200 The temperature is set to 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. is 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less In this embodiment, for example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. Alternatively, before the conductive films 707 to 710 are formed, moisture or hydrogen may be reduced. Similar to the heat treatment performed on the oxide semiconductor film for the purpose of After the insulating film 711 containing oxygen is provided, heat treatment is performed. Therefore, the oxide semiconductor films 705 and 706 were subjected to the heat treatment. Even if oxygen vacancies occur in the oxide semiconductor films 705 and 706, Oxygen is supplied from the insulating film 711 to the oxide semiconductor films 705 and 706. Then, oxygen is supplied to the oxide semiconductor films 705 and 706, whereby oxide In the semiconductor film 705 and the oxide semiconductor film 706, oxygen vacancies serving as donors are reduced, and chemical The oxide semiconductor film 705 and the oxide semiconductor film 706 can satisfy the stoichiometric composition ratio. Preferably, the oxygen content exceeds the stoichiometric ratio. The nitride semiconductor film 705 and the oxide semiconductor film 706 can be made closer to i-type. This reduces the variation in the electrical characteristics of the transistors used, thereby improving their electrical characteristics. Cut.

[0226] Further, the oxide semiconductor films 705 and 706 are subjected to heat treatment in an oxygen atmosphere. In this way, oxygen is added to the oxide semiconductor, and the oxide semiconductor films 705 and 706 The temperature of the heat treatment may be, for example, 100° C. or higher. The heating temperature is set to 350°C or higher, preferably 150°C or higher but lower than 250°C. It is preferable that the oxygen gas used in the treatment does not contain water, hydrogen, etc. The purity of the oxygen gas introduced into the treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration in oxygen is 1 ppm or less, preferably 0 It is preferable to keep it at 0.1 ppm or less.

[0227] Alternatively, the oxide semiconductor film 705 and the oxide semiconductor film 706 may be formed by an ion implantation method, an ion doping method, or the like. By adding oxygen to the compound semiconductor film 706, oxygen vacancies that act as donors may be reduced. For example, oxygen plasma generated by microwaves at 2.45 GHz is used to form the oxide semiconductor film 705. The oxide semiconductor film 706 may be doped with the compound.

[0228] Through the above steps, a transistor 712 and a transistor 713 are formed. The gate electrode 712 is made up of a conductive film 702 that functions as a gate electrode, a gate insulating film 704, and an oxide film. The semiconductor film 705, the conductive film 707 functioning as a source electrode or a drain electrode, and the conductive film 708 functioning as a The transistor 712 includes an insulating film 711 as a component thereof. The transistor 713 includes a conductive film 702 serving as a gate electrode and a gate insulating film 704. The insulating film 704, the oxide semiconductor film 706, and the insulating film 706 functioning as a source electrode or a drain electrode are The transistor 713 includes a conductive film 709 and a conductive film 710. The transistor 713 includes an insulating film 711. It may be included in the components.

[0229] The conductive film 703 and the conductive film 708 overlap with each other with the gate insulating film 704 interposed therebetween. This corresponds to a capacitor element 714. In addition, the conductive film 703 and the conductive film 704 are sandwiched between them. The portion where the conductive film 710 overlaps corresponds to the capacitor element 715 .

[0230] Note that many oxide semiconductors contain Group 13 elements, and insulating materials containing Group 13 elements are The oxide semiconductor has a good compatibility with the insulating film (in this embodiment, The gate insulating film 704 and the insulating film 711 correspond to this. This allows the interface characteristics between the body film and the insulating film to be maintained in good condition.

[0231] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). %), and gallium aluminum oxide is a material with a high gallium content (atomic %). Indicates an aluminum content (atomic %) of 100 or more.

[0232] For example, when an insulating film is formed in contact with an oxide semiconductor film containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor film and the insulating film can be maintained good. For example, an oxide semiconductor film and an insulating film containing gallium oxide can be provided in contact with each other. This can reduce the pileup of hydrogen at the interface between the oxide semiconductor film and the insulating film. In addition, when an element of the same group as the component element of the oxide semiconductor is used for the insulating film, the same For example, it is possible to form an insulating film using a material containing aluminum oxide. It is also effective to form a thin film of aluminum oxide, which has the property of being difficult for water to pass through. Therefore, the use of this material is advantageous in terms of preventing water from entering the oxide semiconductor film. It is also preferred in

[0233] The insulating films in contact with the oxide semiconductor films 705 and 706 are heated under an oxygen atmosphere. By heat treatment using oxygen or oxygen doping, insulating materials are made into a state where there is more oxygen than the stoichiometric composition ratio. Oxygen doping refers to adding oxygen to the bulk. The term "bulk" is used to clarify that oxygen is added not only to the surface of the thin film but also to the interior of the thin film. In addition, oxygen doping is performed by adding oxygen plasma to the bulk. Oxygen doping is performed by using ion implantation or ion doping. It is okay to go there.

[0234] For example, a gallium oxide insulating film may be used as an insulating film in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. When using a silicon dioxide film, heat treatment in an oxygen atmosphere or oxygen doping can be performed to remove gallium oxide. The composition of the aluminum is Ga2O X (X=3+α, 0<α<1).

[0235] Further, an insulating film made of aluminum oxide is used as an insulating film in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. When aluminum is used, heat treatment in an oxygen atmosphere or oxygen doping can be performed to form aluminum oxide. The composition of aluminum is AlO X (X=3+α, 0<α<1).

[0236] Further, gallium oxide was used as an insulating film in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. When aluminum (aluminum gallium oxide) is used, heat treatment under an oxygen atmosphere By performing oxygen doping, gallium aluminum oxide (aluminum gallium oxide) ) composition of Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0237] By performing oxygen doping treatment, an insulating film having a region in which oxygen is present in a larger amount than the stoichiometric composition ratio is formed. When the insulating film having such a region is in contact with the oxide semiconductor film, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor film, and the oxide semiconductor film or the oxide The oxygen defects at the interface between the oxide semiconductor film and the insulating film are reduced, and the oxide semiconductor film is made i-type or i-type. It is possible to make it as close to the mold as possible.

[0238] Note that the insulating film having a region with more oxygen than the stoichiometric composition is the oxide semiconductor film 705, Among the insulating films in contact with the oxide semiconductor film 706, the insulating film located above or the insulating film located below It may be used for only one of the insulating films, but it is preferable to use it for both insulating films. The insulating film having a region where oxygen is more than the stoichiometric composition is formed as the oxide semiconductor film 705 and the oxide The insulating film is used for the insulating film located above and below the insulating film in contact with the oxide semiconductor film 706. The above effect can be further enhanced by sandwiching the oxide semiconductor film 705 and the oxide semiconductor film 706. can be done.

[0239] The insulating films used above or below the oxide semiconductor film 705 and the oxide semiconductor film 706 are The upper and lower insulating films may have the same constituent elements, or may have different constituent elements. For example, both the upper and lower layers may be made of GaO X (X=3+α, 0<α<1 ) gallium oxide, or one of the upper and lower layers may have a composition of GaO X (X=3+α, 0<α<1) and the other is gallium oxide with a composition of AlO X (X=3+α, 0<α<1) Aluminum oxide may also be used.

[0240] The insulating films in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706 have a stoichiometric composition. For example, the oxide semiconductor film 70 may be a stack of insulating films each having a region with a relatively high oxygen content. 5. Above the oxide semiconductor film 706, a layer having a composition of GaO X Oxidation of (X=3+α, 0<α<1) Gallium is formed on it, and the composition is Ga X Al 2-X O 3+α (0 <X<2、0<α<1 ) gallium aluminum oxide (aluminum gallium oxide) may be formed. The oxide semiconductor film 705 and the oxide semiconductor film 706 are formed under the oxide semiconductor film 705 and the oxide semiconductor film 706 by using a compound having a higher oxygen content than the stoichiometric composition. Alternatively, the oxide semiconductor film 705 and the oxide semiconductor film 706 may be stacked. Both the upper and lower portions of the insulating film 06 are made of a material having an area with more oxygen than the stoichiometric composition ratio. It may also be layered.

[0241] This embodiment mode can be implemented in combination with the above embodiment modes.

[0242] (Fourth embodiment) An example of a specific configuration of a driver circuit in a memory device according to one embodiment of the present invention will be described.

[0243] FIG. 13 is a block diagram illustrating a specific configuration example of a memory device according to one embodiment of the present invention. In the block diagram shown in Figure 13, the circuits in the memory device are classified by function and are mutually Although it is shown as an independent block, the actual circuit can be completely separated by function. It is difficult, and one circuit may be involved in multiple functions.

[0244] The memory device 300 shown in FIG. 13 includes a cell array 301 and a driver circuit 302. The drive circuit 302 is a read circuit that generates a signal including data read from the cell array 301. a word line drive circuit 304 for controlling the potential of the word line; A bit line driving circuit controls writing of data in the memory cell selected in step 01. The drive circuit 302 further includes a read circuit 303, a word line drive circuit 304, and a write circuit 305. The control circuit 306 controls the operation of the bit line driver circuit 305 .

[0245] As shown in FIG. 9, when the cell array 301 is configured with a plurality of blocks, A corresponding word line driver circuit and bit line driver circuit may be provided for each block.

[0246] In the memory device 300 shown in FIG. 13, the word line driver circuit 304 is connected to the decoder 307. , a level shifter 308, and a buffer 309. The bit line driver circuit 305 It includes a decoder 310 and a selector 312 .

[0247] The memory device 300 according to one embodiment of the present invention includes at least the cell array 301 as its configuration. Furthermore, the memory device 300 according to one embodiment of the present invention may include the cell array 301. The memory module in which a part or all of the drive circuit 302 is connected to the The memory module is provided with connection terminals that can be mounted on a printed wiring board, etc. The semiconductor device may be in a so-called packaged state, in which the semiconductor device is protected by a resin or the like.

[0248] Also, a cell array 301, a read circuit 303, a word line driving circuit 304, a bit line driving circuit 305, a The circuit 305 and the control circuit 306 may all be formed using a single substrate. One or all of the layers may be formed using different substrates.

[0249] If a different substrate is used, FPC (Flexible Printed Circuit) In this case, the electrical connection can be ensured through the driver circuit 302. A part of it may be connected to the FPC using a COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. This can be done.

[0250] A signal A including the address (Ax, Ay) of the cell array 301 as information is input to the memory device 300. When D is input, the control circuit 306 sends the address Ax in the column direction to the bit line driving circuit 305 and sends a row address Ay to the word line driver circuit 304. The signal DATA including the data input to the memory device 300 is transmitted to the bit line driving circuit 305. Send to.

[0251] The selection of the data write operation or read operation in the cell array 301 is performed by the control circuit 30 6, the signal RE (Read enable) and the signal WE (Write enable) 9, the cell array 301 may be configured to include a plurality of blocks. When the block is configured as a clock, the control circuit 306 receives a signal C for selecting the block. E (Chip enable) may be input. In this case, the signals RE and WE The operation selected by signal CE is executed in the block selected by signal CE.

[0252] In the cell array 301, when a write operation is selected by the signal WE, the control circuit 306 In accordance with the instruction from the decoder 307 of the word line driving circuit 304, the address A signal is generated to select the memory cell corresponding to the level shift Ay. After the amplitude of the potential is adjusted by the lid 308, the waveform is processed in the buffer 309. The signal is input to the cell array 301. On the other hand, the bit line driver circuit 305 controls the control circuit 3 In accordance with the instruction from 06, the address of the memory cell selected by the decoder 310 is A signal for selecting a memory cell corresponding to the selector Ax is generated. The signal DATA is input to the selector 312. The selector 312 samples the signal DATA according to the input signal. The sampled signal is input to the memory cell corresponding to the address (Ax, Ay). To exert effort.

[0253] In addition, in the cell array 301, when a read operation is selected by the signal RE, the control circuit In accordance with the instruction from 306, a decoder 307 included in the word line driving circuit 304 A signal is generated to select a memory cell corresponding to the address Ay. After the amplitude is adjusted by the bell shifter 308, the waveform is processed in the buffer 309. , is input to the cell array 301. Meanwhile, in the read circuit 303, In accordance with this instruction, among the memory cells selected by the decoder 307, the one corresponding to the address Ax is selected. Then, the memory cell corresponding to the address (Ax, Ay) is selected. The stored data is read and a signal containing the data is generated.

[0254] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0255] (Embodiment 5) In this embodiment, an example of a specific configuration of the readout circuit will be described.

[0256] The potential read from the cell array is determined according to the data written in the memory cell. Therefore, ideally, data of the same digital value is stored in multiple memory cells. If so, the potentials read from multiple memory cells will all be at the same level. However, in reality, the transistors that function as memory elements or the transistors that function as readout elements are The characteristics of the transistor that functions as a switching element in In this case, the data to be read out may all be the same digital value. However, the potential actually read out varies, and the potential distribution has a certain width. Therefore, even if there is some variation in the potential read from the cell array, accurate data can be obtained. The readout contains the data and produces a signal whose amplitude and waveform are processed to meet the desired specifications. It is desirable to provide a detection circuit in the drive circuit.

[0257] An example of a readout circuit is shown in a circuit diagram in FIG. 14. The readout circuit shown in FIG. A switch for controlling the input of the potential Vdata read from the The transistor 260 functions as a switching element, and the transistor 261 functions as a resistor. 14 also includes an operational amplifier 262.

[0258] Specifically, the transistors 261 each have a gate electrode and a drain terminal connected to each other. Furthermore, a high-level power supply potential Vdd is applied to the gate electrode and the drain terminal. The source terminal of the transistor 261 is connected to the non-inverting input of the operational amplifier 262. Therefore, the transistor 261 is connected to the terminal (+) when the power supply potential Vdd is applied. A resistor connected between the node connected to the non-inverting input terminal (+) of the operational amplifier 262 In Figure 14, the gate electrode and drain terminal are connected to each other. However, the present invention is not limited to this, and any element that functions as a resistor may be used. Substitutions are possible.

[0259] The transistor 260, which functions as a switching element, has a gate electrode connected to the bit line. The potential of the bit line is connected to the transistor 260. The supply of the potential Vdata to the source electrode is controlled.

[0260] When the transistor 260 connected to the bit line is turned on, the potential Vdata and the power supply potential V dd is obtained by resistively dividing the voltage by transistors 260 and 261. The potential is applied to the non-inverting input terminal (+) of the operational amplifier 262. Then, the power supply potential Vd Since the level of d is fixed, the level of the potential obtained by resistive division is the potential Vd This reflects the ATA level, i.e., the digital value of the data read.

[0261] On the other hand, the inverting input terminal (-) of the operational amplifier 262 is supplied with a reference potential Vref. And, the potential applied to the non-inverting input terminal (+) is higher than the reference potential Vref. Depending on whether the voltage Vout is low or high, the level of the potential Vout at the output terminal can be varied. A signal containing data can be obtained indirectly.

[0262] Even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. The variation in the voltage Vdata also causes variations in the level of the read potential Vdata, and the distribution of the voltage Vdata varies widely. Therefore, the level of the reference potential Vref is Therefore, it is determined taking into consideration the variations in the node potential Vdata.

[0263] Also, since FIG. 14 shows an example of a readout circuit for handling binary digital values, The operational amplifiers used to read the data are connected to the nodes to which the potential Vdata is applied. However, the number of operational amplifiers is not limited to this. When dealing with data, the number of operational amplifiers for the node to which the potential Vdata is applied is n- Let's say it's 1.

[0264] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0265] (Embodiment 6) The mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured in various The mobility is lower than the original mobility due to various reasons. There are internal defects and defects at the interface between the semiconductor and the insulating film, but the Levinson model is used. If we assume that there are no defects inside the semiconductor, we can theoretically derive the mobility. In the embodiment, the mobility of an ideal oxide semiconductor without defects inside the semiconductor is theoretically derived. In addition, we have developed a method for fabricating miniaturized transistors using such oxide semiconductors. The calculation results of the saturation are shown below.

[0266] Let μ0 be the inherent mobility of the semiconductor, μ be the measured mobility, and let μ be the potential of the semiconductor. Assuming that there are barriers (grain boundaries, etc.), the mobility μ can be expressed by the following equation 2.

[0267]

number

[0268] Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, assuming that the potential barrier originates from defects, the Levinson model gives The following equation 3 holds true:

[0269]

number

[0270] where e is the elementary charge, N is the average defect density per unit area in the channel formation region, and ε is the half The dielectric constant of the conductor, n is the number of carriers contained in the channel formation region per unit area, C ox teeth Capacitance per unit area, V g is the gate voltage, and t is the thickness of the channel formation region. If the semiconductor film is 30 nm or less in thickness, the thickness of the channel formation region is the same as the thickness of the semiconductor film. The drain current in the linear region I d can be expressed by the following equation 4.

[0271]

number

[0272] L is the channel length, W is the channel width, and here, L=W=10 μm. d is the drain voltage. g Dividing by and taking the logarithm of both sides gives us the following equation: 5 is obtained.

[0273]

number

[0274] The right side of Equation 5 is V g As can be seen from Equation 5, the vertical axis is a function of ln(I d / V g ) , the horizontal axis is 1 / V g The defect density can be calculated from the slope of the line on the graph obtained by plotting the measured values ​​as N is calculated. That is, the I d -V g The defect density can be evaluated from the characteristics For oxide semiconductors, the ratio of indium (In), tin (Sn), and zinc (Zn) is: In the case of In:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 To an extent .

[0275] Based on the defect density thus obtained, μ0 = 120 cm using Equations 2 and 3. 2 / Vs The mobility measured in the defective In-Sn-Zn oxide is 35 cm 2 / However, the oxide layer is free of defects inside the semiconductor and at the interface between the semiconductor and the insulating film. The semiconductor mobility μ0 is 120 cm 2 It can be expected that / Vs.

[0276] However, even if there are no defects inside the semiconductor, the diffusion at the interface between the channel formation region and the gate insulating film can occur. The transport characteristics of the transistor are affected by the disturbances from the gate insulating film interface to the x The mobility μ1 at a distance of 1000 nm can be expressed by the following equation 6.

[0277]

number

[0278] D is the electric field in the gate direction, and B and G are constants. B and G are determined from actual measurement results. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10nm (field As D increases (i.e., gate voltage V g becomes higher) and the formula It can be seen that the mobility μ1 decreases because the second term of equation 6 increases.

[0279] A transistor that uses an ideal oxide semiconductor with no internal defects in the channel formation region The results of calculating the mobility μ2 of the device are shown in Figure 18. Using the simulation software, Sentaurus Device, The band gap, electron affinity, dielectric constant, and thickness are 2.8 eV and 4.7 eV, respectively. These values ​​are for thin films formed by sputtering. This was obtained by measuring the

[0280] Furthermore, the work functions of the gate electrode, source electrode, and drain electrode are set to 5.5 electron volts. The gate insulating film thickness was 100 nV, 4.6 eV, and 4.6 eV. The channel length L and width W were both 10 μm, and the drain Input voltage V d is 0.1V.

[0281] As shown in Figure 18, the gate voltage V g is just over 1V and the mobility μ2 is 100cm 2 / Vs or later The upper peak is set, but the gate voltage V g If the temperature is further increased, the interface scattering increases and the In order to reduce the interface scattering, the surface of the semiconductor film must be treated at the atomic level. Atomic Layer Flatness is desirable.

[0282] When a miniaturized transistor is fabricated using an oxide semiconductor having such mobility, The results of calculating the electrical characteristics are shown in Figures 19 to 21. The cross-sectional structure of the transistor shown in FIG. + The conductivity type of The semiconductor region 8103 includes a semiconductor region 8103a and a semiconductor region 8103c. a and the resistivity of semiconductor region 8103c is 2 × 10 -3 Let it be Ωcm.

[0283] The transistor shown in FIG. 22A has a base insulating film 8101 and a It is formed on a buried insulator 8102 made of aluminum oxide formed so as to be embedded. The transistor is made up of a semiconductor region 8103a, a semiconductor region 8103c, and a semiconductor region sandwiched between them. The gate electrode 8105 is formed on the semiconductor substrate 8101. do.

[0284] Between the gate electrode 8105 and the semiconductor region 8103b, there is a gate insulating film 8104. In addition, the gate electrode 8105 is provided on both sides with a sidewall insulator 8106a and a sidewall insulator 8106b. On the top of the gate electrode 8105, a thin film is provided to prevent short-circuiting between the gate electrode 8105 and other wirings. The width of the sidewall insulator is set to 5 nm. 3a and the semiconductor region 8103c, a source electrode 8108a and a drain electrode 8 The channel width of this transistor is set to 40 nm.

[0285] The transistor shown in FIG. 22B has a base insulating film 8101 and a thin film made of aluminum oxide. A semiconductor region 8103a and a semiconductor region 8103c are formed on the buried insulator 8102. and an intrinsic semiconductor region 8103b sandwiched therebetween, and a gate electrode 8105 having a width of 33 nm. and the gate insulating film 8104, the sidewall insulator 8106a, the sidewall insulator 8106b, and the insulator 8 107 and the source electrode 8108a and the drain electrode 8108b. This is the same as the transistor shown in

[0286] The transistor shown in FIG. 22(A) differs from the transistor shown in FIG. 22(B) in that the sidewall insulation The conductivity type of the semiconductor region under the insulating layer 8106a and the sidewall insulating layer 8106b is shown in FIG. In the transistor shown in A), the sidewall insulators 8106a and 8106b are The semiconductor region is n + In the semiconductor region 8103a and the semiconductor region 8103c, However, in the transistor shown in FIG. 22(B), it is an intrinsic semiconductor region 8103b. That is, in the oxide semiconductor film shown in FIG. 22B, the semiconductor region 8103a ( There is an area where the region 8103c) and the gate electrode 8105 do not overlap by a width Loff. This area is called the offset area, and its width Loff is called the offset length. As is clear from the figure, the offset length Loff is The width is the same as 6b).

[0287] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. The drain current (I d , solid line) and mobility (μ, dotted line) gate voltage (V g The drain voltage (gate-source potential difference) dependence is shown. Flow I d The drain voltage (potential difference between the drain and source) is set to +1V, and the mobility μ is The calculation was made assuming a voltage of +0.1V.

[0288] In FIG. 19(A), the thickness t of the gate insulating film is set to 15 nm, and in FIG. 19(B), the thickness t is set to 15 nm. In FIG. 19(C), t is set to 10 nm, and in FIG. 19(C), t is set to 5 nm. As the thickness t of the d (Off-state current) is significantly reduced On the other hand, the peak value of the mobility μ and the drain current I d (ON current) is not noticeable At a gate voltage of around 1V, the drain current is 1V, which is the voltage required for memory cells, etc. It was shown to be greater than 0 μA.

[0289] FIG. 20 shows a transistor having the structure shown in FIG. 22(B), in which the offset length Loff is set to 5n m, the drain current I d (solid line) and mobility μ (dotted line) at gate voltage V g dependence The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with a voltage of +0.1V. In FIG. 20(B), t is set to 10 nm, and in FIG. 20(C), t is set to The thickness is set at 5nm.

[0290] FIG. 21 shows the offset length Loff of the transistor having the structure shown in FIG. 22(B). The drain current I d (solid line) and mobility μ (dotted line) The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with the gate insulating film thickness t set to 15 V. In FIG. 21(B), t is set to 10 nm, and in FIG. 21(C), t is set to 5 nm.

[0291] In both cases, the thinner the gate insulating film, the more significantly the off-state current decreases, while the peak of the mobility μ decreases. There is no noticeable change in the on-state current or the on-state voltage.

[0292] The peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 20, cm 2 / Vs, 40cm in Figure 21 2 When the offset length Loff increases, The off-current also shows a similar trend. On the other hand, the on-current also decreases as the offset length L It decreases with increasing off, but it is much slower than the decrease in off current. In addition, the gate voltage is around 1V, and the drain current is 1V, which is required for memory cells, etc. It was shown to be greater than 0 μA.

[0293] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0294] (Embodiment 7) A transistor with a channel formation region made of an oxide semiconductor containing In, Sn, and Zn as its main components is The oxide semiconductor film is formed by heating the substrate. By performing heat treatment after formation, good characteristics can be obtained. In this embodiment, oxide semiconductors are elements that are contained in an amount of 5 atomic % or more. Intentionally heating the substrate after deposition of the semiconductor film improves the mobility of the transistor. This will be explained with reference to FIGS. 23 to 29.

[0295] Intentionally heating the substrate after forming an oxide semiconductor film containing In, Sn, and Zn as its main components This makes it possible to improve the mobility of the transistor. This makes it possible to shift the value voltage positively and make it normally off.

[0296] For example, FIGS. 23A to 23C show a semiconductor device having a channel length L The oxide semiconductor film has a thickness of 3 μm and a channel width W of 10 μm, and a gate insulating film with a thickness of 100 nm. These are the characteristics of a transistor using an insulating film. d was set to 10V.

[0297] Figure 23(A) shows the deposition of In, Sn, and Zn as the main components by sputtering without intentionally heating the substrate. The mobility is 18 .8cm 2 On the other hand, the substrate was intentionally heated to form a thin film of In, Sn, and Zn. The mobility can be improved by forming an oxide semiconductor film containing the element. B) The substrate is heated to 200°C to form an oxide semiconductor film mainly composed of In, Sn, and Zn. The transistor characteristics are shown below. The mobility is 32.2 cm 2 / Vs is obtained.

[0298] The mobility is improved by forming an oxide semiconductor film containing In, Sn, and Zn as its main components and then performing heat treatment. Fig. 23(C) shows a graphite alloy containing In, Sn, and Zn as the main components. The oxide semiconductor film was formed by a sputtering method at 200° C. and then subjected to heat treatment at 650° C. The transistor characteristics are shown below. At this time, the mobility is 34.5 cm 2 / Vs is obtained are.

[0299] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during film formation by sputtering. In addition, by performing heat treatment after film formation, Even if the oxide semiconductor film is heated, hydrogen, a hydroxyl group, or moisture can be released and removed from the oxide semiconductor film. As described above, the mobility can be improved. It is presumed that this is not only due to the removal of impurities by oxidation, but also due to the shortening of interatomic distances due to densification. In addition, impurities are removed from the oxide semiconductor to achieve high purification, thereby achieving crystallization. Such a highly purified non-single-crystal oxide semiconductor can ideally have a capacitance of 100 cm 2 It is estimated that it will be possible to achieve a mobility exceeding / Vs.

[0300] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into a The hydrogen, hydroxyl groups, or moisture contained in the compound semiconductor is released, and the heat treatment is performed simultaneously or in addition to the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0301] The effect of intentionally heating the substrate during film deposition and / or heat treatment after film deposition is to This not only improves the efficiency but also contributes to making the transistor normally off. The oxide semiconductor film, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the plate. The threshold voltage of a transistor with a channel formation region tends to shift negatively. However, when an oxide semiconductor film formed by intentionally heating a substrate is used, The negative shift of the threshold voltage is eliminated. This tendency is seen in the comparison between Figure 23(A) and Figure 23(B). It can also be confirmed from.

[0302] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to achieve a transistor noise by using a composition ratio of In:Sn:Zn=2:1:3. In addition, the atomic ratio of In:Sn:Zn=1:1: In-Sn-Zn based acids shown in 1, 2:1:3, 1:2:2, or 20:45:35 By depositing an oxide semiconductor film using an oxide target, polycrystalline or CAAC can be formed. It becomes easier to achieve.

[0303] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. The temperature is more preferably 400°C or higher, and film formation or heat treatment at higher temperatures can improve the transistor performance. This makes it possible to make the starter normally off.

[0304] In addition, by intentionally heating the substrate during film formation and / or by performing heat treatment after film formation, it is possible to It can improve the stability against as stress. For example, 2MV / cm, 150℃ , and 1 hour application conditions, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0305] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was carried out on the transistor of sample 2 that had undergone the above.

[0306] First, the substrate temperature is set to 25°C, and V d is set to 10V, and the V of the transistor g -I d Measurement of characteristics I went. d indicates the drain voltage (potential difference between the drain and source). The temperature is set to 150°C, and V d Next, the electric field applied to the gate insulating film 608 was set to 0.1 V. V so that the strength is 2MV / cm g A voltage of 20 V was applied to the electrode and the electrode was maintained for 1 hour. , V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, and the V of the transistor g -I d This measurement was called the Plus BT test.

[0307] Similarly, first set the substrate temperature to 25°C, and then V d is set to 10V, and the V of the transistor g -I d characteristics Next, the substrate temperature was set to 150°C, and V d was set to 0.1V. Next, the gate V so that the electric field strength applied to the insulating film 608 becomes −2 MV / cm g Apply -20V to Then, V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, and the V of the transistor g -I d This is called the minus BT test. Boo.

[0308] The results of the positive BT test for sample 1 are shown in Figure 24(A), and the results of the negative BT test are shown in Figure 24(B). The results of the positive BT test for sample 2 are shown in Figure 25(A), and the results of the negative BT test for sample 2 are shown in Figure 25(B). The results are shown in Figure 25(B).

[0309] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 2 were 1.80V and -0.42V. The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively. In both Sample 1 and Sample 2, the change in threshold voltage before and after the BT test was small, and the signal It is known to be highly reliable.

[0310] The heat treatment can be carried out in an oxygen atmosphere, but first, nitrogen or an inert gas, or a reducing gas, It is also possible to perform heat treatment under pressure and then in an oxygen-containing atmosphere. By adding oxygen to the oxide semiconductor after dehydrogenation, the effect of the heat treatment can be further enhanced. To add oxygen later, oxygen ions can be accelerated by an electric field to form a thin film on the oxide semiconductor. A method of injecting the film may also be applied.

[0311] Defects due to oxygen vacancies are generated in the oxide semiconductor and at the interface between the oxide semiconductor and the film. However, by causing the oxide semiconductor to contain excess oxygen through such heat treatment, It is possible to compensate for the oxygen deficiency that is constantly generated by excess oxygen. is mainly interstitial oxygen, and its oxygen concentration is 1×10 16 / cm 3 Over 2×10 20 / cm 3If the following conditions are met, the oxide semiconductor can be incorporated without causing distortion to the crystal. It is possible.

[0312] Furthermore, by making the oxide semiconductor contain crystals at least in part by heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. The film was deposited by sputtering using a 1:1 target without intentionally heating the substrate. The oxide semiconductor film was found to have a halo by X-ray diffraction (XRD). The oxide semiconductor film is then crystallized by heat treatment. The heat treatment temperature can be any temperature, but for example, by performing heat treatment at 650°C, Clear diffraction peaks can be observed by X-ray diffraction.

[0313] In fact, XRD analysis of the In-Sn-Zn oxide semiconductor film was carried out. Out-of-Plate analysis was performed using the X-ray diffraction instrument D8 ADVANCE manufactured by Ruker AXS. Measured by the ane method.

[0314] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0315] A 100 nm thick In-Sn-Zn oxide semiconductor film was formed on a dehydrogenated quartz substrate. The film was formed as follows.

[0316] The In-Sn-Zn oxide semiconductor film was fabricated using a sputtering system under an oxygen atmosphere. The film was deposited at 100 W (DC). The target was In:Sn:Zn=1:1:1 [atomic ratio] The substrate heating temperature during film formation was The temperature was 200° C. The sample thus prepared was designated as Sample A.

[0317] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment for 1 hour. The sample thus prepared was designated as sample B.

[0318] Figure 28 shows the XRD spectra of sample A and sample B. In sample A, peaks derived from crystals However, in sample B, 2θ was observed around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed in g.

[0319] In this way, oxide semiconductors containing In, Sn, and Zn as their main components are intentionally heated during film formation. and / or by performing heat treatment after film formation, the characteristics of the transistor can be improved. Cut.

[0320] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing oxide semiconductors from being included in the film or removing them from the film. High purity can be achieved by removing hydrogen, an impurity that generates donors in the conductor. This allows the transistor to be normally off, and the oxide semiconductor By purifying the material, the off-state current can be reduced to 1 aA / μm or less. The unit of the off-state current value is the current value per 1 μm of channel width.

[0321] Figure 29 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. In Figure 29, the reciprocal of the substrate temperature at the time of measurement multiplied by 1000 (1000 / T) is plotted horizontally. It is the axis.

[0322] As shown in Figure 29, when the substrate temperature is 125°C, the off-state current is 1 aA / μm (1 × 10 -18 A / μm) or less, and at 85°C, the off-state current is 100zA / μm (1×10 -19 A / μm) or less, and at room temperature (27°C), the off-state current is 1zA / μm (1×10 -21 A Preferably, the off-state current at 125° C. can be reduced to 0.1 aA or less. / μm(1×10 -19 A / μm) or less at 85°C, and the off-state current is 10zA / μm ( 1×10 -20 A / μm) or less at room temperature, and the off-state current is 0.1zA / μm (1×10 -22 These off-state current values ​​can be achieved using Si as a semiconductor film. It is clear that this is extremely low compared to the transistors used in the previous study.

[0323] Note that in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the deposition, The purpose of this is to sufficiently suppress gas leakage and gas outflow from the inner walls of the deposition chamber, thereby achieving high purity of sputtering gas. For example, the sputtering gas should have a dew point of -70°C or less to prevent moisture from being contained in the film. It is preferable to use a gas containing impurities such as hydrogen and moisture in the target itself. It is preferable to use a target that has been highly purified so as not to contain In. Oxide semiconductors whose main components are Sn and Zn can be heat-treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0324] In addition, the transistor using Sample B, which was subjected to heat treatment at 650° C. after the oxide semiconductor film was formed, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0325] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov is 0 μm, and dW is 0 μm. d The voltage was set to 10 V. The substrate temperature was -40°C. The test was carried out at temperatures of -25°C, 25°C, 75°C, 125°C and 150°C. In the case of a transistor, the overlap width between the gate electrode and the source and drain electrodes is called Lov, The protrusion of the source electrode and the drain electrode from the oxide semiconductor film is called dW.

[0326] In Figure 26, I d (solid line) and mobility (dotted line) g The dependency is shown in Figure 27(A). FIG. 27(B) shows the relationship between the substrate temperature and the threshold voltage, and FIG. 27(C) shows the relationship between the substrate temperature and the mobility.

[0327] From FIG. 27(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0328] Also, from FIG. 27(B), it can be seen that the higher the substrate temperature, the lower the mobility. The range is -40℃~150℃ and the 2 / Vs~32cm 2 / Vs. Therefore, It can be seen that the fluctuations in the electrical characteristics are small within the above temperature range.

[0329] The above-mentioned oxide semiconductor containing In, Sn, and Zn as its main components is used for the channel formation region. According to the transistor, the mobility can be increased to 30 cm while keeping the off-current below 1 aA / μm. 2 / V s or more, preferably 40cm 2 / Vs or more, preferably 60cm 2 / Vs or more, It is possible to satisfy the on-current value required for LSI. For example, L / W=33nm / 4 0nm FET, the gate voltage is 2.7V, the drain voltage is 1.0V, and the on-state current is 12μA or more. In addition, the transistor can operate within the temperature range required for its operation. It is possible to ensure sufficient electrical characteristics. If such characteristics are available, it is possible to Even if a transistor made of an oxide semiconductor is embedded in an integrated circuit, the operating speed is not sacrificed. It is possible to realize integrated circuits with new functions without sacrificing performance.

[0330] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0331] In this example, an example of a transistor in which an In-Sn-Zn-based oxide is used for an oxide semiconductor film is shown. This will be explained using FIG. 30 etc.

[0332] Figure 30 shows the top of a coplanar top-gate / top-contact transistor. FIG. 30(A) shows a top view of a transistor. FIG. 30B) shows a cross section AB corresponding to the dashed line AB in FIG.

[0333] The transistor shown in FIG. 30B includes a substrate 1100 and a base film provided over the substrate 1100. The insulating film 1102, the protective insulating film 1104 provided around the base insulating film 1102, and the base insulating film A high resistance region 1106a and a low resistance region 1106b are provided on the insulating film 1102 and the protective insulating film 1104. The oxide semiconductor film 1106 has a resistor region 1106b. The gate insulating film 1108 is formed on the oxide semiconductor film 110. A gate electrode 1110 is provided so as to overlap with the gate electrode 6, and a gate electrode 1110 is provided so as to contact with the side surface of the gate electrode 1110. and a pair of sidewall insulating films 1112 provided in contact with at least the low resistance region 1106b. The electrode 1114, at least the oxide semiconductor film 1106, the gate electrode 1110, and a pair of An interlayer insulating film 1116 is provided to cover the electrode 1114, and a layer is provided on the interlayer insulating film 1116. The wiring 11 is connected to at least one of the pair of electrodes 1114 through the opening. 18 and has.

[0334] Although not shown, a protective film is provided to cover the interlayer insulating film 1116 and the wiring 1118. By providing the protective film, the surface conduction of the interlayer insulating film 1116 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, thereby reducing the off-state current of the transistor. It is possible.

[0335] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0336] In this example, an In—Sn—Zn-based oxide semiconductor different from the above was used for the oxide semiconductor film. Another example of a transistor will be described.

[0337] FIG. 31 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 31(A) is a top view of the transistor. Also, FIG. 31(B) is a chain diagram of FIG. 31(A). FIG. 2 is a cross-sectional view corresponding to line AB.

[0338] The transistor shown in FIG. 31B includes a substrate 600 and a base insulating film provided over the substrate 600. a base insulating film 602, an oxide semiconductor film 606 provided over the base insulating film 602, and an oxide semiconductor film A pair of electrodes 614 in contact with the oxide semiconductor film 606 and a pair of electrodes 614 The gate insulating film 608 is provided, and the oxide semiconductor film 606 is provided with the gate insulating film 608 interposed therebetween. The gate electrode 610 is provided so as to overlap with the gate insulating film 608. The insulating interlayer 616 is provided to cover the insulating interlayer 616, and the insulating interlayer 616 is provided with an opening therein. The pair of electrodes 614 and the wiring 618 are connected to each other, and the interlayer insulating film 616 and the wiring 618 are covered with the wiring 618. and a protective film 620 formed thereon.

[0339] The substrate 600 is a glass substrate, the underlying insulating film 602 is a silicon oxide film, and the oxide The semiconductor film 606 is made of an In—Sn—Zn-based oxide semiconductor, and the pair of electrodes 614 is made of A tungsten film is used as the gate insulating film 608, a silicon oxide film is used as the gate electrode 610, The interlayer insulating film 616 is a laminated structure of a tantalum nitride film and a tungsten film. The laminated structure of silicon nitride film and polyimide film is made of titanium film and aluminum film as wiring 618. The laminated structure is made up of an aluminum film and a titanium film in this order, and a polyimide film is used as the protective film 620. were used, respectively.

[0340] In the transistor having the structure shown in FIG. 31A, the gate electrode 610 and the pair of electrodes The width of the overlap with the oxide semiconductor film 606 is referred to as Lov. The protrusion of pole 614 is called dW.

[0341] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0342] The storage device according to one aspect of the present invention can increase the storage capacity per unit area without complicating the process. Therefore, the storage device according to one embodiment of the present invention is characterized in that it can increase the storage capacity. By using this, it is possible to produce small electronic devices with low production costs or electronic devices with high functionality. can be provided.

[0343] The storage device according to one aspect of the present invention is a device for use in a display device, a notebook personal computer, a recording medium, Image playback devices equipped with a DVD (Digital Versatile Digital Used in devices that have a display that can play back recording media such as ISC and display the images In addition, an electronic device in which the memory device according to one embodiment of the present invention can be used As a device, mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, digital cameras, still camera, goggle-type display (head-mounted display), navigation audio systems, sound reproduction devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) ), vending machines, etc. Specific examples of these electronic devices are shown in Figure 32.

[0344] FIG. 32A shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The storage device according to one embodiment of the present invention is a portable game console. It can be used in an integrated circuit for controlling the operation of a portable game machine. By using a memory device according to one embodiment of the present invention for an integrated circuit, a small-sized integrated circuit with low cost can be realized. It is possible to provide a portable game machine or a portable game machine with advanced functions. The portable game machine shown in FIG. 32(A) has two display units 7033 and 7034. However, the number of display units that the portable game machine has is not limited to this.

[0345] FIG. 32B shows a mobile phone, which includes a housing 7041, a display portion 7042, an audio input portion 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The memory device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. The memory device according to one embodiment of the present invention can be included in an integrated circuit for controlling the operation of a mobile phone. By using this technology, it is possible to produce small mobile phones with low production costs or mobile phones with high functionality. can be provided.

[0346] FIG. 32C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 32C has a modem built in a housing 7051. The memory device according to one embodiment of the present invention may be an integrated circuit for controlling the operation of a mobile information terminal. The present invention can be applied to an integrated circuit for controlling the operation of a portable information terminal. By using the storage device according to the embodiment, a small-sized portable information terminal with low cost can be manufactured. Therefore, a highly functional portable information terminal can be provided.

[0347] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0348] 100 cell array 101 memory cells 102 transistor 103 Capacitor element 104 PCB 105 Semiconductor film 106 Conductive film 107 Conductive film 108 insulating film 109 Conductive film 110 insulating film 111 Conductive film 115 Semiconductor Film 116 Conductive film 117 Conductive film 118 insulating film 119 Conductive Film 120 insulating film 121 Conductive film 125 Semiconductor Film 126 Conductive Film 127 Conductive Film 128 insulating film 129 Conductive Film 130 insulating film 131 Conductive film 135 Semiconductor Film 136 Conductive film 137 Conductive Film 138 insulating film 139 Conductive Film 140 insulating film 141 Conductive film 200 cell array 201 memory cells 202 Transistor 202a Transistor 202b Transistor 202c transistor 202d transistor 203 Capacitor 203a Capacitor element 203b Capacitor element 203c Capacitor element 203d Capacitor 204 Substrate 205a Semiconductor film 205b Semiconductor film 205c Semiconductor film 205d Semiconductor film 206a Conductive film 206b Conductive film 206c conductive film 206d Conductive film 207a Conductive film 207b Conductive film 207c conductive film 207d Conductive film 208 insulating film 209 Conductive Film 215a Semiconductor film 215b Semiconductor film 215c Semiconductor film 215d Semiconductor film 216a Conductive film 216b Conductive film 216c conductive film 216d Conductive film 217a Conductive film 217b Conductive film 217c Conductive film 217d Conductive film 218 Insulating film 219 Conductive Film 230 insulating film 231 Conductive Film 232 insulating film 234 Insulating Film 235 insulating film 236 Conductive Film 240 insulating film 241 Insulating Film 242 Conductive film 243 Insulating Film 244 insulating film 245 insulating film 246 Conductive Film 247 Insulating Film 260 transistors 261 Transistor 262 Operational Amplifier 290 blocks 291 blocks 300 storage device 301 Cell Array 302 Drive circuit 303 Circuit 304 Word line driver circuit 305 Bit line driver circuit 306 Control Circuit 307 Decoder 308 Level Shifter 309 Buffer 310 decoder 312 Selector 600 boards 602 Undercoat insulating film 604 Pair of electrodes 606 Oxide semiconductor film 608 Gate insulating film 610 Gate electrode 614 Pair of electrodes 616 Interlayer insulating film 618 Wiring 620 Protective film 700 boards 701 Insulating film 702 Conductive film 703 Conductive film 704 Gate insulating film 705 Oxide semiconductor film 706 Oxide semiconductor film 707 Conductive film 708 Conductive film 709 Conductive film 710 Conductive film 711 Insulating film 712 Transistors 713 Transistor 714 Capacitor 715 Capacitor 1100 board 1102 Undercoat insulating film 1104 Protective insulating film 1106a High resistance area 1106b Low resistance region 1106 Oxide semiconductor film 1108 Gate insulating film 1110 gate electrode 1112 Sidewall insulating film 1114 Pair of electrodes 1116 Interlayer insulating film 1118 Wiring 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key 8101 Undercoat insulating film 8102 Embedded insulators 8103a Semiconductor area 8103b Semiconductor field 8103c Semiconductor field 8104 Gate insulating film 8105 Gate electrode 8106a Sidewall Insulator 8106b Sidewall insulator 8107 Insulators 8108a Source electrode 8108b Drain electrode

Claims

1. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a second conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a fourth conductive film having a region disposed above the first oxide semiconductor film having a channel formation region of the first transistor with an insulating film interposed therebetween and functioning as one of a source electrode and a drain electrode of the second transistor; a fifth conductive film having a function as the other of the source electrode and the drain electrode of the second transistor, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fourth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the third conductive film; the first conductive film functions as a first electrode of the capacitor element, the fourth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

2. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a second conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a fourth conductive film having a region disposed above the first oxide semiconductor film having a channel formation region of the first transistor with an insulating film interposed therebetween and functioning as one of a source electrode and a drain electrode of the second transistor; a fifth conductive film having a function as the other of the source electrode and the drain electrode of the second transistor, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fourth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the third conductive film; the fourth conductive film has a region in contact with the insulating film, the fifth conductive film has a region in contact with the insulating film, the first conductive film functions as a first electrode of the capacitor element, the fourth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

3. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a second conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a fourth conductive film having a region disposed above the first oxide semiconductor film having a channel formation region of the first transistor with an insulating film interposed therebetween and functioning as one of a source electrode and a drain electrode of the second transistor; a fifth conductive film having a function as the other of the source electrode and the drain electrode of the second transistor, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fourth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the third conductive film; the second conductive film has a region disposed above the first oxide semiconductor film, the first conductive film functions as a first electrode of the capacitor element, the fourth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

4. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a second conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a fourth conductive film having a region disposed above the first oxide semiconductor film having a channel formation region of the first transistor with an insulating film interposed therebetween and functioning as one of a source electrode and a drain electrode of the second transistor; a fifth conductive film having a function as the other of the source electrode and the drain electrode of the second transistor, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fourth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the third conductive film; the fourth conductive film has a region in contact with the insulating film, the fifth conductive film has a region in contact with the insulating film, the second conductive film has a region disposed above the first oxide semiconductor film, the first conductive film functions as a first electrode of the capacitor element, the fourth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

5. In any one of claims 1 to 4, each of the first conductive film to the fifth conductive film contains at least one element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; Semiconductor device.

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