Core substrate, substrate, and use of semiconductor packaging substrate

Abstract

To provide a core substrate and a substrate for semiconductor packaging capable of improving processability and manufacturing yield by preventing the substrate from being broken in a manufacturing process.SOLUTION: A core substrate 100 applied to manufacture of a semiconductor packaging substrate is divided into a product region 10 in which a product utilized as a substrate of an individual semiconductor is disposed and a margin region 20 excluding the product region, the margin region includes a protection region 25 disposed between the product region and an edge of the substrate, and the protection region includes a via 251 or a concave. Therefore, even when a core substrate that is easily broken by an external impact is applied, the occurrence of damage to a product region utilized as a substrate for semiconductor packaging may be substantially suppressed.SELECTED DRAWING: Figure 5B

Description

[Technical Field]

[0001] The embodiment relates to applications such as core substrates, substrates, and substrates for semiconductor packaging, which have excellent effects such as crack prevention and improve processability and manufacturing yield.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63 / 396,615, filed with the U.S. Patent and Trademark Office on August 10, 2022, the contents of which are incorporated herein by reference in their entirety. [Background technology]

[0003] In the production of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers so that they can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0004] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, including nano-level line widths below microns, more than 10 million cells, high-speed operation, and high heat dissipation, but the technology to perfectly package this has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0005] Ceramic or resin is used as a material for the packaging substrate. Ceramic substrates have high resistance or high dielectric constant, making it difficult to mount high-performance, high-frequency semiconductor devices. Resin substrates can mount relatively high-performance, high-frequency semiconductor devices, but there is a limit to how much the wiring pitch can be reduced.

[0006] Recently, research has been conducted into the application of silicon and glass to high-end packaging substrates. By forming through-holes in silicon or glass substrates and filling these with conductive materials, the length of the wiring between the device and the motherboard can be shortened, resulting in superior electrical characteristics.

[0007] Korean Patent Publication No. 10-2004-0017552 is a prior art in the related technical field, but the invention therein is different in that it relates to a display substrate rather than a packaging substrate. Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present embodiment is to provide a core substrate, a substrate for semiconductor packaging, and uses thereof that can prevent cracks in the substrate during the manufacturing process and improve processability and manufacturing yield. [Means for solving the problem]

[0009] To achieve the above object, a core substrate according to one embodiment is a core substrate used in manufacturing a semiconductor packaging substrate, and the core substrate is divided into a product area where a product used as a substrate for an individual semiconductor is placed, and a blank area excluding the product area, and the blank area includes a protective area placed between the product area and the edge of the substrate.

[0010] The protective region may include a via or a concave.

[0011] The core substrate may be a ceramic substrate or a glass substrate.

[0012] The core substrate may be a substrate selected from a silicon-based ceramic substrate, a glass-based ceramic substrate, a glass substrate, or a combination thereof.

[0013] The product area may be an area in which one or more individual packaging substrates are disposed.

[0014] The vias or grooves may be arranged side by side around at least a portion of the edge of the product area to form a row.

[0015] The via or the groove may have an oval or rectangular shape with a length that is 20% to 150% of one side of the edge of the product area.

[0016] The interior of the via or trench may be disposed with an electrically conductive material, an insulating material, or both.

[0017] The protective area may include two or more rows having different distances from the edge of the product area.

[0018] The two or more rows may include a first row and a second row disposed alongside one another.

[0019] The vias in the first row and the vias in the second row may be offset from each other.

[0020] The protective area protects the product area from damage that progresses from the edge of the core substrate to the inside of the core substrate.

[0021] A substrate according to another embodiment is a substrate used in manufacturing a semiconductor packaging substrate, and includes the above-described core substrate, the core substrate having one side and another side facing each other.

[0022] An upper redistribution layer may be disposed on one surface of the core substrate.

[0023] A lower rewiring layer may be disposed below the other surface of the core substrate.

[0024] The upper redistribution layer may include an upper insulating layer and an upper electrically conductive layer disposed within the upper insulating layer.

[0025] The lower redistribution layer may include a lower insulating layer and a lower electrically conductive layer disposed within the lower insulating layer.

[0026] Bumps may be disposed on the upper redistribution layer, the lower redistribution layer, or both.

[0027] The lower redistribution layer or the bump may have a thermal expansion coefficient greater than that of the core substrate.

[0028] The via or the groove can act as a stopper when damage occurs to the core substrate.

[0029] The via or the groove is formed by removing a part of the core substrate from the core substrate.

[0030] The removed area may be a space that is not filled with other material.

[0031] The removed area may be filled with a filler material.

[0032] The filler material may include a heat dissipating material, an insulating material, or both.

[0033] According to another embodiment, a substrate used for semiconductor packaging includes a core substrate, the core substrate being divided into a product region where a product used as a substrate for an individual semiconductor is disposed and a blank region excluding the product region, the blank region including a protective region disposed to surround the product region, and the protective region substantially preventing cracks that occur from an edge of the core substrate in a direction generally perpendicular to a thickness direction from progressing to the product region.

[0034] In another embodiment, a substrate is used to manufacture a semiconductor packaging substrate, the substrate including a glass sheet, the core substrate including a glass sheet, the core substrate being divided into a product area where a product to be used as a packaging substrate for an individual semiconductor is disposed, and a blank area excluding the product area, the blank area including a protective area disposed to surround the product area, the substrate being used to mount a semiconductor element, the semiconductor element being mounted on one surface of the substrate and / or within a cavity space of the substrate.

[0035] A semiconductor device according to another embodiment includes the substrate described above and a device mounted on the substrate. [Effects of the Invention]

[0036] In the core substrate, substrate, substrate application, semiconductor device, etc. of the embodiment, even if a core substrate that is easily broken by external impact is used, damage to a product area used as a substrate for semiconductor packaging can be substantially suppressed. Even if cracks occur in the glass sheet itself due to stress applied to the substrate itself during various processes such as via formation, redistribution layer formation, and / or electrode formation in the glass sheet substrate, the embodiment can prevent the product area from cracking, thereby substantially improving process efficiency. [Brief explanation of the drawings]

[0037] [Figure 1] 1 is a conceptual diagram illustrating an example configuration of a core substrate according to one or more embodiments. [Figure 2] 10A and 10B are conceptual diagrams illustrating other exemplary configurations of a core substrate according to one or more embodiments. [Figure 3] 1 is a conceptual diagram illustrating an example configuration of a core substrate according to one or more embodiments. [Figure 4A] 1 is a schematic diagram illustrating a top view of a substrate according to one or more embodiments; [Figure 4B] 1 is a schematic diagram illustrating a top view of a substrate according to one or more embodiments; [Figure 5A]1 is a schematic diagram illustrating a top view of a core substrate according to one or more embodiments; [Figure 5B] 6 is a schematic diagram illustrating an example of a cross section of the core substrate taken along line AA' in FIG. 5. FIG. [Figure 5C] 1 is a schematic diagram illustrating a top view of a core substrate according to one or more embodiments; [Figure 6A] 1 is a schematic diagram illustrating a top view of a core substrate according to one or more embodiments; [Figure 6B] 6B is a schematic diagram illustrating another example of a cross section of the core substrate taken along line AA' in FIG. 6A. FIG. [Figure 7] 1 is a conceptual diagram illustrating an example of a protection region according to one or more embodiments. [Figure 8] 1 is a conceptual diagram illustrating an example of a protection region according to one or more embodiments. [Figure 9] 1 is a conceptual diagram illustrating a cross-sectional view of a substrate structure according to one or more embodiments; [Figure 10] 1 is a conceptual diagram illustrating a cross-sectional view of a substrate structure according to one or more embodiments; [Figure 11A] 1A and 1B are cross-sectional conceptual diagrams illustrating how damage occurs to a core substrate during a substrate manufacturing process applied to manufacturing a semiconductor packaging substrate. [Figure 11B] 1A and 1B are cross-sectional conceptual diagrams illustrating how damage occurs to a core substrate during a substrate manufacturing process applied to manufacturing a semiconductor packaging substrate. BEST MODE FOR CARRYING OUT THE INVENTION

[0038] The present invention will now be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0039] Throughout this specification, the term "combinations thereof" contained in a Markush form phrase means a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, and means including one or more selected from the group of elements.

[0040] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish between identical terms, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0041] In this specification, the term "-" may mean that the compound includes a compound corresponding to "-" or a derivative of "-".

[0042] In this specification, the term "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0043] In this specification, the expression "B is linked to A" means that A and B are directly linked or that A and B are linked via another component therebetween, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0044] In this specification, unless otherwise specified, the singular expression is to be construed as including the singular or plural as the context requires.

[0045] In this specification, high frequency means a frequency of about 1 GHz to about 300 GHz. Specifically, it may mean a frequency of about 1 GHz to about 30 GHz, or may mean a frequency of about 1 GHz to about 15 GHz.

[0046] In this specification, unless otherwise specified, a fine line means a line having a width of 5 μm or less, and illustratively means a line having a width of 1 to 4 μm or less.

[0047] In this specification, the shape, relative size, angle, etc. of each component in the drawings are illustrative and may be exaggerated for the purpose of explanation, and the rights should not be interpreted as being limited to the drawings.

[0048] FIG. 1 is a conceptual diagram illustrating an exemplary configuration of a core substrate, FIG. 2 is a conceptual diagram illustrating another exemplary configuration of a core substrate, and FIG. 3 is a conceptual diagram illustrating an exemplary configuration of a core substrate according to an embodiment. FIG. 4A is a schematic diagram illustrating a top view of a substrate according to an embodiment, and FIG. 4B is a schematic diagram illustrating a top view of a substrate according to another embodiment. FIG. 5A is a schematic diagram illustrating a top view of a core substrate according to an embodiment, FIG. 5B is a schematic diagram illustrating an example cross section of the core substrate taken along line A-A' in FIG. 5, and FIG. 5C is a schematic diagram illustrating a top view of a core substrate according to an embodiment. FIG. 6A is a schematic diagram illustrating a top view of a core substrate according to another embodiment, and FIG. 6B is a schematic diagram illustrating another example cross section of the core substrate taken along line A-A' in FIG. 6A. FIGS. 7 and 8 are conceptual diagrams illustrating exemplary protective regions according to embodiments, and FIGS. 9 and 10 are conceptual diagrams illustrating cross-sectional views of substrate structures according to embodiments. 11A and 11B are cross-sectional conceptual diagrams illustrating how damage occurs to a core substrate during a substrate manufacturing process used in manufacturing a semiconductor packaging substrate. Hereinafter, specific examples will be described in detail with reference to the drawings.

[0049] The manufacturing process of a semiconductor packaging substrate essentially involves forming multiple build-up layers on a core substrate. The build-up layers are formed by repeating heating and cooling processes tens to hundreds of times. During this process, the core substrate acts as a support and is continuously subjected to stress due to heat and pressure.

[0050] The inventors have observed that unique damage occurs to the core substrate when an impact is applied to the substrate during or after the formation of the build-up layer. Generally, when a ceramic or glass substrate is damaged in response to an external impact P, a portion of the edge falls off or the substrate breaks into two or more pieces. The damage observed by the inventors was unique, being damage D in a direction perpendicular to the thickness of the substrate (see FIGS. 11A and 11B). The inventors have determined that one of the various causes of this phenomenon is stress accumulated in the core substrate during the manufacturing process of the build-up layer.

[0051] The inventors provide a substrate in an embodiment that can substantially prevent damage to a product area even if damage occurs to a portion of a core substrate during the manufacturing process of a semiconductor packaging substrate.

[0052] Core substrate 100 To achieve the above object, a core substrate 100 according to an embodiment is applied to the manufacture of a semiconductor packaging substrate.

[0053] In one or more embodiments, the core substrate 100 serves as a support in the packaging substrate, and is therefore distinguished from a redistribution layer, a dielectric layer, or an insulating layer disposed above or below the core substrate.

[0054] In one or more embodiments, the core substrate 100 may be a ceramic substrate, a glass substrate, or a combination thereof.

[0055] The ceramic substrate may be, for example, a silicon-based ceramic substrate, a glass-based ceramic substrate, etc. The silicon-based ceramic substrate may be a substrate that partially or entirely includes a silicon substrate, a silicon carbide substrate, etc. The glass-based ceramic substrate may be a substrate that partially or entirely includes a quartz substrate, a sapphire substrate, etc.

[0056] The glass substrate can be any glass plate used for electronic components.

[0057] The glass substrate may be, for example, an alkali borosilicate plate glass, an alkali-free borosilicate plate glass, an alkali-free alkaline earth borosilicate plate glass, or the like.

[0058] The thickness of the core substrate 100 may be 50 μm or more, 100 μm or more, 150 μm or more, 200 μm or more, 250 μm or more, 300 μm or more, or 350 μm or more. The thickness of the core substrate may be 3000 μm or less, 1000 μm or less, 700 μm or less, or 500 μm or less. When the core substrate is used within these thickness ranges, it can be highly useful as a substrate for semiconductor packaging.

[0059] The core substrate 100 is divided into a product area 10 where products used as packaging substrates for individual semiconductors are placed, and a blank area 20 excluding the product area.

[0060] A substrate used in the manufacture of semiconductor packaging substrates usually has a margin area called a margin region. The area to be manufactured, which is usually located in the center of the substrate, is separated from the substrate as a product through a singulation process, and the line separating the substrate during the singulation process is called the product boundary line 1.

[0061] One product boundary line may be arranged per substrate, in which case one semiconductor packaging substrate product is manufactured from one substrate. Two or more product boundary lines may be arranged per substrate, in which case multiple semiconductor packaging substrate products may be manufactured from one substrate. That is, one or more products may be arranged in a product area, and one product boundary line used as an individual semiconductor substrate may be arranged within the product area boundary line (see FIG. 2). Two or more product boundary lines may also be arranged within the product area boundary line (see FIG. 1).

[0062] The area outside the boundary of the product area is generally maintained during the manufacturing process of the semiconductor packaging substrate and removed when the product is completed. In the illustrated embodiment, the area to be manufactured—e.g., the area inside the line connecting the outermost edges of the product boundary—is referred to as the product area 10. Furthermore, the non-product area to be removed when the product is completed—e.g., the area from the line connecting the outermost edges of the product boundary to the edge of the substrate—is referred to as the margin area 20 (see FIGS. 1 and 2).

[0063] In this embodiment, a protective area 25 is introduced into the substrate along with the product area 10 and the blank area 20 to prevent damage to the product.

[0064] The protective area 25 is disposed between the product area 10 and the edge of the substrate. The protective area 25 is disposed in the margin area 20 (see FIG. 3).

[0065] The protective area 25 may be disposed between one edge of the product area and an edge of the substrate, or may be disposed so as to surround the product area.

[0066] The protective region 25 may be arranged as a single region on one core substrate (see FIG. 4A), or two or more protective regions 25 may be arranged separately (see FIG. 4B).

[0067] The protective area 25 can protect the product area from damage that propagates from the edge of the core substrate to the inside of the core substrate.

[0068] In one or more embodiments, the protection region 25 may include a via 251 (see FIGS. 5A and 5B).

[0069] In the illustrated embodiment, via 251 refers to a through hole that penetrates the core substrate in the thickness direction. The shape of the via entrance (the surface where the via meets the surface of the core substrate) is not limited to a circle. Exemplarily, the entrance may have various shapes such as a circle, ellipse, square, rectangle, square, diamond, or triangle, and although it is called a via, the entrance shape is not limited to a circle.

[0070] In one or more embodiments, the protective region 25 may include a concave 255 (see FIGS. 6A and 6B).

[0071] In the illustrated embodiment, the groove 255 refers to a groove recessed in the thickness direction of the core substrate. The shape of the groove entrance (the surface where the groove meets the surface of the core substrate) is not limited to a circle. Exemplarily, the entrance may have various shapes such as a circle, ellipse, square, rectangle, square, diamond, or triangle, and although it is called a concave, the shape of the entrance is not limited to a circle. The groove may have a depth of 99% or less, 90% or less, 70% or less, or 60% or less of the thickness, or a depth of 30% or more, or 40% or more.

[0072] In one or more embodiments, the entrance of the groove 255 may be located on one side of the core substrate or on the other side of the core substrate, and multiple grooves 255 may be located on both sides of the core substrate.

[0073] The cross-sectional shape of the via or trench may be a mixture of circular, elliptical, rectangular, and other shapes. Also, a via (or trench) with an opening shaped like an elongated ellipse or elongated rectangle may be used (see FIG. 5C). In this case, a long ellipse or elongated rectangle may mean that the ratio of the length to the width of the opening when viewed from above is 5 or more (see FIG. 5C). Specifically, the ratio may be 200 or less.

[0074] The via 251 or the groove 255 may be disposed on one side of the edge of the product area and may be manufactured in an elongated shape. It has been substantially difficult to form vias or grooves through chemical etching in substrates such as prepreg, which have been used conventionally as semiconductor packaging substrates. The substrate of the present embodiment allows vias or holes to be formed through a process that includes chemical etching, allowing for greater freedom in determining the shape of the via or hole and the area to be removed. That is, the core substrate 100 of the present embodiment has the advantage that it is relatively easy to form elongated or large-area holes or vias.

[0075] There is no particular limitation on the diameter (or length) of the via 251 or the groove 255. Exemplarily, the size of the via or groove may be 30 μm or more, 50 μm or more, or 100 μm or more, based on the length of the inlet. Exemplarily, the size may be 20 mm or less, or 10 mm or less.

[0076] The via 251 or groove 255 may have an oval or rectangular shape with a length that is 20% to 150% of one side of the edge of the product area. The length of the via or groove may be 30% to 120%, or 40% to 100% of one side of the edge of the product area. When a via or groove is formed in this way, the product area can be more efficiently protected regardless of the location of damage caused by impact.

[0077] The vias 251 or the grooves 255 may be arranged side by side around at least a portion of the edge of the product area to form a row. The row refers to a number of vias arranged at regular or irregular intervals. The vias or grooves included in the row are not necessarily limited to being arranged at regular intervals in a single row. For example, vias or grooves may be formed at approximately regular intervals from the product area, and this group of vias or grooves may be treated as the protection area.

[0078] The protective area 25 may include two or more rows arranged at different distances from the edge of the product area 10 (see FIGS. 7 and 8).

[0079] The two or more rows may include a first row 252 and a second row 253 arranged side by side. The vias in the first row and the vias in the second row may be offset from each other.

[0080] In one or more embodiments, the via 251 or the groove 255 may be hollow. Since the via or groove is not disposed in a product area, it may be hollow and not filled with an insulating layer or an electrically conductive layer (e.g., a metal such as copper).

[0081] In one or more embodiments, the via 251 or the groove 255 may be filled with a material different from the material of the core substrate. A metal layer may be plated inside the via or groove. An electrically conductive layer may be disposed inside the via or groove. The electrically conductive layer may be made of, but is not limited to, copper, copper alloy, or the like. An insulating layer may be disposed inside the via or groove. The insulating layer may be made of, but is not limited to, a mixture of inorganic particles and a polymer resin. The via or groove may contain both a metal and an insulating layer. When the via or groove is filled with a material different from the material of the core substrate, it is believed that the crack prevention effect of the protective region is more excellent.

[0082] The vias 251 or grooves 255 can act as stoppers to prevent damage that may occur in the substrate in a direction generally perpendicular to the thickness of the core substrate from progressing to the product area, thereby improving the yield of product manufacturing.

[0083] A substrate used in manufacturing a semiconductor packaging substrate may have grooves or vias formed in its margins to mark the product or to distinguish the top and bottom of the substrate. In this case, grooves or vias are usually formed on the edge of the substrate, or letters may be etched.

[0084] On the other hand, the core substrate of the embodiment may be distinguished from a mark that serves to identify the type of substrate, distinguish between the top and bottom, etc. by repeatedly forming vias or grooves between the edge of the core substrate and the product area. However, the vias or grooves of the embodiment that are formed asymmetrically or in a specific shape may form the protective area of ​​the embodiment and also serve as a mark.

[0085] A method for manufacturing the core substrate of the embodiment will now be described.

[0086] The core substrate is fabricated by etching a plate-shaped ceramic substrate or a plate-shaped glass substrate (hereinafter referred to as a substrate material for convenience) that will serve as the core substrate material, to form a protective region. The ceramic substrate may be a conventional silicon substrate or silicon carbide substrate, and its thickness is adjustable. The glass substrate may be a glass substrate for electronic devices, and examples thereof include, but are not limited to, those manufactured by Schott, AGC, Corning, etc.

[0087] The trenches or vias formed in the protection region can be manufactured in substantially the same manner as through-holes (through silicon vias, TSVs; through glass vias, TGVs) formed in the product region. Exemplarily, they can be manufactured by intentionally forming defects in the substrate material and then performing etching. The defects can be formed by mechanical etching, laser irradiation, or the like. The etching can be chemical etching, or a combination of chemical etching and physical etching. Exemplarily, the chemical etching can be performed by placing the glass substrate with the trenches formed in a bath containing hydrofluoric acid and / or nitric acid and then ultrasonicating the substrate. The concentration of the hydrofluoric acid can be 0.5 M or more, or 1.1 M or more. The concentration of the hydrofluoric acid can be 3 M or less, or 2 M or less. The concentration of the nitric acid can be 0.5 M or more, or 1 M or more. The concentration of the nitric acid can be 2 M or less. The ultrasonication can be performed at a frequency of 40 Hz to 120 Hz, or 60 Hz to 100 Hz.

[0088] The formation of the grooves or vias in the protection area can be performed simultaneously with the etching process for forming the vias, cavity spaces, etc. in the product area. Thus, even when the protection area is formed, the manufacturing speed is not substantially reduced and the defect rate is reduced, thereby significantly improving the yield of packaging substrate manufacturing.

[0089] The filling of the grooves or vias in the protection region with a different material may be performed together with the process of forming electrodes and / or an insulating layer in the product region. The process of forming the redistribution layer including the electrodes and insulating layer of the packaging substrate may be performed by copper plating, vacuum lamination of an ABF layer, etc., and any method capable of forming a redistribution layer may be used, and detailed description thereof will be omitted.

[0090] Substrate 900 and its use as a semiconductor packaging substrate To achieve the above object, a substrate 900 according to another embodiment is adapted for manufacturing a semiconductor packaging substrate and includes a core substrate 100 .

[0091] The core substrate 100 may be any of the above-described core substrates.

[0092] The core substrate 100 has one surface and another surface facing each other.

[0093] An upper redistribution layer 300 is disposed on one surface of the core substrate, and the upper redistribution layer includes an upper insulating layer and an upper electrically conductive layer disposed within the upper insulating layer.

[0094] In the present embodiment, the upper redistribution layer may be formed by mixing an insulating layer and an electrically conductive layer made of metal or the like, and the electrically conductive layer may be embedded in the insulating layer at a predetermined position and shape. The electrically conductive layer may be formed as a thin line in at least a portion of the upper redistribution layer.

[0095] A lower redistribution layer 500 and / or bumps 600 may be disposed under the other surface of the core substrate.

[0096] The lower redistribution layer 500 may include a lower insulating layer and a lower electrically conductive layer disposed within the lower insulating layer.

[0097] In the embodiment, the lower redistribution layer 500 may be formed by mixing an insulating layer and an electrically conductive layer made of metal or the like, and by embedding the electrically conductive layer in the insulating layer at a predetermined position and shape.

[0098] In addition, the lower redistribution layer and the upper redistribution layer arranged in the product area can be electrically connected to each other by an electrically conductive layer passing through the core substrate according to a predetermined layout.

[0099] The bumps may be arranged in a predetermined pattern in a portion of the product area. For example, the bumps may be arranged in a portion of the upper surface of the substrate, which is an area where a semiconductor element is mounted. For example, the bumps may be arranged in a portion of the lower surface of the product area that is arranged to contact a main board or the like.

[0100] The thermal expansion coefficient of the lower redistribution layer 500 or the thermal expansion coefficient of the bump 600 may be greater than the thermal expansion coefficient of the core substrate.

[0101] In the embodiment, the upper redistribution layer or the lower redistribution layer disposed on the substrate 900 may be formed by repeatedly forming and removing an insulating layer and an electrically conductive layer, and during this process, an insulating layer and / or an electrically conductive layer may be naturally formed in the groove or via of the protection area (see FIG. 10).

[0102] In the embodiment, the upper or lower redistribution layer disposed on the substrate 900 may be formed excluding a part or all of the protection region (see FIG. 9).

[0103] The trenches or vias in the protective region may be filled with a filling material.

[0104] The filling material may be an insulating material, a heat dissipating material, or both.

[0105] It may be filled with an insulating material or a heat dissipating material.

[0106] The insulating material may be, for example, a build-up layer material such as Ajinomoto Build-up Film (ABF) manufactured by Ajinomoto Co., Ltd., an undercoat material, or the like, but is not limited thereto.

[0107] The heat dissipation material may be a material having a higher thermal conductivity than ceramic or glass, and may be, for example, a metal heat dissipation material, a polymer composite heat dissipation material, etc. Specifically, the heat dissipation material may be, but is not limited to, an aluminum-based heat dissipation material, a copper-based heat dissipation material, etc.

[0108] The trench or via may be left unfilled.

[0109] The grooves or vias may be left unfilled and connected to the outside of the substrate, which may help dissipate heat from the core substrate during the substrate manufacturing process.

[0110] The trench or via may be completely filled or only partially filled.

[0111] If the trench or via is filled, the generation of stress on the substrate can be reduced or eliminated depending on the fill material.

[0112] The protection area 25 of the core substrate 100 protects the product area from damage that progresses from the edge of the core substrate to the inside of the core substrate. The groove or the via can act as a stopper when damage occurs in the core substrate.

[0113] The substrate 900 of the embodiment is a substrate including a core substrate used for semiconductor packaging, and the core substrate 100 is divided into a product area 10 where products used as substrates for individual semiconductors are placed, and a blank area 20 excluding the product area, and the blank area 20 includes a protective area 25 arranged to surround the product area, and the protective area 25 can substantially prevent cracks from progressing from the edge of the core substrate in a direction approximately perpendicular to the thickness direction to the product area.

[0114] The use of the substrate according to the embodiment is a use of a substrate including a glass sheet for manufacturing a substrate for semiconductor packaging, in which the core substrate is divided into a product area where a product to be used as a packaging substrate for individual semiconductors is placed and a blank area excluding the product area, and the blank area includes a protective area arranged to surround the product area, and the substrate is used to mount a semiconductor element, and the semiconductor element may be mounted on one side of the substrate or within a cavity space of the substrate.

[0115] Packaged Semiconductors A packaged semiconductor (not shown) according to another embodiment includes a semiconductor packaging substrate and a device mounted on the substrate. The description of the substrate is the same as that described above, so further description will be omitted.

[0116] The elements may be computing elements such as CPUs and GPUs, storage elements such as memory chips, etc., and these may be applied together side by side or stacked.

[0117] The elements may be disposed on one surface of the substrate or within the substrate, and may be mounted such that a space called a cavity is formed within the substrate, and some or all of the elements are disposed substantially within the substrate.

[0118] The device may be a high-frequency semiconductor device. When a high-frequency semiconductor device is applied to a packaging substrate, unlike a silicon substrate, parasitic elements are not substantially generated in a high-frequency environment, thereby improving efficiency, and unlike a prepreg substrate, it is possible to realize a redistribution line with a compact size.

[0119] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also fall within the scope of the present invention. [Explanation of symbols]

[0120] 900 boards 100 core board 10 product areas 1 Product boundaries 20 Margin Area 25 Protected area 251 Beer 252 1st row 253 2nd row 255 Groove 300 Upper redistribution layer 500 Lower redistribution layer 600 Bump P external force D Damage

Claims

[Claim 1] A core substrate used in manufacturing a semiconductor packaging substrate, The core substrate is divided into a product area and a blank area, the product area is an area where a product to be used as a substrate for an individual semiconductor is placed, and the margin area is an area excluding the product area; A protection area is disposed in the margin area, The core substrate, wherein the protection area is an area where a concave or a via is arranged.

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