Multi-die integrated circuit

Abstract

To provide a multi-die integrated circuit capable of suppressing a change in a value of a signal transmitted between dies.SOLUTION: A multi-die integrated circuit includes a first die, a second die coupled to the first die via a plurality of signal lines, and a signal transmission unit provided in the first die and configured to transmit a plurality of signals generated in the first die to the second die via the plurality of signal lines. The signal transmission unit detects whether or not any value of a signal included in any group among a plurality of groups each including one or more signals is changed, transmits all signals in the group including the signal whose value is changed to the second die and holds the signals in the register when any value of the signal is changed, and does not transmit the signal to the second die when any value of the signal is not changed.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present disclosure relates to multi-die integrated circuits. [Background technology]

[0002] The multi-die integrated circuit disclosed in Patent Document 1 has many inter-die signal lines for communicating data between multiple dies. As the number of inter-die signal lines increases, the area occupied by the connection terminals on the dies increases, increasing chip costs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-510512 Summary of the Invention [Problem to be solved by the invention]

[0004] To address this issue, if signals are transmitted in a time-division manner, the signal values ​​transmitted between the dies may constantly change, resulting in increased current consumption. Specifically, each die may use a different semiconductor process, resulting in different signal voltages. This difference in signal voltage necessitates a level shifter to change the signal voltage. For example, each time a signal is transmitted from one die to another, the level shifter changes the signal voltage from 1.8V to 1.2V, or from 1.2V to 1.8V. Frequent signal voltage changes result in increased current consumption by the level shifter. Therefore, the prior art leaves room for improvement in reducing the number of inter-die signal lines while simultaneously reducing the power consumption of multi-die integrated circuits due to changes in the signal values ​​transmitted between the dies.

[0005] In view of the above circumstances, the present disclosure aims to provide a multi-die integrated circuit that can suppress changes in the values ​​of signals transmitted between dies. [Means for solving the problem]

[0006] In order to solve the above problem, the multi-die integrated circuit of the present disclosure comprises a first die, a second die connected to the first die via a plurality of signal lines, and a signal transmitting unit provided on the first die that transmits a plurality of signals generated by the first die to the second die via the plurality of signal lines, wherein the signal transmitting unit detects whether a value of any of the signals included in any of a plurality of groups, each including one or more of the signals, has changed, and if the value of any of the signals has changed, transmits all signals in the group including the signal whose value has changed to the second die and holds them in a register, and if the value of any of the signals has not changed, does not transmit the signal to the second die. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A is a diagram illustrating a multi-die integrated circuit 100 according to an embodiment of the present disclosure. [Figure 1B] FIG. 1B is a hardware block diagram of a multi-die integrated circuit 100 according to an embodiment of the present disclosure. [Figure 2A] FIG. 2A is a diagram illustrating an example configuration of a multi-die integrated circuit 100 according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a diagram illustrating an example configuration of a multi-die integrated circuit 100 according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing the configuration of the transmission priority control unit 1. [Figure 4A] FIG. 4A is a diagram for explaining the transmission priority order of a group. [Figure 4B] FIG. 4B is a diagram for explaining a specific example of the value of a signal indicating a group including a changed signal. [Figure 5] FIG. 5 is a timing chart for explaining the operation of the multi-die integrated circuit 100. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the signal transmission method according to the comparative example. [Figure 7A]FIG. 7A is a diagram showing an example of the configuration of a multi-die integrated circuit 100A according to a modified example. [Figure 7B] FIG. 7B is a diagram showing an example of the configuration of a multi-die integrated circuit 100A according to a modified example. [Figure 8] FIG. 8 is a diagram for explaining the relationship between the number of signal lines and the number of signals in the multi-die integrated circuits 100 and 100A. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0009] (Embodiment) FIG. 1A is an external view of a multi-die integrated circuit 100 according to an embodiment of the present disclosure. FIG. 1B is a hardware configuration diagram of the multi-die integrated circuit 100 according to an embodiment of the present disclosure. The multi-die integrated circuit 100 may include a first die 101 and a second die 102. The second die 102 is connected to the first die 101 via multiple signal lines SW and multiple buses BUS. The first die 101 includes a CPU (Central Processing Unit) 10, a ROM (Read Only Memory) 11, a RAM (Random Access Memory) 12, a signal section 13, an internal bus 14, and a bus BUS. The CPU 10, the ROM 11, and the RAM 12 are connected to each other via the internal bus 14 and to the multiple buses BUS. The second die 102 includes a peripheral circuit 21, an internal bus 23, and a signal section 22. The peripheral circuit 21 is connected to the multiple buses BUS via the internal bus 23.

[0010] 2A and 2B are diagrams illustrating an example configuration of a multi-die integrated circuit 100 according to an embodiment of the present disclosure. Fig. 2A illustrates the configuration of a first die 101, and Fig. 2B illustrates the configuration of a second die 102.

[0011] (First die 101) As shown in Fig. 2A, the first die 101 may include a signal transmitting unit 41 and a plurality of level shifters 42. The signal unit 13 shown in Fig. 1B may include the signal transmitting unit 41 and a plurality of level shifters 42 shown in Fig. 2A.

[0012] The signal transmitting unit 41 may transmit multiple signals (e.g., snd_sig[15:0]) generated by the first die 101 to the second die 102 via multiple signal lines SW. The multiple signals (snd_sig[15:0]) may be interpreted as a 16-bit signal. The number of signal lines SW may be interpreted as seven, for example. Note that these numbers of signals and signal lines SW are merely examples in the present disclosure, and the embodiments of the present disclosure are not limited to these.

[0013] The signal transmitting unit 41 may have a function to transmit all signals in a group including a signal whose value has changed among a plurality of signals (for example, snd_sig[15:0]) and to perform control to not transmit signals whose values ​​have not changed. Specifically, the signal transmitting unit 41 may include a signal change detecting unit 2, a plurality of selectors S_0 to S_3, a selector S_n, a plurality of registers R_0 to R_3, a register R_a, a register R_b, a transmission priority control unit 1, and a selection signal output unit 4.

[0014] (Signal change detection unit 2) The signal change detection section 2 may detect whether or not the value of any of the signals included in any of a plurality of groups, each of which includes one or more signals, has changed.

[0015] Specifically, if the values ​​of all signals held in each of the multiple registers R_0 to R_3 match the values ​​of the signals included in a group that can be newly transmitted, the signal change detection unit 2 may determine that the values ​​of the signals included in the group have not changed.If the values ​​of all signals held in each of the multiple registers R_0 to R_3 do not match the values ​​of the signals included in the group that can be newly transmitted (i.e., there is a mismatch), the signal change detection unit 2 may determine that the value of any of the signals included in the group has changed.

[0016] (Group 0) More specifically, the signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[3:0]) included in group 0 has changed, by comparing the value of the signal (snd_sig[3:0]) included in group 0 among multiple signals (for example, snd_sig[15:0]) that may be newly transmitted with the value of the signal held in register R_0. The signals (snd_sig[3:0]) included in group 0 may be interpreted as the lowest 4 bits of the 16-bit signal.

[0017] (Group 1) The signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[7:4]) included in group 1 among multiple signals (for example, snd_sig[15:0]) that may be newly transmitted has changed by comparing the value of the signal (snd_sig[7:4]) included in group 1 with the value of the signal held in register R_1. The signals (snd_sig[7:4]) included in group 1 may be interpreted as the upper 4 bits of the signals in group 0 among the 16-bit signals.

[0018] (Group 2) The signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[11:8]) included in group 2 among multiple signals (for example, snd_sig[15:0]) that may be newly transmitted has changed by comparing the value of the signal (snd_sig[11:8]) included in group 2 with the value of the signal held in register R_2. The signals (snd_sig[11:8]) included in group 2 may be interpreted as the upper 4 bits of the signals in group 1 among the 16-bit signals.

[0019] (Group 3) The signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[15:12]) included in group 3 among multiple signals (for example, snd_sig[15:0]) that may be newly transmitted has changed by comparing the value of the signal (snd_sig[15:12]) included in group 3 with the value of the signal held in register R_3. The signals (snd_sig[15:12]) included in group 3 may be interpreted as the upper 4 bits of the signals in group 2 among the 16-bit signal, that is, the most significant 4 bits of the 16-bit signal.

[0020] When the value of any of the signals changes, the signal change detection unit 2 inputs to the transmission priority control unit 1 a signal (snd_chg[3:0]) indicating the group that includes the signal whose value has changed among the multiple groups.

[0021] For example, if the value of any of the signals included in group 0 changes, the signal change detection unit 2 inputs a signal (snd_chg[0]) indicating group 0 to the transmission priority control unit 1, and if the value of any of the signals included in group 1 changes, the signal change detection unit 2 inputs a signal (snd_chg[1]) indicating group 1 to the transmission priority control unit 1. Furthermore, if the value of any of the signals included in group 2 changes, the signal change detection unit 2 inputs a signal (snd_chg[2]) indicating group 2 to the transmission priority control unit 1, and if the value of any of the signals included in group 3 changes, the signal change detection unit 2 inputs a signal (snd_chg[3]) indicating group 3 to the transmission priority control unit 1.

[0022] When the signal change detection unit 2 detects that the value of any of the signals included in any of the groups has changed, it inputs a signal (snd_update) indicating that there is a group including the signal whose value has changed to the register R_b. As a result, the signal held in the register R_b is transmitted to the second die 102 via the level shifter 42.

[0023] (Transmission priority control unit 1) When there are multiple groups in which signals have changed, the transmission priority control unit 1 determines the priority order in order to transmit the signals included in each of the multiple groups in accordance with a specific priority order.

[0024] Specifically, the transmission priority control unit 1 determines the transmission priority of signals in the group including the signal whose value has changed based on the signal (snd_chg[3:0]) from the signal change detection unit 2, and inputs a signal (snd_num[1:0]) indicating the group number to be transmitted to the register R_a. The signal held in the register R_a is input to the selector S_n and further transmitted to the second die 102 via the level shifter 42. For example, by providing the transmission priority control unit 1, it is possible to avoid a situation where, when signals in group 0 continue to change, all signals in group 0 continue to be transmitted, and signals in other groups are not transmitted even if the signals in other groups change. The configuration of the transmission priority control unit 1 will be described in detail later.

[0025] (Selection signal output unit 4) The selection signal output unit 4 outputs a selection signal for storing the signal of the group to be transmitted in a register R_0 or the like. The selection signal (snd_sel[0]) may be interpreted as a signal for the selector S_0 to output the signal (snd_sig[3:0]) included in group 0. The selection signal (snd_sel[1]) may be interpreted as a signal for the selector S_1 to output the signal (snd_sig[7:4]) included in group 1. The selection signal (snd_sel[2]) may be interpreted as a signal for the selector S_2 to output the signal (snd_sig[11:8]) included in group 2. The selection signal (snd_sel[3]) may be interpreted as a signal for the selector S_3 to output the signal (snd_sig[15:12]) included in group 3.

[0026] (Selector S_n) The selector S_n selects all signals in the group to be transmitted from the registers R_0 to R_3 based on the signal, and the selected signals are transmitted to the second die 102 via the level shifter 42.

[0027] (Registers R_0 to R_3) The registers R_0 to R_3 hold the signals selected by the selectors S_0 to S_3, respectively. Specifically, the register R_0 holds the signal (snd_sig[3:0]) included in group 0 from the selector S_0. The register R_1 holds the signal (snd_sig[7:4]) included in group 1 from the selector S_1. The register R_2 holds the signal (snd_sig[11:8]) included in group 2 from the selector S_2. The register R_3 holds the signal (snd_sig[15:12]) included in group 3 from the selector S_3.

[0028] (Selectors S_0 to S_3) The selector S_0 may input a selection signal (snd_sel[0]) to output a signal (snd_sig[3:0]) included in group 0. When the selector S_0 does not input a selection signal (snd_sel[0]), the selector S_0 may output a signal held in the register R_0.

[0029] The selector S_1 may input a selection signal (snd_sel[1]) to output a signal (snd_sig[7:4]) included in group 1. When the selector S_1 does not input a selection signal (snd_sel[1]), the selector S_1 may output a signal held in the register R_1.

[0030] The selector S_2 may input a selection signal (snd_sel[2]) to output a signal (snd_sig[11:8]) included in group 2. When the selector S_2 does not input a selection signal (snd_sel[2]), the selector S_2 may output a signal held in the register R_2.

[0031] The selector S_3 may receive a selection signal (snd_sel[3]) to output a signal (snd_sig[15:12]) included in group 3. When the selector S_3 does not receive a selection signal (snd_sel[3]), it may output a signal held in the register R_3.

[0032] These selection signals may be generated from snd_num[1:0]. These selection signals may be input in a specific order, such as snd_sel[0], snd_sel[1], snd_sel[2], snd_sel[3], snd_sel[0], snd_sel[1], etc., each time a specific counter value is incremented.

[0033] The signal transmitting section 41 configured in this manner may not transmit the signal to the second die 102 if the value of any of the signals in the group does not change.

[0034] Furthermore, if there are two or more groups among the multiple groups in which the values ​​of any of the signals included in a specific group have changed simultaneously, the signal transmitting unit 41 may select a specific group from these groups and transmit all of the signals included in the selected group to the second die 102.

[0035] For example, if the value of any of the signals included in group 0 and the value of any of the signals included in group 1 have changed, but none of the signals included in group 2 have changed, and none of the signals included in group 3 have changed, the signal transmitting unit 41 may transmit the signals included in group 0 and the signals included in group 1 to the second die 102, and may not transmit the signals included in group 2 and the signals included in group 3 to the second die 102. Furthermore, the signal transmitting unit 41 may store these transmitted signals in register R_0 and register R_1.

[0036] In this way, the signal transmitting unit 41 detects whether or not a signal in a group has changed, and transmits all signals in the group only if a change has occurred. Also, if signals in multiple groups change simultaneously, the transmission priority control unit 1 selects one group to transmit from, and transmits all signals in the selected group, and simultaneously holds the values ​​of the transmitted signals.

[0037] (Second die 102) As shown in FIG. 2B, the second die 102 includes a signal receiving unit 52. The signal unit 22 shown in FIG. 1B may include the signal receiving unit 52 shown in FIG. 2B. The signal receiving unit 52 may include a selection signal output unit 5. The selection signal output unit 5 outputs a selection signal for storing the received group signal in a register R_0 or the like. The selection signal (rcv_sel[0]) may be interpreted as a signal for the selector S_0 to output a signal included in group 0 (rcv_sig[3:0]). The selection signal (rcv_sel[1]) may be interpreted as a signal for the selector S_1 to output a signal included in group 1 (rcv_sig[7:4]). The selection signal (rcv_sel[2]) may be interpreted as a signal for the selector S_2 to output a signal included in group 2 (rcv_sig[11:8]). The selection signal (rcv_sel[3]) may be interpreted as a signal for the selector S_3 to output the signal included in group 3 (rcv_sig[15:12]).

[0038] The signal receiving unit 52 is configured similarly to the signal transmitting unit 41. For example, when a signal (snd_num[1:0], snd_update) from the signal transmitting unit 41 is input as a received signal (rcv_num[1:0], rcv_update), the signal receiving unit 52 generates selection signals (rcv_sel[0] to rcv_sel[3]) that select one of the signals (rcv_data[3:0]) received by the multiple selectors S_0 to S_3 in response to the input signal. The signal selected by the selection signal is held in the registers R_0 to R_3 and output as a received signal (rcv_sig[15:0]). In this way, the values ​​of snd_sig, snd_reg, and rcv_sig are all set to match.

[0039] FIG. 3 is a configuration diagram of the transmission priority control unit 1. The transmission priority control unit 1 rotates the transmission priorities of multiple groups 0 to 3 by incrementing snd_cnt[1:0] with counter 3. In other words, in order to transmit only signals in the group that includes a signal whose value has changed, a signal (snd_num[1:0]) indicating the group number to be transmitted is output at the timing when counter 3 increments the group number. By rotating the transmission priorities of the groups, signals included in each group are transmitted equally. In other words, multiple groups are transmitted evenly over a fixed period of time.

[0040] FIG. 4A is a diagram for explaining the transmission priority order of groups. FIG. 4B is a diagram for explaining a specific example of the value of a signal indicating a group including a changed signal. As shown in FIG. 4A, when snd_cnt[1:0] is 00 (binary: 0), for example, the order of transmission priority of groups is group 0, group 1, group 2, and group 3. In other words, group 0 has the highest priority. When snd_cnt[1:0] is 01 (binary: 1), the order of priority is group 1, group 2, group 3, and group 4. In other words, group 1 has the highest priority.

[0041] 4A, when groups 0, 2, and 3 change but group 1 remains unchanged (snd_chg[3:0]=1101), and snd_cnt[1:0]=01, snd_chg_rot[3:0]=1110, snd_num_pre[1:0]=01, and snd_num[1:0]=01+01=10, group 2 is transmitted. In other words, because snd_cnt[1:0]=01, group 1 has the highest priority, but because the signal within group 1 has not changed, group 2, which has the next highest priority, is transmitted.

[0042] If there is only one group in which signals have changed, the value of the signal (snd_chg[3:0]) indicating the group containing the signal whose value has changed will be 0001 (binary: 1) if only the signals in group 0 have changed, as shown in FIG. 4B. Similarly, if only the signals in group 1 have changed, the value of the signal (snd_chg[3:0]) will be 0010 (binary: 2). If only the signals in group 2 have changed, the value of the signal (snd_chg[3:0]) will be 0100 (binary: 4). If only the signals in group 3 have changed, the value of the signal (snd_chg[3:0]) will be 1000 (binary: 8).

[0043] When there are multiple groups whose signals changed at the same time, the value of the signal (snd_chg[3:0]) indicating the group containing the signal whose value changed is 0101 (binary: 5) when the signals of group 0 and group 2 change, as shown in FIG. 4B, for example. In this case, snd_cnt[1:0] may be 10 (binary: 2) indicating that group 2 has the highest priority, and snd_num[1:0] may be 10 (binary: 2). Similarly, when the signals of all groups 0 to 3 change, the value of the signal (snd_chg[3:0]) is 1111 (binary: 15). In this case, snd_cnt[1:0] may be 11 (binary: 3) indicating that group 3 has the highest priority, and snd_num[1:0] may be 11 (binary: 3).

[0044] 5 is a timing chart for explaining the operation of the multi-die integrated circuit 100. As shown in FIG. 5, when a change in the signal of group 0 occurs at a specific timing (e.g., time t1), causing the value of the 16-bit signal to change from "3B7A" to "3B75," only the signal of group 0 is transmitted. Then, when the signal transmission is completed, no group contains a changed signal from the time of transmission completion until a specific timing (e.g., time t2) after time t1, and therefore no signals of any group are transmitted.

[0045] At time t2, if all signals in groups 0 to 3 change, causing the value of the 16-bit signal to change from "3B75" to "2019," all signals in groups 0 to 3 are transmitted in order. Then, when transmission of these signals is completed, no group contains a changed signal from the time transmission is completed until a specific timing after time t2 (for example, time t3), and therefore no signals in any group are transmitted.

[0046] FIG. 6 is a timing chart illustrating the operation of a signal transmission method according to a comparative example. The signal transmission method according to the comparative example can be interpreted as, for example, the method of transmitting signals using the time-division method in the prior art described above. With this method, the value of the signal transmitted between dies constantly changes, so the voltage must be changed using a level shifter. Frequent changes in the signal voltage increase the current consumed by the level shifter. Therefore, the prior art leaves room for improvement in reducing the number of inter-die signal lines while also reducing the power consumption of multi-die integrated circuits associated with changes in the value of the signal transmitted between dies.

[0047] 7A and 7B are diagrams showing an example configuration of a multi-die integrated circuit 100A according to a modified example. The multi-die integrated circuit 100A may have a signal diagnosis function, a signal refresh function, and the like in addition to the same functions as the multi-die integrated circuit 100 described above. To realize these functions, the multi-die integrated circuit 100A may have a first register SFR1, a second register SFR2, and a diagnosis unit 60.

[0048] (Configuration for realizing signal diagnostic function) The first register SFR1 may be provided in the first die 101A and may hold a diagnostic signal. The second register SFR2 may be provided in the second die 102A and may hold a diagnostic signal transmitted from the first die 101A to the second die 102A by the signal transmitting unit 41. The diagnosing unit 60 may read the diagnostic signals respectively held in the first register SFR1 and the second register SFR2 via the bus BUS and determine whether the read signals match, thereby diagnosing whether the signal transmitting unit 41 is transmitting the signal normally. The diagnosing unit 60 may be interpreted as a processor such as a CPU.

[0049] (Operations related to signal diagnostic function) (1) The diagnostic unit 60 writes the value of the signal to be transmitted into the first register SFR1. (2) The signal values ​​written to the first register SFR1 are sequentially transmitted as transmission signals (snd_sig[0], snd_sig[4], snd_sig[8], snd_sig

[12] ) from the first die 101A to the second die 102A. (3) The second die 102A receives these signals as received signals (rcv_sig[0], rcv_sig[4], rcv_sig[8], rcv_sig

[12] ) and stores them in the second register SFR2. The diagnostic unit 60 reads them from the second register SFR2 via the bus BUS. (4) The diagnostic section 60 may determine that the signal transmission operation is normal when the value of the received signal read from the second register SFR2 matches the value of the transmitted signal.

[0050] (Configuration that realizes signal refresh function) For example, if the second die 102A is temporarily powered off, a state in which snd_sig and rcv_sig do not match may occur. In this case, the diagnostic unit 60 may write the above-mentioned diagnostic signal to the first register SFR1, and then write a specific signal whose value is different from the value of the signal written to the first register SFR1 to the first register SFR1. The signal transmitting unit 41 may read this specific signal from the first register SFR1 and transmit the read specific signal to the second die. As a result, the value of the signal held in the second register SFR2 is refreshed, that is, updated, to the value of the specific signal transmitted from the signal transmitting unit 41.

[0051] (Operation related to signal refresh function) (1) The diagnostic unit 60 writes the value of the signal to be transmitted (for example, a signal whose value is the inverse of the value of the signal transmitted last time) into the first register SFR1. (2) The signal values ​​written to the first register SFR1 are sequentially transmitted as transmission signals (snd_sig[0], snd_sig[4], snd_sig[8], snd_sig

[12] ) from the first die 101A to the second die 102A. (3) After a certain time has passed since the transmission of the transmitted signal, the values ​​of the transmitted signal and the received signal all match.

[0052] 8 is a diagram illustrating the relationship between the number of signal lines and the number of signals in the multi-die integrated circuit 100, 100A. In the multi-die integrated circuit 100 according to an embodiment of the present disclosure, when the number of groups is 4, snd_chg[1:0], snd_cnt[1:0], and snd_num[1:0] are 2 bits long. Therefore, the number of signal lines between the dies is 4 + 2 + 1 = 7. For example, if the number of signals in a group is 4, the number of groups is 4, the total number of signals included in these groups is 16, and the number of signal lines between the dies is 7, the ratio of the number of signal lines to the total number of signals is 2.3.

[0053] Similarly, when the number of groups is 8, snd_chg[2:0], snd_cnt[2:0], and snd_num[2:0] are 3 bits long. Therefore, the number of signal lines between dies is 32 + 3 + 1 = 36. If the number of signals in a group is 32, the number of groups is 8, the total number of signals contained in these groups is 256, and the number of signal lines between dies is 36, the ratio of the number of signal lines to the total number of signals is 12.0.

[0054] When the number of groups is 16, snd_chg[3:0], snd_cnt[3:0], and snd_num[3:0] are 4 bits long. Therefore, the number of signal lines between dies is 64 + 4 + 1 = 69. If the number of signals in a group is 64, the number of groups is 16, the total number of signals contained in these groups is 1024, and the number of signal lines between dies is 69, the ratio of the number of signal lines to the total number of signals is 21.0.

[0055] This disclosure describes an example in which 16 signal lines are reduced to 7 signal lines to transmit signals, but it is possible to reduce 1024 signal lines to 69 signal lines to transmit signals using a method similar to that described in this disclosure.

[0056] As described above, the multi-die integrated circuit 100, 100A transmits all signals in a group including signals whose values ​​have changed, and does not transmit signals whose values ​​have not changed. As a result, the level shifter 42 reduces the voltage change of signals by the amount that the signals whose values ​​have not changed are not transmitted, thereby reducing the power consumption of the multi-die integrated circuit 100, 100A.

[0057] In this disclosure, a configuration example has been described in which a signal transmitted from the signal transmitting unit 41 of the first die 101, 101A is received by the second die 102, 102A, but the configuration of the present disclosure is not limited to this. The first die 101, 101A may be provided with the functions of the second die 102, 102A, and the second die 102, 102A may be provided with the functions of the first die 101, 101A. In this case, the signal transmitted from the signal transmitting unit of the second die 102, 102A is received by the first die 101, 101A. In other words, the signal transmission direction may be bidirectional.

[0058] In addition, the following supplementary notes are provided in relation to the above description.

[0059] (Appendix 1) A first die; a second die connected to the first die via a plurality of signal lines; a signal transmitting unit provided in the first die, the signal transmitting unit transmitting a plurality of signals generated in the first die to the second die via the plurality of signal lines; Equipped with The signal transmission unit Detecting whether or not a value of any of the signals included in any of a plurality of groups, each of which includes one or more of the signals, has changed; When the value of any of the signals changes, all signals in the group including the signal whose value has changed are sent to the second die and stored in a register; If the value of any of the signals does not change, then the signal is not sent to the second die. Multi-die integrated circuit.

[0060] (Appendix 2) The signal transmission unit 2. The multi-die integrated circuit of claim 1, wherein, if there are two or more groups among the plurality of groups in which the values ​​of any of the signals change simultaneously, a specific group is selected from these groups, and all signals in the selected group are sent to the second die and stored in the register.

[0061] (Appendix 3) The signal transmission unit If the value of the signal held in the register matches the value of the signal to be transmitted, it is determined that the value of any one of the signals has not changed; 3. The multi-die integrated circuit of claim 1, wherein if the value of the signal held in the register does not match the value of the signal to be transmitted, it is determined that the value of one of the signals has changed.

[0062] (Appendix 4) a first register provided on the first die for holding a diagnostic signal; a second register provided in the second die and configured to hold the diagnostic signal transmitted from the first die to the second die by the signal transmitting unit; a diagnostic unit that diagnoses whether the signal transmission unit is transmitting a signal normally by determining whether the diagnostic signals stored in the first register and the second register match each other; 4. The multi-die integrated circuit of any one of claims 1 to 3, comprising:

[0063] (Appendix 5) the diagnostic unit writes the diagnostic signal to the first register, and then writes a specific signal, the value of which is different from the value of the diagnostic signal, to the first register; 5. The multi-die integrated circuit of claim 4, wherein the signal transmitting unit reads the specific signal from the first register and transmits it to the second die, thereby updating the value of the signal held in the second register to the value of the specific signal.

[0064] (Appendix 6) 6. The multi-die integrated circuit of claim 1, further comprising a transmission priority control unit that determines a specific priority order for transmitting signals included in each of the plurality of groups when there are two or more groups in which the values ​​of any of the signals have changed simultaneously among the plurality of groups. [Explanation of symbols]

[0065] 1 Transmission priority control section 2. Signal change detection section 3 Counter 4 Selection signal output section 5 Selection signal output section 10 CPU 11 ROM 12 RAM 13 Signal Section 14 Internal Bus 21 Peripheral circuits 22 Signal Section 23 Internal Bus 41 Signal transmitter 42 Level Shifter 52 Signal receiving unit 60 Diagnostic Department 100 Multi-Die Integrated Circuits 100A Multi-Die Integrated Circuit 101 First Die 101A First Die 102 Second Die 102A Second Die BUS R_0, R_1, R_2, R_3, R_a, R_b registers SFR1 First register SFR2 Second Register SW signal line S_0, S_1, S_2, S_3, S_n selectors

Claims

1. a first die; a second die connected to the first die via a plurality of signal lines; a signal transmitting unit provided in the first die and configured to transmit a plurality of signals generated in the first die to the second die via the plurality of signal lines; Equipped with The signal transmission unit Detecting whether or not a value of any of the signals included in any of a plurality of groups, each of which includes one or more of the signals, has changed; When the value of any of the signals changes, all signals in the group including the signal whose value has changed are sent to the second die and stored in a register; If the value of any of the signals does not change, the signal is not sent to the second die. Multi-die integrated circuit.

2. The signal transmission unit 2. The multi-die integrated circuit according to claim 1, wherein, when there are two or more groups among the plurality of groups in which the values ​​of any of the signals change simultaneously, a specific group is selected from these groups, and all signals in the selected group are transmitted to the second die and held in the register.

3. The signal transmission unit If the value of the signal held in the register matches the value of the signal to be transmitted, it is determined that the value of any one of the signals has not changed; The multi-die integrated circuit according to claim 1 , wherein when the value of the signal held in the register does not match the value of the signal to be transmitted, it is determined that the value of one of the signals has changed.

4. a first register provided on the first die for holding a diagnostic signal; a second register provided in the second die and configured to hold the diagnostic signal transmitted from the first die to the second die by the signal transmitting unit; a diagnostic unit that diagnoses whether the signal transmission unit is transmitting a signal normally by determining whether the diagnostic signals stored in the first register and the second register match each other; The multi-die integrated circuit of claim 1 , comprising:

5. the diagnostic unit writes the diagnostic signal to the first register, and then writes a specific signal, the value of which is different from the value of the diagnostic signal, to the first register; 5. The multi-die integrated circuit of claim 4, wherein the signal transmitting unit reads the specific signal from the first register and transmits it to the second die, thereby updating a value of the signal held in the second register to the value of the specific signal.

6. 2. The multi-die integrated circuit according to claim 1, further comprising: a transmission priority control unit that determines a specific priority order for transmitting signals included in each of the plurality of groups in a case where two or more groups have simultaneously changed values ​​of any of the signals among the plurality of groups.

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