Semiconductor device and method of manufacturing the same

Abstract

To improve the performance of a semiconductor device.SOLUTION: The substrate SUB has a p type substrate body SB, a p type semiconductor layer EP2 formed on the p type substrate body SB, an n type buried layer BL formed on the p type semiconductor layer EP2, and a p type semiconductor layer EP1 formed on the n type buried layer BL. The DTI region 3 penetrates the insulating film IL, the p type semiconductor layer EP1, and the n type buried layer BL, and reaches the p type semiconductor layer EP2. The plug PG1 penetrates the insulating film IL and the p type semiconductor layer EP1, and reaches the n type buried layer BL. The insulating film ZF is interposed between the side surface of the plug side PG1 and the substrate SUB. The bottom surface of the plug side PG1 is shallower than the bottom surface of the n-type buried layer BL. The plug PG1 is electrically coupled to the n-type buried layer BL.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a semiconductor device having a transistor as a power switching element and a manufacturing method thereof. [Background technology]

[0002] Power switching elements such as LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors) are used in power conversion circuits such as inverter circuits. The power switching elements are formed on a semiconductor substrate. In some cases, transistors constituting other circuits are also formed on the same semiconductor substrate on which the power switching elements are formed.

[0003] Patent Document 1 (JP 2018-88436 A) discloses a technique for forming a plug PSUB in a deep trench DT2 that penetrates an n-type buried layer NBL and reaches a p-type epitaxial layer PEP1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-88436 Summary of the Invention [Problem to be solved by the invention]

[0005] It is desirable to improve the performance of semiconductor devices having power switching elements.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a semiconductor device includes a semiconductor substrate, a transistor formed on a major surface of the semiconductor substrate, a first insulating film formed on the major surface of the semiconductor substrate, a DTI region, and a first contact plug. The semiconductor substrate has a substrate region of a first conductivity type, a buried layer of a second conductivity type formed on the substrate region, and a semiconductor layer of the first conductivity type formed on the buried layer. The DTI region penetrates the first insulating film, the semiconductor layer, and the buried layer and reaches the substrate region. The first contact plug penetrates the first insulating film and the semiconductor layer and reaches the buried layer to be electrically connected. A second insulating film is interposed between a side surface of the first contact plug and the semiconductor substrate. [Effects of the Invention]

[0008] According to one embodiment, the performance of the semiconductor device can be improved. Alternatively, the semiconductor device can be downsized. Alternatively, the performance of the semiconductor device can be improved and the semiconductor device can be downsized. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 3] 2 is a cross-sectional view of a main part of the semiconductor device in the manufacturing process of the first embodiment. FIG. [Figure 4] 4 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 3. [Figure 5] 5 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 4. [Figure 6] 6 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 5. [Figure 7] 7 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 7. [Figure 9]9 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 9. [Figure 11] 11 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 16. [Figure 18] FIG. 2 is a circuit diagram showing an inverter circuit. [Figure 19] FIG. 2 is a circuit diagram showing an inverter circuit. [Figure 20] FIG. 2 is a circuit diagram showing an inverter circuit. [Figure 21] FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a study example. [Figure 22] 10 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment during a manufacturing process. FIG. [Figure 23] 23 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 23. [Figure 25] FIG. 25 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 24. [Figure 26] FIG. 11 is a plan view of a main part of a semiconductor device according to a third embodiment. [Figure 27] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment. [Figure 28] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 29] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0012] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0013] Furthermore, the plan view corresponds to the view from a plane substantially parallel to the main surface or rear surface of the semiconductor substrate SUB. The bottom surface and lower surface have the same meaning.

[0014] In this application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) includes not only MOSFETs that use an oxide film as a gate insulating film, but also MOSFETs that use an insulating film other than an oxide film as a gate insulating film. LDMOSFETs are also sometimes called HV-MOSFETs (High Voltage Metal Oxide Semiconductor Field Effect Transistors) or DEMOSFETs (Drain Extended Metal Oxide Semiconductor Field Effect Transistors).

[0015] An n-channel MOSFET can be considered an n-type MOSFET, and a p-channel MOSFET can be considered a p-type MOSFET. In this case, n-type means that the conductivity type of the channel when on is n-type, and p-type means that the conductivity type of the channel when on is p-type.

[0016] (Embodiment 1) <About the structure of semiconductor devices> The semiconductor device of the first embodiment will be described with reference to the drawings.

[0017] The semiconductor device of the first embodiment has a power switching element used in a power conversion circuit such as an inverter circuit, and here has an LDMOSFET as a transistor constituting the power switching element.

[0018] As shown in FIG. 1, the semiconductor device of the first embodiment includes a semiconductor substrate SUB, an STI region 2, a DTI region 3, a conductive plug (contact plug) PG1, a conductive plug (contact plug) PG2, an LDMOSFET 1 formed on the main surface of the semiconductor substrate SUB, and an insulating film IL formed on the main surface of the semiconductor substrate SUB.

[0019] As shown in FIG. 1, the semiconductor substrate SUB has a p-type substrate body SB that reaches the back surface of the semiconductor substrate SUB, a p-type semiconductor layer EP2 formed on the p-type substrate body SB, an n-type buried layer BL formed on the p-type semiconductor layer EP2, and a p-type semiconductor layer EP1 formed on the n-type buried layer BL.

[0020] The p-type substrate body SB is made of p-type single crystal silicon or the like doped with p-type impurities such as boron (B). The thickness of the p-type substrate body SB is approximately uniform. The p-type semiconductor layer EP2 is made of p-type single crystal silicon or the like formed on the p-type substrate body SB. The n-type buried layer BL is an n-type semiconductor layer and is made of n-type single crystal silicon or the like. The p-type semiconductor layer EP1 is made of p-type single crystal silicon or the like formed on the n-type buried layer BL. The p-type impurity concentration of the p-type substrate body SB is higher than the p-type impurity concentrations of the p-type semiconductor layers EP1 and EP2.

[0021] The p-type semiconductor layer EP2 and the p-type substrate body SB are in contact with each other, and therefore the entire combination of the p-type semiconductor layer EP2 and the p-type substrate body SB can be considered as a p-type substrate region.

[0022] There may be a case where the p-type semiconductor layer EP2 is not formed on the p-type substrate body SB. In that case, the n-type buried layer BL and the p-type substrate body SB are in contact with each other. In that case, the p-type semiconductor layer EP2 in FIG. 1 is composed of a part of the p-type substrate body SB.

[0023] The main surface of the semiconductor substrate SUB is synonymous with the main surface of the semiconductor layer EP1. The back surface of the semiconductor substrate SUB is synonymous with the back surface of the p-type substrate body SB. The main surface and the back surface of the semiconductor substrate SUB are located on opposite sides of each other.

[0024] The STI (Shallow Trench Isolation) region 2 is made of an insulating film buried in a trench formed in the semiconductor substrate SUB. The DTI (Deep Trench Isolation) region 3 is made of an insulating film buried in a trench formed continuously in the insulating film IL, the STI region 2, and the semiconductor substrate SUB. Both the STI region 2 and the DTI region 3 can be considered as insulating regions.

[0025] The depth of the DTI region 3 is greater than the depth of the STI region 2. That is, the bottom surface of the DTI region 3 is deeper than the bottom surface of the STI region 2.

[0026] The DTI region 3 penetrates the insulating film IL, the STI region 2, the p-type semiconductor layer EP1, and the n-type buried layer BL, and reaches the p-type semiconductor layer EP2. The side surfaces of the DTI region 3 contact the insulating film IL, the STI region 2, the p-type semiconductor layer EP1, the n-type buried layer BL, and the p-type semiconductor layer EP2, and the bottom surface of the DTI region 3 contacts the p-type semiconductor layer EP2. The bottom surface of the DTI region 3 is deeper than the bottom surface of the n-type buried layer BL and is located midway through the thickness of the p-type semiconductor layer EP2. The bottom surface of the STI region 2 is shallower than the top surface of the n-type buried layer BL and is located midway through the thickness of the semiconductor layer EP1.

[0027] Each of the plugs PG1 and PG2 is made of a conductive film (metal film) embedded in a trench formed successively in the insulating film IL, the STI region 2, and the semiconductor substrate SUB. Each of the plugs PG1 and PG2 is made of a metal material. The depth of the plug PG1 is smaller than the depth of the plug PG2. That is, the bottom surface of the plug PG1 is shallower than the bottom surface of the plug PG2. The depth of the plug PG1 is smaller than the depth of the DTI region 3. That is, the bottom surface of the plug PG1 is shallower than the bottom surface of the DTI region 3. The depth of the plug PG2 is approximately the same as the depth of the DTI region 3. That is, the depth of the bottom surface of the plug PG2 is approximately the same as the depth of the bottom surface of the DTI region 3.

[0028] The plug PG1 penetrates the insulating film IL, the STI region 2, and the p-type semiconductor layer EP1 to reach the n-type buried layer BL. The plug PG1 does not penetrate the n-type buried layer BL. The bottom surface of the plug PG1 is deeper than the top surface of the n-type buried layer BL and shallower than the bottom surface of the n-type buried layer BL, and is located midway through the thickness of the n-type buried layer BL. The entire side surface of the plug PG1 is covered with the insulating film ZF. Therefore, the side surface of the plug PG1 is not in contact with the semiconductor substrate SUB, and the insulating film ZF is interposed between the side surface of the plug PG1 and the p-type semiconductor layer EP1, and between the side surface of the plug PG1 and the n-type buried layer BL. The bottom surface of the plug PG1 is in contact with the n-type buried layer BL, and the plug PG1 is electrically connected to the n-type buried layer BL.

[0029] In the first embodiment, a silicon film pattern (conductive film pattern) SP is formed on the STI region 2. The silicon film pattern SP surrounds the plug PG1 in a plan view. The silicon film pattern SP is covered with an insulating film IL. The plug PG1 penetrates the silicon film pattern SP. Since an insulating film ZF is interposed between the side surface of the plug PG1 and the silicon film pattern SP, the plug PG1 does not contact the silicon film pattern SP. Although the silicon film pattern SP is not essential, when the manufacturing processes of FIGS. 3 to 17 described later are applied, the silicon film pattern SP is formed. When the manufacturing processes of FIGS. 22 to 25 described later are applied, the silicon film pattern SP is not formed.

[0030] The plug PG2 penetrates the insulating film IL, the STI region 2, the p-type semiconductor layer EP1, and the n-type buried layer BL to reach the p-type semiconductor layer EP2. The bottom surface of the plug PG2 is deeper than the bottom surface of the n-type buried layer BL and is located midway through the thickness of the p-type semiconductor layer EP2. The entire side surface of the plug PG2 is covered with the insulating film ZF. Therefore, the side surface of the plug PG2 is not in contact with the semiconductor substrate SUB, and the insulating film ZF is interposed between the side surface of the plug PG2 and the p-type semiconductor layer EP1, between the side surface of the plug PG2 and the n-type buried layer BL, and between the side surface of the plug PG2 and the p-type semiconductor layer EP2. The bottom surface of the plug PG2 is in contact with the p-type semiconductor layer EP2, and the plug PG2 is electrically connected to the p-type semiconductor layer EP2.

[0031] The LDMOSFET 1 is an n-type (n-channel) LDMOSFET.

[0032] The LDMOSFET 1 has a p-type well region PB, an n-type drift region ND, an n-type drain region DR, an n-type source region SR, a p-type semiconductor region PR, a gate insulating film GF, and a gate electrode GE.

[0033] The p-type well region PB, n-type drift region ND, n-type drain region DR, n-type source region SR, and p-type semiconductor region PR are formed in the p-type semiconductor layer EP1. The gate electrode GE is formed on the p-type semiconductor layer EP1 via a gate insulating film GF. The insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the LDMOSFET1.

[0034] A p-type well region (p-type semiconductor region) PB and an n-type drift region (n-type semiconductor region) ND are formed in the upper part of the p-type semiconductor layer EP1. A part of the p-type semiconductor layer EP1 exists below the bottom surfaces of the n-type drift region ND and the p-type well region PB. The n-type drift region ND and the p-type well region PB are adjacent to each other in the gate length direction of the LDMOSFET1. The gate length direction of the LDMOSFET1 corresponds to the gate length direction of the gate electrode GE, and the gate width direction of the LDMOSFET1 corresponds to the gate width direction of the gate electrode GE.

[0035] The p-type well region PB surrounds the n-type source region SR and the p-type semiconductor region PR. The p-type well region PB can function as a back gate. The p-type well region PB can also function as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET 1. The channel of the LDMOSFET 1 is formed in the upper part of the p-type well region PB, which is located between the n-type source region SR and the n-type drain region DR and below the gate electrode GE. Hereinafter, the region where the channel of the LDMOSFET 1 is formed will be referred to as the channel formation region.

[0036] An n-type source region (n-type semiconductor region) SR and a p-type semiconductor region PR are formed in the p-type well region PB. The n-type source region SR is adjacent to the channel formation region of the LDMOSFET 1. The p-type impurity concentration of the p-type semiconductor region PR is higher than the p-type impurity concentration of the p-type well region PB.

[0037] 1, the p-type semiconductor region PR and the n-type source region SR are adjacent to each other in the gate length direction of the LDMOSFET 1. In this case, the n-type source region SR is arranged between the gate electrode GE and the p-type semiconductor region PR in a plan view. In some cases, the p-type semiconductor regions PR and the n-type source regions SR are arranged alternately in the gate width direction of the LDMOSFET 1.

[0038] The bottom surfaces of the p-type semiconductor region PR and the n-type source region SR are in contact with the p-type well region PB. The top surfaces of the p-type semiconductor region PR and the n-type source region SR reach the main surface of the semiconductor substrate SUB. The p-type semiconductor region PR can function as a contact portion for the p-type well region PB.

[0039] An n-type drain region (n-type semiconductor region) DR is formed in the n-type drift region ND. The upper surface of the n-type drain region DR reaches the main surface of the semiconductor substrate SUB. The n-type impurity concentration of the n-type drain region DR is higher than the n-type impurity concentration of the n-type drift region ND. The n-type drain region DR and the n-type source region SR are spaced apart from each other in the gate length direction of the LDMOSFET1.

[0040] The gate electrode GE is formed on the main surface of the semiconductor substrate SUB between the n-type source region SR and the n-type drain region DR via a gate insulating film GF. The gate insulating film GF is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a single film of polycrystalline silicon film (doped polysilicon film) or a laminated film of a polycrystalline silicon film and a metal silicide layer.

[0041] In a plan view, an STI region 2 is disposed between the channel formation region and n-type drain region DR of the LDMOSFET 1, and a portion of the gate electrode GE is located on the STI region 2. An n-type drift region ND is present below the STI region 2 interposed between the channel formation region and n-type drain region DR of the LDMOSFET 1. The bottom surface of the n-type drain region DR is in contact with the n-type drift region ND, and the side surface of the n-type drain region DR is in contact with the STI region 2. Therefore, the n-type drift region ND below the STI region 2 can also function as a conduction path between the channel of the LDMOSFET 1 and the n-type drain region DR.

[0042] 1 shows a case where a gate insulating film GF is interposed between the STI region 2 and the gate electrode GE, but there may be a case where the gate insulating film GF is not interposed between the STI region 2 and the gate electrode GE. Also, a sidewall spacer (not shown) made of an insulating film may be formed on the side surface of the gate electrode GE.

[0043] A part of the p-type well region PB is located below the gate electrode GE, and a part of the n-type drift region ND is located below the gate electrode GE. A PN junction is formed at the boundary between the p-type well region PB and the n-type drift region ND. The boundary between the p-type well region PB and the n-type drift region ND is located below the gate electrode GE and extends in the gate width direction of the LDMOSFET1.

[0044] In plan view, the gate electrode GE is disposed between the n-type source region SR and the n-type drain region DR. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, a channel is formed in the upper part of the p-type well region PB located below the gate electrode GE. The n-type source region SR and the n-type drain region DR are electrically connected to each other through the channel and the n-type drift region ND.

[0045] In the gate length direction of the LDMOSFET 1, an n-type drift region ND is interposed between the p-type well region PB and the n-type drain region DR. Therefore, the n-type drift region ND exists between the channel formation region and the n-type drain region DR of the LDMOSFET 1. Therefore, in the gate length direction of the LDMOSFET 1, the channel formation region and the n-type drift region ND exist between the n-type source region SR and the n-type drain region DR, and the channel formation region is located between the n-type source region SR and the n-type drift region ND.

[0046] A p-type resurf region (not shown) may be formed in the p-type semiconductor layer EP1 below the n-type drift region ND and the p-type well region PB. A p-type buried region (not shown) may be formed in the p-type semiconductor layer EP1 below the p-type resurf region.

[0047] Furthermore, a metal silicide layer (not shown) may be formed on each of the n-type drain region DR, the n-type source region SR, and the p-type semiconductor region PR. This metal silicide layer can be formed by using a salicide (Self Aligned Silicide) technique.

[0048] Next, the structure on the semiconductor substrate SUB will be described.

[0049] As shown in FIG. 1, the semiconductor device of the first embodiment further includes a plug (contact plug) PGD, a plug (contact plug) PGP, a plug (contact plug) PGS, a wire M1D, a wire M1N, a wire M1P, and a wire M1S.

[0050] The insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the gate electrode GE. The insulating film IL includes, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film. The upper surface of the insulating film IL is planarized.

[0051] A plurality of contact holes (through holes) are formed in the insulating film IL, and a plurality of conductive plugs are formed in the contact holes. The plurality of plugs include a plug PGD, a plug PGS, and a plug PGP. The plugs PGD, the plug PGP, and the plug PGS each penetrate the insulating film IL.

[0052] The plug PGD is disposed on the n-type drain region DR and is electrically connected to the n-type drain region DR. The plug PGS is disposed on the n-type source region SR and is electrically connected to the n-type source region SR. The plug PGP is disposed on the p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR. Therefore, the plug PGP is electrically connected to the p-type well region PB via the p-type semiconductor region PR.

[0053] A plug is also disposed on the gate electrode GE, but the plug on the gate electrode GE is not shown in the cross-sectional view of FIG.

[0054] When a metal silicide layer (not shown) is formed on the n-type drain region DR, the n-type source region SR, and the p-type semiconductor region PR, each plug contacts the metal silicide layer and is electrically connected to each region below the metal silicide layer via the metal silicide layer.

[0055] A plurality of wirings are formed on the insulating film IL, including a wiring M1S, a wiring M1D, a wiring M1N, and a wiring M1P.

[0056] The wiring M1D is electrically connected to the n-type drain region DR via a plug PGD, and a drain potential is supplied from the wiring M1D to the n-type drain region DR via the plug PGD.

[0057] The wiring M1S is electrically connected to the n-type source region SR via the plug PGS, and is also electrically connected to the p-type semiconductor region PR via the plug PGP. That is, the wiring M1S is electrically connected to both the plug PGS arranged on the n-type source region SR and the plug PGP arranged on the p-type semiconductor region PR.

[0058] Therefore, the potential (source potential) supplied from the plug PGS to the n-type source region SR and the potential supplied from the plug PGP to the p-type semiconductor region PR are the same. Therefore, the source potential is supplied from the plug PGS to the n-type source region SR, and is also supplied from the plug PGP to the p-type well region PB via the p-type semiconductor region PR.

[0059] A gate wiring electrically connected to the gate electrode GE via a plug is formed on the insulating film IL, but the gate wiring is not shown in FIG.

[0060] The wiring M1N is electrically connected to the n-type buried layer BL via the plug PG1, and a predetermined potential is supplied from the wiring M1N to the n-type buried layer BL via the plug PG1.

[0061] The wiring M1P is electrically connected to the p-type semiconductor layer EP2 via the plug PG2. A predetermined potential is supplied from the wiring M1P to the p-type semiconductor layer EP2 via the plug PG2, and the potential is further supplied from the p-type semiconductor layer EP2 to the p-type substrate body SB.

[0062] The wiring M1S, wiring M1D, wiring M1N, wiring M1P and gate wiring are not connected to each other and are separated from each other.

[0063] The illustration and description of the structure above the insulating film IL, the wiring M1D, the wiring M1N, the wiring M1P, and the wiring M1S will be omitted.

[0064] The LDMOSFET 1 may have a configuration in which a plurality of unit LDMOSFETs are connected in parallel. In the case of Fig. 1, the LDMOSFET 1 has a configuration in which two unit LDMOSFETs that share an n-type drain region DR are connected in parallel. The number of unit LDMOSFETs connected in parallel can be set as needed.

[0065] 2 shows an example of a planar layout of the LDMOSFET formation region 1a, the plugs PG1 and PG2, and the DTI region 3. The LDMOSFET formation region 1a corresponds to the planar region in which the LDMOSFET 1 is formed.

[0066] 2, in a plan view, the DTI region 3 surrounds the LDMOSFET formation region 1a (LDMOSFET1). That is, in a plan view, the DTI region 3 surrounds the gate electrode GE, the n-type source region SR, and the n-type drain region DR. This allows the DTI region 3 to electrically isolate the p-type semiconductor layer EP1 in which the LDMOSFET1 is formed from the surrounding p-type semiconductor layers EP1.

[0067] In the case of FIG. 2, in plan view, the plug PG1 surrounds the LDMOSFET formation region 1a, the plug PG2 surrounds the LDMOSFET formation region 1a and the plug PG1, and the DTI region 3 surrounds the LDMOSFET formation region 1a, the plug PG1 and the plug PG2.

[0068] <About the manufacturing method of semiconductor devices> As shown in Figure 3, a semiconductor substrate SUB is prepared, which includes a p-type substrate body SB, a p-type semiconductor layer EP2 on the p-type substrate body SB, an n-type buried layer BL on the p-type semiconductor layer EP2, and a p-type semiconductor layer EP1 on the n-type buried layer BL. The thickness of the p-type semiconductor layer EP1 is, for example, about 4 micrometers or more and 5 micrometers or less. The thickness of the n-type buried layer BL is, for example, about 4 micrometers or more and 6 micrometers or less. The thickness of the p-type semiconductor layer EP2 is, for example, about 9 micrometers or more and 12 micrometers or less.

[0069] For example, an n-type buried layer BL can be formed by ion implantation in a surface layer portion of an epitaxial substrate consisting of a p-type semiconductor substrate and a p-type epitaxial semiconductor layer formed on the p-type semiconductor substrate, and then a p-type semiconductor layer EP1 can be formed on the n-type buried layer BL by epitaxial growth. In this case, the p-type epitaxial semiconductor layer below the n-type buried layer BL corresponds to the p-type semiconductor layer EP2, and the p-type semiconductor substrate corresponds to the p-type substrate body SB.

[0070] Alternatively, the n-type buried layer BL may be formed in the surface layer portion of the p-type silicon substrate by ion implantation, and then the p-type semiconductor layer EP1 may be formed on the n-type buried layer BL by epitaxial growth. In this case, the p-type semiconductor layer EP2 is not formed, and the p-type semiconductor layer EP2 in FIG. 3 is composed of a part of the p-type substrate body SB.

[0071] In either case, the entire region below the n-type buried layer BL in the semiconductor substrate SUB has p-type conductivity. The entire p-type region below the n-type buried layer BL in the semiconductor substrate SUB can be considered as a p-type substrate region.

[0072] 4, an n-type drift region ND and a p-type well region PB are formed in the p-type semiconductor layer EP1 by ion implantation or the like. The p-type impurity concentration of the p-type well region PB is higher than the p-type impurity concentration of the p-type semiconductor layer EP1.

[0073] The n-type drift region ND is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. The p-type well region PB is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. Either the n-type drift region ND or the p-type well region PB may be formed first.

[0074] Next, as shown in FIG. 5, an STI region 2 is formed using an STI method.

[0075] After forming a trench in the main surface of the semiconductor substrate SUB, an insulating film made of a silicon oxide film or the like is formed on the main surface of the semiconductor substrate SUB so as to fill the trench. Thereafter, the insulating film disposed outside the trench is removed using a CMP (Chemical Mechanical Polishing) method or the like. This allows the formation of an STI region 2 made of the insulating film buried in the trench.

[0076] 6, a gate electrode GE is formed on the main surface of the semiconductor substrate SUB via a gate insulating film GF. The gate electrode GE is made of, for example, a polycrystalline silicon film. The gate insulating film GF is made of, for example, a silicon oxide film.

[0077] When forming the gate electrode GE, a silicon film pattern SP is formed on the STI region 2. For example, after forming a gate insulating film GF using a thermal oxidation method, a polycrystalline silicon film (conductive film) is formed using a CVD method. Thereafter, the polycrystalline silicon film is patterned using photolithography and etching techniques to form the gate electrode GE and the silicon film pattern SP. The gate electrode GE and the silicon film pattern SP can be formed in the same process using a common film (here, a polycrystalline silicon film). In a plan view, the silicon film pattern SP is formed in a region where a plug PG1 is to be formed. In a plan view, the silicon film pattern SP is not formed in a region where a plug PG2 is to be formed and in a region where a DTI region 3 is to be formed.

[0078] Next, as shown in FIG. 7, an n-type drain region DR and an n-type source region SR are formed in the p-type semiconductor layer EP1 by using an ion implantation method or the like.

[0079] The n-type drain region DR is formed in the n-type drift region ND. The n-type source region SR is formed in the p-type well region PB. The n-type drain region DR and the n-type source region SR can be formed by the same ion implantation process to reduce the number of manufacturing processes, but they can also be formed by separate ion implantation processes.

[0080] 7, a p-type semiconductor region PR is formed in the p-type semiconductor layer EP1 by using an ion implantation method, etc. The p-type semiconductor region PR is formed in the p-type well region PB.

[0081] In the first embodiment, the p-type semiconductor region PR is formed after the n-type source region SR and the n-type drain region DR are formed, but the n-type source region SR and the n-type drain region DR can also be formed after the p-type semiconductor region PR is formed.

[0082] A metal silicide layer (not shown) may be formed on the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PR, and the gate electrode GE. The metal silicide layer is formed using a salicide (Self Aligned Silicide) technique. The metal silicide layer is not formed on the silicon film pattern SP.

[0083] 8, an insulating film IL is formed on the main surface of the semiconductor substrate SUB so as to cover the gate electrode GE and the silicon film pattern SP by using a CVD (Chemical Vapor Deposition) method or the like. After the insulating film IL is formed, the upper surface of the insulating film IL can be polished and flattened by using a CMP method or the like.

[0084] 8, a photoresist pattern RP1 is formed on the insulating film IL using photolithography. The photoresist pattern RP1 has an opening OP1 for forming the trench 4, an opening OP2 for forming the trench 5, and an opening OP3 for forming the trench 6. In a plan view, the opening OP1 overlaps with the silicon film pattern SP. In a plan view, the openings OP2 and OP3 do not overlap with the silicon film pattern SP.

[0085] 9, the photoresist pattern RP1 is used as an etching mask to selectively etch the insulating film IL and the STI region 2, thereby forming the grooves 4, 5, and 6. This etching step is referred to as the etching step of FIG.

[0086] The trench 4 is formed by etching the insulating film IL exposed from the opening OP1 of the photoresist pattern RP1. In plan view, the trench 4 is formed at a position overlapping the opening OP1 of the photoresist pattern RP1. The trench 5 is formed by etching the insulating film IL exposed from the opening OP2 of the photoresist pattern RP1, and further etching the STI region 2. In plan view, the trench 5 is formed at a position overlapping the opening OP2 of the photoresist pattern RP1. The trench 6 is formed by etching the insulating film IL exposed from the opening OP3 of the photoresist pattern RP1, and further etching the STI region 2. In plan view, the trench 6 is formed at a position overlapping the opening OP3 of the photoresist pattern RP1.

[0087] The etching step of FIG. 9 is performed under etching conditions in which the etching rates of the insulating film IL and the STI region 2 are higher than the etching rate of the semiconductor substrate SUB (p-type semiconductor layer EP1) and higher than the etching rate of the silicon film pattern SP.

[0088] 9, the semiconductor substrate SUB (p-type semiconductor layer EP1) and the silicon film pattern SP can function as an etching stopper. As a result, in the etching step of Fig. 9, the trenches 4 penetrate the insulating film IL to reach the silicon film pattern SP, but the silicon film pattern SP exposed from the trenches 4 is hardly etched. Therefore, the trenches 4 do not penetrate the silicon film pattern SP.

[0089] 9, the trenches 5 and 6 each penetrate the insulating film IL and the STI region 2 to reach the semiconductor substrate SUB (p-type semiconductor layer EP1), but the semiconductor substrate SUB (p-type semiconductor layer EP1) exposed from the trenches 5 and 6 is hardly etched. Therefore, the depth of the bottom surface of each of the trenches 5 and 6 is approximately the same as the depth of the bottom surface of the STI region 2.

[0090] 10, the photoresist pattern RP1 is used as an etching mask to selectively etch the silicon film pattern SP exposed from the groove 4 and the semiconductor substrate SUB exposed from each of the grooves 5 and 6. This etching step is referred to as the etching step of FIG.

[0091] The etching step of FIG. 10 is performed under etching conditions in which the etching rate of the silicon film pattern SP and the semiconductor substrate SUB (p-type semiconductor layer EP1, n-type buried layer BL, and p-type semiconductor layer EP2) is higher than the etching rate of the STI region 2.

[0092] 10, the STI region 2 can function as an etching stopper. As a result, in the etching step of Fig. 10, the trench 4 penetrates the silicon film pattern SP and reaches the STI region 2, but the STI region 2 exposed from the trench 4 is hardly etched. Therefore, the trench 4 does not penetrate the STI region 2.

[0093] By performing the etching step of Figure 10, the depths of groove 5 and groove 6 increase. That is, the bottom surface of groove 5 after the etching step of Figure 10 is completed is deeper than the bottom surface of groove 5 after the etching step of Figure 9 is completed. The bottom surface of groove 6 after the etching step of Figure 10 is completed is deeper than the bottom surface of groove 6 after the etching step of Figure 9 is completed. After the etching step of Figure 10 is completed, the depths of the bottom surfaces of groove 5 and groove 6 are approximately the same.

[0094] 10, the grooves 5 and 6 each penetrate the p-type semiconductor layer EP1 and the n-type buried layer BL and reach the p-type semiconductor layer EP2. In this case, at the stage after the etching step of Fig. 10 is completed, the bottom surfaces of the grooves 5 and 6 are deeper than the bottom surface of the n-type buried layer BL. At the stage after the etching step of Fig. 10 is completed, the bottom surfaces of the grooves 5 and 6 may be deeper than the top surface of the n-type buried layer BL and shallower than the bottom surface of the n-type buried layer BL, or the bottom surfaces of the grooves 5 and 6 may be shallower than the top surface of the n-type buried layer BL.

[0095] At the stage where the etching step of FIG. 10 is completed, the distance (depth) from the bottom surface of the STI region 2 to the bottom surfaces of the trenches 5 and 6 is, for example, about 10 micrometers or more and 12 micrometers or less.

[0096] 11, the photoresist pattern RP1 is used as an etching mask to selectively etch the STI region 2 exposed from the trench 4. This etching step is referred to as the etching step of FIG.

[0097] The etching step of FIG. 11 is performed under etching conditions in which the etching rate of the STI region 2 is higher than the etching rate of the semiconductor substrate SUB (p-type semiconductor layer EP1, n-type buried layer BL, and p-type semiconductor layer EP2).

[0098] 11, the semiconductor substrate SUB can function as an etching stopper. As a result, in the etching step of Fig. 11, the trench 4 penetrates the STI region 2 and reaches the semiconductor substrate SUB (p-type semiconductor layer EP1), but the semiconductor substrate SUB (p-type semiconductor layer EP1) exposed from the trench 4 is hardly etched. Therefore, the depth of the bottom surface of the trench 4 is approximately the same as the depth of the bottom surface of the STI region 2.

[0099] 11, the depths of groove 5 and groove 6 remain almost the same. That is, the depth of the bottom surface of groove 5 after the etching step of FIG. 11 is completed is almost the same as the depth of the bottom surface of groove 5 after the etching step of FIG. 10 is completed. The depth of the bottom surface of groove 6 after the etching step of FIG. 11 is completed is almost the same as the depth of the bottom surface of groove 6 after the etching step of FIG. 10 is completed.

[0100] 12, the photoresist pattern RP1 is used as an etching mask to etch the semiconductor substrate SUB exposed from the grooves 4, 5, and 6. This etching step is referred to as the etching step of FIG.

[0101] By performing the etching step of Figure 12, the depths of grooves 4, 5, and 6 increase. That is, the bottom surface of groove 4 after the etching step of Figure 12 is completed is deeper than the bottom surface of groove 4 after the etching step of Figure 11 is completed. The bottom surface of groove 5 after the etching step of Figure 12 is completed is deeper than the bottom surface of groove 5 after the etching step of Figure 11 is completed. The bottom surface of groove 6 after the etching step of Figure 12 is completed is deeper than the bottom surface of groove 6 after the etching step of Figure 11 is completed.

[0102] 11 is completed, the bottom surface of groove 4 is shallower than the bottom surface of groove 5 and also shallower than the bottom surface of groove 6. Reflecting this, at the stage at which the etching step of FIG. 12 is completed, the bottom surface of groove 4 is shallower than the bottom surface of groove 5 and also shallower than the bottom surface of groove 6. At the stage at which the etching step of FIG. 12 is completed, the depth of the bottom surface of groove 5 and the depth of the bottom surface of groove 6 are approximately the same. In the etching step of FIG. 12, the amount of etching of the semiconductor substrate SUB exposed from groove 4 is approximately the same as the amount of etching of the semiconductor substrate SUB exposed from groove 5 and also approximately the same as the amount of etching of the semiconductor substrate SUB exposed from groove 6. At the stage at which the etching step of FIG. 12 is completed, the difference between the depth of the bottom surface of groove 4 and the depth of the bottom surfaces of grooves 5 and 6 is, for example, not less than 10 micrometers and not more than 12 micrometers.

[0103] 12 is performed under etching conditions such that the trenches 4 penetrate the p-type semiconductor layer EP1 to reach the n-type buried layer BL but do not reach the p-type semiconductor layer EP2 (i.e., do not penetrate the n-type buried layer BL). Therefore, at the stage where the etching step of FIG. 12 is completed, the bottom surfaces of the trenches 4 are deeper than the top surfaces of the n-type buried layer BL and shallower than the bottom surfaces of the n-type buried layer BL.

[0104] 12, each of the grooves 5 and 6 does not reach the p-type substrate body SB. In this case, at the stage when the etching step of Fig. 12 is completed, the bottom surfaces of each of the grooves 5 and 6 are deeper than the bottom surface of the n-type buried layer BL and shallower than the bottom surface of the p-type semiconductor layer EP2. At the stage when the etching step of Fig. 12 is completed, each of the grooves 5 and 6 may reach the p-type substrate body SB.

[0105] Next, the photoresist pattern RP1 is removed by ashing or the like.

[0106] Next, as shown in FIG. 13, the DTI region 3, the dummy DTI region 3a, and the dummy DTI region 3b are formed.

[0107] For example, an insulating film ZF made of a silicon oxide film or the like is formed on the insulating film IL by a CVD method or the like so as to fill the trenches 4, 5, and 6, and then the insulating film ZF arranged outside the trenches 4, 5, and 6 is removed by a CMP method or the like. The insulating film ZF inside the trenches 4, 5, and 6 remains without being removed. This makes it possible to form a DTI region 3 made of the insulating film ZF buried in the trench 6, a dummy DTI region 3a made of the insulating film ZF buried in the trench 4, and a dummy DTI region 3b made of the insulating film ZF buried in the trench 5. A void may be formed in each of the dummy DTI region 3a, the dummy DTI region 3b, and the DTI region 3.

[0108] 14, a photoresist pattern RP2 is formed on the insulating film IL using photolithography. A portion of the dummy DTI region 3a and a portion of the dummy DTI region 3b are exposed from the photoresist pattern RP2, and the entire top surface of the DTI region 3 is covered with the photoresist pattern RP2.

[0109] Next, as shown in Figure 15, the insulating film IL, the dummy DTI region 3a, and the dummy DTI region 3b are etched using the photoresist pattern RP2 formed on the insulating film IL as an etching mask, thereby forming contact holes CTD, CTP, CTS, trenches 4a, and trenches 5a. This etching step is referred to as the etching step of Figure 15. In the etching step of Figure 15, the DTI region 3 is not etched because it is covered with the photoresist pattern RP2.

[0110] 15 is performed under etching conditions in which the etching rate of each of the insulating film IL and the insulating film ZF is higher than the etching rate of the semiconductor substrate SUB (p-type semiconductor layer EP1, n-type buried layer BL, and p-type semiconductor layer EP2). Therefore, in the etching step of FIG. 15, the semiconductor substrate SUB can function as an etching stopper.

[0111] The trench 4a is formed in the trench 4 by etching a part of the dummy DTI region 3a (the insulating film ZF in the trench 4). The trench 4a penetrates the dummy DTI region 3a and reaches the n-type buried layer BL, but the n-type buried layer BL exposed from the trench 4a is hardly etched. Therefore, the depth of the bottom surface of the trench 4a is approximately the same as the depth of the bottom surface of the trench 4. In a plan view, the trench 4a is contained within the trench 4, and the planar dimensions (planar area) of the trench 4a are smaller than the planar dimensions (planar area) of the trench 4. The side surface of the trench 4a is formed by the insulating film ZF, and the bottom surface of the trench 4a is formed by the n-type buried layer BL. In other words, the insulating film ZF remains on the side surface of the trench 4, and the surface of the remaining insulating film ZF forms the side surface of the trench 4a. Therefore, the n-type buried layer BL is exposed from the bottom surface of the trench 4a, and the semiconductor substrate SUB (n-type buried layer BL, p-type semiconductor layer EP1) is not exposed from the side surface of the trench 4a. An insulating film ZF is interposed between the side surface of the trench 4a and the side surface of the trench 4.

[0112] The trenches 5a are formed in the trenches 5 by etching a portion of the dummy DTI regions 3b (the insulating film ZF in the trenches 5). The trenches 5a penetrate the dummy DTI regions 3b to reach the p-type semiconductor layer EP2, but the p-type semiconductor layer EP2 exposed from the trenches 5a is hardly etched. Therefore, the depth of the bottom surface of the trenches 5a is approximately the same as the depth of the bottom surface of the trenches 5. In a plan view, the trenches 5a are contained within the trenches 5, and the planar dimensions (planar area) of the trenches 5a are smaller than the planar dimensions (planar area) of the trenches 5. The side surfaces of the trenches 5a are formed by the insulating film ZF, and the bottom surfaces of the trenches 5a are formed by the p-type semiconductor layer EP2. In other words, the insulating film ZF remains on the side surfaces of the trenches 5, and the surfaces of the remaining insulating film ZF form the side surfaces of the trenches 5a. Therefore, the p-type semiconductor layer EP2 is exposed from the bottom surface of the trench 5a, and the semiconductor substrate SUB (the p-type semiconductor layer EP2, the n-type buried layer BL, and the p-type semiconductor layer EP1) is not exposed from the side surface of the trench 5a. An insulating film ZF is interposed between the side surface of the trench 5a and the side surface of the trench 5.

[0113] The contact holes CTD, CTP, and CTS are formed by etching the insulating film IL so as to penetrate the insulating film IL. The contact holes CTD are formed on the n-type drain region DR, the contact holes CTP are formed on the p-type semiconductor region PR, and the contact holes CTS are formed on the n-type source region SR.

[0114] Next, the photoresist pattern RP2 is removed by ashing or the like.

[0115] 16, plugs PG1, PG2, PGD, PGP, and PGS are formed. The plug PG1 is formed in the trench 4a, the plug PG2 is formed in the trench 5a, the plug PGD is formed in the contact hole CTD, the plug PGP is formed in the contact hole CTP, and the plug PGS is formed in the contact hole CTS.

[0116] For example, a barrier conductor film is formed on the bottom surfaces of the contact holes CTD, CTP, CTS, trenches 4a, and 5a, on the side surfaces of the contact holes CTD, CTP, CTS, trenches 4a, and 5a, and on the upper surface of the insulating film IL. Then, a main conductor film (metal film) made of tungsten or the like is formed on the barrier conductor film so as to fill the contact holes CTD, CTP, CTS, trenches 4a, and 5a. Then, the main conductor film and barrier conductor film disposed outside the contact holes CTD, CTP, CTS, trenches 4a, and 5a are removed by CMP or the like. This allows the formation of plugs PG1, PG2, PGD, PGP, and PGS.

[0117] The side surface of the plug PG1 formed in the trench 4a is covered with the insulating film ZF and therefore does not contact the semiconductor substrate SUB. The bottom surface of the plug PG1 is in contact with the n-type buried layer BL and therefore the plug PG1 is electrically connected to the n-type buried layer BL. The side surface of the plug PG2 formed in the trench 5a is covered with the insulating film ZF and therefore does not contact the semiconductor substrate SUB. The bottom surface of the plug PG2 is in contact with the p-type semiconductor layer EP2 and therefore the plug PG2 is electrically connected to the p-type semiconductor layer EP2.

[0118] In the first embodiment, the trenches 4a, 5a, contact holes CTD, CTP, and contact holes CTS are formed in a common etching process. Furthermore, plugs PG1, PG2, PGD, PGP, and PGS are formed in the same process. This reduces the number of manufacturing processes for the semiconductor device. As a modified example, the etching process for forming contact holes CTD, CTP, and CTS can be performed after the etching process for forming trenches 4a and 5a. Alternatively, the etching process for forming trenches 4a and 5a can be performed after the etching process for forming contact holes CTD, CTP, and CTS.

[0119] Next, as shown in FIG. 17, wirings M1D, M1N, M1P, and M1S are formed on the insulating film IL. For example, after forming a conductive film (metal film) on the insulating film IL, the conductive film can be patterned using photolithography and etching techniques to form the wirings M1D, M1N, M1P, and M1S. Although aluminum wiring is suitable for the wirings M1D, M1N, M1P, and M1S, wirings using other metal materials, such as tungsten wiring, can also be used. Furthermore, copper wiring formed using damascene technology can also be used for the wirings M1D, M1N, M1P, and M1S.

[0120] Further, illustration and description of the process of forming the upper insulating film and wiring will be omitted.

[0121] <About the process of the review> FIG. 18 is a circuit diagram showing an inverter circuit INV as an example of a power conversion circuit.

[0122] The inverter circuit INV shown in FIG. 18 has a power transistor TR1 and a power transistor TR2 connected in series. Each of the power transistor TR1 and the power transistor TR2 is a power switching element. The power transistor TR1 is used as a high-side switch (high potential side switch), and the power transistor TR2 is used as a low-side switch (low potential side switch). An LDMOSFET1 can be used as the power transistor TR1 or the power transistor TR2.

[0123] The power transistor TR1 and the power transistor TR2 are connected in series between the terminal T1 and the terminal T2. The drain D1 of the power transistor TR1 is connected to the terminal T1. The source S1 of the power transistor TR1 is connected to the drain D2 of the power transistor TR2. The source S2 of the power transistor TR2 is connected to the terminal T2. The terminal T3 is electrically connected to both the source S1 of the power transistor TR1 and the drain D2 of the power transistor TR2. A power supply potential VIN is supplied to the terminal T1 from a power supply or the like. A reference potential lower than the power supply potential VIN, for example, a ground potential GND, is supplied to the terminal T2. The terminal T3 is connected to a load. For example, the terminal T3 is connected to a coil CL used in a motor or the like.

[0124] The gate G1 of the power transistor TR1 and the gate G2 of the power transistor TR2 are connected to a drive circuit, and gate voltages are supplied from the drive circuit to the gate G1 of the power transistor TR1 and the gate G2 of the power transistor TR2, respectively. By controlling the gate voltage supplied to the gate G1 of the power transistor TR1 and the gate voltage supplied to the gate G2 of the power transistor TR2, the operations of the power transistor TR1 and the power transistor TR2 can be controlled.

[0125] Here, a part of the operation of the inverter circuit INV shown in FIG. 18 will be described.

[0126] When the inverter circuit INV is in standby mode, the gate voltage of the power transistor TR1 and the gate voltage of the power transistor TR2 are each lower than their threshold voltages, for example, 0 V. Therefore, both the power transistor TR1 and the power transistor TR2 are in the off state (non-conducting state), and no current flows through the coil CL.

[0127] Next, while the gate voltage of the power transistor TR2 is kept lower than the threshold voltage (for example, 0 V), a gate voltage equal to or higher than the threshold voltage is supplied to the gate G1 of the power transistor TR1. As shown in the circuit diagram of Fig. 19, the power transistor TR1 is turned on (conductive), and the power transistor TR2 is turned off (non-conductive). In the state shown in Fig. 19, a current Ion flows from the terminal T1 to which the power supply potential Vin is supplied through the power transistor TR1 and terminal T3 to the coil CL.

[0128] Next, consider the case where the gate voltage of power transistor TR1 is reduced from a voltage equal to or greater than the threshold voltage to a voltage lower than the threshold voltage (e.g., 0 V) ​​while the gate voltage of power transistor TR2 remains lower than the threshold voltage (e.g., 0 V). In this case, power transistor TR1 changes from an on state to an off state, and both power transistors TR1 and TR2 transition to the off state. At this time, an electromotive force acts to suppress the change in magnetic flux density of coil CL, causing terminal T3 to assume a negative potential, as shown in the circuit diagram of FIG. 20, creating a transient state in which current IOF flows from terminal T3 to coil CL. This transient state (terminal T3 assumes a negative potential) resolves over time. In other words, this transient state (terminal T3 assumes a negative potential) temporarily occurs when power transistor TR1 changes from an on state to an off state, and both power transistors TR1 and TR2 switch to the off state.

[0129] The source of the current IOF flowing through the coil CL is composed of a current flowing from the terminal T2 to the terminal T3 through a parasitic diode formed in the power transistor TR2, and a current supplied to the terminal T3 from the semiconductor substrate on which the power transistor TR2 is formed. That is, in the above-mentioned transient state shown in Fig. 20, electrons are injected from the drain D2 of the power transistor TR2 into the semiconductor substrate, reflecting the current being supplied to the terminal T3 from the semiconductor substrate on which the power transistor TR2 is formed.

[0130] The above-mentioned transient state corresponds to a state in which the potential of the source S2 of the power transistor TR2 is the ground potential GND and the potential of the drain D2 of the power transistor TR2 is a negative potential. When the LDMOSFET1 of the semiconductor device of the first embodiment is used as the power transistor TR2, the potential of the n-type drain region DR of the LDMOSFET1 becomes a negative potential in the above-mentioned transient state shown in FIG.

[0131] When the potential of the n-type drain region DR of the LDMOSFET 1 becomes negative, electrons are injected from the n-type drain region DR into the semiconductor substrate SUB. From another perspective, reflecting the injection of electrons from the n-type drain region DR into the semiconductor substrate SUB, holes (positive holes) move from the n-type drain region DR to the plug PGD and further move through the wiring M1D and the like to the terminal T3 outside the semiconductor device, causing a current IOF to flow from the terminal T3 to the coil CL.

[0132] When the drain region of the LDMOSFET 1 becomes at a negative potential, it is necessary to prevent electrons from being injected from the drain region of the LDMOSFET 1 into the semiconductor substrate SUB, which would cause a malfunction in the semiconductor device.

[0133] <About the study example> FIG. 21 is a cross-sectional view of a semiconductor device of an example studied by the present inventors, and shows a cross section corresponding to FIG.

[0134] The semiconductor device of the study example shown in FIG. 21 differs from the semiconductor device shown in FIG. 1 in the following points.

[0135] In the case of the study example shown in FIG. 21, the plug PG1 is not formed, an n-type semiconductor region DN is formed in the p-type semiconductor layer EP1, and a plug PG101 is formed on the n-type semiconductor region DN.

[0136] The n-type semiconductor region DN is composed of an n-type semiconductor region DN2 and an n-type semiconductor region DN1 formed in the upper part of the n-type semiconductor region DN2. The n-type impurity concentration of the n-type semiconductor region DN1 is higher than the n-type impurity concentration of the n-type semiconductor region DN2. The bottom surface of the n-type semiconductor region DN2 is in contact with the n-type buried layer BL. The plug PG101 is embedded in a contact hole penetrating the insulating film IL and is electrically connected to the n-type semiconductor region DN1. The wiring M1N101 corresponding to the above wiring M1N is electrically connected to the n-type semiconductor region DN1 via the plug PG101 and is further electrically connected to the n-type buried layer BL via the n-type semiconductor region DN1 and the n-type semiconductor region DN2.

[0137] <Features and Effects of the First Embodiment> As described with reference to FIGS. 18 to 20 , when the LDMOSFET 1 is used as the power transistor TR2 for the low-side switch, the n-type drain region DR of the LDMOSFET 1 may have a negative potential. When the n-type drain region DR has a negative potential, electrons are injected from the n-type drain region DR into the semiconductor substrate SUB. The injected electrons pass through the p-type semiconductor layer EP1 and are then injected into the n-type buried layer BL, and further from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB below the n-type buried layer BL. When the potential of the n-type drain region DR becomes negative, the potential of the n-type buried layer BL below the n-type drain region DR also tends to become negative. Therefore, electrons are likely to be injected from the n-type buried layer BL below the p-type semiconductor layer EP1 into the p-type semiconductor layer EP2 and the p-type substrate body SB below the n-type buried layer BL.

[0138] In a p-type semiconductor region, holes behave as majority carriers, and electrons behave as minority carriers. Therefore, when electrons are injected from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB below the n-type buried layer BL, the electrons injected into the p-type semiconductor layer EP2 and the p-type substrate body SB behave as minority carriers. Therefore, the electrons can diffuse within the p-type semiconductor layer EP2 and the p-type substrate body SB until they recombine with holes and disappear. Therefore, the electrons injected from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB may travel a long distance within the p-type semiconductor layer EP2 and the p-type substrate body SB. As a result, the electrons that travel within the p-type substrate body SB may affect the operation of other semiconductor elements formed in the semiconductor substrate SUB. Therefore, the injection of electrons from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB is undesirable because it may affect the characteristics of the other semiconductor elements and lead to a decrease in the performance of the semiconductor device. The other semiconductor element is formed in a p-type semiconductor layer EP1 electrically isolated from the p-type semiconductor layer EP1 in which the LDMOSFET 1 is formed via a DTI region 3 or the like, and is, for example, a MOSFET constituting an information processing circuit or an analog circuit. A MOSFET 11 shown in Fig. 29, which will be described later, is an example of the other semiconductor element.

[0139] Therefore, in the semiconductor device of the first embodiment shown in FIG. 1 , a plug PG1 electrically connected to the n-type buried layer BL is formed. The plug PG1 can function as a power supply region to the n-type buried layer BL. Therefore, a fixed potential can be supplied from the plug PG1 to the n-type buried layer BL. As a result, even when the potential of the n-type drain region DR becomes negative, the potential of the n-type buried layer BL below the n-type drain region DR does not fluctuate and is fixed to the potential supplied from the plug PG1 to the n-type buried layer BL. Therefore, it is possible to prevent the negative potential of the n-type drain region DR from fluctuating the potential of the n-type buried layer BL. As a result, it is possible to suppress injection of electrons from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB when the potential of the n-type drain region DR becomes negative. Since the number of electrons injected from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB can be suppressed, it is possible to reduce the possibility that electrons that have moved within the p-type semiconductor layer EP2 and the p-type substrate body SB will affect the operation of other semiconductor elements formed within the semiconductor substrate SUB, thereby improving the performance of the semiconductor device.

[0140] In the case of the semiconductor device of the study example of FIG. 21, a fixed potential can be supplied to the n-type buried layer BL from the plug PG101 via the n-type semiconductor region DN. That is, in the case of the study example of FIG. 21, the n-type semiconductor region DN functions as a power supply region to the n-type buried layer BL. However, in the case of the semiconductor device of the study example of FIG. 21, the following concerns arise.

[0141] The n-type semiconductor region DN2 is formed by ion implantation of n-type impurities and thermal diffusion of the implanted n-type impurities. Because the n-type semiconductor region DN2 needs to be formed so as to reach the n-type buried layer BL, the thermal diffusion distance of the n-type impurities when forming the n-type semiconductor region DN2 needs to be relatively large. Therefore, the width W1 (see FIG. 21) of the n-type semiconductor region DN2 is relatively large. Here, the width W1 of the n-type semiconductor region DN2 corresponds to the width (dimension) in a direction parallel to the main surface of the semiconductor substrate SUB and substantially perpendicular to the extending direction of the n-type semiconductor region DN2 in a plan view. As a result, in the case of the semiconductor device of the study example shown in FIG. 21, there is a concern that the total area of ​​the semiconductor device will increase due to the area of ​​the n-type semiconductor region DN increasing due to thermal diffusion.

[0142] If the electrical resistance of the power supply region (n-type semiconductor region DN) to the n-type buried layer BL increases, there is a concern that a parasitic thyristor may operate. To suppress the parasitic thyristor operation, it is desirable to reduce the electrical resistance of the power supply region (n-type semiconductor region DN) to the n-type buried layer BL. However, since the n-type semiconductor region DN2 is formed by ion implantation of n-type impurities and thermal diffusion treatment of the implanted n-type impurities, there is a limit to how high the n-type impurity concentration of the n-type semiconductor region DN2 can be, and it is difficult to sufficiently increase the conductivity of the n-type semiconductor region DN2. As a result, in the case of the study example of FIG. 21, it is difficult to sufficiently reduce the electrical resistance of the n-type semiconductor region DN, and there is a concern that a parasitic thyristor may operate.

[0143] In contrast, in the semiconductor device of the first embodiment, a plug PG1 is formed as a power supply region to the n-type buried layer BL, instead of the n-type semiconductor region DN. The plug PG1 is formed not by ion implantation of impurities and thermal diffusion treatment, but by embedding a conductive film (metal film) in a trench 4a formed in the insulating film IL and the semiconductor substrate SUB. Therefore, the width W2 of the plug PG1 in the first embodiment (see FIG. 1) can be made smaller than the width W1 of the n-type semiconductor region DN2 in the study example (see FIG. 21). Here, the width W2 of the plug PG1 corresponds to the width (dimension) in a direction parallel to the main surface of the semiconductor substrate SUB and substantially perpendicular to the extending direction of the plug PG1 in a plan view. For example, the width W2 of the plug PG1 can be set to a dimension of about 30 to 50 percent of the width W1 of the n-type semiconductor region DN2. This makes it possible to reduce the area of ​​the power supply region (plug PG1) to the n-type buried layer BL, thereby reducing the total area of ​​the semiconductor device. Therefore, the semiconductor device can be made smaller.

[0144] Furthermore, in the semiconductor device of the first embodiment, the plug PG1, which functions as a power supply region to the n-type buried layer BL, is formed by burying a conductive film (metal film) in the insulating film IL and the trench 4a formed in the semiconductor substrate SUB. The plug PG1 is preferably made of a metal material. This makes it possible to increase the conductivity of the plug PG1 and suppress the electrical resistance of the plug PG1. This makes it possible to suppress the operation of the parasitic thyristor. Therefore, the performance of the semiconductor device can be improved.

[0145] In the first embodiment, the potential supplied from the wiring M1N to the plug PG1 is supplied from the plug PG1 to the n-type buried layer BL. The potential supplied from the plug PG1 to the n-type buried layer BL is a fixed potential, preferably a ground potential (zero volts) or a positive potential. That is, the potential supplied from the plug PG1 to the n-type buried layer BL is preferably a fixed potential that is not a negative potential. This makes it possible to reliably suppress the phenomenon of electrons being injected from the n-type buried layer BL into the p-type semiconductor layer EP2 and the p-type substrate body SB.

[0146] When the LDMOSFET1 is used as a power transistor TR2 for a low-side switch, the potential supplied from the plug PG1 to the n-type buried layer BL can be set to the same potential (ground potential) as the source potential supplied from the plug PGS to the n-type source region SR, thereby simplifying the circuit configuration of the semiconductor device.

[0147] When the LDMOSFET1 is used as a power transistor TR1 for a high-side switch, the potential supplied from the plug PG1 to the n-type buried layer BL can be set to the same potential (positive power supply potential) as the drain potential supplied from the plug PGD to the n-type drain region DR, thereby simplifying the circuit configuration of the semiconductor device.

[0148] The semiconductor device of the first embodiment further includes a DTI region 3. The DTI region 3 penetrates the p-type semiconductor layer EP1 and the n-type buried layer BL, and surrounds the LDMOSFET 1 in plan view. The DTI region 3 electrically isolates the p-type semiconductor layer EP1 in which the LDMOSFET 1 is formed from the surrounding p-type semiconductor layers EP1. In plan view, the LDMOSFET 1 and the plug PG1 are surrounded by the DTI region 3.

[0149] The plug PG1 can be formed by utilizing the process of forming the DTI region 3. That is, when forming the DTI region 3, the dummy DTI region 3a is also formed. Then, the dummy DTI region 3a is etched to form the trench 4a, and the plug PG1 can be formed in the trench 4a. This reduces the number of additional steps required to form the plug PG1. The ion implantation step and thermal diffusion step for forming the n-type semiconductor region DN2 are not required. This reduces the number of steps required to manufacture the semiconductor device.

[0150] By applying the plug PG1 of this embodiment 1 to a semiconductor device having a DTI region 3, it is possible to form a low-resistance power supply region (here, the plug PG1) to the n-type buried layer BL while reducing the number of manufacturing steps.

[0151] The semiconductor device of the first embodiment further has a plug PG2. The potential supplied from the wiring M1P to the plug PG2 is supplied from the plug PG2 to the p-type semiconductor layer EP2 and the p-type substrate body SB. The potential supplied from the plug PG1 to the n-type buried layer BL is a fixed potential, preferably the ground potential (0V). This makes it possible to fix the potential of the p-type substrate body SB to the fixed potential (preferably the ground potential). Therefore, it is possible to suppress or prevent the potential of the p-type substrate body SB from fluctuating, thereby stabilizing the operation of the semiconductor device.

[0152] When a back electrode is formed on the back surface of the semiconductor substrate SUB, a fixed potential can be supplied from the back electrode to the p-type substrate body SB. In this case, a process for forming the back electrode is required, which increases the manufacturing cost of the semiconductor device.

[0153] In the case of the first embodiment, since a fixed potential can be supplied from the plug PG2 to the p-type semiconductor layer EP2 and the p-type substrate body SB, there is no need to form a back surface electrode on the back surface of the semiconductor substrate SUB. By not forming a back surface electrode on the back surface of the semiconductor substrate SUB, the manufacturing cost of the semiconductor device can be suppressed.

[0154] As a modified example, there may be a case where the plug PG2 is not formed, in which case it is preferable to form a back surface electrode on the back surface of the semiconductor substrate SUB.

[0155] In the first embodiment, the trenches 4, 5, and 6 can be formed in the same process, and the dummy DTI region 3a, dummy DTI region 3b, and DTI region 3 can be formed in the same process. The trenches 4a and 5a can be formed in the same process, and the plugs PG1 and PG2 can be formed in the same process. This reduces the number of manufacturing processes for the semiconductor device.

[0156] (Embodiment 2) FIG. 22 corresponds to FIG. 8 and shows the stage where the photoresist pattern RP1 has been formed.

[0157] In the second embodiment, the silicon film pattern SP (see FIG. 6) is not formed when the gate electrode GE is formed. In the second embodiment, except that the silicon film pattern SP is not formed, the steps up to the formation of the insulating film IL are performed in substantially the same manner as in the first embodiment. Thereafter, as shown in FIG. 22, a photoresist pattern RP1 is formed on the insulating film IL. For this reason, in FIG. 22, the silicon film pattern SP is not formed on the STI region 2. In FIG. 22, the width W3a of the opening OP1 of the photoresist pattern RP1 is smaller than the width W3b of the opening OP2 of the photoresist pattern RP1 and is also smaller than the width W3c of the opening OP3 of the photoresist pattern RP1.

[0158] 23, the insulating film IL and the STI region 2 are selectively etched using the photoresist pattern RP1 as an etching mask, thereby forming grooves 4, 5, and 6. This etching step is referred to as the etching step of FIG. 23. The etching step of FIG. 23 is performed under etching conditions such that the etching rates of the insulating film IL and the STI region 2 are higher than the etching rate of the semiconductor substrate SUB (p-type semiconductor layer EP1).

[0159] 9 and 23, the planar position and depth of groove 5 are the same. The planar position and depth of groove 6 are the same in the etching process of FIG. 9 and 23. On the other hand, the planar position of groove 4 is the same in the etching process of FIG. 9 and 23, but the depth of groove 4 is different. This is because the silicon film pattern SP does not exist in the etching process of FIG. 23.

[0160] 23, the semiconductor substrate SUB (p-type semiconductor layer EP1) can function as an etching stopper. As a result, in the etching step of Fig. 23, the trenches 4, 5, and 6 each penetrate the insulating film IL and the STI region 2 to reach the semiconductor substrate SUB (p-type semiconductor layer EP1), but the semiconductor substrate SUB (p-type semiconductor layer EP1) exposed from the trenches 4, 5, and 6 is hardly etched. For this reason, the depth of the bottom surface of each of the trenches 4, 5, and 6 is approximately the same as the depth of the bottom surface of the STI region 2. That is, the depth of the bottom surface of each of the trenches 4, 5, and 6 is approximately the same as one another.

[0161] 24, the photoresist pattern RP1 is used as an etching mask to selectively etch the semiconductor substrate SUB exposed from the grooves 4, 5, and 6. This etching step is referred to as the etching step of FIG.

[0162] By performing the etching step of Figure 24, the depths of grooves 4, 5, and 6 increase. That is, the bottom surface of groove 4 after the etching step of Figure 24 is completed is deeper than the bottom surface of groove 4 after the etching step of Figure 23 is completed. The bottom surface of groove 5 after the etching step of Figure 24 is completed is deeper than the bottom surface of groove 5 after the etching step of Figure 23 is completed. The bottom surface of groove 6 after the etching step of Figure 24 is completed is deeper than the bottom surface of groove 6 after the etching step of Figure 23 is completed.

[0163] 24 is completed, the depth of the bottom surface of groove 5 and the depth of the bottom surface of groove 6 are approximately the same. At the stage when the etching step of FIG. 24 is completed, the bottom surface of groove 4 is shallower than the bottom surface of groove 5 and is also shallower than the bottom surface of groove 6. That is, in the etching step of FIG. 24, the etching amount of the semiconductor substrate SUB exposed from groove 5 and the etching amount of the semiconductor substrate SUB exposed from groove 6 are approximately the same. Meanwhile, in the etching step of FIG. 24, the etching amount of the semiconductor substrate SUB exposed from groove 4 is smaller than the etching amount of the semiconductor substrate SUB exposed from groove 5 and is also smaller than the etching amount of the semiconductor substrate SUB exposed from groove 6. This is because, in the second embodiment, the width W4 of groove 4 (see FIG. 24) is smaller than the width W5 of groove 5 (see FIG. 24) and is also smaller than the width W6 of groove 6 (see FIG. 24). Here, the width W4 of the trench 4 corresponds to the width (dimension) in a direction parallel to the main surface of the semiconductor substrate SUB and substantially perpendicular to the extension direction of the trench 4 in a plan view. The width W5 of the trench 5 corresponds to the width (dimension) in a direction parallel to the main surface of the semiconductor substrate SUB and substantially perpendicular to the extension direction of the trench 5 in a plan view. The width W6 of the trench 6 corresponds to the width (dimension) in a direction parallel to the main surface of the semiconductor substrate SUB and substantially perpendicular to the extension direction of the trench 6 in a plan view.

[0164] The width W4 of groove 4 is approximately the same as the width W3a of opening OP1 in photoresist pattern RP1, the width W5 of groove 5 is approximately the same as the width W3b of opening OP2 in photoresist pattern RP1, and the width W6 of groove 6 is approximately the same as the width W3c of opening OP3 in photoresist pattern RP1. Therefore, reflecting the fact that the width W3a of opening OP1 in photoresist pattern RP1 is smaller than the width W3b of opening OP2 and also smaller than the width W3c of opening OP3, the width W4 of groove 4 is smaller than the width W5 of groove 5 and also smaller than the width W6 of groove 6.

[0165] When forming a trench by etching, etching of the object to be etched (here, the semiconductor substrate SUB) proceeds while deposits resulting from etching are accumulated on the side surfaces of the trench, so that if the width of the trench is reduced, the trench that is formed tends to be shallower. Utilizing this, by reducing the width W3a of the opening OP1 in the photoresist pattern RP1, the width W4 of the trench 4 is reduced, and as a result, the depth of the trench 4 can be made smaller than the depths of the trenches 5 and 6.

[0166] 24 is performed under etching conditions such that the trenches 4 penetrate the p-type semiconductor layer EP1 to reach the n-type buried layer BL but do not reach the p-type semiconductor layer EP2 (i.e., do not penetrate the n-type buried layer BL). Therefore, at the stage where the etching step of FIG. 24 is completed, the bottom surfaces of the trenches 4 are deeper than the top surfaces of the n-type buried layer BL and shallower than the bottom surfaces of the n-type buried layer BL.

[0167] 24, the grooves 5 and 6 each penetrate the p-type semiconductor layer EP1 and the n-type buried layer BL to reach the p-type semiconductor layer EP2, but do not reach the p-type substrate body SB. In this case, at the stage when the etching step of Fig. 24 is completed, the bottom surfaces of the grooves 5 and 6 are deeper than the bottom surface of the n-type buried layer BL and shallower than the bottom surface of the p-type semiconductor layer EP2. However, this is not limiting, and there may be cases where the grooves 5 and 6 each reach the p-type substrate body SB at the stage when the etching step of Fig. 24 is completed.

[0168] Next, the photoresist pattern RP1 is removed by ashing or the like.

[0169] Next, as shown in Fig. 25, the DTI region 3, the dummy DTI region 3a, and the dummy DTI region 3b are formed. The process of forming the DTI region 3, the dummy DTI region 3a, and the dummy DTI region 3b in the second embodiment is the same as the process in Fig. 13 in the first embodiment. Air gaps may be formed in each of the DTI region 3, the dummy DTI region 3a, and the dummy DTI region 3b.

[0170] The subsequent steps in the second embodiment are the same as those in the first embodiment.

[0171] In the case of the above-described first embodiment, grooves 4, 5, and 6 are formed by the etching step of Fig. 9, the etching step of Fig. 10, the etching step of Fig. 11, and the etching step of Fig. 12. In the case of the second embodiment, grooves 4, 5, and 6 can be formed by the etching step of Fig. 23 and the etching step of Fig. 24. Therefore, in the case of the second embodiment, the number of etching steps required to form grooves 4, 5, and 6 can be reduced. Therefore, the number of manufacturing steps for the semiconductor device can be reduced.

[0172] On the other hand, in the case of the first embodiment, it is easy to control the depth of each of the grooves 4, 5, and 6 to the target depth. This makes it easier to control the etching process, and facilitates the manufacture of semiconductor devices.

[0173] (Embodiment 3) FIG. 26 is a plan view of a main part of the semiconductor device of the third embodiment, showing the planar layout of the LDMOSFET formation region 1a, the plugs PG1 and PG2, and the DTI region 3. FIG. 27 is a cross-sectional view of the semiconductor device taken along the line A1-A1 in FIG. 26. In FIG. 26, the X direction is the gate length direction of the gate electrode GE, and therefore the channel length direction. In FIG. 26, the Y direction is the gate width direction of the gate electrode GE, and therefore the channel width direction.

[0174] 26, a DTI region 3 is formed that surrounds the LDMOSFET formation region 1a (LDMOSFET1) in a planar view. This allows the p-type semiconductor layer EP1 (the p-type semiconductor layer EP1 in which the LDMOSFET1 is formed) surrounded by the DTI region 3 to be electrically isolated from the surrounding p-type semiconductor layer EP1. In the case of FIG. 26, the LDMOSFET formation region 1a, the multiple plugs PG1, and the multiple plugs PG2 are surrounded by the DTI region 3 in a planar view.

[0175] In the LDMOSFET formation region 1a, a plurality of unit LDMOSFETs are arranged in the X direction, and the LDMOSFETs are connected in parallel to form an LDMOSFET 1.

[0176] In the third embodiment, as shown in FIG. 26, a plurality of plugs PG1 and a plurality of plugs PG2 are arranged alternately in the X direction.

[0177] Fig. 28 is a plan view of a main part of the semiconductor device of the first embodiment, and corresponds to Fig. 26. In the case of Fig. 28, in plan view, a plug PG1 extending in the Y direction and a plug PG2 extending in the Y direction are adjacent to each other in the X direction.

[0178] 28, in a plan view, a plug PG2 is arranged between the plug PG1 and the DTI region 3. In contrast, in the case of FIG. 26, multiple plugs PG1 and multiple plugs PG2 are arranged alternately in the X direction, so that, in a plan view, the plug PG2 is not arranged between the plug PG1 and the DTI region 3, and the plug PG1 is not arranged between the plug PG2 and the DTI region 3. Reflecting this, the distance L1 shown in FIG. 26 is smaller than the distance L2 shown in FIG. 28. Here, the distance L1 and the distance L2 each correspond to the dimension in the Y direction of the p-type semiconductor layer EP1 that is surrounded by the DTI region 3 and in which the LDMOSFET1 is formed, in a plan view.

[0179] In the third embodiment, the distance L1 shown in Fig. 26 can be made smaller than the distance L2 shown in Fig. 28, and therefore the total area of ​​the semiconductor device can be reduced, thereby enabling the semiconductor device to be miniaturized.

[0180] (Fourth embodiment) 29 shows regions RG1, RG2, and RG3. Region RG1 is surrounded by DTI region 3c in a plan view and includes LDMOSFET 1. Region RG2 is surrounded by DTI region 3d in a plan view and includes MOSFET 11. Region RG3 is located between regions RG1 and RG2 in a plan view. MOSFET 11 constitutes, for example, an information processing circuit or an analog circuit.

[0181] In FIG. 29, the structure of the semiconductor device in the region RG1 is the same as that in FIG. 1, and therefore a repeated description thereof will be omitted here.

[0182] The structure of the semiconductor device in the region RG2 will be described.

[0183] In region RG2, a MOSFET 11 is formed on the main surface of the semiconductor substrate SUB. Here, the case where the MOSFET 11 is an n-channel MOSFET will be described, but the MOSFET 11 may also be a p-channel MOSFET. Both an n-channel MOSFET and a p-channel MOSFET may also be formed.

[0184] The MOSFET 11 has a p-type well PW, an n-type source region SR1, an n-type drain region DR1, a gate insulating film GF1, and a gate electrode GE1.

[0185] A p-type well PW is formed in the semiconductor layer EP1 in the region RG2. An n-type source region SR1 and an n-type drain region DR1 are formed in the p-type well PW. A gate electrode GE1 is formed on the p-type well PW via a gate insulating film GF1. Plugs PG1 that penetrate the insulating film IL are disposed on the n-type source region SR1 and the n-type drain region DR1, respectively, and wiring M1 is connected to each plug PG1.

[0186] The structure of the semiconductor device in the region RG3 will be described.

[0187] A plug PG1 is formed in region RG3. The structure of the plug PG1 (hereinafter referred to as plug PG1a) in region RG3 is similar to the structure of the plug PG1 in region RG1. The plug PG1a is made of a conductive film (metal film) embedded in a trench continuously formed in the insulating film IL, the STI region 2, and the semiconductor substrate SUB. The depth of the plug PG1a arranged in region RG3 is approximately the same as the depth of the plug PG1 arranged in region RG1.

[0188] The plug PG1a penetrates the insulating film IL, the STI region 2, and the p-type semiconductor layer EP1 to reach the n-type buried layer BL. The plug PG1a does not penetrate the n-type buried layer BL, and the bottom surface of the plug PG1a is deeper than the top surface of the n-type buried layer BL and shallower than the bottom surface of the n-type buried layer BL. Since the entire side surface of the plug PG1a is covered with the insulating film ZF, the side surface of the plug PG1a does not contact the semiconductor substrate SUB, and the insulating film ZF is interposed between the side surface of the plug PG1a and the p-type semiconductor layer EP1, and between the side surface of the plug PG1a and the n-type buried layer BL. The bottom surface of the plug PG1a contacts the n-type buried layer BL, and the plug PG1a is electrically connected to the n-type buried layer BL.

[0189] 3 to 17, the silicon film pattern SP is also formed in the region RG3. When the manufacturing processes shown in FIGS. 22 to 25 are applied, the silicon film pattern SP is not formed in the region RG3.

[0190] When the potential of the n-type drain region DR becomes negative, there is a concern that electrons injected from the n-type buried layer BL in region RG1 into the p-type semiconductor layer EP2 and the p-type substrate body SB will move through the p-type substrate body SB in region RG3 to the p-type substrate body SB in region RG2, affecting the operation of the MOSFET 11 formed in the p-type semiconductor layer EP1 in region RG2.

[0191] In the fourth embodiment, the plug PG1a is disposed in the region RG3. Therefore, in the region RG3, some of the electrons moving through the p-type substrate body SB and the p-type semiconductor layer EP2 can be discharged to the outside of the semiconductor substrate SUB via the n-type buried layer BL and the plug PG1a. This further reduces the number of electrons that travel from the p-type substrate body SB in the region RG1 through the p-type substrate body SB in the region RG3 to the p-type substrate body SB in the region RG2 when the potential of the n-type drain region DR becomes negative. As a result, when the potential of the n-type drain region DR becomes negative, it is possible to further reduce the possibility that electrons injected from the n-type buried layer BL in the region RG1 into the p-type semiconductor layer EP2 and the p-type substrate body SB affect the operation of the MOSFET 11 in the region RG2. This further improves the performance of the semiconductor device.

[0192] In the fourth embodiment, it is preferable to form the plug PG1 in the region RG1, but there may be cases where the plug PG1 is not formed in the region RG1. Even when the plug PG1 is not formed in the region RG1, some of the electrons moving through the p-type substrate body SB and the p-type semiconductor layer EP2 in the region RG3 can be discharged to the outside of the semiconductor substrate SUB via the n-type buried layer BL and the plug PG1a. This makes it possible to suppress the possibility that electrons injected from the n-type buried layer BL in the region RG1 into the p-type semiconductor layer EP2 and the p-type substrate body SB when the potential of the n-type drain region DR becomes negative will affect the operation of the MOSFET 11 in the region RG2.

[0193] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0194] 1 LDMOSFET 2 STI area 3 DTI area 3a,3b Dummy DTI area 4,4a,5,5a,6 groove 11 MOSFET BL n-type buried layer CL coil D1, D2 drain DN, DN1, DN2 n-type semiconductor region DR, DR1 n-type drain region EP1, EP2 p-type semiconductor layer G1, G2 gates GE,GE1 gate electrode GF,GF1 Gate insulating film IL insulating film INV Inverter circuit M1D, M1N, M1P, M1S wiring ND n-type drift region OP1, OP2, OP3 opening PB p-type well region PG1, PG2, PGD, PGN, PGS plugs PR p-type semiconductor region PW p-type well RG1,RG2,RG3 area RP1,RP2 photoresist pattern S1,S2 source SB p-type substrate area SP silicon film pattern SR, SR1 n-type source region SUB Semiconductor substrate TR1, TR2 power transistors ZF insulating film

Claims

1. a semiconductor substrate having a main surface; a transistor formed on the main surface of the semiconductor substrate; a first insulating film formed on the main surface of the semiconductor substrate and covering the transistor; a DTI region; and a first contact plug; Including, The semiconductor substrate is a substrate region of a first conductivity type; a buried layer of a second conductivity type opposite to the first conductivity type formed on the substrate region; a semiconductor layer of the first conductivity type formed on the buried layer; and the DTI region penetrates the first insulating film, the semiconductor layer, and the buried layer and reaches the substrate region; the first contact plug penetrates the first insulating film and the semiconductor layer and reaches the buried layer; a second insulating film is interposed between a side surface of the first contact plug and the semiconductor substrate; a bottom surface of the first contact plug is shallower than a bottom surface of the buried layer; The first contact plug is electrically connected to the buried layer.

2. 2. The semiconductor device according to claim 1, the DTI region includes a trench and a third insulating film buried in the trench; The DTI region surrounds the transistor in a plan view.

3. 3. The semiconductor device according to claim 2, The DTI region surrounds the transistor and the first contact plug in a plan view.

4. 4. The semiconductor device according to claim 3, The semiconductor device, wherein the first contact plug is made of a metal material.

5. 4. The semiconductor device according to claim 3, A first fixed potential is supplied from the first contact plug to the buried layer.

6. 6. The semiconductor device according to claim 5, the first conductivity type is p-type, the second conductivity type is n-type, The semiconductor device, wherein the first fixed potential is a ground potential or a positive potential.

7. 2. The semiconductor device according to claim 1, further comprising an STI region formed on the main surface of the semiconductor substrate; The semiconductor device, wherein the bottom surface of the DTI region is deeper than the bottom surface of the STI region.

8. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the transistor is a power switching element.

9. 9. The semiconductor device according to claim 8, The semiconductor device, wherein the transistor is a transistor of the second conductivity type.

10. 9. The semiconductor device according to claim 8, the first conductivity type is p-type, the second conductivity type is n-type, The semiconductor device, wherein the transistor is an n-type MOSFET.

11. 2. The semiconductor device according to claim 1, a second contact plug that penetrates the first insulating film, the semiconductor layer, and the buried layer and reaches the substrate region; a fourth insulating film is interposed between a side surface of the second contact plug and the semiconductor substrate; The second contact plug is electrically connected to the substrate region.

12. 12. The semiconductor device according to claim 11, The DTI region surrounds the transistor, the first contact plug, and the second contact plug in a plan view.

13. 12. The semiconductor device according to claim 11, a plurality of the first contact plugs and a plurality of the second contact plugs; the DTI region surrounds the transistor, the first contact plugs, and the second contact plugs in a plan view; The semiconductor device, wherein the plurality of first contact plugs and the plurality of second contact plugs are alternately arranged in a gate length direction of the MOSFET.

14. (a) providing a semiconductor substrate having a substrate region of a first conductivity type, a buried layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, and a semiconductor layer of the first conductivity type formed on the buried layer; (b) forming a transistor on the main surface of the semiconductor substrate; (c) after the step (b), forming a first insulating film on the main surface of the semiconductor substrate so as to cover the transistor; (d) after the step (c), forming a first trench that penetrates the first insulating film, the semiconductor layer, and the buried layer and reaches the substrate region, and a second trench that penetrates the first insulating film and the semiconductor layer and reaches the buried layer; (e) after the step (d), forming a second insulating film in the first trench and the second trench; (f) after the step (e), forming a third groove in the second groove by etching a part of the second insulating film in the second groove; (g) after the step (f), forming a first contact plug in the third trench; and a DTI region is formed by the second insulating film formed in the first trench in the step (e); the DTI region penetrates the first insulating film, the semiconductor layer, and the buried layer and reaches the substrate region; the first contact plug penetrates the first insulating film and the semiconductor layer and reaches the buried layer; the second insulating film is interposed between a side surface of the first contact plug and the semiconductor substrate; a bottom surface of the first contact plug being shallower than a bottom surface of the buried layer and being electrically connected to the buried layer;

15. 15. The method for manufacturing a semiconductor device according to claim 14, the transistor and the first contact plug are surrounded by the DTI region in a plan view.

16. 15. The method for manufacturing a semiconductor device according to claim 14, (a1) forming an STI region on the main surface of the semiconductor substrate after the step (a) and before the step (b); and The step (b) comprises: (b1) forming a gate electrode of the transistor on the semiconductor layer via a gate insulating film; (b2) forming a source region of the transistor and a drain region of the transistor in the semiconductor layer; A method for manufacturing a semiconductor device, comprising:

17. 17. The method of manufacturing a semiconductor device according to claim 16, In the step (b1), a silicon film pattern is formed on the STI region; In the step (d), the second trench is formed to penetrate the first insulating film, the silicon film pattern, the STI region, and the semiconductor layer and to reach the buried layer.

18. 18. The method of manufacturing a semiconductor device according to claim 17, The step (d) (d1) forming the first trench so as to penetrate the first insulating film and the STI region and reach the semiconductor layer by etching the first insulating film and the STI region using the silicon film pattern and the semiconductor layer as an etching stopper, and forming the second trench so as to penetrate the first insulating film and reach the silicon pattern; A method for manufacturing a semiconductor device, comprising:

19. 15. The method for manufacturing a semiconductor device according to claim 14, In the step (d), the width of the second groove is smaller than the width of the first groove.

20. 15. The method for manufacturing a semiconductor device according to claim 14, In the step (d), the first trench is formed so as to penetrate through the first insulating film, the semiconductor layer, and the buried layer and reach the substrate region, the second trench is formed so as to penetrate through the first insulating film and the semiconductor layer and reach the buried layer, and a fourth trench is formed so as to penetrate through the first insulating film, the semiconductor layer, and the buried layer and reach the substrate region; In the step (e), the second insulating film is formed in the first trench, the second trench, and the fourth trench; in the step (f), a third groove is formed in the second groove by etching a part of the second insulating film in the second groove, and a fifth groove is formed in the fourth groove by etching a part of the second insulating film in the fourth groove; In the step (g), the first contact plug is formed in the third trench, and a second contact plug is formed in the fifth trench.

Images