Micro-transfer printing for MEMS

Abstract

To provide a semiconductor structure including a MEMS and a circuit, and a method for use in manufacturing such a structure.SOLUTION: A method of forming a semiconductor structure includes providing a semiconductor substrate, forming a microelectromechanical structure (MEMS) device in and / or on the semiconductor substrate, providing a semiconductor chiplet including circuitry configured to provide an input to and / or process an output from the MEMS device, microtransfer printing the semiconductor chiplet onto the semiconductor substrate, and connecting the circuitry to the MEMS device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to micro-transfer printing for micro-electromechanical systems (MEMS). [Background technology]

[0002] A piezoelectric MEMS system includes a MEMS section in which the piezo stack is used to actuate the material and / or sense mechanical stress applied to the material, and an external electronic controller, typically including high-voltage transistors. The MEMS section typically includes an array of MEMS devices that can be connected to electronics by external wiring.

[0003] For example, an inkjet printhead may include such a MEMS system. The electronics include a high-voltage driver on a separate die or substrate. The MEMS elements (e.g., made from lead zirconate titanate, commonly known as PZT) that carry the ink are arranged in a large array of dots near the paper. The dots are connected to the driver by wide ribbon cables.

[0004] For large printheads, the system can become very bulky and require many wires. The size of the array is effectively limited by the ribbon cable. Therefore, improved systems are needed, especially for large MEMS arrays. Summary of the Invention

[0005] Aspects of the present invention provide semiconductor structures and methods for use in the manufacture of such structures as set out in the accompanying claims.

[0006] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1]1 shows a schematic cross-sectional view of a portion of a printhead including a semiconductor structure. [Figure 2] 1 shows a schematic cross-sectional view of a chiplet. [Figure 3] 1 shows a schematic plan view of an apparatus including multiple MEMS devices. [Figure 4A] 4A through 4D show successive schematic cross-sectional views of a semiconductor structure during processing. [Figure 4B] 4A through 4D show successive schematic cross-sectional views of a semiconductor structure during processing. [Figure 4C] 4A through 4D show successive schematic cross-sectional views of a semiconductor structure during processing. [Figure 4D] 4A through 4D show successive schematic cross-sectional views of a semiconductor structure during processing. [Figure 5A] 5A through 5D show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 5B] 5A through 5D show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 5C] 5A through 5D show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 5D] 5A through 5D show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 6A] 6A-6C show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 6B] 6A-6C show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 6C] 6A-6C show successive schematic cross-sectional views of a semiconductor structure during processing according to another embodiment. [Figure 7] 1 shows a schematic diagram of a portion of a semiconductor structure. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 shows a schematic cross-sectional view of a portion of a printhead including a semiconductor structure 2 including a micro-electro-mechanical structure (MEMS) device 4 formed in and on a semiconductor substrate 6 .

[0009] The MEMS device includes a membrane 8 including a membrane layer 10 having an aperture 12. The MEMS device further includes a piezoelectric element 14. The piezoelectric element 14 actuates the membrane 8 by applying a voltage to the piezoelectric element 14. Typically, the piezoelectric element includes a stack including two electrodes sandwiching a piezoelectric material (e.g., Al(Sc)N). A cavity 16 behind the membrane is configured to hold ink, which can be ejected through the aperture 12 by actuating the membrane 8 with the piezoelectric element 14. The semiconductor structure further includes a circuit 17 including a driver 18. The driver 18 drives the MEMS device 4 by providing electrical signals to the MEMS device 4. The driver 18 includes multiple active and passive components, such as transistors, diodes, resistors, capacitors, and conductors. The driver 18 is configured to provide input to the MEMS device 4. In other embodiments, the circuit 17 may additionally or alternatively include a sensor circuit for receiving and processing output from the MEMS device 4. The printhead includes multiple drivers 18 and their associated MEMS devices 4, each providing one of the so-called "nozzles" of the printhead. For example, the printhead may include 100 or more nozzles.

[0010] The drivers 18 are disposed in / on the chiplets 20, which are portions of a chip removed from its native substrate (i.e., the substrate on which the chip was formed). Typically, the chiplets 20 include multiple drivers 18 for driving multiple MEMS devices 4 (one of which is shown). The chiplets 20 are transfer printed onto a semiconductor substrate 6 (the "target" substrate). The semiconductor substrate 6 is included in a MEMS wafer (i.e., a semiconductor wafer on which MEMS devices are formed). Preferably, the printhead is made from a single die. After the chiplets 20 are micro-transfer printed onto the (MEMS) semiconductor substrate 6, the chiplets 20 are electrically connected to the MEMS devices 4 by a redistribution layer (RDL) 22. The RDL 22 may include metal lines (e.g., copper) between the chiplets 20 and the MEMS devices 4. The RDL 22 provides input / output connections to the drivers 18. The chiplets 20 are typically attached to the substrate 6 by an adhesion layer 26 (e.g., a glue layer).

[0011] The semiconductor structure 2 includes a dielectric layer 23 (e.g., SiO2) on the membrane layer 10 and a passivation layer 24 covering both the MEMS device 4 and the chiplet 20. The passivation layer 24 may be a silicon nitride layer. Alternatively, the passivation layer may include bisbenzocyclobutane (BCB) (e.g., having a thickness of approximately 2 μm to 3 μm) to provide a flat surface with relatively low mechanical stiffness. The passivation layer 24 includes openings 27 for connecting to the semiconductor structure 2. The passivation layer 24 provides a smooth upper surface that can be wiped clean with a print head. The dielectric layer 23 has a thickness of approximately 500 nm and may be patterned to provide connections. The dielectric layer 23 is patterned to facilitate connections between the chiplet 20 and the MEMS device 4.

[0012] FIG. 2 shows a schematic cross-sectional view of a chiplet 20, which may be the chiplet 20 described in connection with FIG. 1 above. To facilitate understanding, the same reference numbers are used for equivalent or similar features in different figures, but these do not limit the illustrated embodiment. The chiplet 20 includes an active silicon layer 30 having a doped region 32 of a transistor 34. Vias 36 and metal layers 38 provide electrical connections and wiring within the chiplet 20. The metal layers 38 are separated by dielectric layers 40 (typically silicon oxide layers). The transistors 34, along with other components (not shown) of the chiplet 20, form a driver for driving a MEMS device (not shown).

[0013] 3 shows a schematic plan view of an apparatus 42 (e.g., a printhead or an ultrasonic transducer array) including multiple MEMS devices 4 and chiplets 20 connected to the MEMS devices. The apparatus 42 may be the printhead described in connection with FIG. 1 above. Each chiplet 20 is configured to control a row of MEMS devices 4 in the apparatus 42.

[0014] 4A-4D show successive schematic cross-sectional views of a semiconductor structure 2 during processing. In this embodiment, chiplets 20 with drivers 18 are transfer printed onto a MEMS wafer midway through MEMS processing. Specifically, the chiplets 20 are transfer printed after the piezoelectric elements 14 are formed and before the cavities 16 and apertures 12 that complete the formation of the membrane 8 are formed.

[0015] 4A, a semiconductor substrate 6 (i.e., a MEMS wafer) is structured to form piezoelectric elements 14 and associated electronics (not shown) on a membrane layer 10 (e.g., comprising silicon oxide). Trenches 25 are formed in the dielectric layer 23 and membrane layer 10 and may extend into the substrate 6. For example, for thicker chiplets 20, trenches 25 in the substrate 6 may be required, while for thinner chiplets 20, trenches 25 may be shallower. For example, trenches 25 may be formed by photolithography and etching using a photoresist mask.

[0016] In FIG. 4B, chiplets 20 are transfer printed onto substrate 6 in trenches 25. Chiplets 20 include circuitry 17, including drivers 18. For example, chiplets 20 may be the chiplets described in connection with FIG. 2 above. Chiplets 20 may be formed in a CMOS process, for example, on a silicon-on-insulator (SOI) substrate. Chiplets 20 are positioned in trenches 25 to keep the front (top) surface of the printhead flat and compatible with printer applications requiring printhead wiping.

[0017] 4C, RDLs 22 are formed to connect chiplets 20 to piezoelectric elements 14. A passivation layer 24 is deposited over dielectric layer 23 and chiplets 20. Passivation layer 24 may comprise silicon oxide. One or more openings 27 are formed in passivation layer 24 for connection to chiplets 20.

[0018] In FIG. 4D , a cavity 16 and aperture 12 are formed to release the membrane 8 to provide the MEMS device 4. For example, the substrate 6 is back-etched to form the cavity 16. One or more additional etching steps may be used to provide the aperture 12. The MEMS process / sequence may be divided into pre- and post-microimprint steps, which may help ensure that the final device has appropriate coating and fluidic properties. While the piezoelectric elements (e.g., piezo stacks) are provided before the microimprint process, membrane structuring, which involves significant etching on the front and / or backside of the wafer, occurs after the microimprint process. Because thinned wafers with large etching volumes are fragile, it may be advantageous to perform the relevant process steps as late as possible. Additionally, providing the actuators first may avoid thermal stress on the microimprinted chiplets 20.

[0019] In general, micro-transfer printing is a wafer-level process in which chiplets are extracted from a donor wafer (also referred to as a native or source wafer / substrate) and attached onto a target wafer. RDLs are then formed to connect the chiplets to structures on the target wafer. Micro-transfer printing allows for the assembly of incompatible technologies onto a single die and also allows for cost improvements when chiplets from expensive technologies (e.g., CMOS) are transferred onto a larger (cheaper) wafer. Wafer-level integration methods also allow for the efficient implementation of a large number of connections between the wafer and the chiplets.

[0020] While the MEMS device 4 with mechanical actuators is relatively large and the manufacturing process involves a small number of layers (e.g., less than 10), the chiplet 20 may have only a small number of high-voltage transistors made with a complex process on an expensive SOI substrate and using 40 or more mask layers.

[0021] Micro-transfer printing allows combining the two dies in an efficient manner. With CMOS chiplets transferred onto a MEMS wafer, a high-density CMOS design can be connected to a larger, lower-density MEMS die. Furthermore, the direct, high-density connection using RDLs (without off-chip wires) allows the integration of large arrays of actuators that must be individually controlled by CMOS drivers. In this case, the entire system looks like an integrated CMOS / MEMS wafer.

[0022] MEMS can benefit from large feature sizes, large die, and low complexity. CMOS, a complex and expensive process, can provide high-performance transistors for individual actuator control. High-voltage transistors can be used to provide the correct waveforms to the MEMS device 4, while low-voltage transistors can be used for the control logic and serial / parallel interface. This significantly reduces the wiring burden. RDLs associated with micro-transfer printing integration can replace discrete wiring with a relatively small pitch compatible with large arrays.

[0023] 5A-5D show successive schematic cross-sectional views of a semiconductor structure 2 during processing according to another embodiment, where chiplets 20 are transfer printed onto a target substrate 6 prior to MEMS processing.

[0024] 5A, a semiconductor substrate 6 is provided with a membrane layer 10. A trench 25 is formed in the membrane layer 10. The trench may extend into the substrate 6.

[0025] 5B, chiplets 20 including drivers 18 are transfer printed onto substrate 6. An adhesive layer 26 may be provided between chiplets 20 and substrate 6.

[0026] 5C, a MEMS structure including piezoelectric elements 14 is formed on membrane layer 10, and RDLs 22 are formed to connect chiplets 20 to piezoelectric elements 14. A passivation layer 24 is provided, and a plurality of openings 27 are formed in the passivation layer to connect to RDLs 22.

[0027] 5D, the cavity 16 and aperture 12 are formed to release the membrane 8 to provide / complete the MEMS device 4. For example, the substrate 6 is back-etched to form the cavity 16. One or more further etching steps can be used to provide the aperture 12.

[0028] 6A-6C show successive schematic cross-sectional views of a semiconductor structure 2 during processing according to another embodiment, where chiplets 20 are transfer printed onto a target substrate 6 after forming MEMS devices 4 on / in the substrate 6.

[0029] 6A, a MEMS device 4 including a piezoelectric element 14 and a membrane 8 is formed in / on a semiconductor substrate 6. An upper dielectric layer 23 is formed on the membrane layer 10. A trench 25 is formed in the dielectric layer 23 and the membrane layer 10. The trench may extend into the substrate 6.

[0030] 6B, chiplet 20 with driver 18 is transfer printed onto substrate 6 in trench 25. An adhesive layer 26 may be provided between chiplet 20 and substrate 6.

[0031] 6C, RDLs 22 are formed to connect chiplets 20 to MEMS devices 4, allowing drivers 18 to drive MEMS devices 4 by applying voltages to piezoelectric elements 14. A passivation layer 24 is provided over chiplets 20 and MEMS devices 4. One or more openings 27 are formed in passivation layer 24 to provide connections to chiplets 20 through RDLs 22.

[0032] 7 shows a schematic diagram of a portion of a semiconductor structure including a piezoelectric element 14. The piezoelectric element 14 includes a stack having a top electrode 28 and a bottom electrode 30 that sandwich a piezoelectric material 32 (e.g., PZT). The piezoelectric element is disposed on a membrane layer 10 and is positioned to actuate (e.g., bend) the membrane when a voltage is applied between the electrodes 28 and 30. The top electrode 28 is connected to a metal layer 34, which connects the piezoelectric element 14 to a chiplet (not shown) through a RDL (not shown). The piezoelectric element 14 is covered by a dielectric layer 23 and a passivation layer 24.

[0033] In general, according to a first aspect, embodiments described herein provide a method of forming a semiconductor construction, the method comprising: providing a semiconductor substrate; forming a microelectromechanical structure (MEMS) device in and / or on a semiconductor substrate; providing a semiconductor chiplet including circuitry configured to provide input to and / or process output from a MEMS device; micro-transfer printing semiconductor chiplets onto a semiconductor substrate; connecting the driver to the MEMS device; Includes:

[0034] The semiconductor structure may be part of a print head, a capacitive MEMS ultrasonic transducer (CMUT), a piezoelectric MEMS ultrasonic transducer (PMUT), or other device incorporating MEMS technology. Print heads, CMUTs, and PMUTs all include an array of MEMS devices, each including a displaceable membrane and an actuator for displacing the membrane. For example, in the case of a PMUT, the MEMS device includes a piezoelectric element for displacing the membrane to generate ultrasonic waves. The semiconductor substrate may be referred to as the target substrate (on which the chiplets are transfer printed). The semiconductor substrate may also be referred to as a MEMS wafer, since MEMS devices are formed in and / or on the semiconductor substrate. Typically, the membrane of a MEMS device is formed by back-etching the semiconductor substrate. This allows for efficient combination of MEMS technology with other (more costly / complex) technologies (e.g., CMOS).

[0035] The method may include forming a plurality of additional MEMS devices in and / or on the semiconductor substrate, where the chiplets include a corresponding plurality of circuits that drive the plurality of additional MEMS devices and / or process output from the plurality of additional MEMS devices. For example, each chiplet may include a plurality of drivers associated with a respective MEMS device, and the method may include micro-transfer printing a plurality of such chiplets onto the same semiconductor substrate. For example, each chiplet may include five to ten drivers.

[0036] The circuit(s) typically include multiple CMOS devices, e.g., transistors such as high voltage transistors formed in a CMOS process.

[0037] The step of providing a semiconductor chiplet includes: providing a second semiconductor substrate; forming a circuit including one or more semiconductor devices in and / or on the second semiconductor substrate; performing an etching process to release the semiconductor chiplets from the second semiconductor substrate; may include:

[0038] The second semiconductor substrate can be a silicon-on-insulator (SOI) substrate. The second substrate is the native substrate of the chiplet and is formed on top of the chiplet before being lifted off during the micro-transfer printing process. The SOI substrate includes a silicon handle wafer and an epitaxial silicon layer (also called the active silicon layer), which are separated by an oxide layer (called the buried oxide, BOX, layer). During the micro-transfer printing process, the chiplet is lifted off from the native substrate.

[0039] The micro-transfer printing process may include forming trenches on and / or in a substrate and placing semiconductor chiplets in the trenches. For example, the trenches may be formed in a membrane layer, optionally in one or more dielectric layers on the semiconductor substrate. The trenches may extend into the semiconductor substrate and may be lined with silicon oxide. The chiplets may be attached directly to the semiconductor substrate (or to the silicon oxide layer lining the trenches) using, for example, an adhesive layer.

[0040] Connecting the drivers to the MEMS devices typically involves forming a redistribution layer (RDL). The RDL may be formed by depositing a metal layer (e.g., copper) over the chiplets and MEMS structures and patterning the metal layer to form metal lines. Alternatively, connecting the drivers to the MEMS devices may involve a micro-transfer printing process followed by deposition of a dielectric or organic material, followed by planarization, via etching, and standard metal deposition or lift-off.

[0041] The process of forming a MEMS device in and / or on a semiconductor substrate comprises: providing an actuator on a semiconductor substrate; Etching the semiconductor substrate to form a membrane; The actuator may include a piezoelectric element. For example, the piezoelectric element may include a so-called piezo stack, which includes a piezoelectric material sandwiched between two electrodes. The electrodes may then be connected to a driver via a RDL. The piezoelectric material may be, for example, PZT or Al(Sc)N.

[0042] The step of micro-transfer printing the semiconductor chiplets may occur after the step of providing the actuators and before the step of etching the semiconductor substrate to form the membrane.

[0043] Alternatively, the step of micro-transfer printing the semiconductor chiplets may occur before the step of forming the MEMS device, i.e., the chiplets may be transfer printed onto the substrate before any MEMS processing.

[0044] Alternatively, the step of micro-transfer printing the semiconductor chiplets can occur after the step of forming the MEMS device, i.e., the MEMS device is fully formed (without driver electronics) and then the chiplets are provided on the substrate and then connected to the MEMS device.

[0045] The MEMS device may include a membrane configured to actuate a fluid (e.g., ink in the case of an inkjet printhead) in contact with the membrane. For example, the MEMS device may include a membrane that provides a nozzle for an inkjet printhead and includes an aperture for ejecting ink. In another embodiment, the nozzle may be located elsewhere (not formed directly on the membrane) and the membrane may be used to pump ink to the nozzle. The method may include applying an ink coating to the MEMS device. For example, the ink coating may include a hydrophobic coating layer.

[0046] According to a second aspect, embodiments described herein provide a semiconductor construction, the semiconductor construction comprising: a semiconductor substrate; a MEMS device disposed in and / or on a semiconductor substrate; a chiplet attached to a semiconductor substrate; and the chiplet includes circuitry coupled to the MEMS device and configured to provide input to and / or process output from the MEMS device.

[0047] The semiconductor construction may be formed according to the method according to the first aspect described above.

[0048] The circuitry may include a driver that drives the MEMS device and / or a sensor circuit that senses the MEMS device.

[0049] The MEMS device may include an actuator and a membrane including a portion of the membrane layer, the actuator being configured to actuate the membrane. The driver may include a plurality of complementary metal-oxide semiconductor (CMOS) devices. For example, the driver may include a plurality of high-voltage transistors.

[0050] The chiplet may comprise a portion of a silicon-on-insulator (SOI) substrate. That is, the chiplet may be formed on / in an SOI substrate, which is the chiplet's native substrate. A portion of this SOI substrate is lifted to provide the chiplet. The chiplet may be attached to the substrate by an adhesive layer. Preferably, the chiplet is disposed in a trench on the semiconductor substrate. The trench may extend through one or more layers on the semiconductor substrate and into the semiconductor substrate. This allows for a flatter topography, which may be particularly beneficial for printheads. The chiplet may also be formed on other types of semiconductor substrates, such as GaN or SiC.

[0051] While specific embodiments of the invention have been described above, it will be understood that the invention may be practiced otherwise than as described. The above description is intended to be illustrative, not limiting. It will be apparent to those skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set forth below.

[0052] Each feature disclosed or illustrated herein may be incorporated into the present invention alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

1. 1. A method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a microelectromechanical structure (MEMS) device in and / or on the semiconductor substrate; providing a semiconductor chiplet including circuitry configured to provide input to and / or process output from the MEMS device; micro-transfer printing the semiconductor chiplets onto the semiconductor substrate; connecting the circuit to the MEMS device; A method comprising:

2. The method of claim 1 , wherein the circuitry includes a driver for driving the MEMS device and / or a sensor circuit for sensing at the MEMS device.

3. forming a plurality of additional MEMS devices in and / or on the semiconductor substrate; 3. The method of claim 1 or 2, wherein the semiconductor chiplet includes a corresponding plurality of further circuits configured to provide input to and / or process output from the plurality of further MEMS devices.

4. The method of claim 1 , wherein the circuit comprises a plurality of CMOS devices.

5. The step of providing a semiconductor chiplet comprises: providing a second semiconductor substrate; forming a circuit including one or more semiconductor devices in and / or on the second semiconductor substrate; performing an etching process to release the semiconductor chiplets from the second semiconductor substrate; 5. The method of claim 1, comprising:

6. The method of claim 5 , wherein the second semiconductor substrate is a silicon-on-insulator (SOI) substrate.

7. micro-transfer printing the semiconductor chiplets, forming a trench on and / or in the substrate; placing the semiconductor chiplet in the trench; The method of any one of claims 1 to 6, comprising:

8. The method of any one of claims 1 to 7, wherein connecting the circuitry to the MEMS device comprises forming a redistribution layer (RDL).

9. forming the MEMS device in and / or on the semiconductor substrate, providing an actuator on the semiconductor substrate; 9. The method of claim 1, further comprising etching the semiconductor substrate to form a membrane, the actuator being arranged to actuate the membrane.

10. The method of claim 9 , wherein the actuator comprises a piezoelectric element.

11. 11. The method of claim 9 or 10, wherein the step of micro-transfer printing the semiconductor chiplets occurs after the step of providing the actuators and before the step of etching the semiconductor substrate to form the membrane.

12. 11. The method of claim 1, wherein the step of micro-transfer printing the semiconductor chiplets occurs before the step of forming the MEMS device.

13. 11. The method of claim 1, wherein the step of micro-transfer printing the semiconductor chiplets occurs after the step of forming the MEMS device.

14. the MEMS device includes a membrane; The method of claim 1 , wherein the membrane is configured to actuate a fluid in contact with the membrane.

15. The method of claim 14 further comprising applying an ink coating to the MEMS device.

16. 1. A semiconductor structure comprising: a semiconductor substrate; a MEMS device disposed in and / or on the semiconductor substrate; a chiplet attached to the semiconductor substrate; Including, The chiplet is a semiconductor construction including circuitry coupled to the MEMS device and configured to provide input to and / or process output from the MEMS device.

17. 17. The semiconductor construction of claim 16, wherein the circuitry includes a driver for driving the MEMS device and / or a sensor circuit for sensing with the MEMS device.

18. The MEMS device is An actuator; a membrane containing a portion of the membrane layer; Including, 18. The semiconductor construction of claim 16 or 17, wherein the actuator is configured to actuate the membrane.

19. 20. The semiconductor structure of claim 18, wherein the actuator comprises a piezoelectric element.

20. 20. The semiconductor construction of claim 18 or 19, wherein the MEMS device comprises an ink coating on at least a portion of the membrane.

21. 21. The semiconductor construction of any one of claims 16 to 20, wherein the circuitry comprises a plurality of complementary metal oxide semiconductor (CMOS) devices.

22. 22. The semiconductor construction of any one of claims 16 to 21, wherein the chiplet comprises a portion of a silicon-on-insulator (SOI) substrate.

23. 23. The semiconductor construction of any one of claims 16 to 22, wherein the chiplets are attached to the substrate by an adhesive layer.

24. 24. The semiconductor construction of claim 16, wherein the chiplets are disposed in trenches above the semiconductor substrate.

25. An inkjet printhead comprising a semiconductor structure according to any one of claims 16 to 24.

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