Two row driving method and pixel array driver for microdisplay device

Abstract

To provide a method for reducing power consumption of a microdisplay.SOLUTION: The method for driving the pixel array includes a process for supplying a ramp signal to one or more columns of the pixel array 608, and a process for supplying a first row driving signal to a first row of the pixel array 608 and supplying a second row driving signal to a second row of the pixel array for each cycle of the ramp signal. The method can further include providing a first amplifier 604 and a second amplifier 606, the first and second amplifiers 604606, each receiving the input ramp signal from the DAC, the first amplifier 604 generating a first amplified ramp signal, and the second amplifier 606 generating a second amplified ramp signal.SELECTED DRAWING: Figure 6

Description

Related Applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 243,411, filed October 19, 2015, and U.S. Provisional Patent Application No. 62 / 247,327, filed October 28, 2015, the entire teachings of which are incorporated herein by reference. [Background technology]

[0002] Mobile computing devices, such as notebook PCs, smartphones, and tablet computing devices, have become everyday tools for generating, analyzing, communicating, and consuming data in both business and personal life. Consumers continue to embrace a mobile digital lifestyle, driven by increasingly easy access to digital information as high-speed wireless communication technologies become ubiquitous. A common use for mobile computing devices is to display large amounts of high-resolution computer graphics information and video content, often streamed wirelessly to the device for display.

[0003] Although these devices typically have a display screen, the physical size of the device itself is limited to promote mobility. This makes it difficult for these mobile devices to replicate the more pleasing visual experience of a large, high-resolution display. Another drawback of these types of devices is that the user interface relies on the human hand. Typically, users are required to enter data or make selections using a (physical or virtual) keyboard or touchscreen display.

[0004] Therefore, today's consumers desire hands-free, high-quality, portable color display solutions to supplement or replace mobile devices that rely on the human hand. Such display solutions are constrained by practical size and weight, which limits available power resources (e.g., battery size, etc.). Because power resources are limited, reducing the display's power consumption extends the amount of time the display can operate on a single charge of that power resource.

[0005] Some types of display devices require a periodic ramp signal to be applied to the columns of pixels in the array for operation. The power requirements of the ramp signal generator can depend on many factors, but two main factors often include (i) the number of pixels in the display, and (ii) the frequency of the ramp signal. Thus, for a fixed display size, the power requirements of the ramp signal generator, and therefore the display device, will be strongly affected by the lamp frequency.

[0006] State-of-the-art display applications require high lamp signal frequencies and therefore have high power requirements for the reasons discussed above.

[0007] Recently developed microdisplays can provide large-format, high-resolution color images and streaming video in extremely small form factors. Applications for such displays include integration into wireless headset computers worn on a user's head, similar to eyeglasses or audio or video eyewear, to keep the display within the user's field of view.

[0008] A "wireless computing headset" device (also referred to herein as a headset computer (HSC) or head-mounted display (HMD)) includes at least one small, high-resolution microdisplay and image magnification optics. Such high-resolution microdisplay may provide Super Video Graphics Array (SVGA) (800x600) or Extended Graphics Array (XGA) (1024x768) resolution, or greater, as known in the art.

[0009] A wireless computing headset has at least one wireless computing and communications interface that enables data and video streaming capabilities, providing greater convenience and mobility over a device that relies on the human hand.

[0010] For more information regarding such devices, see co-pending U.S. patent application Ser. No. 12 / 348,646, filed Jan. 5, 2009, entitled "Mobile Wireless Display Software Platform for Controlling Other Systems and Devices," International Application No. PCT / US09 / 38601, filed Mar. 27, 2009, entitled "Handheld Wireless Display Devices Having High Resolution Display Suitable For Use as a Mobile Internet Device," and U.S. Provisional Patent Application Ser. No. 61 / 638,419, filed Apr. 25, 2012, entitled "Improved Headset Computer," the entire contents of each of which are incorporated herein by reference.

[0011] In this specification, "HSC" (headset computer), "HMD" (head mounted display) device, and "wireless computing headset" device may be used interchangeably. Summary of the Invention [Problem to be solved by the invention]

[0012] The embodiments described herein reduce the power of a microdisplay (e.g., a microdisplay provided in an HSC) by at least one of: (i) lowering the frequency of the ramp signals used to drive columns of the pixel array of the microdisplay; and (ii) increasing the number of rows of the array that are driven per cycle of such column drive ramp signals. [Means for solving the problem]

[0013] In one aspect, the invention may be a method of driving a pixel array, comprising applying a ramp signal to one or more columns of the pixel array, wherein, for each cycle of the ramp signal, a first row drive signal is applied to a first row of the pixel array and a second row drive signal is applied to a second row of the pixel array.

[0014] One embodiment further includes providing a first amplifier and a second amplifier, each receiving an input ramp signal from a digital-to-analog converter, the first amplifier generating a first amplified ramp signal, and the second amplifier generating a second amplified ramp signal. The first amplifier and the second amplifier may be unity-gain (i.e., gain equal to 1) amplifiers, although the gain of these amplifiers may be a fraction less than 1 (i.e., between 0 and 1) or greater than 1.

[0015]

[0010] Another embodiment may further include connecting an output of the first amplifier to a first set of pixels of a pixel array and connecting an output of the second amplifier to a second set of pixels of the pixel array. The first set of pixels of the pixel array may be a first set of pixel columns, and the second set of pixels of the pixel array may be a second set of pixel columns. The first set of pixel columns and the second set of pixel columns may be spatially arranged on the pixel array (i.e., on a base that receives the pixel array, such as on a substrate) such that columns in the first set of pixel columns alternate with columns in the second set of pixel columns.

[0016] An embodiment may further comprise providing the first amplified ramp signal to the first set of pixels of the pixel array and providing the second amplified ramp signal to the second set of pixels of the pixel array.

[0017] In one embodiment, the method further comprises connecting an output of the first amplifier to a first set of pixels of a pixel array and connecting an output of the second amplifier to a second set of pixels of the pixel array. The first set of pixels of the pixel array may be a first set of pixel rows (out of a total of N pixel rows in the pixel array), and the second set of pixels of the pixel array may be a second set of pixel rows (out of a total of N rows in the pixel array). The first set of pixel rows includes pixels from rows 1 through M, and the second set of pixels includes pixels from rows M+1 through N, where M and N are integers.

[0018] One embodiment further comprises providing the first amplified ramp signal to the first set of pixel rows and providing the second amplified ramp signal to the second set of pixel rows.

[0019] Another embodiment further comprises connecting an output of the first amplifier to a first set of pixels of a pixel array and connecting an output of the second amplifier to a second set of pixels of the pixel array, wherein the first set of pixels of the pixel array is a first set of pixel rows and the second set of pixels of the pixel array is a second set of pixel rows, and the first set of pixel rows and the second set of pixel rows are spatially arranged on the pixel array such that rows in the first set of pixel rows alternate with rows in the second set of pixel rows.

[0020] One embodiment comprises providing a digital to analog converter configured to generate the ramp signal.

[0021] In another aspect, the present invention may be a pixel array driver comprising: a ramp signal generator configured to generate a ramp signal; a first amplifier configured to receive the ramp signal and generate a first amplified ramp signal; and a second amplifier configured to receive the ramp signal and generate a second amplified ramp signal, wherein the first amplified ramp signal may be electrically connected to a first set of pixels of a pixel array, and the second amplified ramp signal may be electrically connected to a second set of pixels of the pixel array.

[0022] In one embodiment, the first set of pixels of the pixel array is a first set of pixel columns and the second set of pixels of the pixel array is a second set of pixel columns, and the first set of pixel columns and the second set of pixel columns may be spatially arranged on the pixel array (i.e., with respect to the physical layout of the pixels) such that columns in the first set of pixel columns alternate with columns in the second set of pixel columns.

[0023] In other embodiments, the first set of pixel columns includes the Nth pixel column and the second set of pixel columns includes the (N+1)th pixel column, where N is two or more consecutive even numbers starting with 2. It should be understood that in all embodiments described herein, the total number of pixels (and therefore the number of pixel columns) is finite and is constrained by the size and shape of the display device.

[0024] In another embodiment, the first set of pixel columns receives the first amplified ramp signal and the second set of pixel columns receives the second amplified ramp signal.

[0025] In one embodiment, the first set of pixels and the second set of pixels of the pixel array are arranged in N rows, the first set of pixels including pixels in rows 1 to M, and the second set of pixels including pixels in rows M+1 to N, where M and N are integers.

[0026] 15. The pixel array driver according to claim 14, wherein the pixels in the 1st to Mth rows receive the first amplified ramp signal, and the pixels in the (M+1)th to Nth rows receive the second amplified ramp signal.

[0027] In another embodiment, the first set of pixels of the pixel array is a first set of pixel rows, and the second set of pixels of the pixel array is a second set of pixel rows. The first set of pixel rows and the second set of pixel rows may be spatially arranged on the pixel array such that rows in the first set of pixel rows alternate with rows in the second set of pixel rows. For example, the first set of pixel rows may include a first row, a third row, a fifth row, etc., and the second set of pixel rows may include a second row, a fourth row, a sixth row, etc. Pixels in the first set of pixel rows may receive the first amplified ramp signal, and pixels in the second set of pixel rows may receive the second amplified ramp signal.

[0028] In another embodiment, the ramp signal generator includes a digital-to-analog converter. The ramp signal generator may further include a counter configured to generate a digital word and provide the digital word to the digital-to-analog converter, the digital word counting from an initial value to an end value, returning to the initial value and repeating the counting from the initial value.

[0029] In another embodiment, the first and second amplifiers are unity gain amplifiers.

[0030] The foregoing will become apparent from the following more detailed description of exemplary embodiments of the invention, as illustrated in the accompanying drawings. Like reference characters refer to like structures / components throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the invention. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 illustrates a simple example of a microdisplay according to some embodiments. [Figure 2] FIG. 10 illustrates an example of a lamp DAC arrangement. [Figure 3] 3 is an example timing diagram of signals that may be used to drive the pixel array shown in FIG. 2. [Figure 4] FIG. 10 illustrates another example of a lamp DAC arrangement constructed in accordance with an embodiment of the disclosure. [Figure 5] 5 is an example timing diagram of signals that may be used to drive the pixel array shown in FIG. 4. [Figure 6] FIG. 10 illustrates yet another example of a lamp DAC arrangement constructed in accordance with an embodiment of the disclosure. [Figure 7] FIG. 7 is an example timing diagram of signals that may be used to drive the pixel array shown in FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0032] In the following, exemplary embodiments of the present invention are described.

[0033] The microdisplays described herein generally comprise a pixel array 102 driven by a plurality of data and control signals 103, as shown in the simplified example of Figure 1. For ease of understanding the following discussion, the exemplary microdisplay 100 will be described as having 20 columns and 16 rows for a total of 320 pixels, although, as noted above, actual microdisplays will typically have many more pixels (e.g., XGA with 1024 columns and 768 rows).

[0034] The microdisplay includes a column driver 104 and a row driver 106 that cooperate to provide information to a pixel array 102. The column driver 104 may provide image information to the pixels, and the row driver 106 may provide control information to the pixels. The column drive signal 108 for a particular pixel column 110 may include multiple signals.

[0035] In some embodiments, such as liquid crystal on silicon (LCoS), organic light emitting diode (OLED) display devices, the column driver 104 shown in Figure 1 may include a ramp digital-to-analog converter (DAC) and an amplifier. The column driver 104 generates a voltage ramp signal.

[0036] This voltage ramp signal may be a periodic signal that repeats a linear increase from a first voltage to a second voltage (see, for example, FIG. 3), and this voltage ramp may be sampled at specific times and held to produce a desired constant voltage output for use by the pixel column.

[0037] The DAC may be a device that accepts a digital word (e.g., 8-bit, 16-bit, 32-bit, etc.) representing a binary value. The DAC generates a voltage output corresponding to the value of the digital word. For example, a voltage ramp signal may be generated by having the digital word count sequentially from a low value to a high value (e.g., from 00000000 to 11111111) and periodically repeating the count. For example, in one embodiment, a counter programmed to count from an initial value to an end value and then configured to return to the initial value and repeat may be used to generate such a sequence of digital words.

[0038] The amplifier may receive the voltage ramp signal from the DAC and generate an output signal that is an amplified version of the received voltage ramp signal, i.e., amplifier output = g x (voltage ramp signal), where g is the gain of the amplifier. In some embodiments, the amplifier gain g is a positive real number greater than 1, while in other embodiments the gain g may be between 0 and 1.

[0039] 2 illustrates an example of a lamp DAC arrangement that includes a single lamp DAC 202 driving a first amplifier 204 and a second amplifier 206. In this embodiment, the amplifiers 204, 206 are arranged to drive a pixel array 208 from two portions of the array 208. The arrangement of pixels in the array 208 shown in FIG. 2 is intended to represent the physical arrangement (i.e., physical layout) of the pixels. In this example, the two outlined portions of the pixel array are identified as the top and bottom of the pixel array, although other arrangements of outlined portions may alternatively be employed.

[0040] Figure 3 is an example timing diagram of signals that may be used to drive pixel array 208 of Figure 2. In this example, a 120 Hz HSYNC ramp signal 302 is generated by ramp DAC 202 and relayed to the pixels in pixel array 208 via amplifiers 204, 206. Only one row is driven with each cycle of ramp signal 302. In this example, signal 304 (i.e., row N drive signal) driving row N is active during the first cycle (of the depicted image) of ramp signal 302, signal 306 (i.e., row N+1 drive signal) driving row N+1 is active during the second cycle (of the depicted image) of ramp signal 302, signal 308 (i.e., row N+2 drive signal) driving row N+2 is active during the third cycle (of the depicted image) of ramp signal 302, and signal 310 (i.e., row N+3 drive signal) driving row N+3 is active during the fourth cycle (of the depicted image) of ramp signal 302. The period of a 120 Hz ramp signal is 1 / 120 seconds = 8.333 milliseconds (milliseconds), so it takes approximately 4 × 8.33 mS = approximately 33.33 mS to drive four pixel rows.

[0041] FIG. 4 illustrates another example of a lamp DAC arrangement constructed in accordance with disclosed embodiments, including a single lamp DAC 402 driving a first amplifier 404 and a second amplifier 406. In this embodiment, amplifiers 404, 406 are arranged to drive a pixel array 408 from two sides of the array 408 (the top and bottom of the array 408, as in the example of FIG. 2). However, in the example of FIG. 4, amplifiers 404, 406 each drive a portion of each column (half of each column in this case). That is, amplifier 404 and amplifier 406 share responsibility for driving the same pixel column. In other embodiments, the amplifiers may drive more or less than half of the column.

[0042] In the exemplary embodiment of Figure 4, the signal driving the Tth (top) row (i.e., row T drive signal) and the signal driving the Bth (bottom) row (i.e., row B drive signal) are active during the first ramp cycle, similar to the interaction of the ramp signal 302 and row N drive signal 304 shown in Figure 3. The signal driving the T+1th (top) row (i.e., row T+1 drive signal) and the signal driving the B+1th (bottom) row (i.e., row B+1 drive signal) are active during the second ramp cycle, similar to the interaction of the ramp signal 302 and row N+1 drive signal shown in Figure 3. The signal driving the T+2th (top) row (i.e., row T+2 drive signal) and the signal driving the B+2th (bottom) row (i.e., row B+2 drive signal) are active during the third ramp cycle, similar to the interaction of the ramp signal 302 and row N+2 drive signal shown in Figure 3.

[0043] Because the configuration shown in FIG. 4 allows two rows (e.g., rows T and B, rows T+1 and B+1, etc.) to be driven simultaneously, the entire array can be driven with less power than the array configuration shown in FIG. 2. FIG. 5 is an exemplary timing diagram of signals that may be used to drive the pixel array 408 of FIG. 4. In this example, a 60 Hz HSYNC ramp signal 502 is generated by the ramp DAC 402 and relayed to the pixels in the pixel array 408 via amplifiers 404 and 406. As shown in the timing diagram of FIG. 5, the ramp signal 502 may be at half the frequency (i.e., 60 Hz) of the ramp signal 302 of FIGS. 2 and 3, since two rows are driven for each cycle of the ramp signal 502. The signal 504 driving row T and the signal 506 driving row B are each active during the first cycle (of the one depicted) of the ramp signal 502. Signals 508 and 510 driving rows T+1 and B+1 are each active during the second cycle (as depicted) of ramp signal 502 .

[0044] The period of a 60 Hz ramp signal is 1 / 60th of a second = 16.66 mS, but because two rows are driven for each cycle of the ramp signal 502, it takes approximately 2 x 16.66 mS = approximately 33.33 mS to drive four rows. Therefore, the arrangements shown in Figures 4 and 5 take the same amount of time to drive four rows as the arrangements shown in Figures 2 and 3. However, because the arrangements of Figures 4 and 5 use ramp signal 502 at half the frequency of ramp signal 302 used in the arrangements of Figures 2 and 3, the arrangements of Figures 4 and 5 require less power.

[0045] Figure 6 shows yet another example of a ramp DAC arrangement constructed in accordance with disclosed embodiments, including a single ramp DAC 602 driving a first amplifier 604 and a second amplifier 606. In this embodiment, amplifiers 604, 606 are arranged to drive a pixel array 608 from two sides of the array 608 (from the top and bottom of the array, as in the example of Figure 2). However, in the example of Figure 6, amplifier 604 drives the odd rows (e.g., rows 1, 3, 5, ...) and amplifier 606 drives the even rows (e.g., rows 2, 4, 6, ...). The timing diagram shown in Figure 7 applies to the arrangement shown in Figure 6 and is similar to the timing diagram shown in Figure 5.

[0046] The arrangement shown in FIG. 6 offers many advantages. Pixels can be accepted in standard scan order, requiring only one line buffer of memory. FIG. 4 requires one half-frame buffer, adding latency that is highly undesirable for virtual reality (VR) applications. The arrangement of FIG. 6 relaxes the constraints on matching amplifiers 604, 606 because mismatches between even and odd rows are much less perceptible than mismatches between the top and bottom half of the image. The arrangement of FIG. 6 reduces motion artifacts because all rows are scanned nearly simultaneously with their neighbors. In contrast, the arrangement of FIG. 4 scans row T+2 significantly after row B. Because adjacent rows share row lines in the arrangement of FIG. 6, only half the pitch is required per row.

[0047] The layout configuration in Figure 6 requires a column line pitch of two lines per column, which inevitably makes the column lines longer and increases capacitance slightly, but the number of pixels per column line remains the same compared to the architecture shown in Figure 4.

[0048] The exemplary embodiments herein demonstrate the disclosed subject matter by doubling the number of rows driven while halving the lamp frequency. It should be understood that the lamp frequency and number of pixel rows may be changed otherwise (i.e., other than a combination of doubling and halving) to maintain the same number of pixels driven per unit time and consume less power while still following the concepts underlying the disclosed embodiments.

[0049] It will be apparent that one or more embodiments described herein may be implemented in many different forms of software and hardware. The software code and / or specialized hardware used to implement the embodiments described herein is not a limitation of the present invention. For this reason, the operation and behavior of the embodiments have been described without reference to specific software code and / or specialized hardware. Those skilled in the art will be able to design software and / or hardware to implement these embodiments based on the description herein.

[0050] Certain embodiments of the present invention may also be implemented as logic that performs one or more functions. This logic may be hardware-based, software-based, or a combination of hardware and software-based. Some or all of the logic may be stored on one or more tangible computer-readable storage media and may include computer-executable instructions executed by a controller or processor. The computer-executable instructions may include instructions that implement one or more embodiments of the present invention. The tangible computer-readable storage media may be volatile or non-volatile, and may include, for example, flash memory, dynamic memory, removable disks, non-removable disks, etc.

[0051] While the present invention has been particularly shown and described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention as encompassed by the appended claims. The present invention includes the following embodiments. [Aspect 1] 1. A method of driving a pixel array, comprising: applying a ramp signal to one or more columns of the pixel array; providing a first row drive signal to a first row of the pixel array and a second row drive signal to a second row of the pixel array for each cycle of the ramp signal; A method comprising: [Aspect 2] The method of embodiment 1, further comprising: providing a first amplifier and a second amplifier, each of the first and second amplifiers receiving an input ramp signal from a digital-to-analog converter, the first amplifier generating a first amplified ramp signal, and the second amplifier generating a second amplified ramp signal; A method comprising: Aspect 3 3. The method of claim 2, wherein the first amplifier and the second amplifier are unity gain amplifiers. Aspect 4 The method of embodiment 2 further comprises: connecting the output of the first amplifier to a first set of pixels of a pixel array and connecting the output of the second amplifier to a second set of pixels of the pixel array, wherein the first set of pixels of the pixel array is a first set of pixel columns and the second set of pixels of the pixel array is a second set of pixel columns, the first set of pixel columns and the second set of pixel columns being spatially arranged on the pixel array such that columns in the first set of pixel columns alternate with columns in the second set of pixel columns; A method comprising: Aspect 5 The method of embodiment 4, further comprising: providing the first amplified ramp signal to the first set of pixels of the pixel array and providing the second amplified ramp signal to the second set of pixels of the pixel array; A method comprising: Aspect 6 The method of embodiment 2 further comprises: connecting the output of the first amplifier to a first set of pixels of a pixel array and connecting the output of the second amplifier to a second set of pixels of the pixel array, wherein the first set of pixels of the pixel array is a first set of pixel rows of N rows, the second set of pixels of the pixel array is a second set of pixel rows of N rows, the first set of pixel rows includes pixels from rows 1 to M, and the second set of pixels includes pixels from rows M+1 to N, where M and N are integers; A method comprising: Aspect 7 The method of embodiment 6, further comprising: providing the first amplified ramp signal to the first set of pixel rows and providing the second amplified ramp signal to the second set of pixel rows; A method comprising: Aspect 8 The method of embodiment 2 further comprises: connecting the output of the first amplifier to a first set of pixels of a pixel array and connecting the output of the second amplifier to a second set of pixels of the pixel array, wherein the first set of pixels of the pixel array is a first set of pixel rows and the second set of pixels of the pixel array is a second set of pixel rows, the first set of pixel rows and the second set of pixel rows being spatially arranged on the pixel array such that rows in the first set of pixel rows alternate with rows in the second set of pixel rows; A method comprising: Aspect 9 The method of embodiment 1, further comprising: providing a digital to analog converter configured to generate the ramp signal; A method comprising: Aspect 10 a ramp signal generator configured to generate a ramp signal; a first amplifier configured to receive the ramp signal and generate a first amplified ramp signal; a second amplifier configured to receive the ramp signal and generate a second amplified ramp signal; wherein the first amplified ramp signal is electrically connected to a first set of pixels of a pixel array and the second amplified ramp signal is electrically connected to a second set of pixels of the pixel array. Aspect 11 In the pixel array driver of aspect 10, the first set of pixels of the pixel array is a first set of pixel columns, the second set of pixels of the pixel array is a second set of pixel columns, and the first set of pixel columns and the second set of pixel columns are spatially arranged on the pixel array such that columns in the first set of pixel columns alternate with columns in the second set of pixel columns. Aspect 12 In the pixel array driver of aspect 11, the first set of pixel columns includes an Nth pixel column, and the second set of pixel columns includes an (N+1)th pixel column, where N is two or more consecutive even numbers starting from 2. Aspect 13 12. The pixel array driver of claim 11, wherein the first set of pixel columns receives the first amplified ramp signal, and the second set of pixel columns receives the second amplified ramp signal. Aspect 14 In the pixel array driver described in aspect 10, the first pixel set and the second pixel set of the pixel array are arranged in N rows, the first pixel set includes pixels in rows 1 to M, and the second pixel set includes pixels in rows M+1 to N, where M and N are integers. Aspect 15 In the pixel array driver of aspect 14, the pixels in the 1st to Mth rows receive the first amplified ramp signal, and the pixels in the (M+1)th to Nth rows receive the second amplified ramp signal. Aspect 16 In the pixel array driver of aspect 10, the first set of pixels of the pixel array is a first set of pixel rows, the second set of pixels of the pixel array is a second set of pixel rows, and the first set of pixel rows and the second set of pixel rows are spatially arranged on the pixel array such that rows in the first set of pixel rows alternate with rows in the second set of pixel rows. Aspect 17 17. The pixel array driver of claim 16, wherein pixels of the first set of pixel rows receive the first amplified ramp signal, and pixels of the second set of pixel rows receive the second amplified ramp signal. Aspect 18 11. The pixel array driver of claim 10, wherein the ramp signal generator includes a digital-to-analog converter. Aspect 19 The pixel array driver of aspect 18, further comprising: a counter configured to generate a digital word and provide the digital word to the digital-to-analog converter; wherein the digital word counts from an initial value to an end value, and then returns to the initial value and repeats the counting from the initial value. Aspect 20 11. The pixel array driver of claim 10, wherein the first and second amplifiers are unity gain amplifiers.

Claims

1. 1. A method of driving a pixel array, comprising: providing a common ramp signal to one or more columns of the pixel array; For rows Rw, Rx, Ry, and Rz of the pixel array that are different from each other, simultaneously applying an active second row drive signal to row Rx of the pixel array while applying an active first row drive signal to row Rw of the pixel array during a first cycle of the common ramp signal; during a second cycle of the common ramp signal following the first cycle, simultaneously supplying an active fourth row drive signal to the row Rz of the pixel array while supplying an active third row drive signal to the row Ry of the pixel array; applying voltages as image information directly to pixels of the pixel array, the voltages being generated by sampling the common ramp signal at times corresponding to the image information for each pixel; A method comprising:

2. The method of claim 1 further comprising: providing a first amplifier and a second amplifier, each of the first and second amplifiers receiving an input ramp signal from a digital-to-analog converter, the first amplifier generating a first amplified ramp signal, and the second amplifier generating a second amplified ramp signal; A method comprising:

3. 3. The method of claim 2, wherein the first amplifier and the second amplifier are unity gain amplifiers.

4. The method of claim 2 further comprising: connecting the output of the first amplifier to a first set of pixels of a pixel array and connecting the output of the second amplifier to a second set of pixels of the pixel array, wherein the first set of pixels of the pixel array is a first set of pixel rows of N rows and the second set of pixels of the pixel array is a second set of pixel rows of N rows, the first set of pixel rows including pixels in rows 1 through M, and the second set of pixel rows including pixels in rows M+1 through N, where M and N are integers; wherein the rows Rw and Ry are rows of the first set of pixel rows, and the rows Rx and Rz are rows of the second set of pixel rows.

5. The method of claim 4 further comprising: providing the first amplified ramp signal to the first set of pixel rows and providing the second amplified ramp signal to the second set of pixel rows; A method comprising:

6. The method of claim 2 further comprising: connecting the output of the first amplifier to a first set of pixels of a pixel array and connecting the output of the second amplifier to a second set of pixels of the pixel array, wherein the first set of pixels of the pixel array is a first set of pixel rows and the second set of pixels of the pixel array is a second set of pixel rows, the first set of pixel rows and the second set of pixel rows being spatially arranged on the pixel array such that rows in the first set of pixel rows alternate with rows in the second set of pixel rows; wherein the rows Rw and Ry are rows of the first set of pixel rows, and the rows Rx and Rz are rows of the second set of pixel rows.

7. The method of claim 1 further comprising: providing a digital to analog converter configured to generate the ramp signal; A method comprising:

8. a ramp signal generator configured to generate a common ramp signal; a plurality of row drivers configured to supply voltages as image information directly to pixels of a pixel array, the voltages being generated by sampling the common ramp signal at times corresponding to the image information for each pixel; a first amplifier configured to receive the common ramp signal and generate a first amplified ramp signal; a second amplifier configured to receive the common ramp signal and generate a second amplified ramp signal; Equipped with a pixel array driver, for different rows Rw, Rx, Ry, and Rz of the pixel array, the first amplified ramp signal electrically connected to a first set of pixels of the pixel array and configured to simultaneously drive at least rows Rw and Rx during a first cycle of the amplified ramp signal, and the second amplified ramp signal electrically connected to a second set of pixels of the pixel array and configured to simultaneously drive at least rows Ry and Rz during a second cycle of the amplified ramp signal.

9. 9. The pixel array driver of claim 8, wherein the first pixel set and the second pixel set of the pixel array are arranged in N rows, the first pixel row set includes pixels in rows 1 to M, the second pixel row set includes pixels in rows M+1 to N, M and N are integers, the rows Rw and Ry are rows of the first pixel row set, and the rows Rx and Rz are rows of the second pixel row set.

10. 10. The pixel array driver of claim 9, wherein the pixels in the 1st to Mth rows receive the first amplified ramp signal, and the pixels in the (M+1)th to Nth rows receive the second amplified ramp signal.

11. 9. The pixel array driver of claim 8, wherein the first set of pixels of the pixel array is a first pixel row set, the second set of pixels of the pixel array is a second pixel row set, the first pixel row set and the second pixel row set are spatially arranged on the pixel array such that rows in the first pixel row set alternate with rows in the second pixel row set, the rows Rw and the rows Ry are rows of the first pixel row set, and the rows Rx and the rows Rz are rows of the second pixel row set.

12. 12. The pixel array driver of claim 11, wherein pixels of the first set of pixel rows receive the first amplified ramp signal, and pixels of the second set of pixel rows receive the second amplified ramp signal.

13. 9. The pixel array driver of claim 8, wherein the ramp signal generator comprises a digital to analog converter.

14. 14. The pixel array driver of claim 13, further comprising: a counter configured to generate a digital word and provide the digital word to the digital-to-analog converter; wherein the digital word counts from an initial value to an end value, and then returns to the initial value and repeats the counting from the initial value.

15. 9. The pixel array driver of claim 8, wherein the first and second amplifiers are unity gain amplifiers.

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