Method of manufacturing semiconductor device and wafer structure

Abstract

To provide a method of manufacturing a semiconductor device capable of improving manufacturing efficiency, and to provide a wafer structure.SOLUTION: The method for manufacturing a semiconductor device includes a step of preparing the SiC wafer source 1 and the supporting members 11, 21, a supporting step of supporting the SiC wafer source by the supporting members, and a wafer separating step of cutting the wafer source in a horizontal direction from a middle portion in a thickness direction of the wafer source and separating the SiC wafer structure 35 including the SiC wafer 34 separated from the supporting members and the wafer source from the SiC wafer source 1.SELECTED DRAWING: Figure 3E

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-156603 filed with the Japan Patent Office on September 17, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a method for manufacturing a semiconductor device and a wafer structure. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device, which includes a step of thinning a semiconductor wafer by grinding, and a step of cutting out a plurality of semiconductor chips from the thinned semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-016188 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device manufacturing method and wafer structure that can improve manufacturing efficiency. [Means for solving the problem]

[0005] One embodiment of the present invention provides a method for manufacturing a semiconductor device, including the steps of: preparing a wafer source and a support member; supporting the wafer source with the support member; and cutting the wafer source horizontally from a middle portion of the wafer source in the thickness direction, and separating a wafer structure including the support member and a wafer cut off from the wafer source from the wafer source.

[0006] One embodiment of the present invention provides a method for manufacturing a semiconductor device, including the steps of: preparing a first semiconductor and a second semiconductor; bonding the second semiconductor to the first semiconductor by a direct bonding method to form a semiconductor structure having an amorphous bonding layer between the first semiconductor and the second semiconductor; forming a modified layer in the amorphous bonding layer by a laser light irradiation method; and cleaving the semiconductor structure starting from the modified layer to separate the first semiconductor and the second semiconductor.

[0007] One embodiment of the present invention provides a wafer structure including a first wafer, a second wafer supporting the first wafer, and an amorphous bonding layer interposed between the first wafer and the second wafer and bonding the first wafer and the second wafer together.

[0008] The above and other objects, features and advantages will become more apparent from the following description of the embodiments, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a SiC wafer source, a first support member, and a second support member used in a method for manufacturing a SiC semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device performed on a SiC wafer source. [Figure 3A] FIG. 3A is a cross-sectional view for explaining an example of a method for manufacturing a SiC semiconductor device performed on a SiC wafer source. [Figure 3B] FIG. 3B is a cross-sectional view for explaining a step subsequent to FIG. 3A. [Figure 3C] FIG. 3C is a cross-sectional view for explaining a step subsequent to FIG. 3B. [Figure 3D] FIG. 3D is a cross-sectional view for explaining a step subsequent to FIG. 3C. [Figure 3E] FIG. 3E is a cross-sectional view for explaining a step subsequent to FIG. 3D. [Figure 3F]FIG. 3F is a cross-sectional view for explaining a step subsequent to FIG. 3E. [Figure 3G] FIG. 3G is a cross-sectional view for explaining a step subsequent to FIG. 3F. [Figure 3H] FIG. 3H is a cross-sectional view for explaining a step subsequent to FIG. 3G. [Figure 3I] FIG. 3I is a cross-sectional view for explaining a step subsequent to FIG. 3H. [Figure 4] FIG. 4 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device performed on a wafer structure. [Figure 5A] FIG. 5A is a cross-sectional view for explaining an example of a method for manufacturing a SiC semiconductor device performed on a wafer structure. [Figure 5B] FIG. 5B is a cross-sectional view for explaining a step subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view for explaining a step subsequent to FIG. 5B. [Figure 5D] FIG. 5D is a cross-sectional view for explaining a step subsequent to FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view for explaining a step subsequent to FIG. 5D. [Figure 5F] FIG. 5F is a cross-sectional view for explaining a step subsequent to FIG. 5E. [Figure 5G] FIG. 5G is a cross-sectional view for explaining a step subsequent to FIG. 5F. [Figure 5H] FIG. 5H is a cross-sectional view for explaining a step subsequent to FIG. 5G. [Figure 5I] FIG. 5I is a cross-sectional view for explaining the step subsequent to FIG. 5H. [Figure 5J] FIG. 5J is a cross-sectional view for explaining a step subsequent to FIG. 5I. [Figure 5K] FIG. 5K is a cross-sectional view for explaining a step subsequent to FIG. 5J. [Figure 5L] FIG. 5L is a cross-sectional view for explaining a step subsequent to FIG. 5K. [Figure 5M] FIG. 5M is a cross-sectional view for explaining a step subsequent to FIG. 5L. [Figure 5N] FIG. 5N is a cross-sectional view for explaining a step subsequent to FIG. 5M. [Figure 5O] FIG. 5O is a cross-sectional view for explaining a step subsequent to FIG. 5N. [Figure 5P] FIG. 5P is a cross-sectional view for explaining a step subsequent to FIG. 5O. [Figure 5Q] FIG. 5Q is a cross-sectional view for explaining a step subsequent to FIG. 5P. [Figure 5R] FIG. 5R is a cross-sectional view for explaining a step subsequent to FIG. 5Q. [Figure 6] FIG. 6 is a perspective view for explaining the device area and the cutting line. [Figure 7] FIG. 7 is a graph for explaining the formation characteristics of the modified layer according to the step of FIG. 5N. [Figure 8] FIG. 8 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a plan view showing a SiC semiconductor device having a functional device according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is a plan view showing an SiC semiconductor device having a functional device according to another embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a main part of a functional device.

[0010] FIG. 1 is a perspective view showing a SiC wafer source 1, a first support member 11, and a second support member 21 used in a manufacturing method for a SiC (silicon carbide) semiconductor device according to a first embodiment of the present invention. In this embodiment, the SiC wafer source 1 is made of a hexagonal SiC single crystal. The SiC single crystal is also an example of a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap exceeding that of Si (silicon). The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the SiC wafer source 1 is made of a 4H-SiC single crystal, but other polytypes are not excluded.

[0011] The SiC wafer source 1 is a disk-shaped or cylindrical crystal cut from a hexagonal SiC ingot (a SiC single crystal block) by a slicing method. The SiC wafer source 1 is a base member from which at least one (preferably multiple) SiC wafers for device formation are cut until they become inseparable. The SiC wafer source 1 may be a SiC wafer for device formation cut from a SiC ingot. The SiC wafer source 1 may contain n-type (first conductivity type) impurities or p-type (second conductivity type) impurities throughout, depending on the electrical properties of the SiC semiconductor device to be formed. In other words, an n-type SiC wafer source 1 or a p-type SiC wafer source 1 may be used in the method for manufacturing a SiC semiconductor device.

[0012] The SiC wafer source 1 has a first main surface 2 on one side, a second main surface 3 on the other side, and a side surface 4 connecting the first main surface 2 and the second main surface 3. The first main surface 2 and the second main surface 3 face the c-plane of the SiC single crystal. The c-plane includes the silicon face ((0001) face) and the carbon face ((000-1) face) of the SiC single crystal. It is preferable that the first main surface 2 faces the silicon face and the second main surface 3 faces the carbon face.

[0013] The first main surface 2 and the second main surface 3 may have an off angle inclined at a predetermined angle in a predetermined off direction relative to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and less than or equal to 10°. The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and less than or equal to 4.5°. The first main surface 2 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The second main surface 3 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The surface conditions of the first main surface 2 and the second main surface 3 are arbitrary, and the surface condition of the second main surface 3 does not necessarily have to be the same as the surface condition of the first main surface 2.

[0014] The SiC wafer source 1 includes a first edge portion 5 and a second edge portion 6. The first edge portion 5 connects the first main surface 2 and the side surface 4. The first edge portion 5 is angular and not chamfered. That is, the first edge portion 5 connects the first main surface 2 and the side surface 4 at a substantially right angle. The second edge portion 6 connects the second main surface 3 and the side surface 4. The second edge portion 6 is angular and not chamfered. That is, the second edge portion 6 connects the second main surface 3 and the side surface 4 at a substantially right angle.

[0015] The SiC wafer source 1 has a first orientation flat 7 on the side surface 4 as an example of a mark indicating the crystal orientation of the SiC single crystal. The first orientation flat 7 consists of a notch extending linearly. In this embodiment, the first orientation flat 7 extends in the a-axis direction of the SiC single crystal. The first orientation flat 7 does not necessarily have to extend in the a-axis direction, and may extend in the m-axis direction. Of course, the SiC wafer source 1 may have a first orientation flat 7 extending in the a-axis direction and a first orientation flat 7 extending in the m-axis direction.

[0016] The SiC wafer source 1 may have a diameter of 25 mm or more and 300 mm or less (i.e., 1 inch or more and 12 inches or less). The diameter of the SiC wafer source 1 refers to a chord passing through the center of the SiC wafer source 1 outside the first orientation flat 7. The SiC wafer source 1 may have a thickness of 0.1 mm or more and 50 mm or less. The thickness of the SiC wafer source 1 is typically 20 mm or less. When a SiC wafer source 1 made of a SiC wafer for device formation cut from a SiC ingot is used, the thickness of the SiC wafer source 1 may be 0.3 mm or more and 15 mm or less (preferably 10 mm or less). In this case, the diameter of the SiC wafer source 1 may be 2 inches or more and 12 inches or less.

[0017] The first support member 11 is made of a plate-like member that supports the SiC wafer source 1 from the first main surface 2 side. Any member can be used as the first support member 11 as long as it can support the SiC wafer source 1 from the first main surface 2 side. The first support member 11 may be made of a material different from the SiC wafer. The first support member 11 may be made of an inorganic plate, an organic plate, a metal plate, a crystalline plate, or an amorphous plate that is processed into a disk or cylinder shape. The first support member 11 is preferably made of an optically transparent or transparent material. In this embodiment, the first support member 11 is made of an amorphous plate. The first support member 11 is preferably made of glass (silicon oxide).

[0018] The first support member 11 has a first plate surface 12 on one side (the SiC wafer source 1 side), a second plate surface 13 on the other side, and a plate side surface 14 connecting the first plate surface 12 and the second plate surface 13. The first plate surface 12 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The second plate surface 13 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The surface condition of the first plate surface 12 and the second plate surface 13 is arbitrary, and the surface condition of the second plate surface 13 does not necessarily have to be the same as the surface condition of the first plate surface 12.

[0019] The first support member 11 includes a first plate edge portion 15 and a second plate edge portion 16. The first plate edge portion 15 connects the first plate surface 12 and the plate side surface 14. The first plate edge portion 15 is chamfered to be obliquely inclined from the first plate surface 12 toward the plate side surface 14. The first plate edge portion 15 may be R-chamfered or C-chamfered. The second plate edge portion 16 connects the second plate surface 13 and the plate side surface 14. The second plate edge portion 16 is chamfered to be obliquely inclined from the second plate surface 13 toward the plate side surface 14. The second plate edge portion 16 may be R-chamfered or C-chamfered.

[0020] The first plate edge portion 15 and the second plate edge portion 16 may or may not have a chamfered portion. Either or both of the first plate edge portion 15 and the second plate edge portion 16 may be angular and not have a chamfered portion. However, from the viewpoint of handling, it is preferable that both the first plate edge portion 15 and the second plate edge portion 16 have a chamfered portion. In this specification, the term "handling" includes not only loading and unloading from a manufacturing device for manufacturing a SiC semiconductor device, but also distribution to the market.

[0021] The diameter and thickness of the first support member 11 are arbitrary. However, in consideration of handling of the SiC wafer source 1, it is preferable that the first support member 11 has a diameter equal to or greater than the diameter of the SiC wafer source 1. It is also preferable that the first support member 11 has a thickness equal to or greater than the thickness of the SiC wafer source 1. In this embodiment, the first support member 11 has a diameter greater than the diameter of the SiC wafer source 1. When the central portion of the SiC wafer source 1 and the central portion of the first support member 11 are overlapped, the first distance I1 between the periphery of the SiC wafer source 1 and the periphery of the first support member 11 is preferably 0 mm or more and 10 mm or less.

[0022] The second support member 21 is a plate-like member that supports the SiC wafer source 1 from the second main surface 3 side. The second support member 21 is preferably made of an optically transparent or transparent material that suppresses attenuation of the laser light. The melting point of the second support member 21 is preferably equal to or higher than the melting point of the SiC wafer source 1. The ratio of the thermal expansion coefficient of the second support member 21 to the thermal expansion coefficient of the SiC wafer source 1 is preferably 0.5 or higher and 1.5 or lower. It is particularly preferable that the second support member 21 be made of the same material as the SiC wafer source 1 (i.e., SiC). In this case, the second support member 21 may be made of SiC single crystal or SiC polycrystal.

[0023] When the second support member 21 is made of SiC single crystal, it is preferable that the second support member 21 be made of hexagonal SiC single crystal. In this embodiment, an example is shown in which the second support member 21 is made of a SiC wafer made of 4H-SiC single crystal, but other polytypes are not excluded. In this embodiment, the second support member 21 is made of a disk-shaped or cylindrical crystal (i.e., a SiC wafer) cut from a hexagonal SiC ingot (a SiC single crystal block) by a slicing method.

[0024] The impurity concentration of the second support member 21 is set independently of the SiC semiconductor device to be formed in the SiC wafer source 1. The impurity concentration of the second support member 21 is preferably different from the impurity concentration of the SiC wafer source 1. The impurity concentration of the second support member 21 is preferably lower than the impurity concentration of the SiC wafer source 1. It is particularly preferable that no impurities are added to the second support member 21. In this case, absorption (attenuation) of the laser light caused by the second support member 21 is suppressed.

[0025] The second support member 21 may contain vanadium as an impurity. When the second support member 21 contains an n-type impurity or a p-type impurity, the impurity concentration of the second support member 21 is 1×10 18 cm -3 It is preferable that the wavelength is equal to or less than 390 μm. It should be noted that laser light having a wavelength of 390 μm or less tends to be absorbed (attenuated) by SiC single crystal regardless of whether it is doped with impurities.

[0026] The second support member 21 has a first plate surface 22 on one side (the SiC wafer source 1 side), a second plate surface 23 on the other side, and a plate side surface 24 connecting the first plate surface 22 and the second plate surface 23. The first plate surface 22 and the second plate surface 23 face the c-plane of the SiC single crystal. It is preferable that the first plate surface 22 faces the silicon surface and the second plate surface 23 faces the carbon surface.

[0027] The first plate surface 22 and the second plate surface 23 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and less than or equal to 4.5°. The off-angle of the second support member 21 is preferably approximately equal to the off-angle of the SiC wafer source 1. The off-angle of the second support member 21 preferably has a value within a range of ±10% based on the value of the off-angle of the SiC wafer source 1.

[0028] The first plate surface 22 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The second plate surface 23 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The surface condition of the first plate surface 22 and the surface condition of the second plate surface 23 are arbitrary, and the surface condition of the second plate surface 23 does not necessarily have to be the same as the surface condition of the first plate surface 22.

[0029] The second support member 21 includes a first plate edge portion 25 and a second plate edge portion 26. The first plate edge portion 25 connects the first plate surface 22 and the plate side surface 24. The first plate edge portion 25 is chamfered to be obliquely inclined from the first plate surface 22 toward the plate side surface 24. The first plate edge portion 25 may be R-chamfered or C-chamfered. The second plate edge portion 26 connects the second plate surface 23 and the plate side surface 24. The second plate edge portion 26 is chamfered to be obliquely inclined from the second plate surface 23 toward the plate side surface 24. The second plate edge portion 26 may be R-chamfered or C-chamfered.

[0030] The first plate edge portion 25 and the second plate edge portion 26 may or may not have a chamfered portion. Either or both of the first plate edge portion 25 and the second plate edge portion 26 may be angular and not have a chamfered portion. However, from the viewpoint of handling, it is preferable that both the first plate edge portion 25 and the second plate edge portion 26 have a chamfered portion.

[0031] The second support member 21 has a second orientation flat 27 on the plate side surface 24 as an example of a mark indicating the crystal orientation of the SiC single crystal. The second orientation flat 27 preferably indirectly indicates the crystal orientation of the SiC wafer source 1. The second orientation flat 27 is composed of a linearly extending notch. In this embodiment, the second orientation flat 27 extends in the a-axis direction of the SiC single crystal. The second orientation flat 27 does not necessarily have to extend in the a-axis direction, and may extend in the m-axis direction. Of course, the second support member 21 may have a second orientation flat 27 extending in the a-axis direction and a second orientation flat 27 extending in the m-axis direction.

[0032] The diameter and thickness of the second support member 21 are arbitrary. The diameter of the second support member 21 refers to a chord passing through the center of the second support member 21 outside the second orientation flat 27. In consideration of handling of the SiC wafer source 1, the second support member 21 preferably has a diameter equal to or greater than the diameter of the SiC wafer source 1. Furthermore, the second support member 21 preferably has a thickness equal to or greater than the thickness of the SiC wafer source 1. In this embodiment, the second support member 21 has a diameter greater than the diameter of the SiC wafer source 1. When the central portion of the SiC wafer source 1 and the central portion of the second support member 21 are overlapped, the second distance I2 between the periphery of the SiC wafer source 1 and the periphery of the second support member 21 is preferably 0 mm or more and 10 mm or less.

[0033] Fig. 2 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device. Figs. 3A to 3I are cross-sectional views for explaining an example of a method for manufacturing a SiC semiconductor device. For convenience, Figs. 3A to 3I show a simplified view of the SiC wafer source 1, the first support member 11, and the second support member 21. First, referring to Fig. 3A, in manufacturing a SiC semiconductor device, the SiC wafer source 1, the first support member 11, and the second support member 21 (one-side support member) are prepared (step S1 in Fig. 2). Fig. 3A shows only the SiC wafer source 1.

[0034] Next, referring to FIG. 3B, the SiC wafer source 1 is supported by the first support member 11 from the first main surface 2 side (silicon surface side) (step S2 in FIG. 2). The first plate surface 12 of the first support member 11 may be directly bonded to the first main surface 2 of the SiC wafer source 1 by room-temperature bonding, which is an example of a direct bonding method. In the room-temperature bonding method, an activation step and a bonding step are performed. In the activation step, for example, atoms or ions are irradiated onto the first main surface 2 of the SiC wafer source 1 and the first plate surface 12 of the first support member 11 in a high vacuum, and the first main surface 2 and the first plate surface 12 are activated by dangling bonds (unbonded hands).

[0035] In the bonding step, the activated first main surface 2 and the activated first plate surface 12 are bonded together. After bonding, a first amorphous bonding layer 31 (Si / SiC amorphous bonding layer) containing at least Si (silicon) is formed between the first main surface 2 and the first plate surface 12. The SiC wafer source 1 and the first support member 11 are bonded together by the first amorphous bonding layer 31. The room-temperature bonding method may include a heat treatment step and a pressure application step to increase the bonding strength between the SiC wafer source 1 and the first support member 11.

[0036] In this process, an example has been described in which the first support member 11 is bonded to the SiC wafer source 1 by a direct bonding method. However, as long as the first support member 11 can support the SiC wafer source 1, any method can be used to bond the first support member 11 to the SiC wafer source 1. For example, the first support member 11 may be bonded to the SiC wafer source 1 by an adhesive. In this case, an adhesive layer made of an adhesive is formed between the SiC wafer source 1 and the first support member 11.

[0037] 3C, the SiC wafer source 1 is supported by the second support member 21 from the second main surface 3 side (carbon surface side) (step S3 in FIG. 2). In this step, the second support member 21 supports the SiC wafer source 1 so that the second orientation flat 27 extends parallel to the first orientation flat 7 at a position close to the first orientation flat 7. With the SiC wafer source 1 sandwiched between the first support member 11 and the second support member 21, the crystal orientation of the SiC wafer source 1 is determined by both the first orientation flat 7 and the second orientation flat 27.

[0038] In this step, the first plate surface 22 (silicon surface) of the second support member 21 is bonded to the second main surface 3 (carbon surface) of the SiC wafer source 1 by room-temperature bonding, which is an example of a direct bonding method. The room-temperature bonding method includes an activation step and a bonding step. In the activation step, for example, atoms or ions are irradiated onto the second main surface 3 of the SiC wafer source 1 and the first plate surface 22 of the second support member 21 in a high vacuum, and the second main surface 3 and the first plate surface 22 are activated by dangling bonds.

[0039] In the bonding step, the activated second main surface 3 and the activated first plate surface 22 are bonded together. After bonding, a second amorphous bonding layer 32 (SiC amorphous bonding layer) containing at least C (carbon) is formed between the second main surface 3 and the first plate surface 22. The SiC wafer source 1 and the second support member 21 are bonded together by the second amorphous bonding layer 32. The room-temperature bonding method may include a heat treatment step and a pressure application step to increase the bonding strength between the SiC wafer source 1 and the second support member 21.

[0040] The second amorphous bonding layer 32 has an optical absorption coefficient greater than that of the SiC wafer source 1. The optical absorption coefficient of the second amorphous bonding layer 32 is greater than that of the second support member 21. The thickness of the second amorphous bonding layer 32 may be greater than 0 μm and not greater than 5 μm. The thickness of the second amorphous bonding layer 32 is preferably not greater than 1 μm.

[0041] Next, referring to FIG. 3D, a modified layer 33 extending horizontally parallel to the first main surface 2 is formed midway through the thickness of the SiC wafer source 1 (step S4 in FIG. 2). The distance between the first plate surface 22 of the second support member 21 and the modified layer 33 is set according to the thickness of the wafers to be obtained from the SiC wafer source 1. The distance between the first plate surface 22 of the second support member 21 and the modified layer 33 may be 5 μm or more and 300 μm or less. The distance between the first plate surface 22 of the second support member 21 and the modified layer 33 is typically 5 μm or more and 250 μm or less.

[0042] In this process, a focusing section is set midway through the thickness direction of the SiC wafer source 1, and laser light is irradiated from a laser light irradiation device toward the SiC wafer source 1 via a second support member 21. The irradiation position of the laser light on the SiC wafer source 1 is moved along the horizontal direction. As a result, a modified layer 33 is formed in the portion of the SiC wafer source 1 irradiated with the laser light, in which part of the crystal structure of the SiC single crystal is modified to have different properties. In other words, the modified layer 33 is a laser processing mark formed by the irradiation of the laser light. The modified layer 33 is modified to have different properties from those of the SiC wafer source 1 in density, refractive index, mechanical strength (crystal strength), or other physical properties, and is made of a layer with physical properties more fragile than the SiC single crystal.

[0043] The modified layer 33 may include at least one layer selected from the group consisting of an amorphous layer, a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The amorphous layer is a layer in which a portion of the SiC wafer source 1 has become amorphous. The melt-rehardened layer is a layer in which a portion of the SiC wafer source 1 has melted and then hardened again. The defect layer is a layer containing voids, cracks, etc. formed in the SiC wafer source 1. The dielectric breakdown layer is a layer in which a portion of the SiC wafer source 1 has undergone dielectric breakdown. The refractive index change layer is a layer in which a portion of the SiC wafer source 1 has changed to a different refractive index.

[0044] 3E, the SiC wafer source 1 is cut horizontally from the middle in the thickness direction, starting from the modified layer 33 (step S5 in FIG. 2). In this step, an external force is applied to the SiC wafer source 1 while it is sandwiched between the first support member 11 and the second support member 21, and the SiC wafer source 1 is cleaved horizontally, starting from the modified layer 33. The external force applied to the SiC wafer source 1 may be ultrasonic.

[0045] As a result, a SiC wafer structure 35 including the second support member 21 and the SiC wafer 34 is separated from the SiC wafer source 1. The SiC wafer structure 35 includes a second amorphous bonding layer 32 that is interposed between the second support member 21 and the SiC wafer 34 and bonds the second support member 21 and the SiC wafer 34. In this form, the second amorphous bonding layer 32 is formed as a separation starting point (specifically, a cleavage starting point) between the second support member 21 and the SiC wafer 34 in a later step.

[0046] The SiC wafer 34 is separated from the SiC wafer source 1 as a wafer for device formation. The cut surface of the SiC wafer 34 faces the silicon surface. The SiC wafer 34 is separated from the SiC wafer source 1 in a manner that it inherits the first orientation flat 7 from the SiC wafer source 1. Therefore, the SiC wafer 34 also has the first orientation flat 7. After being separated from the SiC wafer source 1, the SiC wafer structure 35 is transported to another location (step S6 in FIG. 2). In other words, the second support member 21 and the SiC wafer 34 are handled as a single unit as the SiC wafer structure 35. The cut surface (cleavage plane) of the SiC wafer source 1 becomes the second main surface 3.

[0047] Next, it is determined whether the SiC wafer source 1 is reusable (step S7 in FIG. 2). If the SiC wafer source 1 has a thickness and condition that allows another SiC wafer 34 to be obtained, it may be determined that the SiC wafer source 1 is reusable. If the SiC wafer source 1 is not reusable (step S7 in FIG. 2: NO), the process for the SiC wafer source 1 ends.

[0048] If the SiC wafer source 1 is not reusable (step S7 in FIG. 2: NO), the first support member 11 may be detached from the SiC wafer source 1 and reused as a first support member 11 supporting another SiC wafer source 1. If the first support member 11 is reused, the first plate surface 12 is preferably planarized (smoothed) by a grinding method and / or an etching method. The SiC wafer source 1 and / or the first amorphous bonding layer 31 remaining on the first plate surface 12 of the first support member 11 may be removed by a grinding method and / or an etching method. The grinding process (polishing process) of the first plate surface 12 may be performed by a CMP (Chemical Mechanical Polishing) method.

[0049] 3F, if the SiC wafer source 1 is reusable (step S7 in FIG. 2: YES), a recycling step is performed for the SiC wafer source 1. In the recycling step for the SiC wafer source 1, the second main surface 3 (cleavage plane) of the SiC wafer source 1 is planarized (smoothed) by a grinding method and / or an etching method while being supported by the first support member 11 (step S8 in FIG. 2).

[0050] The second main surface 3 may be polished by a CMP method. The grinding step may include a polishing step or a mirror polishing step of the second main surface 3. The second edge portion 6 of the SiC wafer source 1 is preferably not chamfered. In other words, it is preferable that the second edge portion 6 of the SiC wafer source 1 remains sharp even after the SiC wafer structure 35 is obtained.

[0051] 3G, through a process similar to that of FIG. 3C, the SiC wafer source 1 is supported from the second main surface 3 side by the second support member 21 (step S3 of FIG. 2). Next, through a process similar to that of FIG. 3D, with reference to FIG. 3H, a modified layer 33 extending in a horizontal direction parallel to the first main surface 2 is formed in a middle portion of the SiC wafer source 1 in the thickness direction (step S4 of FIG. 2). Next, with reference to FIG. 3I, through a process similar to that of FIG. 3E, the SiC wafer source 1 is cut in the horizontal direction from the middle portion of the thickness direction starting from the modified layer 33, and a SiC wafer structure 35 including the second support member 21 and the SiC wafer 34 is separated from the SiC wafer source 1 (step S5 of FIG. 2).

[0052] The SiC wafer structure 35 separated from the SiC wafer source 1 is transported to another location with the second support member 21 and the SiC wafer 34 integrally attached (step S6 in FIG. 2). Thereafter, it is determined again whether the SiC wafer source 1 is reusable (step S7 in FIG. 2). Thus, in the method for manufacturing a SiC semiconductor device, the recycling step of the SiC wafer source 1 is repeatedly performed until the SiC wafer source 1 becomes inseparable.

[0053] Fig. 4 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device performed on the SiC wafer structure 35. Figs. 5A to 5R are cross-sectional views illustrating an example of a method for manufacturing a SiC semiconductor device performed on the SiC wafer structure 35. Fig. 6 is a perspective view illustrating a device region 44 and lines to cut 45 set in the SiC wafer structure 35.

[0054] In the method for manufacturing a SiC semiconductor device, a transfer step of the SiC wafer structure 35 (step S6 in FIG. 2) is followed by a step of forming functional devices on the SiC wafers 34 (steps S11 to S23 in FIG. 4) and a step of singulating the SiC wafers 34 (steps S24 to S29 in FIG. 4). When a plurality of SiC wafers 34 (SiC wafer structures 35) are cut from a single SiC wafer source 1, the types of functional devices formed on the plurality of SiC wafers 34 are arbitrary. That is, a first SiC semiconductor device having a first functional device may be manufactured using a first SiC wafer 34, and a second SiC wafer 34 may be manufactured using a second SiC wafer 34 having a second functional device of the same or different type as the first functional device.

[0055] The functional device may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET).

[0056] The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky Barrier Diode (SBD), and a Fast Recovery Diode (FRD). The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse. The functional device may include a circuit network combining at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device.

[0057] The circuitry may be an integrated circuit such as LSI (Large Scale Integration), SSI (Small Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration), or ULSI (Ultra-Very Large Scale Integration).The functional devices formed on the SiC wafer 34 are typically either or both of a MISFET and an SBD.

[0058] First, referring to FIG. 5A, in manufacturing a SiC semiconductor device, a SiC wafer structure 35 is prepared (step S11 in FIG. 4). Next, referring to FIG. 5B, while the SiC wafer 34 is supported by the second support member 21, a cut surface 36 (cleavage surface) of the SiC wafer 34 is planarized (smoothed) by a grinding method and / or an etching method (step S12 in FIG. 4). The cut surface 36 may be polished by a CMP method. The grinding step may include a polishing step or a mirror-finishing step of the cut surface 36. It is preferable that the edge portion of the SiC wafer 34 is not chamfered. In other words, it is preferable that the edge portion of the SiC wafer 34 is maintained in an angular state.

[0059] Next, referring to FIG. 5C, an SiC epitaxial layer 37 is formed by epitaxial growth on the cut surface 36 after the polishing process (step S13 in FIG. 4). If the SiC wafer 34 contains n-type impurities, the SiC epitaxial layer 37 may have an n-type impurity concentration lower than the n-type impurity concentration of the SiC wafer 34. The thickness of the SiC epitaxial layer 37 may be 1 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 37 is preferably 5 μm or more and 20 μm or less. In this embodiment, the SiC epitaxial layer 37 is also formed on the side surface of the SiC wafer 34 and on the second support member 21.

[0060] As a result, a SiC epi-wafer 41 including the SiC wafer 34 and the SiC epitaxial layer 37 is formed on the second support member 21 in the SiC wafer structure 35. The SiC epi-wafer 41 has a first wafer main surface 42 on one side and a second wafer main surface 43 on the other side. The first wafer main surface 42 is the surface on which functional devices are formed. The second wafer main surface 43 corresponds to the second main surface 3 of the SiC wafer source 1 and is bonded to the second support member 21 via the second amorphous bonding layer 32.

[0061] Next, a plurality of device regions 44 and cutting lines 45 that partition the plurality of device regions 44 are set on the first wafer main surface 42 (step S14 in FIG. 4). In FIG. 5C, four device regions 44 are shown, and the cutting lines 45 are indicated by straight lines (the same applies to FIGS. 5D to 5R below). Referring to FIG. 6, the plurality of device regions 44 respectively correspond to the SiC semiconductor devices and are set, for example, in a matrix pattern along the a-axis and m-axis directions of the SiC single crystal in plan view. The cutting lines 45 are set in a lattice pattern extending in the a-axis and m-axis directions of the SiC single crystal in accordance with the arrangement of the plurality of device regions 44 in plan view.

[0062] Next, referring to Fig. 5D, the internal structure of the functional device is formed in each of a plurality of device regions 44 on the first wafer main surface 42 (step S15 in Fig. 4). In Fig. 5D, for convenience, the internal structure of the functional device is shown by a cross-hatched box (the same applies to Figs. 5E to 5R below). The internal structure of the functional device includes at least one of an n-type semiconductor region, a p-type semiconductor region, and a trench structure, depending on the function of the functional device.

[0063] The n-type semiconductor region is formed by introducing n-type impurities into the SiC epitaxial layer 37 through an ion implantation mask. The p-type semiconductor region is formed by introducing p-type impurities into the SiC epitaxial layer 37 through an ion implantation mask. The trench structure includes a trench formed in the first wafer main surface 42, an insulating film covering the inner wall of the trench, and an electrode embedded in the trench with the insulating film sandwiched therebetween.

[0064] The trenches are formed on the first wafer main surface 42 by etching using a mask. The insulating film is formed by at least one of thermal oxidation and CVD (Chemical Vapor Deposition). The insulating film may cover the entire first wafer main surface 42 as a main surface insulating film in addition to the inner walls of the trenches. The electrodes are formed, for example, by depositing polysilicon by CVD and then removing unnecessary portions of the polysilicon by etch-back.

[0065] Next, referring to FIG. 5E, a first inorganic insulating film 46 is formed on the first wafer main surface 42 (step S16 in FIG. 4). The first inorganic insulating film 46 may be referred to as an interlayer insulating film. The first inorganic insulating film 46 may have a stacked structure including multiple insulating films, or may have a single-layer structure consisting of a single insulating film. The first inorganic insulating film 46 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first inorganic insulating film 46 has a single-layer structure consisting of a silicon oxide film. The thickness of the first inorganic insulating film 46 is preferably 10 nm or more and 1000 nm or less.

[0066] The first inorganic insulating film 46 may have a layered structure in which a plurality of silicon oxide films are stacked. The first inorganic insulating film 46 may have a layered structure including an NSG (nondoped silicate glass) film and a PSG (phosphor silicate glass) film stacked in this order from the first wafer main surface 42 side. The NSG film is made of a silicon oxide film with no impurities added. The PSG film is made of a silicon oxide film with phosphorus added. The thickness of the NSG film may be 10 nm or more and 500 nm or less. The thickness of the PSG film may be 10 nm or more and 500 nm or less.

[0067] The first inorganic insulating film 46 may be formed by a CVD method or a thermal oxidation method. The first inorganic insulating film 46 covers the functional device on the first wafer main surface 42. In this embodiment, the first inorganic insulating film 46 is also formed on the side surface of the SiC wafer 34 and on the second support member 21, with the SiC epitaxial layer 37 sandwiched therebetween.

[0068] 5F, a first resist mask 47 having a predetermined pattern is formed on the first inorganic insulating film 46 (step S17 in FIG. 4). The first resist mask 47 selectively exposes portions of the first inorganic insulating film 46 that cover the plurality of functional devices, and exposes portions that cover the cutting lines 45.

[0069] Next, unnecessary portions of the first inorganic insulating film 46 are removed by etching via the first resist mask 47. The etching may be wet etching and / or dry etching. As a result, at least one contact opening 48 that selectively exposes the functional device is formed in the first inorganic insulating film 46. The first resist mask 47 is then removed.

[0070] Next, referring to FIG. 5G, a first main-surface electrode 50 is formed on the first wafer main surface 42 (step S18 in FIG. 4). The first main-surface electrode 50 covers the entire area of ​​the first inorganic insulating film 46 on the first wafer main surface 42. In this embodiment, the first main-surface electrode 50 is also formed on the side surface of the SiC wafer 34 and on the second support member 21, with the first inorganic insulating film 46 sandwiched therebetween. The first main-surface electrode 50 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the first wafer main surface 42 side. The Ti-based metal film and the Al-based metal film may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method.

[0071] Next, referring to FIG. 5H, a second resist mask 51 having a predetermined pattern is formed on the first principal surface electrode 50 (step S19 in FIG. 4). The second resist mask 51 selectively covers the portions of the first principal surface electrode 50 that cover the device regions 44, and exposes the remaining regions. Next, unnecessary portions of the first principal surface electrode 50 are removed by etching via the second resist mask 51. The etching may be wet etching and / or dry etching. The second resist mask 51 is then removed.

[0072] Next, referring to FIG. 5I, a second inorganic insulating film 52 is formed on the first wafer main surface 42 (step S20 in FIG. 4). The second inorganic insulating film 52 may be referred to as a passivation film. The second inorganic insulating film 52 may have a layered structure including multiple insulating films, or may have a single-layer structure consisting of a single insulating film. The second inorganic insulating film 52 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0073] In this embodiment, the second inorganic insulating film 52 has a single-layer structure made of a silicon nitride film. That is, the second inorganic insulating film 52 is made of an insulator different from that of the first inorganic insulating film 46. The thickness of the second inorganic insulating film 52 is preferably 0.1 μm or more and 2 μm or less. The second inorganic insulating film 52 may be formed by a CVD method. The second inorganic insulating film 52 covers the first main surface electrode 50 on the first wafer main surface 42. In this embodiment, the second inorganic insulating film 52 is also formed on the side surface of the SiC wafer 34 and on the second support member 21, with the SiC epitaxial layer 37 sandwiched therebetween.

[0074] 5J, a third resist mask 53 having a predetermined pattern is formed on the second inorganic insulating film 52 (step S21 in FIG. 4). The third resist mask 53 exposes portions of the second inorganic insulating film 52 that cover the first principal surface electrodes 50 and the cutting lines 45, and covers the remaining areas.

[0075] Next, unnecessary portions of the second inorganic insulating film 52 are removed by etching via the third resist mask 53. The etching may be wet etching and / or dry etching. As a result, first pad openings 54 that selectively expose the first principal surface electrodes 50 and first dicing streets 55 that expose the SiC epitaxial layer 37 along the cutting lines 45 are formed in the second inorganic insulating film 52. The width of the first dicing streets 55 may be 1 μm or more and 25 μm or less. The width of the first dicing streets 55 is the width in a direction perpendicular to the direction in which the first dicing streets 55 extend. The third resist mask 53 is then removed.

[0076] Next, referring to FIG. 5K, an organic insulating film 56 is applied onto the first wafer main surface 42 (step S22 in FIG. 4). The organic insulating film 56 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating film 56 includes polyimide.

[0077] The thickness of the organic insulating film 56 preferably exceeds the thickness of the second inorganic insulating film 52. The thickness of the organic insulating film 56 is preferably 1 μm or more and 30 μm or less. The organic insulating film 56 covers the first main surface electrode 50, the first inorganic insulating film 46, and the second inorganic insulating film 52 on the first wafer main surface 42. In this embodiment, the organic insulating film 56 covers the side surface of the SiC wafer 34 and the second support member 21 with the SiC epitaxial layer 37 sandwiched therebetween.

[0078] 5L, organic insulating film 56 is exposed to light with a pattern corresponding to first pad opening 54 and first dicing street 55 of second inorganic insulating film 52, and then developed (step S23 of FIG. 4). As a result, second pad openings 57 communicating with first pad opening 54 and second dicing streets 58 communicating with first dicing street 55 are formed in organic insulating film 56. The width of second dicing street 58 may be 1 μm or more and 25 μm or less. The width of second dicing street 58 is the width in a direction perpendicular to the direction in which second dicing street 58 extends.

[0079] 5M, the SiC wafer structure 35 is supported by a third support member 61 (other-side support member) from the first wafer main surface 42 side of the SiC epi-wafer 41 (step S24 in FIG. 4). The third support member 61 may be attached to the SiC wafer structure 35 via an adhesive or double-sided adhesive tape.

[0080] The third support member 61 is made of a plate-like member. Any member can be used as the third support member 61 as long as it can support the SiC wafer structure 35 from the first wafer main surface 42 side. The third support member 61 may be made of a material different from that of the SiC epitaxial wafer 41. The third support member 61 may be made of an inorganic plate, an organic plate, a metal plate, a crystalline plate, or an amorphous plate processed into a disk-like or cylindrical shape. The third support member 61 is preferably made of an optically transparent or transparent material. In this embodiment, the third support member 61 is made of an amorphous plate. The third support member 61 may also be made of a glass (silicon oxide) plate.

[0081] The third support member 61 has a first plate surface 62 on one side (the SiC wafer structure 35 side), a second plate surface 63 on the other side, and a plate side surface 64 connecting the first plate surface 62 and the second plate surface 63. The first plate surface 62 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The second plate surface 63 may be a ground surface, a cleaved surface, a polished surface, or a mirror surface. The surface conditions of the first plate surface 62 and the second plate surface 63 are arbitrary, and the surface condition of the second plate surface 63 does not necessarily have to be the same as the surface condition of the first plate surface 62.

[0082] The third support member 61 includes a first plate edge portion 65 and a second plate edge portion 66. The first plate edge portion 65 connects the first plate surface 62 and the plate side surface 64. The first plate edge portion 65 is chamfered to be obliquely inclined from the first plate surface 62 toward the plate side surface 64. The first plate edge portion 65 may be R-chamfered or C-chamfered. The second plate edge portion 66 connects the second plate surface 63 and the plate side surface 64. The second plate edge portion 66 is chamfered to be obliquely inclined from the second plate surface 63 toward the plate side surface 64. The second plate edge portion 66 may be R-chamfered or C-chamfered.

[0083] The first plate edge portion 65 and the second plate edge portion 66 may or may not have a chamfered portion. Either or both of the first plate edge portion 65 and the second plate edge portion 66 may be angular and not have a chamfered portion. However, from the viewpoint of handling, it is preferable that both the first plate edge portion 65 and the second plate edge portion 66 have a chamfered portion.

[0084] The diameter and thickness of the third support member 61 are arbitrary. However, in consideration of handling of the SiC wafer structure 35, the third support member 61 preferably has a diameter equal to or greater than the diameter of the SiC wafer 34. Furthermore, the third support member 61 preferably has a thickness equal to or greater than the thickness of the SiC wafer 34. In this embodiment, the third support member 61 has a diameter greater than the diameter of the SiC wafer 34. When the central portion of the SiC wafer 34 and the central portion of the third support member 61 are overlapped, a third distance I3 between the periphery of the SiC wafer 34 and the periphery of the third support member 61 is preferably 0 mm or more and 10 mm or less.

[0085] 5N, modified layer 70 is formed in second amorphous bonding layer 32 along the horizontal direction parallel to first main surface 2 (step S25 in FIG. 4). In this process, a focusing section is set inside second amorphous bonding layer 32 or near second amorphous bonding layer 32, and laser light is irradiated from a laser light irradiation device toward second amorphous bonding layer 32 via second support member 21. The irradiation position of the laser light on second amorphous bonding layer 32 is moved along the horizontal direction.

[0086] As a result, a modified layer 70 is formed in the portion of second amorphous bonding layer 32 irradiated with the laser light, where part of second amorphous bonding layer 32 is modified to have different properties. In other words, modified layer 70 is a laser processing mark formed by irradiating with laser light. Modified layer 70 is a layer whose density, refractive index, mechanical strength (crystal strength) or other physical properties have been modified to have properties different from those of second amorphous bonding layer 32, and which has physical properties more fragile than second amorphous bonding layer 32.

[0087] The second amorphous bonding layer 32 may include at least one layer selected from the group consisting of a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The melt-rehardened layer is a layer formed by melting a portion of the second amorphous bonding layer 32 and then rehardening. The defect layer is a layer containing voids, cracks, etc. formed in the second amorphous bonding layer 32. The dielectric breakdown layer is a layer formed by dielectric breakdown in a portion of the second amorphous bonding layer 32. The refractive index change layer is a layer formed by changing a portion of the second amorphous bonding layer 32 to a different refractive index.

[0088] In this embodiment, the modified layer 70 is also formed on the portion of the SiC epitaxial layer 37 that is formed on the second support member 21. The portion of the modified layer 70 that is formed on the SiC epitaxial layer 37 is modified to have density, refractive index, mechanical strength (crystal strength), or other physical properties that are different from those of a SiC single crystal, and is made of a layer that has physical properties that are more fragile than a SiC single crystal.

[0089] FIG. 7 is a graph illustrating the formation characteristics of the modified layer 70 according to the process of FIG. 5N. In FIG. 7, the vertical axis represents the depth position (thickness position) inside the SiC wafer structure 35 when the second plate surface 23 of the second support member 21 is used as the reference (zero point). On the other hand, the horizontal axis represents the output power [W] of the laser light. Here, the laser light is irradiated onto the irradiation target at an output power in the range of more than 0 W and not more than 5 W. The output power of the laser light is adjusted depending on the position, size, etc. of the modified layer 70 to be formed, and is not limited to the range of more than 0 W and not more than 5 W.

[0090] 7 shows a formation position P (see dashed line) of the second amorphous bonding layer 32, a first broken line L1, a second broken line L2, and a third broken line L3. The region located below the formation position P is the second support member 21, and the region located above the formation position P is the SiC wafer 34. The first broken line L1 indicates the formation position of the modified layer 70 when the laser light is irradiated inside the second support member 21. The second broken line L2 indicates the formation position of the modified layer 70 when the laser light is irradiated inside the SiC wafer 34.

[0091] Third broken line L3 indicates the position where modified layer 70 is formed when laser light is irradiated inside or near second amorphous bonding layer 32. The vicinity of second amorphous bonding layer 32 refers to a thickness range within ±50 μm from formation position P of second amorphous bonding layer 32. The vicinity of second amorphous bonding layer 32 is preferably set to a thickness range within ±10 μm from formation position P.

[0092] With reference to the first broken line L1, when the laser beam was irradiated onto the inside of the second support member 21, the formation position of the modified layer 70 shifted from the first plate surface 22 side to the second plate surface 23 side as the output of the laser beam increased. With reference to the second broken line L2, when the laser beam was irradiated onto the inside of the SiC wafer 34, the formation position of the modified layer 70 shifted from the first wafer main surface 42 side to the second wafer main surface 43 side as the output of the laser beam increased.

[0093] In contrast, referring to the third broken line L3, when the laser beam is irradiated inside or near the second amorphous bonding layer 32, the position where the modified layer 70 is formed remains within a substantially constant thickness range even when the output of the laser beam is increased. In other words, when the laser beam is irradiated inside or near the second amorphous bonding layer 32, variation in the position where the modified layer 70 is formed relative to the output of the laser beam is suppressed, and the modified layer 70 can be formed with high precision. This is because the optical absorption coefficient of the modified layer 70 is greater than the optical absorption coefficients of the SiC wafer 34 and the second support member 21.

[0094] 5O, the SiC wafer structure 35 is cut horizontally from the middle in the thickness direction starting from the modified layer 70 (second amorphous bonding layer 32), and the SiC epi-wafer 41 (SiC wafer 34) is separated from the second support member 21 (step S26 in FIG. 4). In this process, an external force is applied to the second amorphous bonding layer 32 while it is sandwiched between the second support member 21 and the third support member 61, and the SiC wafer source 1 is cleaved in the horizontal direction starting from the modified layer 70. The external force applied to the second amorphous bonding layer 32 may be ultrasonic.

[0095] After being separated from the SiC epi-wafer 41, the second support member 21 may be reused as a second support member 21 for supporting the same SiC wafer source 1 or another SiC wafer source 1. When the second support member 21 is reused, the bonding surface (first plate surface 22) is preferably planarized (smoothed) by grinding and / or etching. The SiC epi-wafer 41 (SiC wafer 34) and / or the second amorphous bonding layer 32 (modified layer 70) remaining on the first plate surface 22 of the second support member 21 may be removed by grinding and / or etching. The grinding process may be performed by CMP. The grinding process may include a polishing process or a mirror-finishing process of the first plate surface 22.

[0096] Next, referring to FIG. 5P, the cut surface (cleavage plane / second wafer main surface 43) of SiC epitaxial wafer 41 is planarized (smoothed) by grinding and / or etching while supported by third support member 61 (step S27 in FIG. 4). The grinding step may be performed by CMP. The grinding step may include polishing or mirror-finishing second wafer main surface 43.

[0097] Next, referring to FIG. 5Q, a second principal surface electrode 71 is formed on the second wafer principal surface 43 (step S28 in FIG. 4). In this embodiment, the second principal surface electrode 71 is also formed on a portion of the SiC epitaxial layer 37 that covers the side surface of the SiC wafer 34. The second principal surface electrode 71 forms ohmic contact with the second wafer principal surface 43. The second principal surface electrode 71 may include at least one of a Ti film, a Ni film, a Pd film, an Au film, and an Ag film.

[0098] The second principal surface electrode 71 only needs to include at least a Ti film, and the presence or absence and stacking order of the Ni film, Pd film, Au film, and Ag film are optional. For example, the second principal surface electrode 71 may include a Ti film, a Ni film, a Pd film, and an Au film stacked in this order from the second wafer principal surface 43 side. For another example, the second principal surface electrode 71 may have a stacked structure including a Ti film, a Ni film, and an Au film. The Ti film, the Ni film, the Pd film, the Au film, and the Ag film may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method (sputtering method in this embodiment).

[0099] The second main surface electrode 71 preferably includes a Ti film as an ohmic electrode directly connected to the second wafer main surface 43. In this case, the second wafer main surface 43 may be annealed by laser irradiation via the Ti film. In this process, annealing marks are formed on the second wafer main surface 43. The annealing marks may include amorphous SiC and / or SiC (specifically, Si) silicided (alloyed) with a metal (Ti). This results in the second wafer main surface 43 becoming an ohmic surface having grinding marks and annealing marks (laser irradiation marks). After the second main surface electrode 71 is formed, the third support member 61 is removed from the SiC epitaxial wafer 41.

[0100] Next, referring to FIG. 5R, the SiC epi-wafer 41 is cut along the lines to cut 45 (step S29 in FIG. 4). The cutting step of the SiC epi-wafer 41 may include a cutting step using a dicing blade. In this case, the SiC epi-wafer 41 is cut along the lines to cut 45 defined by first dicing streets 55 (second dicing streets 58). The dicing blade preferably has a blade width less than the width of the first dicing streets 55 (second dicing streets 58). The first inorganic insulating film 46, the second inorganic insulating film 52, and the organic insulating film 56 are not located on the lines to cut 45 and are therefore not cut by the dicing blade.

[0101] The cutting step of the SiC epi-wafer 41 may include a cleaving step using a laser light irradiation method. In this case, a laser light is irradiated from a laser light irradiation device (not shown) onto the interior of the SiC epi-wafer 41 via the first dicing street 55 (second dicing street 58). The laser light is preferably irradiated in pulses onto the interior of the SiC epi-wafer 41 from the side of the first wafer main surface 42 that does not have the second main surface electrode 71. The focusing point (focus) of the laser light is set inside the SiC epi-wafer 41 (midway in the thickness direction), and the irradiation position of the laser light is moved along the line 45 to cut.

[0102] As a result, a modified layer extending in a grid pattern along the cutting lines 45 (first dicing streets 55) in a plan view is formed inside the SiC epitaxial wafer 41. The modified layer is preferably formed inside the SiC epitaxial wafer 41 at a distance from the first wafer main surface 42. The modified layer is preferably formed inside the SiC epitaxial wafer 41 in a portion consisting of the SiC wafer 34. It is particularly preferable that the modified layer be formed on the SiC wafer 34 at a distance from the SiC epitaxial layer 37. It is most preferable that the modified layer is not formed on the SiC epitaxial layer 37.

[0103] After the modified layer formation step, an external force is applied to the SiC epi-wafer 41, and the SiC epi-wafer 41 is cleaved starting from the modified layer. The external force is preferably applied to the SiC epi-wafer 41 from the second wafer main surface 43 side. The second main surface electrode 71 is cleaved simultaneously with the cleavage of the SiC epi-wafer 41. The first inorganic insulating film 46, the second inorganic insulating film 52, and the organic insulating film 56 are not located on the cutting line 45, and are therefore spared from cleavage. A SiC semiconductor device is manufactured through the steps including those described above.

[0104] As described above, the method for manufacturing a SiC semiconductor device includes a step of preparing the SiC wafer source 1 (step S1 in FIG. 2), a step of supporting the SiC wafer source 1 with the second support member 21 (step S3 in FIG. 2), and a step of separating the SiC wafer structure 35 from the SiC wafer source 1 (step S5 in FIG. 2). In the preparation step, the SiC wafer source 1 including the first main surface 2 on one side and the second main surface 3 on the other side is prepared. In the support step, the SiC wafer source 1 is supported from the second main surface 3 side by the second support member 21.

[0105] In the separation step, the SiC wafer source 1 is cut horizontally along the first main surface 2 from a midpoint in the thickness direction, and a SiC wafer structure 35 including the second support member 21 and the SiC wafers 34 cut from the SiC wafer source 1 is separated from the SiC wafer source 1. This manufacturing method allows the SiC wafer structure 35 to be efficiently separated from the SiC wafer source 1. Furthermore, with the SiC wafer structure 35, the SiC wafers 34 are handled integrally with the second support member 21, improving the convenience of handling the SiC wafers 34. Therefore, a method for manufacturing a SiC semiconductor device and a SiC wafer structure 35 that can improve manufacturing efficiency can be provided.

[0106] The SiC wafer source 1 is preferably made of a hexagonal SiC single crystal (4H-SiC single crystal). The SiC wafer source 1 is preferably cut from a hexagonal SiC ingot (a SiC single crystal block) by a slicing method. The SiC wafer source 1 is particularly preferably made of a SiC wafer for device formation cut from the SiC ingot. The SiC wafer source 1 preferably has a thickness sufficient to allow at least one (preferably multiple) SiC wafers 34 for device formation to be cut out until the SiC wafer source 1 becomes inseparable.

[0107] The SiC wafer source 1 may have a diameter of 25 mm or more and 300 mm or less (i.e., 1 inch or more and 12 inches or less). The SiC wafer source 1 may have a thickness of 0.1 mm or more and 50 mm or less. The thickness of the SiC wafer source 1 is typically 20 mm or less. When the SiC wafer source 1 is cut from an SiC ingot as a SiC wafer for device formation, the thickness of the SiC wafer source 1 may be 0.3 mm or more and 15 mm or less (preferably 10 mm or less). In this case, the diameter of the SiC wafer source 1 may be 2 inches or more and 12 inches or less.

[0108] The second support member 21 is preferably made of a plate-like member that supports the SiC wafer source 1 from the second main surface 3 side. The second support member 21 is preferably made of an optically transmissive or transparent material that suppresses attenuation of the laser light. The melting point of the second support member 21 is preferably equal to or higher than the melting point of the SiC wafer source 1. In this case, melting or deformation of the second support member 21 during the manufacturing process can be suppressed.

[0109] The ratio of the thermal expansion coefficient of the second support member 21 to the thermal expansion coefficient of the SiC wafer source 1 is preferably 0.5 or more and 1.5 or less. In this case, the stress difference that occurs between the stress on the SiC wafer 34 side and the stress on the second support member 21 side during the manufacturing process can be reduced. Therefore, warping of the SiC wafer 34 can be suppressed.

[0110] It is particularly preferable that the second support member 21 be made of the same material as the SiC wafer source 1 (i.e., SiC). In this case, the second support member 21 may be made of SiC single crystal or SiC polycrystal. When the second support member 21 is made of SiC single crystal, it is preferable that the second support member 21 be made of hexagonal SiC single crystal (4H—SiC single crystal). It is preferable that the second support member 21 be made of a disk-shaped or cylindrical wafer cut from a hexagonal SiC ingot (SiC single crystal block) by a slicing method.

[0111] The second support member 21 preferably has a diameter equal to or greater than the diameter of the SiC wafer source 1. In this case, handling can be made easier and the SiC wafer source 1 (SiC wafer 34) can be adequately protected by the second support member 21. The second support member 21 preferably has a thickness equal to or greater than the thickness of the SiC wafer 34. The second support member 21 preferably has a thickness equal to or greater than the thickness of the SiC wafer source 1. When the central portion of the SiC wafer source 1 and the central portion of the second support member 21 are overlapped, the second distance I2 between the periphery of the SiC wafer source 1 and the periphery of the second support member 21 is preferably 0 mm or more and 10 mm or less.

[0112] The manufacturing method preferably includes a step of transporting the SiC wafer structure 35 after the separation step. This step allows the SiC wafer 34 and the second support member 21 to be transported integrally, thereby improving the convenience of handling.

[0113] The manufacturing method preferably includes a recycling step (steps S3 to S8 in FIG. 2) of the SiC wafer source 1, in which a series of steps including the supporting step and the separating step are repeated until the SiC wafer source 1 becomes inseparable. This step allows the SiC wafer source 1 to be efficiently consumed, while also increasing the number of SiC semiconductor devices that can be obtained from one SiC wafer source 1. This reduces manufacturing costs and improves manufacturing efficiency.

[0114] In the manufacturing method, the cutting step of the SiC wafer source 1 preferably includes a step of forming a modified layer 70 along the horizontal direction at a midpoint in the thickness direction of the SiC wafer source 1 by laser light irradiation, and then cleaving the SiC wafer source 1 in the horizontal direction starting from the modified layer 70 (steps S4 to S5 in FIG. 2). This step eliminates the need to cut the SiC wafer source 1 by grinding. Furthermore, the SiC wafer source 1 can be cleaved in advance to a thickness corresponding to the thickness of the SiC semiconductor device to be manufactured. This prevents excessive consumption of the SiC wafer source 1 and reduces costs associated with grinding. This improves manufacturing efficiency.

[0115] The SiC wafer source 1 preferably includes at least an angular second edge portion 6. If the second edge portion 6 of the SiC wafer source 1 has a chamfered portion, a gap is formed between the second edge portion 6 and the second support member 21. Errors occurring in the focused portion (focus) of the laser light include those caused by this gap. Therefore, by making the second edge portion 6 of the SiC wafer source 1 angular, the gap between the SiC wafer source 1 and the second support member 21 can be reduced. This allows the laser light to be properly irradiated onto the inside of the SiC wafer source 1, thereby properly forming the modified layer 70.

[0116] The manufacturing method may include a step of forming a SiC epitaxial layer 37 on the cut surface of the SiC wafer 34 (step S13 in FIG. 4). According to this step, after obtaining the SiC wafer structure 35, the SiC epitaxial layer 37 can be formed on the cut surface of the SiC wafer 34. This improves manufacturing efficiency. The manufacturing method preferably includes a step of polishing the cut surface of the SiC wafer 34, and the SiC epitaxial layer 37 is formed on the polished surface of the SiC wafer 34 (steps S12 to S13 in FIG. 4). According to this step, the SiC epitaxial layer 37 can be formed appropriately.

[0117] The manufacturing method may include a step of fabricating functional devices on the cut surfaces of the SiC wafer 34 (steps S11 to S23 in FIG. 4). This step allows functional devices to be formed on the cut surfaces of the SiC wafer 34 after the SiC wafer structure 35 is obtained, thereby improving manufacturing efficiency. The functional devices may include at least one or both of a SiC-SBD and a SiC-MISFET.

[0118] The manufacturing method preferably includes a step of polishing the cut surface of the SiC wafer 34, and the functional device is formed on the polished surface of the SiC wafer 34 (steps S12 to S13 in FIG. 4). This step allows the functional device to be formed appropriately.

[0119] The manufacturing method may include a step of removing the second support member 21 from the SiC wafer 34 after the functional device is formed (step S26 in FIG. 4). The second support member 21 is preferably bonded to the second main surface 3 of the SiC wafer source 1 by a direct bonding method (step S3 in FIG. 2). In this case, a SiC wafer structure 35 is formed having a second amorphous bonding layer 32 between the SiC wafer 34 and the second support member 21. The second amorphous bonding layer 32 preferably has an optical absorption coefficient greater than that of the SiC wafer 34. The optical absorption coefficient of the second amorphous bonding layer 32 is preferably greater than that of the second support member 21.

[0120] The step of removing the second support member 21 preferably includes a step of forming a modified layer 70 on the second amorphous bonding layer 32 by laser light irradiation, and a step of cleaving the SiC wafer structure 35 starting from the modified layer 70 (steps S25 to S26 in FIG. 2). This step allows the SiC wafer 34 and the second support member 21 to be separated. This step also eliminates the need to cut the SiC wafer structure 35 by grinding. This makes it possible to suppress excessive consumption of the SiC wafer structure 35 and reduce costs associated with grinding. This improves manufacturing efficiency.

[0121] In this step, the laser light is preferably irradiated to the inside of second amorphous bonding layer 32 or the vicinity of second amorphous bonding layer 32. This step allows modified layer 70 to be formed with high precision inside or the vicinity of second amorphous bonding layer 32. In other words, the irradiation of laser light can appropriately prevent modified layer 70 from being formed on either or both of SiC wafer 34 and second support member 21.

[0122] This makes it possible to suppress changes in the physical and electrical properties of the SiC wafers 34 due to the modified layer 70, thereby enabling appropriate manufacturing of SiC semiconductor devices from the SiC wafers 34. Furthermore, it makes it possible to suppress changes in the physical and electrical properties of the second support member 21 due to the modified layer 70, thereby enabling appropriate reuse of the second support member 21.

[0123] 8 is a flowchart showing an example of a method for manufacturing a SiC semiconductor device according to a second embodiment of the present invention. In the method for manufacturing a SiC semiconductor device according to the first embodiment, the SiC wafer source 1 is supported by the second support member 21, and then a modified layer 33 is formed on the SiC wafer source 1 (steps S3 to S4 in FIG. 2). In contrast, in the manufacturing method according to the second embodiment, the modified layer 33 is formed inside the SiC wafer source 1, and then the SiC wafers 34 are supported by the second support member 21 (steps S3 to S4 in FIG. 8).

[0124] That is, according to the manufacturing method of the second embodiment, prior to the supporting step using the second support member 21, laser light is directly irradiated from the second main surface 3 side of the SiC wafer source 1 toward the interior of the SiC wafer source 1 (step S4 in FIG. 8). Thereafter, the SiC wafer source 1 having the modified layer 33 is supported by the second support member 21 from the second main surface 3 side (step S3 in FIG. 8). Therefore, attenuation of the laser light caused by the second support member 21 can be suppressed, and the modified layer 33 can be appropriately formed inside the SiC wafer source 1.

[0125] If the SiC wafer source 1 is reusable (step S7 in FIG. 8: YES), a recycling step for the SiC wafer source 1 is carried out. In the recycling step for the SiC wafer source 1, the second main surface 3 (cleavage plane) of the SiC wafer source 1 is planarized (smoothed) by a grinding method and / or an etching method while being supported by the first support member 11 (step S8 in FIG. 8). The grinding step may be carried out by a CMP method. The grinding step may also include a polishing step or a mirror-finishing step for the second main surface 3.

[0126] Next, after a modified layer 33 is formed inside the SiC wafer source 1, the SiC wafer source 1 is supported by the second support member 21 (steps S3 to S4 in FIG. 8). In the manufacturing method according to the second embodiment, similar to the manufacturing method according to the first embodiment, the recycling step of the SiC wafer source 1 is repeatedly performed until the SiC wafer source 1 becomes inseparable. Steps S11 to S29 shown in FIG. 4 are performed on the SiC wafer structure 35 obtained from the SiC wafer source 1.

[0127] As described above, the method for manufacturing a SiC semiconductor device according to the second embodiment can also achieve the same effects as those described for the method for manufacturing a SiC semiconductor device according to the first embodiment.

[0128] The present invention can be embodied in still other forms.

[0129] In the above-described embodiments, examples have been described in which a SiC wafer source 1 is used. However, instead of the SiC wafer source 1, a WBG (Wide Band Gap) wafer source made of a WBG semiconductor other than SiC may be used. A WBG semiconductor is a semiconductor having a band gap that exceeds the band gap of Si (silicon). Examples of WBG semiconductors include GaN (gallium nitride) and diamond. Of course, in the above-described embodiments, instead of the SiC wafer source 1, a Si wafer source made of Si (silicon) may be used.

[0130] In each of the above-described embodiments, an example has been described in which the step of supporting the SiC wafer source 1 by the second support member 21 (step S2 in FIGS. 2 and 8) is performed after the step of supporting the SiC wafer source 1 by the first support member 11 (step S1 in FIGS. 2 and 8). However, the step of supporting the SiC wafer source 1 by the second support member 21 may be performed prior to the step of supporting the SiC wafer source 1 by the first support member 11.

[0131] In the above-described embodiments, an example has been described in which the SiC wafer source 1 is supported from the first main surface 2 side by the first support member 11 (see step S2 in FIG. 2 and FIG. 3B, etc.). However, the SiC wafer source 1 does not necessarily have to be supported by the first support member 11. For example, when a tool that supports or clamps the SiC wafer source 1 from the side surface 4 side is used, the step of supporting the SiC wafer source 1 by the first support member 11 may be omitted. In other words, instead of the step of supporting the SiC wafer source 1 by the first support member 11, a step of supporting the SiC wafer source 1 by a tool that supports or clamps the SiC wafer source 1 from the side surface 4 side may be performed.

[0132] In the above-described embodiments, examples have been described in which the first support member 11 is made of a material (amorphous plate) different from the SiC wafer source 1. However, in the above-described embodiments, a first support member 11 having a similar configuration to the second support member 21 may be employed. In this case, the description of the second support member 21 applies to the specific configuration of the first support member 11.

[0133] In each of the above-described embodiments, the first edge portion 5 and the second edge portion 6 of the SiC wafer source 1 are not chamfered. However, a configuration in which the first edge portion 5 is chamfered while the second edge portion 6 is not chamfered may be employed. In this case, the first edge portion 5 may be obliquely inclined from the first main surface 2 toward the side surface 4. In this case, the first edge portion 5 may be R-chamfered or C-chamfered.

[0134] In each of the above-described embodiments, the SiC wafer source 1 has the first orientation flat 7 as an example of a mark indicating the crystal orientation of the SiC single crystal. However, the SiC wafer source 1 may have an orientation notch as an example of a mark indicating the crystal orientation of the SiC single crystal instead of the first orientation flat 7.

[0135] The orientation notch may be a triangular notch recessed from the side surface 4 toward the center. The orientation notch may be recessed in the a-axis direction of the SiC single crystal. The orientation notch does not necessarily have to be recessed in the a-axis direction, but may be recessed in the m-axis direction. Of course, the SiC wafer source 1 may have an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.

[0136] In each of the above-described embodiments, the second support member 21 has the second orientation flat 27 as an example of a mark indicating the crystal orientation of the SiC single crystal (the crystal orientation of the SiC wafer source 1). However, instead of the second orientation flat 27, the second support member 21 may have an orientation notch as an example of a mark indicating the crystal orientation of the SiC single crystal (the crystal orientation of the SiC wafer source 1).

[0137] The orientation notch may be a triangular cutout recessed from the plate side surface 24 toward the center. The orientation notch may be recessed in the a-axis direction of the SiC single crystal. The orientation notch does not necessarily have to be recessed in the a-axis direction, but may be recessed in the m-axis direction. Of course, the second support member 21 may have an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction. Furthermore, in each of the above-described embodiments, a second support member 21 without a second orientation flat 27 (orientation notch) may be used.

[0138] In the above-described embodiments, examples have been described in which the SiC wafer structure 35 is supported from the first wafer main surface 42 side by the third support members 61 (see step S24 in FIG. 4 and FIG. 5M, etc.). However, the SiC wafer structure 35 does not necessarily have to be supported by the third support members 61. For example, when a tool that supports or clamps the SiC wafer structure 35 from the side surface 4 side is used, the step of supporting the SiC wafer structure 35 by the third support members 61 may be omitted. In other words, instead of the step of supporting the SiC wafer structure 35 by the third support members 61, a step of supporting the SiC wafer structure 35 by a tool that supports or clamps the SiC wafer structure 35 from the side surface 4 side may be performed.

[0139] In each of the above-described embodiments, examples have been described in which laser light is irradiated inside or near second amorphous bonding layer 32 to form modified layer 70 along the horizontal direction parallel to first main surface 2 (see also step S25 of FIG. 4 and FIG. 5N, etc.). However, although modified layer 70 is preferably formed inside or near second amorphous bonding layer 32, it does not necessarily have to be formed inside or near second amorphous bonding layer 32.

[0140] For example, a modified layer 70 may be formed in the middle of the thickness direction of the SiC epi-wafer 41 (SiC wafer 34) along a horizontal direction parallel to the first main surface 2 by irradiating the middle of the thickness direction of the SiC epi-wafer 41 (SiC wafer 34) with laser light. The laser light may be irradiated into the interior of the SiC epi-wafer 41 (SiC wafer 34) through the second support member 21 and the second amorphous bonding layer 32.

[0141] In this case, the modified layer 70 is preferably formed in the region of the SiC epi-wafer 41 between the second amorphous bonding layer 32 and the SiC epitaxial layer 37. That is, the modified layer 70 is preferably formed only on the SiC wafer 34. According to this process, by utilizing the process of removing the second support member 21, the thickness of the SiC epi-wafer 41 (SiC wafer 34) can be adjusted afterwards even after the SiC wafer structure 35 is obtained.

[0142] Fig. 9 is a plan view showing an SiC semiconductor device having a functional device according to one embodiment (hereinafter referred to as "SiC semiconductor device 81") Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 9.

[0143] 9 and 10, SiC semiconductor device 81 includes a SiC-SBD as an example of a functional device. SiC semiconductor device 81 includes a SiC chip 82 made of a hexagonal SiC single crystal. SiC chip 82 is made of an individual piece of SiC epi-wafer 41 and is formed in a rectangular parallelepiped shape. SiC chip 82 has a first main surface 83 on one side, a second main surface 84 on the other side, and first to fourth side surfaces 85A to 85D connecting first main surface 83 and second main surface 84.

[0144] The first main surface 83 and the second main surface 84 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 83 and the second main surface 84 face the c-plane of the SiC single crystal. It is preferable that the first main surface 83 faces the silicon face, and the second main surface 84 faces the carbon face.

[0145] When the SiC epi-wafer 41 has an off-axis angle, the first main surface 83 and the second main surface 84 each have an off-axis angle corresponding to the off-axis angle of the SiC epi-wafer 41. The second main surface 84 may be a rough surface having either or both of grinding marks and annealing marks (specifically, laser irradiation marks). The annealing marks may include amorphous SiC and / or SiC (specifically, Si) silicided (alloyed) with a metal (Ti).

[0146] The first side surface 85A and the second side surface 85B extend in a first direction X along the first main surface 83 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 85C and the fourth side surface 85D extend in the second direction Y and face the first direction X. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal.

[0147] The SiC semiconductor device 81 includes an n-type (first conductivity type) first semiconductor region 86 (high-concentration region) formed in a surface layer portion of the second main surface 84. The first semiconductor region 86 forms the cathode of the SiC-SBD. The first semiconductor region 86 may also be referred to as a cathode region. The first semiconductor region 86 has a substantially constant n-type impurity concentration in the thickness direction. The first semiconductor region 86 is formed over the entire surface layer portion of the second main surface 84. In other words, the first semiconductor region 86 includes parts of the second main surface 84 and the first to fourth side surfaces 85A to 85D. The first semiconductor region 86 is formed by an n-type SiC substrate that is part of the SiC wafer 34.

[0148] The SiC semiconductor device 81 includes an n-type second semiconductor region 87 (low-concentration region) formed in a surface layer portion of the first main surface 83. The second semiconductor region 87 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 86. The second semiconductor region 87 is electrically connected to the first semiconductor region 86 and forms a cathode of the SiC-SBD together with the first semiconductor region 86. The second semiconductor region 87 may also be referred to as a drift region. The second semiconductor region 87 is formed over the entire surface layer portion of the first main surface 83 and includes parts of the first main surface 83 and the first to fourth side surfaces 85A to 85D. The second semiconductor region 87 is formed by an n-type SiC epitaxial layer 37.

[0149] The SiC semiconductor device 81 includes an n-type third semiconductor region 88 (concentration transition region) interposed between the first semiconductor region 86 and the second semiconductor region 87 in the SiC chip 82. The third semiconductor region 88 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration of the first semiconductor region 86 to the n-type impurity concentration of the second semiconductor region 87. The third semiconductor region 88 is interposed over the entire area between the first semiconductor region 86 and the second semiconductor region 87, and has parts of the first to fourth side surfaces 85A to 85D.

[0150] The third semiconductor region 88, together with the first semiconductor region 86 and the second semiconductor region 87, forms the cathode of the SiC-SBD. The third semiconductor region 88 may also be referred to as a buffer region. The third semiconductor region 88 is formed by the n-type SiC epitaxial layer 37.

[0151] SiC semiconductor device 81 includes a p-type (second conductivity type) guard region 89 formed in a surface layer portion of first main surface 83. Guard region 89 is formed on first main surface 83 at a distance inward from the periphery (first to fourth side surfaces 85A to 85D) of first main surface 83, exposing an inner portion of first main surface 83. In this embodiment, guard region 89 is formed in a quadrangular ring shape surrounding the inner portion of first main surface 83 in a plan view.

[0152] The SiC semiconductor device 81 includes a first inorganic insulating film 46 formed on a first main surface 83. In this embodiment, the first inorganic insulating film 46 is made of a field oxide film containing an oxide of the SiC chip 82 (second semiconductor region 87). The first inorganic insulating film 46 is formed in a quadrangular ring shape surrounding the inner part of the first main surface 83 in a plan view, and has contact openings 48 that expose the inner edge portions of the second semiconductor region 87 and the guard region 89.

[0153] In plan view, contact opening 48 is formed in a quadrangular shape having four sides parallel to the periphery of first main surface 83. In plan view, first inorganic insulating film 46 covers the entire outer periphery of guard region 89 and exposes the entire inner periphery of guard region 89. First inorganic insulating film 46 is formed at a distance inward from the periphery of first main surface 83, exposing the periphery of first main surface 83 (second semiconductor region 87).

[0154] The SiC semiconductor device 81 includes a first principal surface electrode 50 that forms a Schottky junction with the first principal surface 83 within the contact opening 48. This forms a SiC-SBD that includes the first principal surface electrode 50 as an anode and the second semiconductor region 87 as a cathode. The first principal surface electrode 50 is formed in a quadrangle shape having four sides parallel to the periphery of the first principal surface 83 in a plan view. The first principal surface electrode 50 includes an extension portion that is extended onto the first inorganic insulating film 46. The extension portion faces the guard region 89 with the first inorganic insulating film 46 sandwiched therebetween.

[0155] In this embodiment, the first principal surface electrode 50 has a layered structure including a first electrode film 91, a second electrode film 92, and a third electrode film 93, which are layered in this order from the SiC chip 82 side. The first electrode film 91 is formed in a film shape along the first principal surface 83 and the principal surface of the first inorganic insulating film 46. The first electrode film 91 is made of a Schottky barrier electrode film, and forms a Schottky junction with the first principal surface 83 (second semiconductor region 87). The electrode material of the first electrode film 91 is arbitrary as long as a Schottky junction with the first principal surface 83 (second semiconductor region 87) is formed. In this embodiment, the first electrode film 91 is made of a titanium film.

[0156] The second electrode film 92 is made of a metal barrier film formed in a film shape on the first electrode film 91. The second electrode film 92 may be made of a Ti-based metal film. In this embodiment, the second electrode film 92 includes a titanium nitride film. The third electrode film 93 is formed in a film shape along the main surface of the second electrode film 92. The third electrode film 93 is made of a Cu-based metal film or an Al-based metal film. The third electrode film 93 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0157] The SiC semiconductor device 81 includes a second inorganic insulating film 52 that selectively covers the first main surface 83, the first inorganic insulating film 46, and the first main surface electrode 50. The second inorganic insulating film 52 has a first pad opening 54 that exposes the first main surface electrode 50. The first pad opening 54 is formed in a quadrangle shape having four sides parallel to the periphery of the first main surface 83 in a plan view. The second inorganic insulating film 52 has a first dicing street 55 that exposes a peripheral portion of the first main surface 83 between itself and the periphery of the first main surface 83. The first dicing street 55 is defined in a quadrangular ring shape that extends along the periphery of the first main surface 83.

[0158] The SiC semiconductor device 81 includes an organic insulating film 56 formed on the second inorganic insulating film 52. The organic insulating film 56 has a second pad opening 57 that communicates with the first pad opening 54 and exposes the first main surface electrode 50. The second pad opening 57 is formed in a quadrangular shape having four sides parallel to the periphery of the first main surface 83 in a plan view. The organic insulating film 56 has a first dicing street 55 and a second dicing street 58 that exposes the periphery of the first main surface 83. The second dicing street 58 is defined in a quadrangular ring shape that extends along the periphery of the first main surface 83.

[0159] The SiC semiconductor device 81 includes a second principal surface electrode 71 covering the second principal surface 84. The second principal surface electrode 71 may be referred to as a cathode electrode. The second principal surface electrode 71 covers the entire second principal surface 84 and is continuous with the periphery (first to fourth side surfaces 85A to 85D) of the first principal surface 83. The second principal surface electrode 71 forms ohmic contact with the first semiconductor region 86 (second principal surface 84).

[0160] Fig. 11 is a plan view showing an SiC semiconductor device having a functional device according to another embodiment (hereinafter referred to as "SiC semiconductor device 101"). Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 11. Fig. 13 is a cross-sectional view showing a main part of the functional device.

[0161] 11 to 13, SiC semiconductor device 101 includes a SiC-MISFET as an example of a functional device. SiC semiconductor device 101 includes a SiC chip 102. SiC chip 102 is made of an individual piece of SiC epi-wafer 41 and is formed in a rectangular parallelepiped shape. SiC chip 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and first to fourth side surfaces 105A to 105D connecting first main surface 103 and second main surface 104.

[0162] The first main surface 103 and the second main surface 104 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 103 and the second main surface 104 are formed in a quadrangular shape in a plan view. The first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. It is preferable that the first main surface 103 faces the silicon face and the second main surface 104 faces the carbon face.

[0163] When the SiC epitaxial wafer 41 has an off-axis angle, the first main surface 103 and the second main surface 104 each have an off-axis angle corresponding to the off-axis angle of the SiC epitaxial wafer 41. The second main surface 104 may be a rough surface having either or both of grinding marks and annealing marks (specifically, laser irradiation marks). The annealing marks may include amorphous SiC and / or SiC (specifically, Si) silicided (alloyed) with a metal (Ti).

[0164] The first to fourth side surfaces 105A to 105D form the periphery of the first main surface 103 and the periphery of the second main surface 104. The first side surface 105A and the second side surface 105B extend in a first direction X along the first main surface 103 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 105C and the fourth side surface 105D extend in the second direction Y and face the first direction X. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal.

[0165] The SiC semiconductor device 101 includes an n-type (first conductivity type) first semiconductor region 106 formed in a surface layer portion of the second main surface 104. The first semiconductor region 106 forms the drain of the SiC-MISFET. The first semiconductor region 106 may also be referred to as a drain region. The first semiconductor region 106 has a substantially constant n-type impurity concentration in the thickness direction. The first semiconductor region 106 is formed over the entire surface layer portion of the second main surface 104, and includes parts of the second main surface 104 and the first to fourth side surfaces 105A to 105D. The first semiconductor region 106 is formed by an n-type SiC substrate consisting of part of the SiC wafer 34.

[0166] The SiC semiconductor device 101 includes an n-type second semiconductor region 107 formed in a surface layer portion of the first main surface 103. The second semiconductor region 107 is electrically connected to the first semiconductor region 106 and, together with the first semiconductor region 106, forms the drain of the SiC-MISFET. The second semiconductor region 107 may also be referred to as a drift region. The second semiconductor region 107 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 106. The second semiconductor region 107 is formed over the entire surface layer portion of the first main surface 103 and includes parts of the first main surface 103 and the first to fourth side surfaces 105A to 105D. The second semiconductor region 107 is formed by an n-type SiC epitaxial layer 37.

[0167] The SiC semiconductor device 101 includes an n-type third semiconductor region 108 (concentration transition region) interposed between the first semiconductor region 106 and the second semiconductor region 107 in the SiC chip 102. The third semiconductor region 108 is electrically connected to the first semiconductor region 106 and the second semiconductor region 107, and forms the drain of the SiC-MISFET together with the first semiconductor region 106 and the second semiconductor region 107. The third semiconductor region 108 may also be referred to as a buffer region.

[0168] The third semiconductor region 108 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration of the first semiconductor region 106 to the n-type impurity concentration of the second semiconductor region 107. The third semiconductor region 108 is interposed over the entire area between the first semiconductor region 106 and the second semiconductor region 107, and has parts of the first to fourth side surfaces 105A to 105D. The third semiconductor region 108 is formed of an n-type epitaxial layer (SiC epitaxial layer 37).

[0169] The SiC semiconductor device 101 includes a p-type (second conductivity type) body region 110 formed in a surface layer portion of the first main surface 103. The body region 110 forms a part of the body diode of the SiC-MISFET.

[0170] The SiC semiconductor device 101 includes an n-type source region 111 formed in a surface layer portion of a body region 110. The source region 111 forms the source of the SiC-MISFET. The source region 111 has an n-type impurity concentration that exceeds the n-type impurity concentration of the second semiconductor region 107. The source region 111 forms a channel of the SiC-MISFET together with the second semiconductor region 107 in the body region 110.

[0171] The SiC semiconductor device 101 includes a plurality of trench gate structures 121 formed on the first main surface 103 so as to cross the body region 110 and the source region 111 and reach the second semiconductor region 107. The plurality of trench gate structures 121 form gates of the SiC-MISFET and control the on / off of the channel. In other words, the SiC-MISFET is of a trench gate type.

[0172] The plurality of trench gate structures 121 may each be formed in a strip shape (rectangular shape) extending in the first direction X in a plan view, and may be formed at intervals in the second direction Y. The trench gate structures 121 are formed at intervals from the bottom of the second semiconductor region 107 toward the first main surface 103, and face the first semiconductor region 106 (third semiconductor region 108) with part of the second semiconductor region 107 in between. Each of the plurality of trench gate structures 121 has a first depth D1.

[0173] Each trench gate structure 121 includes a gate trench 122, a gate insulating film 123, and a gate electrode 124. The gate trench 122 is formed in the first main surface 103 and forms the sidewalls and bottom wall (inner wall and outer wall) of the trench gate structure 121. The gate insulating film 123 is formed in the form of a film on the inner wall of the gate trench 122 and covers the second semiconductor region 107, the body region 110, and the source region 111. The gate electrode 124 is buried in the gate trench 122 with the gate insulating film 123 sandwiched between them. The gate electrode 124 faces the second semiconductor region 107, the body region 110, and the source region 111 with the gate insulating film 123 sandwiched between them. A gate potential is applied to the gate electrode 124.

[0174] The SiC semiconductor device 101 includes a plurality of trench source structures 131 formed in the first main surface 103 so as to cross the body region 110 and the source region 111 and reach the second semiconductor region 107. The plurality of trench source structures 131 are each formed in a region between two adjacent trench gate structures 121 on the first main surface 103. The plurality of trench source structures 131 may each be formed in a strip shape extending in the first direction X in a plan view. Each trench source structure 131 is formed at an interval from the bottom of the second semiconductor region 107 toward the first main surface 103, and faces the first semiconductor region 106 (third semiconductor region 108) with a part of the second semiconductor region 107 sandwiched between them.

[0175] Each trench source structure 131 has a second depth D2 (D1 < D2) that exceeds the first depth D1 of the trench gate structure 121. The second depth D2 is preferably 1.5 times or more and 3 times or less the first depth D1. The bottom wall of each trench source structure 131 is located on the bottom side of the second semiconductor region 107 with respect to the bottom wall of each trench gate structure 121. Of course, each trench source structure 131 may have a second depth D2 that is approximately equal to the first depth D1 (D1 ≒ D2).

[0176] Each trench source structure 131 includes a source trench 132, a source insulating film 133, and a source electrode 134. The source trench 132 is formed on the first main surface 103 and forms the side wall and the bottom wall (inner wall and outer wall) of the trench source structure 131. The source insulating film 133 is formed in a film shape on the inner wall of the source trench 132 and covers the second semiconductor region 107, the body region 110, and the source region 111. The source electrode 134 is embedded in the source trench 132 with the source insulating film 133 interposed therebetween. A source potential is applied to the source electrode 134.

[0177] The SiC semiconductor device 101 includes a plurality of p-type contact regions 140 formed in regions along the plurality of trench source structures 131 in the surface layer portion of the first main surface 103. The plurality of contact regions 140 each have a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 110.

[0178] The plurality of contact regions 140 may be formed in a one-to-many correspondence with respect to each trench source structure 131 in a plan view. In this case, the plurality of contact regions 140 are formed at intervals along each trench source structure 131 in a plan view, partially exposing each trench source structure 131. Each contact region 140 may be formed in a strip shape extending in the first direction X in a plan view. Each contact region 140 covers the side wall and the bottom wall of each trench source structure 131 in the second semiconductor region 107 and is electrically connected to the body region 110.

[0179] The SiC semiconductor device 101 includes a plurality of p-type well regions 141 formed in regions along the plurality of trench source structures 131 in a surface layer portion of the first main surface 103. The plurality of well regions 141 each have a p-type impurity concentration less than the p-type impurity concentration of each contact region 140. It is preferable that the p-type impurity concentration of the plurality of well regions 141 exceeds the p-type impurity concentration of the body region 110.

[0180] The multiple well regions 141 cover the corresponding trench source structures 131 in a one-to-one correspondence with the multiple trench source structures 131, respectively. Each well region 141 may be formed in a strip shape extending along the corresponding trench source structure 131. Each well region 141 covers the sidewalls and bottom wall of each trench source structure 131 and is electrically connected to the body region 110. Each well region 141 may include a portion that directly covers each trench source structure 131 and a portion that covers each trench source structure 131 with a contact region 140 sandwiched therebetween.

[0181] The SiC semiconductor device 101 includes a plurality of p-type gate well regions 142 formed in regions along the plurality of trench gate structures 121 in a surface layer portion of the first main surface 103. The plurality of gate well regions 142 have p-type impurity concentrations lower than the p-type impurity concentrations of the plurality of contact regions 140. It is preferable that the p-type impurity concentration of each gate well region 142 be approximately equal to the p-type impurity concentration of each well region 141.

[0182] The multiple gate well regions 142 may cover the corresponding trench gate structures 121 in a one-to-one correspondence with the multiple trench gate structures 121. Each gate well region 142 may be formed in a strip shape extending along the corresponding trench gate structure 121. Each gate well region 142 covers the sidewall and bottom wall of the corresponding trench gate structure 121 and is electrically connected to the body region 110. The bottoms of the multiple gate well regions 142 are located closer to the bottom wall of the trench gate structure 121 than the bottoms of the multiple well regions 141.

[0183] The SiC semiconductor device 101 includes a main surface insulating film 150 covering the first main surface 103. The main surface insulating film 150 may have a single-layer structure made of a silicon oxide film. The main surface insulating film 150 is continuous with the gate insulating film 123 and the source insulating film 133, and exposes the gate electrode 124 and the source electrode 134.

[0184] The SiC semiconductor device 101 includes a first inorganic insulating film 46 formed on a main surface insulating film 150. The first inorganic insulating film 46 selectively covers the plurality of trench gate structures 121 and the plurality of trench source structures 131. The first inorganic insulating film 46 has a plurality of contact openings 48 that selectively expose the plurality of trench gate structures 121 and the plurality of trench source structures 131, respectively.

[0185] The SiC semiconductor device 101 includes a first principal surface electrode 50 formed on the first inorganic insulating film 46. The first principal surface electrode 50 includes a gate principal surface electrode 151, a source principal surface electrode 152, and a gate wiring electrode 153. The gate principal surface electrode 151 may also be referred to as a gate pad electrode. The source principal surface electrode 152 may also be referred to as a source pad electrode. The gate wiring electrode 153 may also be referred to as a gate finger electrode.

[0186] The gate principal surface electrode 151 is electrically connected to the plurality of trench gate structures 121 (gate electrodes 124), and applies an externally input gate potential (gate signal) to the plurality of trench gate structures 121. In this embodiment, the gate principal surface electrode 151 is disposed in a region facing the center of the first side surface 105A on the periphery of the first principal surface 103. The gate principal surface electrode 151 is formed in a quadrilateral shape having four sides parallel to the first principal surface 103 in a plan view.

[0187] The source principal surface electrode 152 is disposed on the first principal surface 103 at a distance from the gate principal surface electrode 151. The source principal surface electrode 152 is electrically connected to the plurality of trench source structures 131 (source electrodes 134), and applies a source potential input from the outside to the plurality of trench source structures 131. In this embodiment, the source principal surface electrode 152 is formed in a quadrilateral shape having four sides parallel to the first principal surface 103 in a plan view.

[0188] Specifically, the source principal surface electrode 152 is formed in a polygonal shape having a recess recessed inward into the first principal surface 103 so as to align with the gate principal surface electrode 151 on the side along the first side surface 105A in a plan view. The source principal surface electrode 152 extends from above the first inorganic insulating film 46 into the plurality of contact openings 48 and is electrically connected to the plurality of trench source structures 131, the plurality of source regions 111, and the plurality of contact regions 140.

[0189] The gate wiring electrode 153 is drawn out from the gate principal surface electrode 151 onto the first inorganic insulating film 46. The gate wiring electrode 153 transmits the gate potential applied to the gate principal surface electrode 151 to other regions. The gate wiring electrode 153 is formed in a strip shape extending along the first to fourth side surfaces 105A to 105D in a plan view, and faces the source principal surface electrode 152 from multiple directions.

[0190] The gate wiring electrode 153 intersects (specifically, is perpendicular to) the end of the trench gate structure 121 in plan view. The gate wiring electrode 153 enters the plurality of contact openings 48 from above the first inorganic insulating film 46 and is electrically connected to the plurality of trench gate structures 121 (gate electrodes 124). As a result, the gate potential applied to the gate principal surface electrode 151 is imparted to the plurality of trench gate structures 121 via the gate wiring electrode 153.

[0191] The first principal surface electrode 50 has a laminated structure including a first electrode film 154 and a second electrode film 155 laminated in this order from the first inorganic insulating film 46 side. The first electrode film 154 is made of a metal barrier film formed in a film shape along the first inorganic insulating film 46. In this embodiment, the first electrode film 154 is made of a Ti-based metal film. The first electrode film 154 may include at least one of a titanium film and a titanium nitride film.

[0192] The second electrode film 155 is formed in a film shape along the first electrode film 154. The first electrode film 154 is made of a Cu-based metal film or an Al-based metal film. The first electrode film 154 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0193] The SiC semiconductor device 101 includes a second inorganic insulating film 52 that selectively covers the first main surface 103, the first inorganic insulating film 46, and the first main surface electrode 50. The second inorganic insulating film 52 has a plurality of first pad openings 54 that expose the first main surface electrode 50. The plurality of first pad openings 54 include a first gate pad opening 161 and a first source pad opening 162.

[0194] The first gate pad opening 161 selectively exposes an inner portion of the gate principal surface electrode 151. The first source pad opening 162 selectively exposes an inner portion of the source principal surface electrode 152. The second inorganic insulating film 52 has a first dicing street 55 between itself and the periphery of the first principal surface 103, exposing the periphery of the first principal surface 103. The first dicing street 55 is defined in a quadrangular ring shape extending along the periphery of the first principal surface 103.

[0195] The SiC semiconductor device 101 includes an organic insulating film 56 that selectively covers the first inorganic insulating film 46, the second inorganic insulating film 52, and the first principal surface electrode 50. The organic insulating film 56 has a plurality of second pad openings 57. The plurality of second pad openings 57 includes a second gate pad opening 171 and a second source pad opening 172.

[0196] The second gate pad opening 171 communicates with the first gate pad opening 161 and exposes an inner portion of the gate principal surface electrode 151. The second source pad opening 172 communicates with the first source pad opening 162 and exposes an inner portion of the source principal surface electrode 152. The organic insulating film 56 has second dicing streets 58 that expose the peripheral portion of the first main surface 103 together with the first dicing streets 55. The second dicing streets 58 are defined in the shape of a quadrangular ring that extends along the peripheral edge of the first main surface 103.

[0197] The SiC semiconductor device 101 includes a second principal surface electrode 71 covering the second principal surface 104. The second principal surface electrode 71 may also be referred to as a drain electrode. The second principal surface electrode 71 covers the entire second principal surface 104 and is continuous with the periphery (first to fourth side surfaces 105A to 105D) of the first principal surface 103. The second principal surface electrode 71 forms ohmic contact with the first semiconductor region 106 (second principal surface 104).

[0198] 11 to 13 have been described as examples in which the SiC-MISFET has the trench gate structure 121 and the trench source structure 131, but it is also possible to employ a SiC-MISFET that does not have the trench source structure 131. Also, while a trench-gate type SiC-MISFET has been described as examples in Fig. 11 to 13, a planar-gate type SiC-MISFET may also be employed.

[0199] Below are examples of features extracted from this specification and drawings.

[0200] [A1] A method for manufacturing a semiconductor device, comprising: a step of preparing a wafer source and a support member; a support step of supporting the wafer source with the support member; and a wafer separation step of cutting the wafer source horizontally from a middle portion of the wafer source in the thickness direction, and separating from the wafer source a wafer structure including the support member and a wafer cut off from the wafer source.

[0201] [A2] The method for manufacturing a semiconductor device according to A1, wherein the wafer source is prepared by cutting it from an ingot.

[0202] [A3] The method for manufacturing a semiconductor device according to A1 or A2, further comprising a step of transporting the wafer structure.

[0203] [A4] The method for manufacturing a semiconductor device according to any one of A1 to A3, further comprising a wafer source recycling step of repeating a series of steps including the supporting step and the wafer separating step until the wafer source becomes inseparable.

[0204] [A5] A method for manufacturing a semiconductor device according to any one of A1 to A4, wherein the cutting step of the wafer source includes a step of forming a modified layer along the horizontal direction in the middle of the thickness direction of the wafer source by a laser light irradiation method, and then cleaving the wafer source in the horizontal direction starting from the modified layer.

[0205] [A6] The method for manufacturing a semiconductor device according to any one of A1 to A5, further comprising the step of forming an epitaxial layer on the cut surface of the wafer.

[0206] [A7] The method for manufacturing a semiconductor device according to A6, further comprising the step of polishing the cut surface, wherein the epitaxial layer is formed on the polished surface of the wafer.

[0207] [A8] The method for manufacturing a semiconductor device according to any one of A1 to A5, further comprising the step of fabricating a functional device on the cut surface of the wafer.

[0208] [A9] The method for manufacturing a semiconductor device according to A8, further comprising the step of polishing the cut surface, wherein the functional device is formed on the polished surface of the wafer.

[0209] [A10] The method for manufacturing a semiconductor device according to A8 or A9, further comprising the step of removing the support member from the wafer after the functional device is formed.

[0210] [A11] The method for manufacturing a semiconductor device according to any one of A1 to A10, wherein the support member is made of the same material as the wafer source.

[0211] [A12] The method for manufacturing a semiconductor device according to A11, wherein the wafer source is made of SiC single crystal, and the support member is made of SiC single crystal or SiC polycrystal.

[0212] [A13] The method for manufacturing a semiconductor device according to any one of A1 to A12, wherein the support member is bonded to the wafer source by a direct bonding method.

[0213] [A14] A method for manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor and a second semiconductor; bonding the second semiconductor to the first semiconductor by a direct bonding method to form a semiconductor structure having an amorphous bonding layer between the first semiconductor and the second semiconductor; forming a modified layer in the amorphous bonding layer by a laser light irradiation method; and cleaving the semiconductor structure starting from the modified layer to separate the first semiconductor and the second semiconductor.

[0214] [A15] The method for manufacturing a semiconductor device according to A14, wherein the amorphous junction layer has a light absorption coefficient greater than the light absorption coefficient of the first semiconductor.

[0215] [A16] A method for manufacturing a semiconductor device according to A14 or A15, wherein the first semiconductor is made of SiC single crystal, the second semiconductor is made of SiC single crystal or SiC polycrystal, and the amorphous bonding layer is made of SiC amorphous bonding layer.

[0216] [B1] A method for manufacturing a SiC semiconductor device, comprising: a step of preparing a SiC wafer source having a silicon surface and a carbon surface; a supporting step of supporting the SiC wafer source from the carbon surface side using a supporting member; and a wafer separating step of cutting the SiC wafer source from a midpoint in the thickness direction of the SiC wafer source in a horizontal direction along the silicon surface, and separating from the SiC wafer source a SiC wafer structure including the supporting member and the SiC wafer cut off from the SiC wafer source.

[0217] [B2] The method for producing a SiC semiconductor device according to B1, wherein the SiC wafer structure includes the SiC wafer having a cut surface facing a silicon surface.

[0218] [B3] The method for producing a SiC semiconductor device according to B1 or B2, wherein the SiC wafer source is prepared by cutting it from a SiC ingot.

[0219] [B4] The method for producing a SiC semiconductor device according to any one of B1 to B3, further comprising the step of transporting the SiC wafer structure.

[0220] [B5] The method for manufacturing a SiC semiconductor device according to any one of B1 to B4, further comprising a SiC wafer source recycling step of repeating a series of steps including the supporting step and the wafer separating step until the SiC wafer source becomes inseparable.

[0221] [B6] The method for manufacturing a SiC semiconductor device according to any one of B1 to B5, wherein the cutting step of the SiC wafer source includes a step of forming a modified layer along the horizontal direction in a middle portion of the thickness direction of the SiC wafer source by a laser light irradiation method, and then cleaving the SiC wafer source in the horizontal direction starting from the modified layer.

[0222] [B7] The method for producing a SiC semiconductor device according to any one of B1 to B6, further comprising the step of forming a SiC epitaxial layer on a cut surface of the SiC wafer.

[0223] [B8] The method for manufacturing a SiC semiconductor device according to B7, further comprising the step of polishing the cut surface, wherein the SiC epitaxial layer is formed on the polished surface of the SiC wafer.

[0224] [B9] The method for manufacturing a SiC semiconductor device according to any one of B1 to B6, further comprising the step of fabricating a functional device on a cut surface of the SiC wafer.

[0225] [B10] The method for manufacturing a SiC semiconductor device according to B9, further comprising the step of polishing the cut surface, wherein the functional device is formed on the polished surface of the SiC wafer.

[0226] [B11] The method for manufacturing a SiC semiconductor device according to B9 or B10, further comprising the step of removing the support member from the SiC wafer after the functional device is formed.

[0227] [B12] The method for manufacturing a SiC semiconductor device according to any one of B9 to B11, wherein the functional device includes at least one of an SBD and a MISFET.

[0228] [B13] The method for manufacturing a SiC semiconductor device according to any one of B1 to B12, wherein the support member is made of a SiC support wafer.

[0229] [B14] The method for manufacturing a SiC semiconductor device according to any one of B1 to B13, wherein the support member is bonded to the carbon surface by a direct bonding method.

[0230] [B15] A method for manufacturing a SiC semiconductor device, comprising the steps of: preparing first SiC and second SiC; bonding the second SiC to the first SiC by a direct bonding method to form a SiC structure having a SiC amorphous bonding layer between the first SiC and the second SiC; irradiating the amorphous bonding layer with laser light to form a modified layer in the amorphous bonding layer; and cleaving the SiC structure starting from the modified layer to separate the first SiC and the second SiC.

[0231] [B16] The method for manufacturing a SiC semiconductor device according to B15, wherein the amorphous bonding layer has a light absorption coefficient greater than the light absorption coefficient of SiC.

[0232] [C1] A method for processing a SiC wafer source, comprising: a step of preparing a SiC wafer source having a silicon surface and a carbon surface; a supporting step of supporting the SiC wafer source from the carbon surface side using a supporting member; and a wafer separating step of cutting the SiC wafer source from a midpoint in the thickness direction of the SiC wafer source in a horizontal direction along the silicon surface, and separating from the SiC wafer source a SiC wafer structure including the supporting member and the SiC wafer cut off from the SiC wafer source.

[0233] [C2] The method for processing a SiC wafer source according to C1, wherein the SiC wafer structure includes the SiC wafer having a cut surface facing the silicon surface.

[0234] [C3] The method for processing a SiC wafer source according to C2, further comprising a step of polishing the cut surface of the SiC wafer.

[0235] [C4] The method for processing a SiC wafer source according to any one of C1 to C3, wherein the support member is made of a SiC support wafer.

[0236] [C5] The method for processing a SiC wafer source according to any one of C1 to C4, wherein the support member is bonded to the carbon surface by a direct bonding method.

[0237] [C6] A method for processing a SiC wafer source according to C5, wherein the support member is bonded to the carbon surface by a SiC amorphous bonding layer, and the SiC wafer structure includes the SiC amorphous bonding layer between the support member and the SiC wafer.

[0238] [C7] The method for processing a SiC wafer source according to C6, wherein the SiC amorphous bonding layer has an optical absorption coefficient greater than the optical absorption coefficient of SiC.

[0239] [C8] A method for processing a SiC wafer source according to C6 or C7, further comprising the steps of: irradiating the SiC amorphous bonding layer with laser light to form a modified layer in the SiC amorphous bonding layer; and cleaving the SiC wafer structure starting from the modified layer to separate the support member and the SiC wafer.

[0240] [D1] A wafer structure comprising: a first wafer; a second wafer supporting the first wafer; and an amorphous bonding layer interposed between the first wafer and the second wafer and bonding the first wafer and the second wafer together.

[0241] [D2] The wafer structure according to D1, wherein the amorphous bonding layer has a light absorption coefficient greater than the light absorption coefficient of the second wafer.

[0242] [D3] The wafer structure according to D1 or D2, wherein the first wafer is made of a single crystal of a wide bandgap semiconductor, the second wafer is made of a single crystal or polycrystal of a wide bandgap semiconductor, and the amorphous bonding layer is made of an amorphous layer of a wide bandgap semiconductor.

[0243] [D4] A wafer structure described in any one of D1 to D3, wherein the first wafer is made of SiC single crystal, the second wafer is made of SiC single crystal or SiC polycrystal, and the amorphous bonding layer is made of SiC amorphous bonding layer.

[0244] [D5] The wafer structure described in D4, wherein the first wafer has a first main surface formed by the silicon surface of the SiC single crystal and a second main surface formed by the carbon surface of the SiC single crystal, the second wafer has a third main surface formed by the silicon surface of the SiC single crystal and supporting the first wafer from the second main surface side, and a fourth main surface formed by the carbon surface of the SiC single crystal, and the amorphous bonding layer is interposed between the second main surface of the first wafer and the third main surface of the second wafer.

[0245] [D6] The wafer structure according to D5, wherein the first main surface has an off-angle of 10° or less with respect to the a-axis direction of the SiC single crystal.

[0246] [D7] The wafer structure according to D5 or D6, wherein the first main surface is a cleaved surface, a ground surface, a polished surface, or a mirror surface.

[0247] [D8] The wafer structure according to any one of D1 to D7, wherein the amorphous bonding layer has a thickness of 5 μm or less.

[0248] [D9] The wafer structure according to any one of D1 to D8, wherein the first wafer is formed in a disk shape or a cylindrical shape, and the second wafer is formed in a disk shape or a cylindrical shape.

[0249] [D10] The wafer structure according to any one of D1 to D9, wherein the second wafer has a planar area larger than that of the first wafer.

[0250] [D11] The wafer structure according to any one of D1 to D10, wherein the second wafer is thicker than the first wafer.

[0251] [D12] The wafer structure according to any one of D1 to D11, wherein the second wafer has an impurity concentration different from that of the first wafer.

[0252] [D13] The wafer structure according to D12, wherein the second wafer has an impurity concentration lower than the impurity concentration of the first wafer.

[0253] [D14] The wafer structure according to D12 or D13, wherein the second wafer is undoped.

[0254] [D15] A wafer structure described in any one of D1 to D14, wherein the first wafer includes a first mark indicating a crystal orientation, and the second wafer includes a second mark indirectly indicating the crystal orientation of the first wafer.

[0255] [D16] A wafer structure according to D15, wherein the first mark includes either or both of a first orientation flat and a first orientation notch, and the second mark includes either or both of a second orientation flat and a second orientation notch.

[0256] [D17] A SiC wafer structure comprising: a first SiC wafer having a first main surface on one side and a second main surface on the other side; a second SiC wafer supporting the first SiC wafer from the second main surface side; and an amorphous bonding layer interposed between the first SiC wafer and the second SiC wafer and bonding the first SiC wafer and the second SiC wafer together.

[0257] [D18] The SiC wafer structure according to D17, wherein the amorphous bonding layer has a light absorption coefficient greater than the light absorption coefficient of the second SiC wafer.

[0258] [D19] The SiC wafer structure according to D17 or D18, wherein the second SiC wafer has a diameter larger than that of the first SiC wafer.

[0259] [D20] The SiC wafer structure according to any one of D17 to D19, wherein the amorphous bonding layer contains at least carbon.

[0260] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0261] 1. SiC wafer source 21 second support member 32 Second amorphous bonding layer 33 Modified layer 34 SiC wafers 35 SiC wafer structure 36 Cut surface 37 SiC epitaxial layer 70 Modified layer

Claims

1. providing a wafer source and one side support member; a supporting step of supporting the wafer source by the one-side support member; a wafer separation step of cutting the wafer source horizontally from a middle portion in a thickness direction of the wafer source, and separating from the wafer source a wafer structure including the one-side support member and the wafer cut off from the wafer source; fabricating functional devices on the cut surfaces of the wafer; a step of supporting the wafer supported by the one-side support member from the cut surface side by a second-side support member after the functional device is formed; removing the one-side support member from the wafer supported by the other-side support member; A method for manufacturing a semiconductor device, wherein the cutting process of the wafer source includes a process of forming a modified layer along the horizontal direction in the middle of the thickness direction of the wafer source by a laser light irradiation method, and then cleaving the wafer source in the horizontal direction starting from the modified layer.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the wafer source is cut from an ingot.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of transporting the wafer structure.

4. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a wafer source recycling step of repeating a series of steps including the supporting step and the wafer separating step until the wafer source becomes unseparable.

5. 5. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming an epitaxial layer on the cut surface of the wafer.

6. further comprising a step of polishing the cut surface; 6. The method for manufacturing a semiconductor device according to claim 5, wherein the epitaxial layer is formed on a polished surface of the wafer.

7. further comprising a step of polishing the cut surface; 7. The method for manufacturing a semiconductor device according to claim 1, wherein the functional device is formed on a polished surface of the wafer.

8. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the one-side support member is made of the same material as the wafer source.

9. the wafer source is made of a SiC single crystal; 9. The method for manufacturing a semiconductor device according to claim 8, wherein the one-side support member is made of SiC single crystal or SiC polycrystal.

10. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the one-side support member is bonded to the wafer source by a direct bonding method.

11. providing a first semiconductor made of SiC single crystal and having a first thickness, and a second semiconductor made of SiC single crystal or SiC polycrystal and having a second thickness greater than the first thickness; a step of bonding the second semiconductor to the first semiconductor by a direct bonding method to form a semiconductor structure having an amorphous bonding layer made of a SiC amorphous bonding layer between the first semiconductor and the second semiconductor; a step of forming a modified layer in the amorphous bonding layer by a laser beam irradiation method, by setting a focusing part within the amorphous bonding layer or within a thickness range of ±50 μm from a position where the amorphous bonding layer is formed, and irradiating the amorphous bonding layer with a laser beam through the second semiconductor; cleaving the semiconductor structure starting from the modified layer to separate the first semiconductor and the second semiconductor.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the amorphous junction layer has a light absorption coefficient greater than a light absorption coefficient of the first semiconductor.

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