Semiconductor substrate and method for manufacturing semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of improving the handleability of the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes the steps of preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion so as to form a resonator surface at least in the compound semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion into a plurality of element portions.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor substrates and the like. [Background technology]

[0002] When semiconductor devices such as semiconductor laser elements are made smaller, the handling of the semiconductor devices becomes difficult. Patent Document 1 describes a technique relating to the handling of semiconductor laser elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-252069 Summary of the Invention

[0004] A method for manufacturing a semiconductor device in one aspect of the present disclosure includes the steps of preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion so as to form a resonator surface in at least the compound semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion into a plurality of element portions.

[0005] In addition, a method for manufacturing a semiconductor device according to an aspect of the present disclosure includes the steps of: preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion; and dividing the base semiconductor portion and the compound semiconductor portion to form a plurality of optical resonators, each including a resonator surface. In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number of resonators less than the number of the plurality of optical resonators.

[0006] A template substrate according to one aspect of the present disclosure includes a main substrate, a seed portion, and a mask, wherein the mask includes an elongated opening and a mask portion, and the opening is provided with a notch.

[0007] A semiconductor device according to an embodiment of the present disclosure includes a base semiconductor portion and a compound semiconductor portion located above the base semiconductor portion and having an optical resonator including a pair of resonator planes. The base semiconductor portion and the compound semiconductor portion include GaN-based semiconductors. The base semiconductor portion includes an m-plane cleavage plane of the GaN-based semiconductor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view illustrating a structure of a semiconductor laser element according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a perspective view for explaining an optical resonator included in the semiconductor laser element. [Figure 3] 1 is a flowchart illustrating an example of a manufacturing method of a semiconductor laser device according to an embodiment of the present disclosure. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating a configuration of a template substrate according to an embodiment of the present disclosure. [Figure 5] FIG. 2 is a cross-sectional view illustrating a semiconductor substrate according to an embodiment of the present disclosure. [Figure 6A] FIG. 10 is a plan view for explaining an example of an element isolation process. [Figure 6B] FIG. 6B is a cross-sectional view taken along the line B-VI in FIG. 6A. [Figure 7] 1 is a flowchart illustrating an example of a mounting stage of a method for manufacturing a semiconductor laser device according to an embodiment of the present disclosure. [Figure 8] FIG. 1 is a block diagram illustrating an example of a manufacturing apparatus. [Figure 9] 3 is a flowchart showing an example of a method for manufacturing the semiconductor laser device in the first embodiment. [Figure 10]FIG. 2 is a cross-sectional view showing the configuration of a template substrate in Example 1. [Figure 11A] FIG. 11 is an enlarged view of a main part of FIG. [Figure 11B] FIG. 2 is a plan view showing an example of an initiation inducing part of the first embodiment. [Figure 11C] FIG. 4 is a plan view showing another example of the initiation inducing part of the first embodiment. [Figure 11D] FIG. 4 is a plan view showing another example of the initiation inducing part of the first embodiment. [Figure 11E] FIG. 4 is a plan view showing another example of the initiation inducing part of the first embodiment. [Figure 12] 3 is a cross-sectional view showing an example of lateral growth of a base semiconductor layer in Example 1. FIG. [Figure 13] FIG. 2 is a plan view for explaining a base semiconductor layer in the first embodiment. [Figure 14] 4 is an enlarged view for explaining the growth of the base semiconductor layer around the initiation site inducing portion in Example 1. FIG. [Figure 15] 1 is a cross-sectional view showing the configuration of a compound semiconductor layer in Example 1. FIG. [Figure 16] FIG. 2 is a plan view for explaining a compound semiconductor layer in the first embodiment. [Figure 17] FIG. 2 is a plan view for explaining an example of an element isolation process in the first embodiment. [Figure 18] FIG. 2 is an exploded perspective view for explaining the configuration of a half element portion in Example 1. [Figure 19] FIG. 2 is a perspective view for explaining the configuration of an element portion in Example 1. [Figure 20] 1 is a cross-sectional view showing the configuration of an element portion in Example 1. FIG. [Figure 21] 4A to 4C are cross-sectional views schematically illustrating a step of separating an element portion from a template substrate in the manufacturing method of the semiconductor laser element of Example 1. [Figure 22] FIG. 2 is a perspective view schematically showing a state in which an element portion is bonded to a support substrate. [Figure 23]FIG. 10 is a cross-sectional view schematically showing a state in which an element portion DS is bonded to a support substrate SK. [Figure 24] 4A to 4C are cross-sectional views schematically illustrating a step of forming a reflective film on a cavity facet in a manufacturing method of the semiconductor laser device of Example 1. [Figure 25] FIG. 2 is a plan view showing the configuration of the compound semiconductor layer after a reflector film is formed. [Figure 26] 4A to 4C are cross-sectional views schematically illustrating a step of dividing the support substrate in the manufacturing method of the semiconductor laser device of Example 1. [Figure 27] 10 is a plan view for explaining another example of the base semiconductor layer in the first embodiment. FIG. [Figure 28] FIG. 10 is an exploded perspective view for explaining another example of the configuration of the half element portion in the first embodiment. [Figure 29] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor laser device in Example 2. [Figure 30] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor laser device in Example 2. [Figure 31] 10 is a flowchart showing an example of a method for manufacturing a semiconductor laser device according to a third embodiment. [Figure 32] FIG. 10 is a plan view showing the configuration of a semiconductor substrate on which a base semiconductor layer is formed in Example 3. [Figure 33] FIG. 10 is a plan view showing the configuration of a semiconductor substrate on which an element structure is formed in Example 3. [Figure 34] FIG. 34 is a cross-sectional view showing the configuration of the semiconductor substrate of FIG. 33. [Figure 35] FIG. 10 is a plan view showing an example of element isolation in Example 4. [Figure 36] FIG. 10 is a schematic diagram illustrating the configuration of an electronic device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following description is intended to facilitate a better understanding of the gist of the present disclosure and does not limit the present disclosure unless otherwise specified. Unless otherwise specified in this specification, "A to B" representing a numerical range means "A or more and B or less." Furthermore, the shapes and dimensions (length, width, etc.) of the configurations shown in each drawing in this application do not necessarily reflect the actual shapes and dimensions, and have been changed as appropriate for clarity and simplification of the drawings.

[0010] In the embodiments of the present disclosure, a semiconductor laser (laser diode; LD) element will be described as an example of a semiconductor device, but the semiconductor device of the present disclosure is not necessarily limited to this. The semiconductor device of the present disclosure may be, for example, a sensor having an optical resonator or a sensor on which a resonator surface is formed.

[0011] In the following description, first, a structure of a semiconductor laser device according to an embodiment of the present disclosure will be briefly described, and then a manufacturing method of a semiconductor laser device according to an embodiment of the present disclosure will be described in detail.

[0012] [Semiconductor laser element] A semiconductor laser device 20 according to an embodiment of the present disclosure will be described below with reference to Fig. 1 and Fig. 2. Fig. 1 is a perspective view illustrating the structure of the semiconductor laser device 20. Fig. 2 is a perspective view illustrating the optical resonator LK of the semiconductor laser device 20. Note that Fig. 1 is merely an example, and the semiconductor laser device 20 may have a shape in which the depth direction in the perspective view shown in Fig. 1 is the longitudinal direction.

[0013] The semiconductor laser device 20 in one embodiment of the present disclosure has a structure having electrodes on the upper and lower sides (hereinafter referred to as a "double-sided electrode structure"), but is not limited thereto and may have, for example, a structure having two electrodes (anode and cathode) on the upper side (hereinafter referred to as a "single-sided, dual-electrode structure"). The semiconductor laser device 20 may be mounted on a support substrate (also referred to as a submount), and the support substrate is omitted in FIG. 1.

[0014] 1 and 2, a semiconductor laser element (semiconductor device) 20 in this embodiment includes a base semiconductor portion 8, a compound semiconductor portion 9 located above the base semiconductor portion 8 and including an optical resonator LK, a first electrode E1, a second electrode E2, and an insulating film DF. In the optical resonator LK, the surface from which the laser is emitted is referred to as an emission surface F1, and the surface opposite to the emission surface F1 is referred to as an opposing surface F2. The emission surface F1 and the opposing surface F2 form a pair of resonator surfaces in the optical resonator LK. Note that the specific aspect (element structure) of the optical resonator LK is not particularly limited.

[0015] The base semiconductor portion 8 and the compound semiconductor portion 9 are typically layered. Therefore, the base semiconductor portion 8 can also be called a base semiconductor layer 8, and the compound semiconductor portion 9 can also be called a compound semiconductor layer 9. In the following description, they will be referred to as the base semiconductor layer 8 and the compound semiconductor layer 9, but the base semiconductor layer 8 and the compound semiconductor layer 9 are not necessarily limited to being layered.

[0016] The base semiconductor layer 8 may include, for example, a nitride semiconductor. A nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include gallium nitride (GaN)-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor layer 8 may be a doped layer (e.g., an n-type layer containing donors) or a non-doped layer.

[0017] Furthermore, the compound semiconductor layer 9 may include, for example, the nitride semiconductor. Generally, it is difficult to reduce the defect density of nitride semiconductors. If the base semiconductor layer 8 has few surface defects, the number of dislocations (defects) inherited from the base semiconductor layer 8 to the compound semiconductor layer 9 will be reduced. This makes it possible to reduce the defect density of the compound semiconductor layer 9. The semiconductor laser device 20 in this embodiment may have, as the base semiconductor layer 8, a semiconductor layer formed by an ELO (Epitaxial Lateral Overgrowth) method (hereinafter, sometimes referred to as an ELO semiconductor layer). Note that the base semiconductor layer 8 is not limited to an ELO semiconductor layer as long as it can reduce the defect density of the optical resonator LK of the compound semiconductor layer 9.

[0018] The method for manufacturing the base semiconductor layer 8 is not particularly limited, and the base semiconductor layer 8 may be, for example, a general semiconductor layer including a nitride semiconductor. This "general semiconductor layer" refers to a semiconductor layer epitaxially grown in the vertical direction on a growth substrate. In this specification, for convenience of explanation, such a general semiconductor layer may be referred to as a "GE semiconductor layer." Since the GE semiconductor layer can be formed by a known method, explanation thereof will be omitted.

[0019] In this specification, a substrate used for growing various semiconductor layers of a semiconductor laser element may be referred to as a "growth substrate."

[0020] In this embodiment, a semiconductor laser device 20 will be described in which the base semiconductor layer 8 is an ELO semiconductor layer, as shown in Fig. 1. A method for manufacturing the base semiconductor layer 8 using the ELO method will be described later.

[0021] The base semiconductor layer 8, which is an ELO semiconductor layer, includes a first portion (first section) B1, and a second portion (second section) B2 and a third portion (third section) B3, each of which has a lower density (threading dislocation density) of threading dislocations KD extending in the thickness direction (Z direction) than the first portion B1. The second portion B2, the first portion B1, and the third portion B3 are arranged in this order in the X direction, and the first portion B1 is located between the second portion B2 and the third portion B3. The threading dislocations KD are dislocations (defects) that extend from the lower surface or the interior of the base semiconductor layer 8 to its surface or surface layer along the thickness direction of the base semiconductor layer 8. The threading dislocation densities of the second portion B2 and the third portion B3 are 1 / 5 or less (e.g., 5×10) of the threading dislocation density of the first portion B1. 6 / cm 2 (See below).

[0022] In the semiconductor laser element 20, a compound semiconductor layer 9 including multiple layers is stacked on a base semiconductor layer 8, and the stacking direction can be referred to as the "upper direction." Hereinafter, the positive Z-axis side of the XYZ coordinate system shown in FIG. 1 will be referred to as the "upper side," and the negative Z-axis side will be referred to as the "lower side." The surface of each component facing the positive Z-axis side will be referred to as the "upper surface," and the surface of each component facing the negative Z-axis side will be referred to as the "lower surface." For a substrate-like or substantially substrate-like object, such as the semiconductor laser element 20, viewing the object from a line of sight parallel to the normal direction to the upper surface can be referred to as a "planar view." While not described again below, the up-down direction will be similarly defined in other figures, and the expression "in a planar view" may also be used.

[0023] The compound semiconductor layer 9 includes, from the base semiconductor layer 8 upward, an n-type semiconductor portion (first-type semiconductor portion) 9N, an active portion 9K, and a p-type semiconductor portion (second-type semiconductor portion) 9P, in this order. The n-type semiconductor portion 9N, the active portion 9K, and the p-type semiconductor portion 9P are typically layered. Therefore, the n-type semiconductor portion 9N can also be referred to as an n-type semiconductor layer 9N. The active portion 9K can also be referred to as an active layer 9K. The p-type semiconductor portion 9P can also be referred to as a p-type semiconductor layer 9P. In the following description, the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P are referred to as the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P, but they are not necessarily limited to being layered.

[0024] The p-type semiconductor layer 9P may have a ridge portion RJ. The n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P may contain the nitride semiconductors described above. The various layers included in the compound semiconductor layer 9 will be described in detail later. The compound semiconductor layer 9 may have a high threading dislocation density above the first portion B1 due to the influence of the first portion B1 of the base semiconductor layer 8.

[0025] The compound semiconductor layer 9 has an optical resonator LK at a position overlapping with the second portion B2 in a plan view. The optical resonator LK includes a waveguide extending between an output surface F1 and an opposing surface F2 that constitute a pair of resonator faces. The distance between the output surface F1 and the opposing surface F2 can be set as the resonator length (resonant length) L1 of the optical resonator LK. The end face of the active layer 9K included in the output surface F1 and the end face of the active layer 9K included in the opposing surface F2 may each be coated with a reflective film (e.g., a dielectric film).

[0026] In the semiconductor laser element 20, at least one of the emission surface F1 and the opposing surface F2 may be the m-plane or the c-plane of the compound semiconductor layer 9 containing a nitride semiconductor. In FIG. 1 and other figures, the positive X-axis direction on the XYZ coordinate axes can be the [11-20] direction of the nitride semiconductor, the positive Y-axis direction can be the [-1100] direction of the nitride semiconductor, and the positive Z-axis direction (thickness direction) can be the

[0001] direction of the nitride semiconductor. The m-plane that at least one of the emission surface F1 and the opposing surface F2 may have is a plane parallel to the (1-100) plane (or the (-1100) plane) of the nitride semiconductor. The c-plane that at least one of the emission surface F1 and the opposing surface F2 may have is a plane parallel to the (0001) plane of the nitride semiconductor.

[0027] In the semiconductor laser device 20, at least one of the emission surface F1 and the opposing surface F2 may be included in a cleavage plane of the compound semiconductor layer 9. Each of the emission surface F1 and the opposing surface F2 may be included in a cleavage plane of the compound semiconductor layer 9. The semiconductor laser device 20 may also be configured so that the cavity length L1 is 200 μm or less.

[0028] The semiconductor laser element 20 is provided with a first electrode E1 and a second electrode E2 for supplying current to the optical resonator LK. The first electrode E1 can be arranged so as to overlap with the optical resonator LK in a plan view seen in the thickness direction of the base semiconductor layer 8. Note that "two members overlap" in a plan view means that at least a portion of one member overlaps the other member in a plan view seen in the thickness direction of each member (including a perspective plan view), and these members may or may not be in contact with each other.

[0029] The first electrode E1 may be located above the compound semiconductor layer 9, overlap at least a portion of the ridge portion RJ in a plan view, and have a shape extending along the longitudinal direction of the optical resonator LK. The first electrode E1 is electrically connected to the ridge portion RJ in the p-type semiconductor layer 9P and functions as an anode. The first electrode E1 and the ridge portion RJ may be in contact with each other or may be connected via another layer.

[0030] The second electrode E2 may be located below the compound semiconductor layer 9, and is disposed, for example, on the lower surface of the base semiconductor layer 8. The second electrode E2 may have a shape that overlaps at least a part of the first electrode E1 in a plan view. The second electrode E2 is electrically connected to the base semiconductor layer 8 and functions as a cathode. The second electrode E2 and the base semiconductor layer 8 may be in contact with each other or may be connected via another layer. The second electrode E2 may be in contact with the compound semiconductor portion 9 (for example, the n-type semiconductor layer 9N).

[0031] The insulating film DF is located above the compound semiconductor layer 9. The insulating film DF may cover the upper surface of the p-type semiconductor layer 9P except for the contact portion between the first electrode E1 and the ridge portion RJ.

[0032] [Manufacturing of semiconductor laser elements] Semiconductor lasers are sometimes manufactured from a stack of multiple semiconductor layers (called the conventional CT method). In the conventional CT method, multiple semiconductor lasers are formed on a growth substrate, and then the growth substrate is divided into multiple semiconductor lasers.

[0033] The present inventors have conducted extensive research into techniques different from the conventional technique CT and have arrived at the method for manufacturing a semiconductor laser device of the present disclosure. In general, the semiconductor laser device 20 in this embodiment is manufactured by a technique including a step of forming an optical resonator on a growth substrate (forming at least the resonator facets in the compound semiconductor layer 9).

[0034] Hereinafter, a method for manufacturing a semiconductor laser device (a semiconductor laser device in which the base semiconductor layer 8 is an ELO semiconductor layer) according to an embodiment of the present disclosure will be described. Fig. 3 is a flowchart showing an example of a method for manufacturing the semiconductor laser device according to this embodiment. Fig. 4 is a plan view and a cross-sectional view showing the configuration of a template substrate according to this embodiment.

[0035] (Step of preparing a template substrate) As shown in Fig. 3, in a method for manufacturing a semiconductor laser device according to an embodiment of the present disclosure, a template substrate is first prepared. As shown in Fig. 4, the template substrate 7 according to this embodiment includes a main substrate 1, a base portion 4 located above the main substrate 1, and a mask 6 located above the main substrate 1 and having an opening KS and a mask portion 5. Hereinafter, the main substrate 1 and base portion 4 may be collectively referred to as the base substrate UK. The base substrate UK and template substrate 7 are examples of the growth substrate described above.

[0036] The base portion 4 and the mask 6 are typically layered. Therefore, the base portion 4 can also be called the base layer 4, and the mask 6 can also be called the mask layer 6. In the following description, they will be referred to as the base layer 4 and the mask layer 6, but they are not necessarily limited to being layered. The mask 6 may be a mask pattern including mask portions 5 and openings KS. The openings KS are areas where the mask portions 5 are not present, and the openings KS do not necessarily have to be surrounded by the mask portions 5.

[0037] The main substrate 1 can be a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor. Examples of heterogeneous substrates include a silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate. The surface orientation of the main substrate 1 is, for example, the (111) surface of a Si substrate, the (0001) surface of an Al2O3 substrate, or the 6H—SiC (0001) surface of a SiC substrate. However, these are merely examples, and the main substrate 1 is not particularly limited as long as it is a substrate and has a surface orientation on which the base semiconductor layer 8 can be grown by the ELO method.

[0038] The template substrate 7 may have, as the underlayer 4, a buffer portion 2 and a seed portion 3 in this order from the main substrate 1 side. The buffer portion 2 and the seed portion 3 are typically layered. Therefore, the buffer portion 2 can also be called a buffer layer 2, and the seed portion 3 can also be called a seed layer 3. In the following description, they will be referred to as the buffer layer 2 and the seed layer 3, but the buffer layer 2 and the seed layer 3 are not necessarily limited to being layered.

[0039] The buffer layer 2 is a melting suppression layer that can reduce the possibility of the main substrate 1 and the seed layer 3 coming into direct contact and melting with each other. It also has the effect of increasing the crystallinity of the seed layer 3. The seed layer 3 is a layer that serves as the growth starting point for the base semiconductor layer 8 when the base semiconductor layer 8, described below, is formed. Note that, for example, if a main substrate 1 that does not melt with the seed layer 3, which is a GaN-based semiconductor, is used, a configuration without providing the buffer layer 2 is possible. On the other hand, if a Si substrate or the like is used for the main substrate 1, the GaN-based semiconductor and the Si substrate may melt with each other when they come into contact with each other. For this reason, a buffer layer 2 such as an AlN layer or a SiC layer is provided. This reduces the possibility of the GaN-based semiconductor and the Si substrate melting.

[0040] The mask layer 6 formed on the base substrate UK has a plurality of mask portions 5 and a plurality of openings KS. The mask portions 5 and the openings KS may each be elongated, with the width direction being the first direction (X direction) and the length direction being the second direction (Y direction). The openings KS may be tapered (with a width that narrows downward). The mask layer 6 may be made of an inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride film (SiON), or a titanium nitride (TiNx) film. The mask layer 6 may be made of a laminated film containing the above materials, such as a laminated film containing a silicon oxide film and a silicon nitride film.

[0041] The mask layer 6 may be formed, for example, as follows: a SiO2 film is formed over the entire surface of the base substrate UK using a sputtering method, and then wet-etched while being partially protected by a resist. Part of the SiO2 film is removed to form the mask portion 5 and the opening KS.

[0042] The openings KS of the mask layer 6 function as growth initiation holes that expose the seed layer 3 and initiate the growth of the base semiconductor layer 8, and the mask portions 5 of the mask layer 6 function as selective growth masks that cause the base semiconductor layer 8 to grow laterally. The width WK of the openings KS may be, for example, about 0.1 μm to 20 μm. The smaller the width of the openings KS, the fewer the number of threading dislocations that propagate from the openings KS to the base semiconductor layer 8. This may also facilitate peeling of the base semiconductor layer 8 in a later process. Furthermore, the areas of the second portion B2 and the third portion B3, which have fewer surface defects, can be increased. The width WM of the mask portions 5 may be, for example, about 25 μm to 200 μm.

[0043] In the method for manufacturing a semiconductor laser device according to this embodiment, for example, in the step of preparing the template substrate 7, the mask layer 6 may be formed so that the opening KS has a notched shape, in other words, so that the mask portion 5 has a shape that partially protrudes in the X direction. Hereinafter, the portion of the mask portion 5 that partially protrudes in the X direction is referred to as an initiation point inducing portion. By having the initiation point inducing portion in the mask layer 6, the base semiconductor layer 8 and the compound semiconductor layer 9 can be formed on the template substrate 7 so as to have initiation points that serve as initiation points for cleavage. This will be described in more detail in Example 1 below.

[0044] (Step of forming a semiconductor layer) 5 is a cross-sectional view illustrating a semiconductor substrate according to this embodiment. A method for manufacturing a semiconductor laser device according to one aspect of the present disclosure may include a step of forming a semiconductor layer (see FIG. 3). In the step of forming the semiconductor layer, for example, a base semiconductor layer 8 is formed on a template substrate 7 by an ELO method, and then a compound semiconductor layer 9 is formed above the base semiconductor layer 8.

[0045] In the ELO method, for example, a seed layer 3 containing a GaN-based semiconductor is used, and an inorganic compound film such as an SiO2 film is used as the mask layer 6, and the base semiconductor layer 8 can be grown laterally on the mask portion 5. The thickness direction (Z direction) of the base semiconductor layer 8 formed by the ELO method is oriented in the direction of the GaN-based crystal. <0001> The direction (c-axis direction) of the opening KS can be set to the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the opening KS can be set to the <1-100> direction (m-axis direction) of the GaN-based crystal.

[0046] As shown in FIG. 5 , the base semiconductor layer 8 includes a second portion B2 and a third portion B3 that overlap the mask portion 5 in a planar view and have relatively few threading dislocations KD, and a first portion B1 that overlaps the opening KS in a planar view and has more threading dislocations KD than the second portion B2 and the third portion B3. The compound semiconductor layer 9 includes many threading dislocations KD above the first portion B1 due to the influence of the threading dislocations KD present on the surface of the first portion B1. The optical resonator LK can be provided so as to overlap the second portion B2 in a planar view. This reduces the possibility of performance degradation of the optical resonator LK due to the influence of the threading dislocations KD. This is because the compound semiconductor layer 9 on the second portion B2 has a relatively small number of dislocations (defects) introduced due to surface defects in the second portion B2 during deposition of the compound semiconductor layer 9.

[0047] The threading dislocations KD are dislocations (defects) that extend from the lower surface or the interior of the base semiconductor layer 8 to the surface or surface layer of the base semiconductor layer 8 along the thickness direction of the base semiconductor layer 8. The threading dislocations KD can be observed by, for example, performing CL (Cathode Luminescence) measurement on the surface (parallel to the c-plane) of the base semiconductor layer 8.

[0048] Part 2 B2 or Part 3 B3 <0001> The non-threading dislocation density in a cross section parallel to the thickness direction can be greater than the threading dislocation density on the top surface. Non-threading dislocations are dislocations measured by CL in a cross section along a plane parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.

[0049] The semiconductor substrate 10 in this embodiment may include a template substrate 7 and a base semiconductor layer 8 formed on the template substrate 7. The semiconductor substrate 10 may also include the template substrate 7, the base semiconductor layer 8, and a compound semiconductor layer 9 formed above the base semiconductor layer 8.

[0050] In the semiconductor substrate 10 of this embodiment, a plurality of base semiconductor layers 8 are formed so as to have a gap Gp between different base semiconductor layers 8. The width WG of the gap Gp may be 4 μm or less, or may be 3 μm or less. Note that the semiconductor substrate 10 is not limited to having the gap Gp, and the base semiconductor layers 8 that have grown laterally from the seed layer 3 exposed in two adjacent openings KS may be in contact (meet) with each other on the mask portion 5.

[0051] When the base semiconductor layer 8 is formed using the ELO method, a template substrate 7 including a main substrate 1 and a mask layer 6 on the main substrate 1 may be used, and the template substrate 7 may have a growth-inhibiting region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5 and a seed region corresponding to the opening KS. For example, the growth-inhibiting region and the seed region may be formed on the main substrate 1, and the base semiconductor layer 8 may be formed on the growth-inhibiting region and the seed region using the ELO method.

[0052] (Process for isolating elements on a template substrate) Fig. 6A is a plan view for explaining an example of an element isolation process, and Fig. 6B is a cross-sectional view taken along line B-VI shown in Fig. 6A.

[0053] In the method for manufacturing a semiconductor laser device according to this embodiment, the base semiconductor layer 8 and the compound semiconductor layer 9 may be separated into multiple half-element portions (first element portions) sDS on the template substrate 7 so as to form cavity planes in at least the compound semiconductor layer 9. Here, the term "half-element portion sDS" refers to a portion (a laminate) including a base semiconductor layer 8 piece 8V and a compound semiconductor layer 9 piece 9V located above the base semiconductor layer 8 piece 8V, among multiple pieces aligned along the Y-axis direction formed by separating the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7. The half-element portion sDS can be considered a type of element portion, but since it does not have components such as electrodes for operating as an element, it can be considered a state in the middle of manufacturing the element portion as a product, i.e., a semi-finished product. Such half-element portions sDS also fall within the scope of the semiconductor device of the present disclosure. The boundary between adjacent half-element portions sDS is referred to as a separation portion PS, and the separation portion PS is indicated by a thick black line in FIGS. 6A and 6B .

[0054] In this specification, separating the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7 into a plurality of half-device portions sDS is sometimes referred to as "device isolation." "Device isolation" means the following (i) and (ii). (i) At the time when the base semiconductor layer 8 and the compound semiconductor layer 9 are separated on the template substrate 7, each of the plurality of half-element portions sDS has an optical resonator LK individually (in other words, each of the plurality of half-element portions sDS has a resonator surface formed at least in the compound semiconductor layer 9 individually). (ii) Until the half element portion sDS becomes the element portion (second element portion) DS in a later process, the piece 8V of the base semiconductor layer 8 and the piece 9V of the compound semiconductor layer 9 that the half element portion sDS has are not further divided.

[0055] 6B illustrates various forms of the division portion PS, but is not limited to these. As shown in FIG. 6B, in the process of isolating elements on the template substrate 7, the division portion PS may divide part or all of the mask portion 5 in the thickness direction of the semiconductor substrate 10, or the mask portion 5 may not be divided, or the mask portion 5 and the base layer 4 may be divided. In this process, the main substrate 1 may not be divided entirely in the thickness direction. Note that cracks may occur in part of the main substrate 1 in the thickness direction.

[0056] In the manufacturing method of the semiconductor laser device of this embodiment, the specific technique for the step of separating elements on the template substrate 7 is not particularly limited. For example, as described above, the base semiconductor layer 8 may be formed after the mask layer 6 is formed so that the mask portion 5 has an initiation point inducing portion. In this case, the base semiconductor layer 8 may have an initiation point portion that is a portion that is likely to become a cleavage initiation point. Similarly to the base semiconductor layer 8, the compound semiconductor layer 9 may also have a cleavage initiation point portion. Multiple half-element portions sDS may be formed by cleavage from the initiation point portion due to thermal stress or physical external force. Note that cleavage may be induced in the base semiconductor layer 8 before the compound semiconductor layer 9 is formed. In this case, the base semiconductor layer 8 may be cleaved, and then the compound semiconductor layer 9 may be formed on each of the multiple pieces of the base semiconductor layer 8. The compound semiconductor layer 9 can be separated into multiple half-element portions sDS by cleaving or dividing the compound semiconductor layer 9.

[0057] Furthermore, for example, the mask portion 5 may not have an initiation point inducing portion. In this case, the initiation points of cleavage may be formed in the base semiconductor layer 8 or the compound semiconductor layer 9 by processing such as scribing. Cleavage may be induced from the initiation points by applying an external force to at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. Furthermore, scribing the compound semiconductor layer 9 may cause natural cleavage due to internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0058] Furthermore, for example, the base semiconductor layer 8 or the compound semiconductor layer 9 can be etched to separate the device into a plurality of half-device portions sDS, and in this case, the separation portions PS may be grooves (trench) formed by etching.

[0059] As described above, the method for manufacturing a semiconductor laser device according to this embodiment may include the steps of: (i) preparing the main substrate 1, the base semiconductor portion 8 formed above the main substrate 1, and the compound semiconductor portion 9 formed on the base semiconductor portion 8; and (ii) separating the base semiconductor portion 8 and the compound semiconductor portion 9 so as to form cavity facets in at least the compound semiconductor portion 9, and separating the base semiconductor portion 8 and the compound semiconductor portion 9 into a plurality of device portions (e.g., half-device portions sDS). In the step of separating into a plurality of device portions, the base semiconductor layer 8 and the compound semiconductor portion 9 may be separated into a plurality of half-device portions sDS each having a cavity facet (e.g., an emission facet F1 and an opposing facet F2) on a growth substrate (e.g., on a template substrate 7). By separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of device portions (e.g., half-device portions sDS), an optical resonator LK including a cavity facet (e.g., an emission facet F1 and an opposing facet F2) may be formed.

[0060] Furthermore, the method for manufacturing a semiconductor laser device according to this embodiment includes the steps of (i) preparing a main substrate 1, a base semiconductor portion 8 formed above the main substrate 1, and a compound semiconductor portion 9 formed on the base semiconductor portion 8, and (ii) dividing the base semiconductor portion 8 and the compound semiconductor portion 9 to form a plurality of optical resonators LK, each of which includes a resonator surface (e.g., an emission surface F1 and an opposing surface F2). For example, the base semiconductor layer 8 and the compound semiconductor layer 9 may be divided on a growth substrate (e.g., on a template substrate 7) to form a plurality of optical resonators LK, each of which includes a resonator surface. In the step of forming the plurality of optical resonators LK, the main substrate 1 may not be divided, or the main substrate 1 may be divided into a number of pieces fewer than the number of optical resonators LK. For example, the main substrate 1 may be divided into a plurality of pieces formed by dividing the main substrate 1, such that one of the pieces has a plurality of semi-element portions sDS.

[0061] According to the method for manufacturing a semiconductor laser device in this embodiment, it is easy to form the resonator facets even when the semiconductor laser device 20 is miniaturized. Therefore, it is easy to form the optical resonator LK. Then, by peeling the formed device portion DS from the growth substrate as described below, the device portion DS can be mounted on a support substrate to manufacture the semiconductor laser device 20. This improves handling. Furthermore, a substrate suitable for mounting can be used as the support substrate.

[0062] (Process for forming element structure) In the method for manufacturing a semiconductor laser device according to this embodiment, a step of forming an element structure on the half element portion sDS on the template substrate 7 is performed. This forms the element portion DS. At this stage, the base semiconductor layer 8 included in the element portion DS is van der Waals-bonded to the mask portion 5, and the element portion DS may be part of the semiconductor substrate 10.

[0063] In the process of forming the device structure, for example, a ridge portion RJ is formed in the p-type semiconductor layer 9P of the compound semiconductor layer 9, an insulating film DF is formed, and then a first electrode E1 (anode) is formed at a position in contact with the ridge portion RJ. Then, for example, in the case where the semiconductor laser device 20 has a single-sided two-electrode structure, a part of the upper surface of the base semiconductor layer 8 may be exposed by etching or the like, and then a second electrode E2 may be formed on the upper surface of the base semiconductor layer 8. This can form the device portion DS. By providing the ridge portion RJ and the insulating film DF in the device portion DS, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, allowing efficient light emission within the resonator LK. Furthermore, the ridge portion RJ may overlap the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in a planar view, but may not overlap the first portion B1. The second electrode E2 may overlap the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in a planar view. As a result, a current path from the first electrode E1 through the compound semiconductor portion 9 and the base semiconductor portion 8 to the second electrode E2 is formed in a portion overlapping with the second portion B2 in a planar view (a portion with few threading dislocations), thereby improving the light emission efficiency in the active layer 9K. This is because threading dislocations act as non-radiative recombination centers. Furthermore, the second electrode E2 may overlap with the second portion B2 and the third portion B3 (low-dislocation portions) of the base semiconductor portion 8 in a planar view, in which case the efficiency of electron injection from the second electrode E2 to the base semiconductor portion 8 is improved.

[0064] If the semiconductor laser element 20 has a double-sided electrode structure, the second electrode E2 may be formed in a later process. In this specification, an element having an element structure without the second electrode E2, obtained by the process of forming the element structure, is also referred to as an element portion DS.

[0065] (Process for mounting the element part) FIG. 7 is a flowchart showing an example of the mounting stage of the method for manufacturing the semiconductor laser device according to this embodiment.

[0066] As shown in FIG. 7, first, a step of separating the element portion DS from the template substrate 7 is performed. For example, after bonding the first electrode E1 to a pad of the support substrate, the element portion DS can be separated from the template substrate 7 using the support substrate. Then, a step of coating the end face of the optical resonator LK of the element portion DS may be performed to form the semiconductor laser element 20. The support substrate on which the element portion DS is mounted may be divided to form the semiconductor laser element 20. The support substrate may function as a submount, which allows a chip on which the semiconductor laser element 20 is mounted to be formed on the divided support substrate. A specific example of the support substrate will be described later.

[0067] According to the manufacturing method of the semiconductor laser device 20 in this embodiment, the template substrate 7 or the base substrate UK can also be reused. Moreover, the semiconductor laser device 20 can be formed by transferring the device portion DS from a substrate that is not suitable for mounting to a substrate (support substrate) that is suitable for mounting.

[0068] [Manufacturing equipment] 8 is a block diagram showing an example of a manufacturing apparatus 70. As shown in Fig. 8, the manufacturing apparatus 70 includes a semiconductor layer forming unit 72 that forms a base semiconductor layer 8 and a compound semiconductor layer 9 on a template substrate 7, a processing unit 73 that forms an element structure, and a control unit 74 that controls the semiconductor layer forming unit 72 and the processing unit 73.

[0069] The semiconductor layer forming unit 72 may include, for example, an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus, and forms a base semiconductor layer 8 using an ELO method, and forms a compound semiconductor layer 9 on the base semiconductor layer 8. When the processing object is removed from a processing apparatus (film forming apparatus) such as an MOCVD apparatus, an element isolation process may be performed. The semiconductor layer forming unit 72 may be controlled so that after forming the base semiconductor layer 8, the processing object is temporarily removed from the processing apparatus, and then the processing object is loaded into the processing apparatus again to form the compound semiconductor layer 9 on the base semiconductor layer 8. The semiconductor layer forming unit 72 may have a function of manufacturing the template substrate 7.

[0070] The processing unit 73 may perform an element separation process to form half-element portions sDS. The processing unit 73 performs various processes on the half-element portions sDS located on the template substrate 7 to form element portions DS. The processing unit 73 may perform a process of separating the element portions DS from the template substrate 7 using a support substrate, or may perform a process of coating the end faces of the optical resonators LK.

[0071] The control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor layer forming unit 72 and the processing unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above program and a recording medium on which the above program is stored are also included in this embodiment.

[0072] Other Embodiments (a) In the manufacturing method of the semiconductor laser device 20 according to another embodiment of the present disclosure, a GaN substrate may be used as the growth substrate instead of the base substrate UK, and in this case, the main substrate 1 may be the GaN substrate. That is, the main substrate 1 may be the growth substrate. A semiconductor substrate in which a semiconductor layer containing a nitride semiconductor (the above-mentioned GE semiconductor layer) is formed on a GaN substrate without forming a mask layer 6 may also be used.

[0073] For example, by removing a part of the GE semiconductor layer in the semiconductor substrate by etching, it is possible to form a plurality of island-shaped semiconductor layers having a shape as shown in Fig. 5. Then, after forming a compound semiconductor layer on this semiconductor layer, an element isolation step is performed to form a plurality of half-element portions sDS.

[0074] (b) In other embodiments of the present disclosure, the method for manufacturing the semiconductor laser device 20 is not limited to using a template substrate 7 in which the seed layer 3 overlaps the entire mask portion 5. Since the seed layer 3 only needs to be exposed from the opening KS, a template substrate 7 in which the seed layer 3 is locally formed so as not to overlap part or all of the mask portion 5 may be used. For example, the buffer layer 2 may be located on the main substrate 1, and the seed layer 3 may be locally provided on the buffer layer 2 so as to overlap the opening KS of the mask layer 6.

[0075] (c) In a manufacturing method of a semiconductor laser device 20 according to another embodiment of the present disclosure, a base substrate UK having no buffer layer 2 between the main substrate 1 and the seed layer 3 may be used as the growth substrate. That is, a template substrate 7 including a base substrate UK having the main substrate 1 and the seed layer 3, and a mask layer 6 formed on the base substrate UK may be used. The template substrate 7 may be configured without the buffer layer 2 when the main substrate 1 is made of a material that does not melt with the seed layer 3, or when the seed layer 3 is made of a material that is less reactive with the main substrate 1. This omits the process of forming the buffer layer 2, thereby reducing the cost of the process.

[0076] For example, the seed layer 3 may be formed of a material that has low reactivity with the main substrate 1 and that can serve as a growth starting point for the base semiconductor layer 8. The seed layer 3 may be, for example, an AlN layer or a SiC layer, or may be a layer containing at least one of AlN and SiC.

[0077] (d) In another embodiment of the present disclosure, the semiconductor laser device 20 may have a configuration in which the base semiconductor layer 8 does not have the first portion B1, i.e., has one second portion B2. For example, the first portion B1 may be removed by etching or the like before separating the device portion DS from the template substrate 7.

[0078] Example 1 The semiconductor device manufacturing method and the like of the present disclosure will be described in further detail below with reference to examples, but the present disclosure is not limited to the configurations described below and various modifications are possible within the scope of the claims. Furthermore, the configurations of the multiple examples of the present disclosure will be described below with the same reference numerals assigned to the same or equivalent parts in the drawings, but unless otherwise specified, forms obtained by appropriately combining the technical means disclosed in the above-mentioned embodiment and multiple different examples described below are also included in the technical scope of the present disclosure.

[0079] 9 is a flowchart showing an example of a method for manufacturing a semiconductor laser device 20 in Example 1. In Example 1, a mask layer 6 of a template substrate 7 includes a mask portion 5 having an origin induction portion. Then, an ELO semiconductor layer having an origin induction portion is formed on the template substrate 7. As shown in FIG. 9, in Example 1, first, a template substrate 7 including an origin induction portion in a mask layer 6 is prepared, and then semiconductor layers (a base semiconductor layer 8 and a compound semiconductor layer 9) including the origin induction portion are formed on the template substrate 7.

[0080] (Step of preparing a template substrate) FIG. 10 is a cross-sectional view showing the configuration of the template substrate 7 in Example 1. FIG. 11A is an enlarged view of a main portion of FIG. 10. A heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used as the main substrate 1 in the template substrate 7. By using a Si substrate as the main substrate 1, the manufacturing cost of the template substrate 7 can be reduced. As a result, the manufacturing cost of the semiconductor laser device 20 can be reduced. The main substrate 1 may be an Al2O3 substrate or a SiC substrate, which can reduce reactivity with Ga. The material and plane orientation of the main substrate 1 are not particularly limited as long as the material and plane orientation allow for growth of an ELO semiconductor layer.

[0081] In the first embodiment, the base substrate UK may be manufactured by forming the base layer 4 (see FIG. 4) on the main substrate 1, or a pre-prepared base substrate UK may be used. When a pre-prepared base substrate UK is used, it is easy to stably grow the base semiconductor layer 8 and the like. This is because when a process for forming the base layer 4 is performed, the process may have an effect on the base semiconductor layer 8 and the like.

[0082] The template substrate 7 may include, for example, a seed layer 3 as the underlayer 4. The seed layer 3 is a layer that serves as a growth starting point for the base semiconductor layer 8 when the base semiconductor layer 8 is formed. The seed layer 3 may include a GaN-based semiconductor, aluminum nitride (AlN), SiC, graphene, or the like. The silicon carbide used for the seed layer 3 may be hexagonal 6H-SiC or 4H-SiC. The seed layer 3 may be, for example, an AlGaN layer, or a graded layer in which the Al composition gradually increases to approach that of GaN. The seed layer 3 may include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the top layer of the graded layer that is the seed layer 3 may be a GaN layer. The seed layer 3 may be made of any material and have any plane orientation that allows the growth of the base semiconductor layer 8 containing a nitride semiconductor.

[0083] The template substrate 7 may include, as the underlayer 4, a buffer layer 2 (see FIG. 4) located between the main substrate 1 and the seed layer 3. For example, when a silicon substrate is used as the main substrate 1 and a GaN-based semiconductor is used as the seed layer 3, providing the buffer layer 2 between the silicon substrate and the GaN-based semiconductor can reduce mutual melting of the silicon substrate and the GaN-based semiconductor. The buffer layer 2 may also have at least one of the effects of increasing the crystallinity of the seed layer 3 and alleviating internal stress in the seed layer 3.

[0084] The buffer layer 2 may typically be an AlN layer or a SiC layer. The SiC used for the buffer layer 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (3C-SiC). The buffer layer 2 may be a multilayer film including at least one of an AlN film and a SiC film. The buffer layer 2 may include a strain relaxation layer. Examples of the strain relaxation layer include an AlGaN superlattice structure and an AlGaN graded structure in which the Al composition varies stepwise. The strain relaxation layer can relieve stress in the longitudinal direction of the base semiconductor layer 8. An AlN layer, which is an example of the buffer layer 2, can be formed to a thickness of approximately 10 nm to 5 μm using, for example, an MOCVD apparatus.

[0085] The base layer 4 can be formed by stacking various layers on the main substrate 1 using an MOCVD apparatus or a sputtering apparatus. For example, at least one of a buffer layer 2 (e.g., aluminum nitride) and a seed layer 3 (e.g., a GaN-based semiconductor) can be deposited on the main substrate 1 using a sputtering apparatus (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). This allows the base substrate UK to be manufactured.

[0086] A mask layer 6 is formed on the base substrate UK to manufacture a template substrate 7. The mask layer 6 may be, for example, a single layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a laminated film including at least two of these.

[0087] In Example 1, a mask layer 6 is formed on a base substrate UK so that a portion of the mask portion 5 has an initiation site inducing portion 5Y. The initiation site inducing portion 5Y in Example 1 has a triangular shape in plan view. In plan view, the initiation site inducing portion 5Y has a vertex 5P and two sides 5A and 5B that intersect at the vertex 5P. In plan view, an imaginary line segment connecting the end of side 5A and the end of side 5B on the opposite side from the vertex 5P is referred to as side 5C. Sides 5A, 5B, and 5C form an imaginary triangle. Side 5C can also be considered the base of the imaginary triangle. The angle between side 5A and side 5B is referred to as θ1, and the angle between side 5B and side 5C is referred to as θ2. The distance from side 5C to the vertex 5P is referred to as the protrusion length H1 of the initiation site inducing portion 5Y.

[0088] The initiator inducing portion 5Y may have the same thickness as the other portions of the mask portion 5. The angle θ1 may be 30° or approximately 30°, for example, approximately 20° to 40°. In this specification, "approximately" means within a variation range of ±10%. The angles θ1 and θ2 may be the same or approximately the same. The side 5A may have a length of, for example, approximately 0.1 μm to 20 μm. The sides 5A and 5B may have the same length or approximately the same lengths. In this specification, "approximately the same" means within a 10% difference range based on the larger numerical value. The initiator inducing portion 5Y may have a protrusion length H1 of, for example, approximately 0.1 μm to 10 μm.

[0089] The specific shape of the initiation inducing portion 5Y is not particularly limited as long as it can form a portion that serves as a cleavage initiation point in the base semiconductor layer 8, as described later. The initiation inducing portion 5Y is not limited to a shape in which the tip of the apex 5P is pointed in a plan view, and the apex 5P may have a rounded shape. The angle θ1 and the angle θ2 of the initiation inducing portion 5Y may be different from each other. The initiation inducing portion 5Y may have a quadrangular shape in a plan view or may have other shapes. The portion of the mask portion 5 other than the initiation inducing portion 5Y is referred to as a main portion, and the initiation inducing portion 5Y and the main portion may have different thicknesses. The initiation inducing portion 5Y and the main portion may be integrally formed, or the initiation inducing portion 5Y may be formed after the main portion is formed.

[0090] The opening KS has an elongated shape except for the portion where the initiation site inducing portion 5Y is provided, and the width of the portion where the initiation site inducing portion 5Y is provided is relatively narrow. In Example 1, by providing the initiation site inducing portion 5Y, the mask layer 6 is formed so that the opening KS has a notch. A plurality of openings KS may be periodically arranged with a first period in the X direction. The width of the opening KS may be approximately 0.1 μm to 20 μm. The smaller the width of the opening KS, the fewer the number of threading dislocations propagating from the opening KS to the base semiconductor layer 8. Furthermore, peeling of the base semiconductor layer 8 in a subsequent process becomes easier. Furthermore, the area of ​​the second portion B2 with fewer surface defects can be increased.

[0091] In Example 1, the mask layer 6 having the mask portions 5 may be formed, for example, as follows. First, a silicon oxide film having a thickness of about 100 nm to 4 μm (preferably about 150 nm to 2 μm) is formed on the entire surface of the underlayer 4 by sputtering. Then, a resist is applied to the entire surface of the silicon oxide film. Thereafter, the resist is patterned by photolithography to form a resist having a plurality of stripe-shaped openings. At this time, in Example 1, the resist is not removed from positions corresponding to the origin induction portions 5Y. Thereafter, a portion of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF), thereby forming the mask portions 5 including the plurality of openings KS and the origin induction portions 5Y. Next, the resist is removed by organic cleaning to form the mask layer 6.

[0092] In the mask layer 6, for example, in one mask portion 5, the protruding directions of the multiple origin-inducing portions 5Y, in other words, the directions of the multiple notches of the opening KS, may be aligned in one direction. As a result, as will be described later, in the semiconductor laser device 20 manufactured using the template substrate 7, a pair of cavity facets (emission facet F1 and opposing facet F2) can be formed in, for example, the second portion B2 (see FIG. 1, etc.), which is located farther from the origin-inducing portion 5Y out of the second portion B2 and the third portion B3. The second portion B2 is less likely to be affected by the origin-inducing portion 5Y. As a result, the possibility of a deterioration in the quality of the pair of cavity facets can be reduced. However, it goes without saying that the mask layer 6 can be formed by appropriately changing the orientation of the origin-inducing portion 5Y.

[0093] (Example of the shape of the initiation induction part) Another example of the specific shape of the initiation inducing part 5Y will be described below.

[0094] 11B is a plan view showing an example of the initiation inducing part 5Y. As shown in FIG. 11B, the initiation inducing part 5Y may have a shape in which the vertex 5P does not extend beyond the center of the opening KS. That is, the initiation inducing part 5Y may have a protrusion length H1 of, for example, 0.1 μm or more and less than (WK / 2) (WK: width of the opening KS). The initiation inducing part 5Y may have, for example, an isosceles triangle shape or an equilateral triangle shape in a plan view.

[0095] 11C is a plan view showing another example of the trigger-inducing portion 5Y. As shown in FIG. 11C, the trigger-inducing portion 5Y may have a shape in which the vertex 5P extends beyond the center of the opening KS. That is, the trigger-inducing portion 5Y may have a protrusion length H1 that is, for example, equal to or greater than (WK / 2) and less than WK. Furthermore, the angle θ1 and the angle θ2 may exceed 40°.

[0096] 11D is a plan view showing another example of the trigger inducing portion 5Y. As shown in FIG. 11D, the trigger inducing portion 5Y may have a virtual pentagonal shape in plan view, which is a combination of a virtual triangle 5Y1 and a virtual rectangle 5Y2. The virtual rectangle 5Y2 may be a square or a rectangle. The virtual rectangle 5Y2 may have a virtual side 5D, the length of which is the width direction of the opening KS, of about 0.1 μm to 10 μm. The side 5D may be a line segment extending parallel or approximately parallel to the width direction of the opening KS. The virtual rectangle 5Y2 may be a trapezoid, for example. The vertex 5P of the virtual triangle 5Y1 may or may not be located beyond the center of the opening KS.

[0097] 11E is a plan view showing another example of the initiator inducing portion 5Y. As shown in FIG. 11E, the initiator inducing portion 5Y may have a quadrangular shape in a plan view. In this case, the initiator inducing portion 5Y does not have a vertex 5P, and the distance between the side 5E, whose length direction is the longitudinal direction of the opening KS, and the main portion of the mask portion 5 is defined as the protrusion length H1. The side 5E may have a length of, for example, about 0.1 μm to 10 μm. The initiator inducing portion 5Y may have a trapezoidal shape or a parallelogram shape in a plan view. The side 5E may or may not be located beyond the center of the opening KS. That is, the side 5E may have a length of, for example, about 0.1 μm to 20 μm.

[0098] (Step of forming a semiconductor layer) Next, a base semiconductor layer 8 is formed on the template substrate 7. In Example 1, for example, the template substrate 7 is loaded into an MOCVD apparatus, and a GaN-based semiconductor layer is formed by the ELO method. FIG. 12 is a cross-sectional view showing an example of lateral growth of the base semiconductor layer 8 in Example 1. The base semiconductor layer 8 in Example 1 is a nitride semiconductor (e.g., a GaN-based semiconductor layer) and is obtained by c-plane deposition on the template substrate 7. The base semiconductor layer 8 may be an n-type semiconductor layer having donors. In FIG. 12 and other figures, the [-1100] direction of the GaN-based semiconductor is the positive Y-axis direction, the [11-20] direction of the GaN-based semiconductor is the positive X-axis direction, and the

[0001] direction of the GaN-based semiconductor is the positive Z-axis direction (thickness direction).

[0099] 12, in the ELO method, an initial growth layer SL is first formed on a seed layer 3, and then a base semiconductor layer 8 can be grown laterally from the initial growth layer SL. The initial growth layer SL is the starting point of the lateral growth of the base semiconductor layer 8 and is part of the first portion B1. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the base semiconductor layer 8 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0100] Here, the ELO deposition conditions may be controlled so that deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rises above the upper surface of the mask portion 5 (the stage where it contacts the upper end of the side surface of the mask portion 5) or just after it rises above the upper surface of the mask portion 5 (i.e., the ELO deposition conditions are switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions at this timing). In this way, lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that material is less likely to be consumed in the thickness direction growth of the base semiconductor layer 8, and the base semiconductor layer 8 can be grown laterally at a high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0101] In Example 1, the base semiconductor layer 8 was an n-type GaN layer, and Si-doped GaN was grown on the template substrate 7 by ELO using an MOCVD apparatus. Examples of ELO conditions include a substrate temperature of 1120°C, growth pressure of 50 kPa, TMG (trimethylgallium) at 22 sccm, NH3 at 15 slm, and V / III = 6000 (the ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). An initial growth layer SL was selectively grown on the seed layer 3 (the GaN layer that is the top layer of the seed layer 3) exposed in the opening KS, and subsequently grew laterally on the mask portion 5. The lateral growth of the base semiconductor layer 8 growing laterally on both sides of the mask portion 5 was stopped before it met.

[0102] In the first embodiment, the initiation site inducing portion 5Y is included in the mask layer 6, which may cause disturbance in the lateral growth of the base semiconductor layer 8 in the portion where the initiation site inducing portion 5Y exists. Fig. 13 is a plan view for explaining the base semiconductor layer 8 in the first embodiment.

[0103] 13, in Example 1, the base semiconductor layer 8 has an initiation portion 8K that serves as a cleavage initiation point, and the initiation portion 8K is naturally formed in the base semiconductor layer 8 by growing the base semiconductor layer 8 from an opening KS having a notch shape. Note that the relationship between the shape of the initiation inducing portion 5Y and the shape of the initiation portion 8K can vary depending on the growth conditions of the base semiconductor layer 8. The initiation portion 8K may be smaller or larger than the shape of the initiation inducing portion 5Y, or may be approximately the same as the shape of the initiation inducing portion 5Y. An example of the initiation portion 8K will be described below.

[0104] For example, the base semiconductor layer 8 may have an oblique meeting portion 8N that extends from the position of the initiation inducing portion 5Y of the mask layer 6 to the position of the initiation portion 8K of the base semiconductor layer 8 in a plan view. The oblique meeting portion 8N is a portion where semiconductor layers grown in a direction oblique to the X direction (a-axis direction) meet. The oblique meeting portion 8N may be, for example, a grain boundary, or may be a portion where the crystal structure is more disturbed (i.e., has more lattice defects) than other portions of the base semiconductor layer 8. In FIG. 13 , the oblique meeting portion 8N is illustrated by a solid line. When the base semiconductor layer 8 has the oblique meeting portion 8N, the oblique meeting portion 8N can be observed by, for example, performing CL measurement.

[0105] 14 is an enlarged view for explaining the growth of the base semiconductor layer 8 around the initiation site induction portion 5Y in Example 1. As shown in FIG. 14, first, an initial growth layer SL is formed from the opening KS. At this time, in a portion of the opening KS other than the periphery of the initiation site induction portion 5Y, the initial growth layer SL is formed so as to climb up onto the upper surface of the mask portion 5 due to lateral growth of the GaN-based semiconductor in the <11-20> direction (i.e., the a-axis direction). In contrast, in the periphery of the initiation site induction portion 5Y in the opening KS, the presence of the initiation site induction portion 5Y may cause a notch in part of the initial growth layer SL that has grown from the opening KS so as to climb up onto the upper surface of the mask portion 5. For example, in a plan view, the direction orthogonal to the side 5A of the initiation site induction portion 5Y may be the m-plane direction of the GaN-based semiconductor (e.g., the [10-10] direction), and the direction orthogonal to the side 5B may be another m-plane direction of the GaN-based semiconductor (e.g., the [01-10] direction). The growth rate in the m-plane direction of a GaN-based semiconductor is lower than the growth rate in the a-plane direction. The base semiconductor layer 8 can grow so as to maintain the notch formed in the initially grown layer SL.

[0106] The oblique meeting portion 8N can be formed, for example, by the mutual meeting of semiconductor layers grown in the [10-10] direction and the [01-10] direction. The oblique meeting portion 8N may be formed near the mask portion 5 and then propagate to the surface of the base semiconductor layer 8 after film formation, thereby also being present on the surface of the base semiconductor layer 8. The starting point portion 8K may have a tapered shape, such as a triangular shape, in a planar view. This facilitates stress concentration at one point during cleavage. As a result, a good cleavage plane can be easily obtained. The starting point portion 8K may also have an end face that is an m-plane of a GaN-based semiconductor. The end face of the starting point portion 8K does not have to be an m-plane of a GaN-based semiconductor.

[0107] If the interval between the multiple starting point portions 8K in the base semiconductor layer 8 (the distance between the tips of two starting point portions 8K) is L2 (see FIG. 17), this interval L2 corresponds to the cavity length L1 (see FIG. 2). The length of the interval L2 may be approximately 20 μm to 200 μm. If the interval L2 is short, more locations will be freed from internal stress by cleavage. This reduces the possibility of element separation occurring at unintended locations during cleavage during cooling, which will be described later. The interval L2 may be 300 μm or more. If the interval L2 is long, the possibility of there being starting point portions 8K that do not cleave during cleavage during cooling, which will be described later, can be reduced, thereby improving the yield of semiconductor device manufacturing.

[0108] In forming the base semiconductor layer 8, it is preferable to reduce the mutual reaction between the base semiconductor layer 8 and the mask portion 5 and maintain a state in which the base semiconductor layer 8 and the mask portion 5 are in contact with each other through van der Waals forces. In other words, the base semiconductor layer 8 and the mask portion 5 may be in contact with each other mainly through van der Waals forces.

[0109] (Process for forming a compound semiconductor layer) In Example 1, a semiconductor substrate 10 having a base semiconductor layer 8 formed on a template substrate 7 is manufactured using an MOCVD apparatus, and then, without removing the semiconductor substrate 10 from the MOCVD apparatus, a compound semiconductor layer 9 is formed on the base semiconductor layer 8 using the MOCVD apparatus. Furthermore, without removing the semiconductor substrate 10 from the MOCVD apparatus during the formation of the layered structure that is the compound semiconductor layer 9, the film formation process for the layered structure is performed continuously using the MOCVD apparatus. The compound semiconductor layer 9 includes a nitride semiconductor layer (for example, a GaN-based semiconductor layer).

[0110] FIG. 15 is a cross-sectional view showing the configuration of the compound semiconductor layer 9 in Example 1. As shown in FIG. 15, the compound semiconductor layer 9 is formed by forming an n-type semiconductor layer 9N having a donor, an active layer 9K, and a p-type semiconductor layer 9P having an acceptor, in this order. The n-type semiconductor layer 9N is formed by forming a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C, in this order. The p-type semiconductor layer 9P is formed by forming a second optical guide layer 9D, an electron blocking layer 9E, a second cladding layer 9F, and a second contact layer 9G, in this order. Note that in the compound semiconductor section 9, the second optical guide layer 9D and the electron blocking layer 9E may be arranged interchangeably in the p-type semiconductor layer 9P. For example, the p-type semiconductor layer 9P may be formed by forming an electron blocking layer 9E, the second optical guide layer 9D, the second cladding layer 9F, and a second contact layer 9G, in this order.

[0111] The first contact layer 9A may be, for example, an n-type GaN layer, and the first cladding layer 9B may be, for example, an n-type AlGaN layer. The first cladding layer 9B may be an n-type GaN-based semiconductor layer, an n-type AlGaN-based semiconductor layer, or an n-type AlInGaN-based semiconductor layer, and may have a thickness of, for example, approximately 0.8 μm to 2 μm. When Al-free GaN or the like is used for the first cladding layer 9B, deposition of GaN-based semiconductor on the surface of the mask portion 5 can be suppressed, improving the yield during peeling (the step of separating the element portion DS from the template substrate 7, which will be described later). The first optical guide layer 9C may be, for example, an n-type GaN layer, and may be an InGaN layer with an In composition of approximately 3 to 10%. The first optical guide layer 9C may have a thickness of approximately 50 nm.

[0112] The active layer 9K may have an MQW (Multi-Quantum Well) structure including, for example, an InGaN layer. The active layer 9K may typically have a structure with 5 to 6 periods. The In composition varies depending on the target emission wavelength. For example, for blue light emission (wavelength around 450 nm), the In concentration may be about 15 to 20%. For green light emission (wavelength around 530 nm), the In concentration may be about 30%.

[0113] The second optical guiding layer 9D may be, for example, a p-type AlGaN layer. The second optical guiding layer 9D may have an Al composition of, for example, about 15 to 25% and a thickness of, for example, about 5 to 25 nm. The electron blocking layer 9E may be, for example, a p-type GaN layer, which may be an InGaN layer with an In composition of, for example, about 3 to 10%. The electron blocking layer 9E may have a thickness of, for example, about 50 nm. The second cladding layer 9F may be, for example, a p-type AlGaN layer. The second cladding layer 9F may be a p-type GaN-based semiconductor layer, an AlGaN-based semiconductor layer, or an AlInGaN-based semiconductor layer and may have a thickness of, for example, about 0.1 μm to 1 μm. The second contact layer 9G may be, for example, a p-type GaN layer. The second contact layer 9G may have a thickness of, for example, about 0.1 μm to 0.3 μm. Although not shown, a highly doped layer with a thickness of about 10 nm and containing Mg as a dopant may be formed on the surface of the second contact layer 9G.

[0114] The thickness of each layer in the compound semiconductor layer 9 can be expressed as base semiconductor layer 8>first cladding layer 9B>first optical guide layer 9C>active layer 9K, and base semiconductor layer 8>second cladding layer 9F>second optical guide layer 9D>active layer 9K. Furthermore, the refractive index of each layer in the compound semiconductor layer 9 (refractive index of light generated in the active layer 9K) can be expressed as first cladding layer 9B<first optical guide layer 9C<active layer 9K, and insulating film DF<second cladding layer 9F<second optical guide layer 9D<active layer 9K.

[0115] FIG. 16 is a plan view illustrating the compound semiconductor layer 9 in Example 1. As shown in FIG. 16, the compound semiconductor layer 9 is formed in a shape having an origin portion 9T corresponding to the origin portion 8K of the base semiconductor layer 8. This is because it is difficult to deposit the compound semiconductor layer 9 at the position of the origin portion 8K of the base semiconductor layer 8. The origin portion 9T may have an end face that is an m-plane of a GaN-based semiconductor by being formed in a shape that corresponds to the origin portion 8K. Note that the end face of the origin portion 9T does not have to be an m-plane of a GaN-based semiconductor.

[0116] The steps described above can be organized as follows. That is, in Example 1, first, a step of preparing a main substrate 1, a base semiconductor layer 8 formed above the main substrate 1, and a compound semiconductor layer 9 formed on the base semiconductor layer 8 is performed. A notch is formed in the opening KS of the mask layer 6. As a result, an origin portion 8K is naturally formed in the base semiconductor layer 8. Then, a compound semiconductor layer 9 is formed on the base semiconductor layer 8 having the origin portion 8K. As a result, an origin portion 9T is naturally formed in the compound semiconductor layer 9.

[0117] (Process for isolating elements on a template substrate) Next, the semiconductor substrate 10 on which the compound semiconductor layer 9 has been formed is cooled, thereby isolating the device into a plurality of half-device portions sDS on the template substrate 7. Fig. 17 is a plan view for explaining an example of the device isolation process in Example 1.

[0118] The compound semiconductor layer 9 may be formed under high temperature conditions using an MOCVD apparatus, in which case a cooling step is performed within the MOCVD apparatus.

[0119] Here, in Example 1, the thermal expansion coefficients of the base semiconductor layer 8 and the compound semiconductor layer 9 may be different from that of the main substrate 1, and in this case, internal stress is generated in the base semiconductor layer 8 and the compound semiconductor layer 9 due to the difference in thermal expansion coefficients between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1.

[0120] In addition, in the first embodiment, the main substrate 1 and the base semiconductor layer 8 may have different lattice constants. In this case, the difference in lattice constants between the main substrate 1 and the base semiconductor layer 8 causes internal stress in the base semiconductor layer 8. The internal stress in the base semiconductor layer 8 may also cause internal stress in the compound semiconductor layer 9. By using a heterogeneous substrate (e.g., a Si substrate) different from a GaN-based semiconductor for the main substrate 1, it is possible to easily generate internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0121] 17 , when the semiconductor substrate 10 is cooled, split portions PS may be generated by cleavage starting from the notched starting point portions 8K and 9T due to internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9. That is, in Example 1, cleavage may occur naturally while the base semiconductor layer 8 and the compound semiconductor layer 9 are being cooled.

[0122] The base semiconductor layer 8 and the compound semiconductor layer 9 may have the initiation points 8K and 9T, respectively, that have a tapered notch shape. In this case, stress tends to concentrate at one point, making it easier to produce a high-quality cleavage plane by cleavage. The shapes of the initiation points 8K and 9T are affected by the shape of the initiation inducing portion 5Y of the mask portion 5 in the mask layer 6. The shape of the initiation inducing portion 5Y can affect the quality of the cleavage plane.

[0123] Furthermore, tensile stress may occur as internal stress in the base semiconductor layer 8. For example, if the thermal expansion coefficient of the main substrate 1 is larger than that of the base semiconductor layer 8, compressive stress occurs in the base semiconductor layer 8, whereas if the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress occurs in the base semiconductor layer 8. When the base semiconductor layer 8 in which tensile stress occurs is cleaved, the possibility that the separated pieces of the base semiconductor layer 8 will come into contact with each other can be reduced. This reduces the possibility that the end faces of the separated base semiconductor layer 8 will be damaged. Furthermore, when cleavage occurs in the base semiconductor layer 8 so as to tear it from the starting point 8K, the cleavage planes are likely to be smooth.

[0124] In the first embodiment, when the semiconductor substrate 10 is cooled, the base semiconductor layer 8 and the compound semiconductor layer 9 may be cleaved to separate the semiconductor laser device 20 into a plurality of half-element portions sDS each having an optical resonator LK on the template substrate 7. In this case, there is no need to perform a separate process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9, thereby reducing the manufacturing cost of the semiconductor laser device 20. Also, half-element portions sDS each having an optical resonator LK with a short resonator length can be manufactured. For example, the length of the interval L2 can be set to about 20 μm to 200 μm, and therefore the resonator length L1 can be set to about 20 μm to 200 μm.

[0125] Furthermore, if there are any portions of the origin portion 9T where no split portion PS has been generated from the origin portion 9T after cooling the semiconductor substrate 10, i.e., no cleavage has occurred, a process for cleaving the origin portion 9T may be further performed. For example, cleavage may be initiated at the origin portion 9T by applying a blade to the origin portion 9T and applying force perpendicular to the surface. In this case, cleavage can be relatively reliably initiated at the origin portion 9T, thereby improving yield. Alternatively, cleavage may be initiated at the origin portion 9T by applying vibration to the origin portion 9T. In this case, cleavage can be relatively easily performed, thereby simplifying the manufacturing process. Furthermore, cleavage may be initiated by raising or lowering the temperature of the semiconductor substrate 10 above room temperature, thereby applying thermal stress to the origin portion 9T by utilizing the difference in thermal expansion coefficients between the main substrate 1 and the base semiconductor layer 8.

[0126] Fig. 18 is an exploded perspective view for explaining the configuration of the half-element unit sDS in Example 1. In Fig. 18, for convenience of explanation, the template substrate 7 and the base semiconductor layer 8 are illustrated as being virtually separated from each other, but in reality, the base semiconductor layer 8 and the mask portion 5 are in contact with each other. In addition, the base semiconductor layer 8 has a junction 8S on its lower surface that corresponds to the initial growth layer SL, and the junction 8S and the seed layer 3 are bonded to each other. In addition, Fig. 18 illustrates only a portion of the template substrate 7, rather than the entirety.

[0127] 18 , the base semiconductor layer 8 in the half-element portion sDS has a first base end face 8X and a second base end face 8Y adjacent to and at an angle to the first base end face 8X. The base semiconductor layer 8 may have a third base end face 8Z adjacent to and at an angle to the second base end face 8Y and corresponding to the a-plane of the GaN-based semiconductor (e.g., parallel to the a-plane). The second base end face 8Y may be located between the first base end face 8X and the third base end face 8Z. The half-element portion sDS may have two first base end faces 8X and two second base end faces 8Y as end faces of the third portion B3.

[0128] The first base end surface 8X may include a first partial surface 8X1, a second partial surface 8X2, and a third partial surface 8X3. The first partial surface 8X1 is a part of the first base end surface 8X and is a surface at a position corresponding to the first portion B1 of the base semiconductor layer 8. The second partial surface 8X2 is a partial surface of the first base end surface 8X at a position corresponding to the second portion B2. The third partial surface 8X3 is a partial surface of the first base end surface 8X at a position corresponding to the third portion B3. The first partial surface 8X1 is located between the second partial surface 8X2 and the third partial surface 8X3.

[0129] The third partial surface 8X3 may be a surface formed by dividing a portion corresponding to the oblique meeting portion 8N, and may be an m-plane cleavage surface formed by cleaving the base semiconductor layer 8 starting from the starting point 8K. The second partial surface 8X2 may be an m-plane cleavage surface formed by cleaving the base semiconductor layer 8 starting from the starting point 8K, and may be flush with the emission surface F1 of the optical resonator LK. The first partial surface 8X1, the second partial surface 8X2, and the third partial surface 8X3 may be flush with one another. The surface roughness of the second partial surface 8X2 may be smaller than that of the third partial surface 8X3. The density of dislocations (dislocations measured by CL on the cleavage surface, mainly basal plane dislocations) in the second partial surface 8X2 may be equal to or greater than the threading dislocation density in the second portion B2.

[0130] The second base end facet 8Y is a surface included in the notch-shaped initiation point portion 8K in the base semiconductor layer 8 before cleavage, and is not a cleavage plane formed by cleavage. Depending on the shape of the initiation point inducing portion 5Y of the mask portion 5, the initiation point portion 8K may have an end face of an ELO semiconductor layer grown in the m-axis direction. In this case, the second base end facet 8Y may not be a cleavage plane but may be the m-plane of a GaN-based semiconductor. Furthermore, the compound semiconductor portion 9 may have a side facet 9S located above the second base end facet 8Y. The surface roughness of at least one of the pair of cavity facets (emission facet F1 and opposing facet F2) can be smaller than the surface roughness of the side facet 9S.

[0131] The angle (interior angle) formed between the first base end surface 8X and the second base end surface 8Y is referred to as θ3. The angle θ3 may be an obtuse angle, for example, 120° or approximately 120°, or may be, for example, about 110° to 130°.

[0132] As described above, in Example 1, the base semiconductor layer 8 and the compound semiconductor layer 9 are separated into a plurality of first element portions (semi-element portions sDS), thereby forming an optical resonator LK (see FIGS. 1 and 2) including a resonator facet. In FIG. 18, the optical resonator LK is exemplarily illustrated at a position overlapping the second portion B2 in a plan view, but the position of the optical resonator LK in the X direction is not necessarily limited in the semi-element portions sDS. The optical resonator LK will be described in more detail below.

[0133] In addition, in the first embodiment, it can be said that the optical resonator LK including the resonator facets is formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 so that the main substrate 1 is not divided entirely in the thickness direction.

[0134] The output surface F1 and the opposing surface F2 of the optical resonator LK may each be an m-plane of the compound semiconductor layer 9 and may be included in the cleavage planes of the compound semiconductor layer 9. The output surface F1 and the opposing surface F2 can each be formed by m-plane cleaving the compound semiconductor layer 9, which is a nitride semiconductor layer (e.g., a GaN-based semiconductor layer). The half-element portion sDS may have traces of cleavage origins (e.g., second base end face 8Y) in at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. By having the output surface F1 and the opposing surface F2 be m-planes, the reflectance of the resonator facets of the optical resonator LK can be improved.

[0135] (Process for forming element structure) Next, a process for forming an element structure is performed on the semiconductor substrate 10 having a plurality of half-element portions sDS. For example, a ridge portion RJ is formed in the p-type semiconductor layer 9P, and then an insulating film DF and a first electrode E1 are formed to form the element portion DS. In Example 1, a semiconductor laser element 20 with a double-sided electrode structure is manufactured. Therefore, the element portion DS does not include the second electrode E2, and the second electrode E2 may be provided in a later process.

[0136] Fig. 19 is a perspective view for explaining the configuration of the element portion DS in Example 1. The template substrate 7 is omitted from the illustration in Fig. 19. Fig. 20 is a cross-sectional view showing the configuration of the element portion DS in Example 1.

[0137] As shown in FIGS. 19 and 20, the compound semiconductor layer 9 may include a ridge portion (ridge portion) RJ that overlaps with the first electrode E1 in plan view. The ridge portion RJ may include a second cladding layer 9F and a part (portion that overlaps with the first electrode E1 in plan view) of the electron blocking layer 9E (see FIG. 15). The ridge portion RJ has a shape with its longitudinal direction in the Y direction, and an insulating film DF may be provided to cover the side surfaces of the ridge portion RJ. The insulating film DF may be a single layer film or a multilayer film containing, for example, an oxide or nitride of Si, Al, Zr, Ti, Nb, or Ta. The insulating film DF may have a thickness of about 10 to 500 nm.

[0138] The refractive index of the insulating film DF is smaller than the refractive indexes of the second optical guide layer 9D and the second cladding layer 9F. By providing the ridge portion RJ and the insulating film DF, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, allowing efficient light emission within the resonator LK.

[0139] The first electrode E1 is provided, for example, on the upper surface of the ridge portion RJ and functions as an anode. Examples of materials for the first electrode E1 include metals or alloys such as Ni, Rh, Cr, Au, W, Pt, Ti, and Al, and single-layer or multilayer films of conductive oxides containing at least one selected from Zn, In, and Sn. Examples of conductive oxides include ITO (indium tin oxide), IZO (indium zinc oxide), and GZO (gallium-doped zinc oxide). The thickness of the first electrode E1 may be, for example, about 0.1 to 2 μm.

[0140] The optical resonator LK includes a portion (portion overlapping with the first electrode E1 in plan view) of each of the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P. For example, the optical resonator LK includes a portion (portion overlapping with the first electrode E1 in plan view) of each of the first cladding layer 9B, the first optical guiding layer 9C, the active layer 9K, the second optical guiding layer 9D, the electron blocking layer 9E, and the second cladding layer 9F.

[0141] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and also decreases in the order of the active layer 9K, the second optical guide layer 9D, and the second cladding layer 9F. Therefore, light generated by the combination of holes supplied from the first electrode E1 and electrons supplied from the second electrode E2 in the active layer 9K is confined within the optical resonator LK (particularly the active layer 9K), and laser oscillation occurs due to stimulated emission and feedback in the active layer 9K. The laser light generated by laser oscillation is emitted from a light emission region EA of the emission surface F1.

[0142] The output surface F1 and the opposing surface F2 of the optical resonator LK are formed by m-plane cleavage, and therefore have excellent flatness and perpendicularity to the c-plane (parallelism between the output surface F1 and the opposing surface F2), resulting in high optical reflectivity. This reduces reflection loss, enabling stable laser oscillation even at short cavity lengths of 200 μm or less, where optical gain is small. The output surface F1 and the opposing surface F2 are formed above the second portion B2, which is a low-dislocation region, and therefore have excellent flatness of the cleavage surface, resulting in high optical reflectivity.

[0143] In the first embodiment, the sum T1 of the thickness of the base semiconductor layer 8 and the thickness of the compound semiconductor layer 9 can be 50 μm or less. If this sum T1 of thicknesses is too large, it may be difficult to cleave the base semiconductor layer 8 so that the cavity length is 200 μm or less. The ratio of the cavity length L1 (see FIG. 2) to the thickness of the second portion B2 of the base semiconductor layer 8 can be 1 to 20. Furthermore, the direction perpendicular to the direction of the cavity length L1 is the first direction (X direction), and the size of the second portion B2 in the X direction is the width W2 of the second portion B2. The ratio of the cavity length L1 to the width W2 of the second portion B2 can be 1 to 10. The size of the first portion B1 in the X direction is the width W1 of the first portion B1. The ratio of the cavity length L1 to the width W1 of the first portion B1 can be 1 to 200.

[0144] (Step of separating the element portion from the template substrate) Next, a step of separating the element portion DS from the template substrate 7 is performed. FIG. 21 is a cross-sectional view that schematically shows the step of separating the element portion DS from the template substrate 7 in the manufacturing method of the semiconductor laser device of Example 1. Although FIG. 21 shows one element portion DS, it goes without saying that the process of separating a plurality of element portions DS from the template substrate 7 may also be performed. Also, the ridge portion RJ is simply illustrated in FIG. 21.

[0145] As shown in FIG. 21 , first, the mask portion 5 of the template substrate 7 may be removed by etching using hydrofluoric acid, buffered hydrofluoric acid, or the like. The insulating film DF may be protected by a resist or the like so that it is not removed along with the mask portion 5. In Example 1, the mask portion 5 may be removed after the element portion DS is formed on the template substrate 7. In this case, the mask portion 5 can be removed while the element portion DS is fixed to the template substrate 7, which can improve the yield in manufacturing the semiconductor laser element 20. By removing the mask portion 5, the base semiconductor layer 8 and the underlying substrate UK are bonded via the bonding portion 8S (weak portion), making it easier to separate the element portion DS from the underlying substrate UK.

[0146] Next, for example, a step of separating the element portion DS from the template substrate 7 may be performed so as to also serve as a step of bonding the element portion DS to the support substrate SK. The specific shape of the support substrate SK is not particularly limited, but the support substrate SK in Example 1 will be described below with reference to FIGS. 22 and 23. FIG. 22 is a perspective view that schematically shows a state in which the element portion DS is bonded to the support substrate SK. FIG. 23 is a cross-sectional view that schematically shows a state in which the element portion DS is bonded to the support substrate SK.

[0147] As shown in FIGS. 21 to 23, the support substrate SK includes conductive first and second pads P1 and P2. For example, the first electrode E1 may be connected to the first pad P1 via a first bonding portion A1. By bonding at least the first electrode E1 to the first bonding portion A1, the element portion DS is supported by the support substrate SK. This breaks the bonding portion 8S (weak portion) protruding downward from the rear surface of the base semiconductor layer 8, allowing the element portion DS to be separated from the template substrate 7. The insulating film DF and the second pad P2 may also be bonded to each other via a second bonding portion A2 (not shown). In this case, the stability of the state in which the element portion DS is supported by the support substrate SK can be improved. The rear surface of the base semiconductor layer 8 may be planarized by polishing or CMP (Chemical Mechanical Polishing). Then, a second electrode E2 can be formed on the lower surface of the base semiconductor layer 8 of the element portion DS while it is supported by the support substrate SK.

[0148] Next, (i) an insulating film D1 covering the side surfaces of the base semiconductor layer 8 and the compound semiconductor layer 9, and (ii) a conductive film MF are formed. The conductive film MF electrically connects the second electrode E2 to the second joint A2 or the second pad P2. The material of the conductive film MF is not particularly limited. The first pad P1 and the second pad P2 may be provided spaced apart from each other. The conductive film MF may be in contact with the second electrode E2, the insulating film D1, and at least one of the second joint A2 and the second pad P2.

[0149] In the first embodiment, the second electrode E2 is located on the back surface of the base semiconductor portion 8, and the compound semiconductor portion 9 and the first electrode E1 are closer to the support substrate SK than the base semiconductor portion 8 (junction-down type).

[0150] A plurality of element portions DS may be arranged on a support substrate SK in a direction (X direction) perpendicular to the direction defining the cavity length so that the cavity length directions are aligned, and the support substrate SK may be provided with first and second pads P1 and P2 corresponding to each of the plurality of element portions DS.

[0151] The support substrate SK can be formed, for example, as follows. That is, it can be formed by providing a plurality of recesses HL (rectangular in plan view) in a matrix on a Si substrate, SiC substrate, AlN substrate, or the like, and providing a plurality of first pads P1, a plurality of second pads P2, and a plurality of first bonding portions A1 in the non-recessed portions. Note that a plurality of second bonding portions A2 may also be provided. The material constituting the main body of the support substrate SK is not particularly limited, and the support substrate SK may be formed, for example, of an insulator or semi-insulator, or may be formed of a conductive material. Examples of conductive materials include metal materials containing Cu, Al, etc. When the support substrate SK is formed of a conductive material, an insulating layer can be disposed on the upper surface of the support substrate SK, and wiring can be disposed on the insulating layer.

[0152] The shape of the support substrate SK is not particularly limited, and may be a substantially quadrangular prism (substantially rectangular parallelepiped), a substantially pentagonal prism, a substantially hexagonal prism, or other shape. In Example 1, the shape of the support substrate SK is a substantially rectangular parallelepiped.

[0153] The first pad P1 and the second pad P2 may have a metal layer containing, for example, Au, Ti, Ni, or the like. The first bonding portion A1 and the second bonding portion A2 may be composed of a single metal layer or multiple metal layers. If the first bonding portion A1 and the second bonding portion A2 are composed of multiple metal layers, the outermost metal layer may be composed of Au. This can suppress corrosion of the first bonding portion A1 and the second bonding portion A2. The first bonding portion A1 is made of a solder material such as AuSi or AuSn. The first pad P1 and the first electrode E1 may be bonded by metal-metal bonding without the first bonding portion A1, and the second pad P2 and the second electrode E2 may be bonded by metal-metal bonding without the second bonding portion A2. In this case, for example, an Au-Au bond may be used.

[0154] The first pad P1 and the second pad P2 may be located on the same plane. The second bonding portion A2 may not be provided in Example 1. The first bonding portion A1 may be, for example, a solder material, and the element portion DS may be held by the first bonding portion A1 and placed on the support substrate SK.

[0155] (Process for forming a reflective film on the cavity surface) Next, a reflector film UF is formed on the output surface F1 and the opposing surface F2 of the optical resonator LK in the device portion DS mounted on the support substrate SK. This allows the semiconductor laser device 20 to be manufactured. Fig. 24 is a cross-sectional view schematically showing a step of forming a reflector film on the resonator facet in the manufacturing method of the semiconductor laser device of Example 1. Fig. 25 is a plan view showing the configuration of the compound semiconductor layer 9 after the reflector film UF has been formed.

[0156] As shown in FIGS. 24 and 25, a reflector film UF (e.g., a dielectric film) is formed on a first facet, which includes the facet of the base semiconductor layer 8 and the facet of the compound semiconductor layer 9. The first facet includes the emission face F1 of the optical resonator LK. Examples of materials for the reflector film UF include dielectrics such as SiO2, Al2O3, AlN, AlON, Nb2O5, Ta2O5, and ZrO2. The reflector film UF may also be a multilayer film. The reflector film UF can be formed by electron beam evaporation, electron cyclotron resonance sputtering, chemical vapor deposition, or the like.

[0157] The semiconductor laser device 20 can be configured such that at least one of a pair of cavity facets (emission facet F1 and opposing facet F2) has an optical reflectivity of 98% or more, and the cavity length L1 is 200 μm or less. The difference between the emission facet F1 and the opposing facet F2 may be the reflectivity. The cavity facet with the lower reflectivity can be used as the emission facet F1. The reflectivity can be controlled by the type, structure, film thickness, etc. of the reflecting mirror film UF.

[0158] A reflector film UF may be provided to cover the opposing surface F2. The light reflectance of each of the light emitting surface F1 and the opposing surface F2 may be 98% or higher. The light reflectance of the opposing surface F2 on the light reflecting surface side is higher than the light reflectance of the light emitting surface F1. The reflector film UF may be formed on the entire cleavage planes (m-planes) of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0159] As described above, the element portion DS can be electrically connected to and mechanically fixed to the support substrate SK. This allows the element portion DS to be disposed on the support substrate SK with its end faces exposed. Therefore, in the next process, it becomes possible to form a reflective film on the exit surface F1 and the opposing surface F2 of the optical resonator LK at the end faces of the element portion DS. In other words, when the element portion DS is disposed on the template substrate 7 (before the element portion DS is separated from the template substrate 7), the resonator facets are not exposed to the outside in the divided portions PS, making it difficult to form a reflective film on the exit surface F1 and the opposing surface F2 of the optical resonator LK.

[0160] In general, in the manufacture of semiconductor laser devices, a dielectric layer can be formed (facet coating) so that the cavity facets of a plurality of devices have desired reflectance.

[0161] In contrast, by using the support substrate SK, it is possible to appropriately coat the cavity facets of the device portion DS after element separation. The support substrate SK not only serves as a jig when coating the end facets of the optical resonator LK, but also functions as a submount in the final device (semiconductor laser device 20). In Example 1, by coating the device portion DS fixed to the support substrate SK, it is possible to increase the reflection efficiency at the opposing surface F2 and provide a semiconductor laser device 20 with excellent light-emitting efficiency. In addition, it is possible to suppress optical damage to the end facet of the emission surface F1 and provide a semiconductor laser device 20 with excellent reliability.

[0162] Furthermore, in conventional CT, when the cavity facets of an optical cavity are formed by cleavage, both the growth substrate and the structure formed on the growth substrate are cleaved, limiting the extent to which the cavity length can be shortened. As far as the inventors are aware, the shortest cavity length of a semiconductor laser manufactured using a technique for forming cavity facets by cleavage is approximately 300 μm. In contrast, the semiconductor laser device 20 can have an ultrashort cavity of 20 to 200 μm. Because at least one of the cavity facets (the emission facet F1 and the opposing facet F2) has high optical reflectivity and low reflection loss, stable laser oscillation is possible even with a short cavity length of 200 μm or less, at which point optical gain becomes small. The short cavity length enables low power consumption in low-light-output applications such as wearable devices.

[0163] (Step of dividing the support substrate) Next, the support substrate SK may be divided into a plurality of support bodies ST. This makes it possible to obtain semiconductor laser chips 21 in which one or more semiconductor laser elements 20 are held by the support bodies ST. Fig. 26 is a cross-sectional view schematically showing a step of dividing the support substrate SK in the manufacturing method of the semiconductor laser element of Example 1.

[0164] 26, the support substrate SK is divided to form a plurality of semiconductor laser chips 21, each of which has a semiconductor laser element 20 disposed thereon. The support ST can be used as a substrate (also called a submount) for the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0165] The support substrate SK may be divided into the support members ST using a known cutting method such as dicing or scribing. The support substrate SK may be cut at any desired location while avoiding damage to the semiconductor laser element 20. The support member ST may include one semiconductor laser element 20, or may include two or more semiconductor laser elements 20.

[0166] In the above-described first embodiment, the base semiconductor layer 8 and the compound semiconductor layer 9 are separated into a plurality of half-device portions sDS by spontaneous cleavage on the template substrate 7, so there is no need to add a separate process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9. As a result, the manufacturing cost of the semiconductor laser device 20 can be reduced.

[0167] [Another configuration example 1] (1A) The ELO method is not limited to forming a plurality of base semiconductor layers 8 in an island shape. Adjacent base semiconductor layers 8 may be joined together by relatively long growth times during deposition of the base semiconductor layers 8. In this case, the upper surface of the base semiconductor layer 8 may be polished. The compound semiconductor layer 9 can be deposited on a flat base semiconductor layer 8. The base semiconductor layer 8 and the compound semiconductor layer 9 may be dry-etched to form a compound semiconductor layer 9 having an origin portion 9T. A base semiconductor layer 8 having an origin portion 8K may also be formed. This allows a semiconductor substrate 10 that can be isolated on a template substrate 7. For example, a semiconductor substrate 10 having a base semiconductor layer 8 and a compound semiconductor layer 9 in the form shown in FIG. 16 may be formed.

[0168] (1B) After growing the base semiconductor layer 8 on the template substrate 7 in an MOCVD apparatus, the semiconductor substrate 10 may be temporarily removed from the MOCVD apparatus before depositing the compound semiconductor layer 9. In this case, removing the semiconductor substrate 10 from the MOCVD apparatus may cause cleavage in the base semiconductor layer 8. The semiconductor substrate 10 having the cleaved base semiconductor layer 8 may then be loaded into the MOCVD apparatus, and the compound semiconductor layer 9 having the starting point portion 9T may be deposited. In this case, the emission surface F1 and the opposing surface F2 are included in the end facets of the epitaxially grown compound semiconductor layer 9. By epitaxially growing the compound semiconductor layer 9 on the base semiconductor layer 8 having a high-quality cleavage surface, the end facets of the compound semiconductor layer 9 can be made high-quality. Therefore, the end facets of the epitaxially grown compound semiconductor layer 9 can be used as cavity facets.

[0169] (1C) In Example 1, the mask portion 5 is removed after the element portion DS is formed on the template substrate 7, but in another configuration example, the mask portion 5 may be removed before the step of forming the element portion DS. For example, after forming the semi-element portion sDS by element isolation on the template substrate 7, the mask portion 5 may be removed before forming the element portion DS. In this case, there is an advantage that it is not necessary to protect the insulating film DF so that the insulating film DF is not removed when the mask portion 5 is removed.

[0170] (1D) In another configuration example, the second electrode E2 and the reflector film UF may be formed while the device portion DS is supported using a temporary substrate, and then the semiconductor laser device 20 may be mounted on the support substrate SK. Alternatively, both the temporary substrate DK and the support substrate SK may be divided while the semiconductor laser device 20 is sandwiched between the temporary substrate and the support substrate SK. In this case, the individual pieces of the divided temporary substrate DK may be removed.

[0171] Alternatively, a first support substrate having wiring may be used instead of the temporary substrate DK, and in this case, both the first support substrate and the support substrate SK (second support substrate) may be cut while the semiconductor laser element 20 is sandwiched between them, thereby providing a semiconductor laser chip 21 including an individual piece of the first support substrate and the support ST.

[0172] (1E) FIG. 27 is a plan view illustrating another example of the base semiconductor layer 8 in Example 1. As shown in FIG. 27, the base semiconductor layer 8 of the example may have an initiation portion 8K in which a notch is formed up to a position close to the initiation portion inducing portion 5Y in a plan view. The tip of the initiation portion 8K is referred to as a tip portion 8P. For example, the initiation portion 8K may be located at a position where the tip portion 8P overlaps the initiation portion in a plan view. The initiation portion 8K may have a virtual triangular shape in a plan view. In this virtual triangle, a virtual line segment corresponding to the base when the tip portion 8P is the apex is referred to as a side 8C. The distance from the side 8C to the tip portion 8P is referred to as a cutout length H2 of the initiation portion 8K. The cutout length H2 may be WM / 4 or more, or may be WM / 3 or more, where WM is the width WM of the mask portion 5 (see FIG. 4). The cutout length H2 may be WM / 2 or less.

[0173] By forming the compound semiconductor layer 9 on the base semiconductor layer 8, the compound semiconductor layer 9 is formed into a shape having an origin portion (not shown) corresponding to the origin portion 8K. The origin portion formed in the compound semiconductor layer 9 may have an end face that is an m-plane of a GaN-based semiconductor by being formed into a shape that corresponds to the origin portion 8K. The end face of the origin portion formed in the compound semiconductor layer 9 does not have to be an m-plane of a GaN-based semiconductor.

[0174] 28 is an exploded perspective view for explaining the configuration of the half-element portion sDS formed by isolating the base semiconductor layer 8 and the compound semiconductor layer 9. In FIG. 28, for convenience of explanation, the template substrate 7 and the base semiconductor layer 8 are shown as being virtually separated from each other, but in reality, the base semiconductor layer 8 and the mask portion 5 are in contact with each other. In addition, the base semiconductor layer 8 has a bonding portion 8S on its lower surface that corresponds to the initial growth layer SL, and the bonding portion 8S and the seed layer 3 are bonded to each other. In addition, in FIG. 28, only a portion of the template substrate 7 is shown, with the omitted portion omitted, rather than the entirety of the template substrate 7.

[0175] 28, in the base semiconductor layer 8 of an example half-element portion sDS, the first base end face 8X may not have a third partial facet 8X3. The angle (interior angle) formed between the second base end face 8Y and the third base end face 8Z is referred to as θ4. θ4 may be an obtuse angle, for example, 120° or approximately 120°, or for example, approximately 110° to 130°. Alternatively, θ4 may exceed 130°. The second base end face 8Y may be an m-plane of a GaN-based semiconductor.

[0176] (1F) In another configuration example of the first embodiment, the element portion DS may have a portion of the compound semiconductor layer 9 removed by etching or the like, or the compound semiconductor layer 9 may be partially formed on the base semiconductor layer 8. In this case, the first electrode E1 may be connected to the first pad P1 via the first joint A1, and the second electrode E2 may be connected to the second pad P2 via the conductive film MF and the second joint A2. In this example, the element portion DS can be mounted on the support substrate SK without the need to form the insulating film D1 that covers the side surfaces of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0177] Example 2 In Example 1, the semiconductor laser device 20 has a double-sided electrode structure, but in Example 2, the semiconductor laser device 20 may have a single-sided, dual-electrode structure. Fig. 29 is a cross-sectional view showing the configuration of the semiconductor laser device 20 in Example 2.

[0178] 29 , the semiconductor laser device 20 in Example 2 may include a device portion DS including a base semiconductor layer 8 and a compound semiconductor layer 9, and a support substrate SK that holds the device portion DS. Examples of materials for the support substrate SK include Si, SiC, and AlN. The support substrate SK is disposed such that the compound semiconductor layer 9, the first electrode E1, and the second electrode E2 are located between the support substrate SK and the base semiconductor layer 8.

[0179] The first electrode E1 overlaps the optical resonator LK (not shown) in a plan view and also overlaps the second portion B2 of the base semiconductor layer 8. The second electrode E2 is provided on the same side of the base semiconductor layer 8 as the first electrode E1. The second electrode E2 is in contact with the base semiconductor layer 8, and the first electrode E1 and the second electrode E2 do not overlap each other in a plan view. Specifically, the base semiconductor layer 8 has a width in the X direction larger than that of the compound semiconductor layer 9, and the second electrode E2 is formed on an exposed portion where the compound semiconductor layer 9 is not formed. The exposed portion may be formed by removing a portion of the compound semiconductor layer 9 by reactive ion etching (RIE) or the like, or by partially depositing the compound semiconductor layer 9 on the base semiconductor layer 8. Although not shown, the compound semiconductor layer 9 may have an optical resonator LK, and a pair of resonator facets of the optical resonator LK may be covered with a reflector film UF.

[0180] The support substrate SK includes conductive first and second pads P1 and P2, with the first electrode E1 connected to the first pad P1 via a first bonding portion A1 and the second electrode E2 connected to the second pad P2 via a second bonding portion A2. In the second embodiment, the second bonding portion A2 is thicker than the first bonding portion A1, and the difference in thickness between the first bonding portion A1 and the second bonding portion A2 is equal to or greater than the thickness of the compound semiconductor layer 9. This allows the first and second electrodes E1 and E2 to be connected to the first and second pads P1 and P2, which are located on the same plane.

[0181] The support substrate SK may be divided into support members ST, and in this case, the semiconductor laser element 20 may be a semiconductor laser chip 21. The support members ST can be used as a substrate (also called a submount) for the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0182] 30 is a schematic cross-sectional view showing an example of a manufacturing method of a semiconductor laser device 20 in Example 2. As shown in FIG. 30, Example 2 includes the steps of preparing a template substrate 7 including a base substrate UK and a mask layer 6, forming a first semiconductor layer S1 (and a third semiconductor layer S3) that will become a base semiconductor layer 8 by an ELO method (described later), and forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) that will become a compound semiconductor layer 9. A mask layer 6 having an origin initiation point inducing portion 5Y may be formed in the mask portion 5. In this case, the first semiconductor layer S1 (and the third semiconductor layer S3) has an origin initiation point portion 8K. Furthermore, when the second semiconductor layer S2 is formed at a position on the first semiconductor layer S1 that includes the origin initiation point portion 8K, it can be formed to have an origin initiation point portion 9T.

[0183] The starting point portion 8K may be formed in the third portion B3, and the second semiconductor layer S2 may be provided above the second portion B2. In this case, the optical resonator LK is provided at a position overlapping the second portion B2 in plan view. The second semiconductor layer S2 does not need to have the starting point portion 9T, and a starting point for cleavage may be formed by scribing as described later (Example 3, etc.).

[0184] Next, the semi-element portion sDS is formed by element isolation on the template substrate 7. After that, a ridge portion RJ is formed in the first semiconductor layer S1, and a first electrode E1, a second electrode E2, etc. are formed. In this way, an element portion DS having a one-side two-electrode structure is formed on the template substrate 7.

[0185] Then, the element portion DS is bonded to the support substrate SK, and the first semiconductor layer S1 is separated from the template substrate 7. For example, after the element portion DS is formed, the mask portion 5 is etched away, and the first and second bonding portions A1 and A2 (e.g., solder) of the support substrate SK are heated and melted, and the element portion DS is bonded to the support substrate SK. Then, one or both of the support substrate SK and the base substrate UK are displaced so that the support substrate SK and the base substrate UK move away from each other. This breaks the bonding portion (downward protrusion) between the back surface of the first semiconductor layer S1 and the base substrate UK, and the first semiconductor layer S1 is separated from the template substrate 7. As a result, a two-dimensionally arranged semiconductor laser substrate (see FIG. 22) is formed.

[0186] The two-dimensionally arranged semiconductor laser substrate may then be divided into rows to form one-dimensionally arranged (rod-shaped) semiconductor laser substrates, after which a reflector film UF is formed on each of the emission surface F1 and the opposing surface F2. Next, a step of dividing the support substrate SK into a plurality of support members ST may be performed. By having each support member ST hold one or more semiconductor laser elements 20, a plurality of semiconductor laser chips 21 can be formed.

[0187] Example 3 In the third embodiment, a template substrate 7 that does not have an origin inducing portion 5Y in the mask portion 5 may be used. In the third embodiment, a semiconductor laser element 20 having a single-side two-electrode structure is manufactured. Fig. 31 is a flowchart showing an example of a method for manufacturing the semiconductor laser element in the third embodiment.

[0188] As shown in Figure 31, in Example 3, first, a template substrate 7 (see Figure 4) having no origin inducing portion in the mask layer 6 is prepared, and then a base semiconductor layer 8 and a compound semiconductor layer 9 are formed on the template substrate 7.

[0189] In Example 3, for example, the template substrate 7 may be prepared as follows. First, a silicon oxide film having a thickness of approximately 100 nm to 4 μm (preferably approximately 150 nm to 2 μm) is formed on the entire surface of the underlayer 4 using sputtering, CVD, vapor deposition, or the like. Then, a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned using photolithography to form a resist with multiple stripe-shaped openings. Then, multiple openings KS and mask portions 5 are formed by removing portions of the silicon oxide film using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF). Next, the resist is removed using organic cleaning to form a mask layer 6. This allows the template substrate 7 shown in FIG. 4 to be obtained.

[0190] Next, the template substrate 7 is loaded into an MOCVD apparatus, and a GaN-based semiconductor layer is formed by the ELO method. In Example 3, the base semiconductor layer 8 is an n-type GaN layer, and Si-doped GaN is formed on the template substrate 7 by ELO using an MOCVD apparatus. Examples of ELO conditions include a substrate temperature of 1120°C, a growth pressure of 50 kPa, TMG (trimethylgallium) at 22 sccm, NH3 at 15 slm, and V / III = 6000 (the ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). An initial growth layer SL is selectively grown on the seed layer 3 (the GaN layer that is the top layer of the seed layer 3) exposed through the opening KS, and subsequently grows laterally on the mask portion 5. The lateral growth of the base semiconductor layer 8 growing laterally from both sides of the mask portion 5 is stopped before it meets.

[0191] The film formation time may be further extended to cause adjacent base semiconductor layers 8 to meet. In this case, after the compound semiconductor layer 9 is formed on the base semiconductor layer 8, the meeting portion of the base semiconductor layer 8 may be removed by dry etching or the like.

[0192] Fig. 32 is a plan view showing the configuration of a semiconductor substrate 10 on which a base semiconductor layer 8 is formed in Example 3. As shown in Fig. 32, in Example 3, the base semiconductor layer 8 does not have a starting point portion 8K.

[0193] Next, the steps of forming a compound semiconductor layer 9, forming an element structure, and forming cleavage starting points are performed. Fig. 33 is a plan view showing the configuration of a semiconductor substrate 10 on which an element structure according to Example 3 is formed. Fig. 34 is a cross-sectional view showing the configuration of the semiconductor substrate 10 of Fig. 33. In Fig. 34, the template substrate 7 is omitted.

[0194] The compound semiconductor layer 9 may be formed on the entire surface of the base semiconductor layer 8, in which case a portion of the base semiconductor layer 8 may be exposed by reactive ion etching. Alternatively, the compound semiconductor layer 9 may be formed partially on the upper surface of the base semiconductor layer 8. A second electrode E2 may be formed on the exposed portion of the base semiconductor layer 8. Then, a ridge portion RJ is formed in the compound semiconductor layer 9, and an insulating film DF and a first electrode E1 are formed. This makes it possible to obtain a semiconductor substrate 10 having the template substrate 7 and the element structure 22 formed on the template substrate 7.

[0195] Next, cleavage starting points are formed in the element structure 22. The cleavage starting points may be formed in the base semiconductor layer 8 or in the compound semiconductor layer 9. The method for forming the cleavage starting points is not particularly limited. For example, the cleavage starting points may be formed by diamond scribing. In this case, the cleavage starting points can be formed in a narrow shape, which makes it easier to concentrate the cleavage starting points in one location. This makes it easier to obtain a smooth cleavage surface. Note that, because the insulating film DF formed on the compound semiconductor layer 9 is thin, the cleavage starting points can be formed in the compound semiconductor layer 9 regardless of the presence of the insulating film DF. The insulating film DF does not need to be formed in the portion of the compound semiconductor layer 9 where the cleavage starting points are to be formed. In other words, the compound semiconductor layer 9 may be exposed in the portion of the insulating film DF where the cleavage starting points are to be formed.

[0196] Alternatively, the starting point for cleavage may be formed by laser scribing, which reduces variation in the scribe length and improves yield. The length of the laser scribe is the scanning distance of the laser. Alternatively, the starting point for cleavage may be formed by dry etching or wet etching, which facilitates obtaining a smooth cleavage surface because cleavage proceeds without deviating from the cleavage plane.

[0197] The starting point for cleavage may be formed by combining the above techniques. In this case, the advantages of each technique can be simultaneously enjoyed. The starting point formed by diamond scribing or laser scribing may be further wet-etched, in which case the shape of the starting point for cleavage can be shaped. Also, the starting point formed by dry etching may be further wet-etched, in which case the shape of the starting point for cleavage can be shaped.

[0198] Next, the element structure 22 having the cleavage starting points formed therein is cleaved. For example, cleavage may be generated at the cleavage starting points by applying a blade to the cleavage starting points and applying a force perpendicular to the surface direction. In this case, a strong force can be applied to the cleavage starting points, improving yield. Alternatively, cleavage may be generated at the cleavage starting points by applying vibration to the cleavage starting points. In this case, the processing is relatively simple, simplifying the manufacturing process.

[0199] Alternatively, cleavage may be caused by applying thermal stress to the starting point by utilizing the difference in thermal expansion coefficient between the main substrate 1 and the base semiconductor layer 8, by raising or lowering the temperature of the semiconductor substrate 10 above room temperature. When the difference in thermal expansion coefficient is utilized, the way in which force is applied is uniform across the surface, improving yield.

[0200] Alternatively, the template substrate 7 may be curved by thinning the main substrate 1 by polishing or the like, thereby applying stress to the element structures 22 on the template substrate 7 to cleave them. In this case, the element structures 22 can be separated into elements, and multiple element portions DS can be formed at once. This reduces the manufacturing cost.

[0201] The element structure 22 may be cleaved by combining the above cleavage techniques, in which case the advantages of each technique can be enjoyed simultaneously.

[0202] In the third embodiment, the timing for removing the mask portion 5 to separate the element portion DS from the template substrate 7 is preferably after the formation of the starting point portions for cleavage or after cleavage, which allows the formation of the starting point portions or cleavage to be performed stably, improving the yield.

[0203] In the third embodiment, a difference in thermal expansion coefficient between the template substrate 7 and the base semiconductor layer 8 may cause internal stress in the base semiconductor layer 8. Furthermore, a difference in lattice constant between the template substrate 7 and the base semiconductor layer 8 may cause internal stress in the base semiconductor layer 8. The internal stress in the base semiconductor layer 8 can make cleavage occur more easily.

[0204] For example, internal stress occurs in the base semiconductor layer 8 and the compound semiconductor layer 9 due to the difference in thermal expansion coefficient between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1. For example, when the base semiconductor layer 8 is formed by the ELO method on a heterogeneous substrate such as a Si substrate, the film formation temperature may be as high as 1000°C or higher. Therefore, when the temperature is lowered to room temperature, stress occurs in the base semiconductor layer 8. Furthermore, strain occurs in the base semiconductor layer 8 due to the difference in lattice constant between the main substrate 1 and the base semiconductor layer 8.

[0205] Here, if the thermal expansion coefficient of the main substrate 1 is larger than that of the base semiconductor layer 8, compressive stress is generated in the base semiconductor layer 8, whereas if the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress is generated in the base semiconductor layer 8. Due to the tensile stress generated in the base semiconductor layer 8, cleavage may occur by scribing the compound semiconductor layer 9. When the base semiconductor layer 8 in which tensile stress is generated is cleaved, the possibility that the individual pieces of the divided base semiconductor layer 8 will come into contact with each other can be reduced. This reduces the possibility that the end faces of the divided base semiconductor layer 8 will be scratched. Furthermore, since cleavage occurs in the element structure 22 as if it is being torn from the starting point due to the application of tensile stress, the cleavage planes are likely to be smooth.

[0206] For example, the internal stress of the base semiconductor layer 8 may be released by scribing the base semiconductor layer 8, causing the element structure 22 to naturally cleave. Alternatively, the internal stress of the base semiconductor layer 8 may be released by scribing the compound semiconductor layer 9, causing the element structure 22 to naturally cleave. "Natural cleavage caused by scribing" means that scribing and cleaving occur at the same or nearly the same time (spontaneous cleavage occurs as a result of scribing). This makes it possible to omit the step of forming a starting point portion (scribing step) and the step of cleaving the starting point portion (breaking step). This reduces the manufacturing cost of the semiconductor laser element 20.

[0207] Next, the element portion DS is separated from the template substrate 7. The subsequent steps are the same as those in Examples 1 and 2, and therefore a description thereof will be omitted.

[0208] As described above, in Example 3, after the element structure is formed, the cleavage starting point can be formed at any position. Therefore, the position where the cleavage starting point is formed can be controlled. As a result, the position where cleavage occurs can be controlled, and the cavity length L1 can be adjusted. Therefore, it is easy to improve the yield.

[0209] [Another configuration example 3] In the above-described third embodiment, the step of forming an element structure is performed, followed by the step of forming a starting point portion and the step of isolating elements on the template substrate 7, but the order is not limited to this. The step of forming an element structure may be performed after the step of forming a starting point portion, and then the step of isolating elements on the template substrate 7 may be performed.

[0210] Example 4 In the fourth embodiment, element isolation may be performed by etching instead of cleavage. Fig. 35 is a plan view showing an example of element isolation in the fourth embodiment.

[0211] 35, after a base semiconductor layer 8 and a compound semiconductor layer 9 are formed on a template substrate 7, etching is performed to form a plurality of trenches TR (separation grooves) in the semiconductor substrate 10. This may separate the template substrate 7 into a plurality of half-device units sDS each having an optical resonator LK. The trenches TR penetrate the compound semiconductor layer 9 and the base semiconductor layer 8. The mask unit 5 and the seed layer 3 or the main substrate 1 may be exposed in the trenches TR.

[0212] Note that etching may cause a taper angle on the end face of the compound semiconductor layer 9 (the end face may deviate from vertical). Therefore, for example, element isolation may be performed as follows. That is, first, the semiconductor substrate 10 is set in a slightly tilted state in an etching apparatus. Next, a trench TR corresponding to one side in the Y direction of the half element portion sDS to be formed by the subsequent etching process is formed by etching. This forms one of the pair of resonator faces of the half element portion sDS (e.g., the emission face F1). As a result, for example, the emission face F1 can be formed vertically or approximately vertically. Next, the semiconductor substrate 10 is set in a slightly tilted state on the other side (the side opposite to when the trench TR was formed) in the etching apparatus. Then, a trench TR corresponding to one side in the Y direction of the half element portion sDS is formed by etching. This forms the other of the pair of resonator faces of the half element portion sDS (e.g., the opposing face F2). As a result, for example, the opposing face F2 can be formed vertically or approximately vertically.

[0213] Example 5 Fig. 36 is a schematic diagram showing the configuration of an electronic device according to Example 5. The electronic device 50 in Fig. 36 includes a semiconductor laser device ZD (semiconductor laser element 20 or semiconductor laser chip 21) and a control unit 80 that includes a processor and controls the semiconductor laser device ZD. Examples of the electronic device 50 include a lighting device, a display device, a communication device, an information processing device, a medical device, and an electric vehicle (EV).

[0214] Example 6 In the first embodiment, the compound semiconductor portion 9 is provided on the c-plane of the base semiconductor portion 8, and the pair of cavity planes are m-planes of a nitride semiconductor, but this is not limiting. For example, the compound semiconductor portion 9 may be provided on the m-plane ((1-100) plane) of the base semiconductor portion 8, and the pair of cavity planes may be c-planes ((0001) planes) of a nitride semiconductor. The cavity length L1 is the length in the c-axis direction. The emission surface F1 and the opposing surface F2 can be formed, for example, by c-plane cleavage of a nitride semiconductor.

[0215] [Additional notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0216] 1 Main board 5 Mask section 5Y Origin Inducer 6 Mask layer (mask) 7 Template substrate 8. Base semiconductor layer (base semiconductor part) 8K, 9T starting point (starting point) 9 Compound semiconductor layer (compound semiconductor section) 20 Semiconductor laser element (semiconductor device) 21 Semiconductor laser chip 70 Manufacturing equipment B1 Part 1 B2 Part 2 B3 Part 3 DS element part E1 1st electrode E2 2nd electrode F1 Output surface (resonator surface) F2 Opposite surface (resonator surface) LK optical resonator RJ Ridge Club sDS half element (element) SK support board

Claims

1. A main board; a mask pattern formed above the main substrate and having a mask portion and an opening whose longitudinal direction is in the first direction and whose lateral direction is in the second direction; a base semiconductor portion including a nitride semiconductor, the base semiconductor portion having a first portion located above the opening and a second portion extending from the first portion above the mask portion; the mask portion has a plurality of protrusions that protrude from an end of the opening in the second direction toward the inside of the opening, In the second direction, the protruding directions of the plurality of protrusions are aligned in one direction.

2. 2. The semiconductor substrate according to claim 1, wherein the protrusion length is 0.1 [mu]m or more and 10 [mu]m or less.

3. The semiconductor substrate according to claim 1 , wherein said convex portion is formed across the thickness of said mask portion.

4. The semiconductor substrate according to claim 1 , wherein the apex of the convex portion is rounded.

5. The semiconductor substrate according to claim 1 , wherein the thickness of the convex portion in the mask portion is different from the thickness of the portion other than the convex portion in the mask portion.

6. The semiconductor substrate according to claim 1 , wherein the opening has a narrower width at a portion where the protrusion is located.

7. The semiconductor substrate according to claim 1 , comprising a plurality of base semiconductor portions, including the base semiconductor portion, arranged in the second direction.

8. The semiconductor substrate according to claim 1 , wherein the protrusion includes a portion tapered in a direction toward the inside of the opening.

9. The semiconductor substrate according to claim 1 , wherein the base semiconductor portion has recesses corresponding to the plurality of protrusions.

10. The semiconductor substrate according to claim 1 , wherein the plurality of protrusions have a shape such that an apex of the protrusion exceeds a center of the opening in a plan view.

11. The semiconductor substrate according to claim 1 , wherein the plurality of protrusions have a shape such that the apex of each protrusion does not extend beyond the center of the opening in a plan view.

12. 12. The semiconductor substrate according to claim 1, wherein the main substrate is a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor.

13. 12. The semiconductor substrate according to claim 1, wherein the threading dislocation density of the second portion is equal to or less than 1 / 5 of the threading dislocation density of the first portion.

14. 12. The semiconductor substrate according to claim 1, wherein the first direction is an m-axis direction of the nitride semiconductor, and the second direction is an a-axis direction of the nitride semiconductor.

15. a step of preparing a semiconductor substrate comprising: a main substrate; a mask pattern formed above the main substrate, the mask pattern having a mask portion and an opening with a first direction as a longitudinal direction and a second direction as a lateral direction; and a base semiconductor portion including a nitride semiconductor, the base semiconductor portion having a first portion located above the opening and a second portion extending from the first portion above the mask portion, the mask portion having a plurality of protrusions protruding from an edge of the opening in the second direction toward the inside of the opening, the plurality of protrusions protruding in one direction in the second direction; and forming a compound semiconductor portion above the semiconductor substrate.

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