Control circuit and semiconductor memory device

Abstract

To provide a control circuit and a semiconductor storage device capable of suppressing the occurrence of overflow or underflow by suppressing the influence of jitter.SOLUTION: The control circuit of the present invention includes a control unit that generates a control signal indicating a delay amount, a delay line unit that performs a delay operation of delaying an input clock signal in accordance with the control signal to generate an output clock signal, and a selection unit that receives the output clock signal and performs a selection operation of selecting a temporary delay signal having a temporary delay amount closest to a required delay amount from a plurality of temporary delay signals generated by delaying the output clock signal by a plurality of different temporary delay amounts. And temporary delay amount selection means for outputting a signal indicating the temporary delay amount of the selected temporary delay signal, wherein the control means sets the delay amount on the basis of the output signal indicating the temporary delay amount.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a control circuit and a semiconductor memory device. [Background technology]

[0002] DRAM (Dynamic Random Access Memory), a type of semiconductor memory device, is a volatile memory that stores information by storing electric charges in capacitors and loses the stored information when power is cut off. DRAM is equipped with a delay locked loop (DLL) circuit as a phase-locked loop circuit. DRAM uses the DLL circuit to generate an internal clock signal for outputting a data signal, synchronized with an externally input clock signal (see, for example, Patent Document 1). During delay operation, the DLL circuit generates a feedback signal from the output signal from a delay line section and compares it with the input clock signal to synchronize it.

[0003] In such a DLL circuit, the input clock signal is compared with the feedback signal during delay operation, and the delay amount added to the input clock signal is gradually changed multiple times to achieve an appropriate delay amount, thereby delaying the input clock signal. However, fluctuations (jitter) occur in the feedback signal. Therefore, if the delay amount is gradually changed multiple times, the effect of this jitter becomes significant, resulting in the problem of overflow or underflow. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2023 / 308103 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a control circuit and a semiconductor memory device that can suppress the influence of jitter and prevent overflow or underflow. [Means for solving the problem]

[0006] The control circuit of the present invention comprises a control means for generating a control signal indicating a delay amount, a delay line section for performing a delay operation of delaying an input clock signal to generate an output clock signal in response to the control signal, and a temporary delay amount selection means for receiving the output clock signal and generating a plurality of temporary delay signals by delaying the output clock signal by a plurality of different temporary delay amounts, and then performing a selection operation of selecting from these plurality of temporary delay signals the temporary delay signal having the temporary delay amount closest to the required delay amount, and outputting a signal indicating the temporary delay amount of the selected temporary delay signal, wherein the control means sets the delay amount based on the signal indicating the temporary delay amount that is output. In the present invention, the temporary delay amount selection means generates a plurality of temporary delay signals and performs a selection operation to select the temporary delay signal having the temporary delay amount closest to the required delay amount from the plurality of temporary delay signals, thereby making it possible to set the delay amount in a single delay operation without performing multiple delay operations, thereby suppressing the influence of jitter and preventing overflow or underflow.

[0007] The semiconductor memory device of the present invention is characterized by including the control circuit described above. By including the control circuit, the influence of jitter can be suppressed and the occurrence of overflow or underflow can also be suppressed, so that the semiconductor memory device of the present invention can operate favorably. [Effects of the Invention]

[0008] According to the control circuit and semiconductor memory device of the present invention, the influence of jitter can be reduced, and the occurrence of overflow or underflow can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of the configuration of a control circuit according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a provisional delay amount generating unit according to the first embodiment of the present invention. [Figure 3] FIG. 2 is a diagram illustrating a relationship between a delayed feedback signal and an input clock signal. [Figure 4] FIG. 10 is a diagram illustrating a configuration of a provisional delay amount generating unit according to a second embodiment of the present invention. [Figure 5] FIG. 2 is a diagram illustrating a relationship between a delayed feedback signal and an input clock signal. [Figure 6] FIG. 10 is a diagram illustrating a modified example of the second phase detection unit. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, a control circuit and a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is merely an example, and the present invention is not limited to this embodiment.

[0011] (Embodiment 1) 1 shows an example of the configuration of a control circuit according to an embodiment of the present invention. In this embodiment, the control circuit 1 is provided in a semiconductor memory device such as a DRAM. In this embodiment, for the sake of simplicity, well-known components provided in a semiconductor memory device such as a DRAM (for example, a command decoder, a memory cell array, an input / output interface unit, etc.) are not shown.

[0012] The control circuit 1 includes an input buffer 11, a first phase detection unit 12, a DLL control unit 13, a delay line unit 14, a replica unit 15, an output buffer 16, a temporary delay generation unit 20, and a selection unit 25. In this embodiment, when identical components are to be distinguished by their positions, the components are distinguished by adding letters or numbers after the components. In this embodiment, the DLL control unit 13 is an example of the "control means" of the present invention, the temporary delay generation unit 20 is an example of the "temporary delay generation means" of the present invention, and the selection unit 25 is an example of the "selection means" of the present invention.

[0013] The input buffer 11 buffers an external clock signal CK input to the input buffer 11 to generate an input clock signal clk. The input clock signal clk is transmitted to a delay line unit 14 and a first phase detection unit 12. The delay line unit 14 generates a delayed signal (output clock signal) dll_clk by delaying the input clock signal clk, and transmits the delayed signal to an output buffer 16 and a replica unit 15. The replica unit 15 outputs the delayed signal dll_clk generated by the delay line unit 14 to the first phase detection unit 12 as a feedback signal fb_clk.

[0014] The first phase detector 12 detects the phase difference between the input clock signal clk and the feedback signal fb_clk. Specifically, the input clock signal clk and the feedback signal fb_clk are input to the first phase detector 12. The first phase detector 12 generates a phase signal up / down indicating the phase lead or lag (phase difference) of the feedback signal fb_clk relative to the input clock signal clk, and inputs the signal to the DLL control unit 13.

[0015] The DLL control unit 13 determines the amount of delay and generates a control signal dll_code based on the amount of delay. Specifically, the DLL control unit 13 generates and outputs a control signal dll_code consisting of multiple bits as a signal indicating the amount of delay in a locking operation (one example of a "delay operation" of the present invention) based on the phase signal up / down and a status signal cdl described later. The output control signal dll_code is input to the delay line unit 14.

[0016] The delay line unit 14 is a variable delay unit that, when a control signal dll_code indicating the delay amount set by the DLL control unit 13 is input, delays the input clock signal clk based on the control signal dll_code to generate a delayed signal dll_clk (output clock signal) and outputs it to the output buffer 16.

[0017] Here, the delay amount indicates how much the delay signal dll_clk is delayed relative to the input clock signal clk during delay operation. The delay time tDLL set based on the delay amount can be expressed as follows: tDLL=X*CDL+Y*FDL (CDL: Coarse Delay Line) (FDL: Fine Delay Line) Therefore, the delay time is determined by the DLL control unit 13 setting the X value and the Y value that indicate the degree to which the coarse delay line (CDL) and the fine delay line (FDL) are activated, respectively.

[0018] The control signal dll_code includes both the X value and the Y value. Here, the X value is a value that the DLL control unit 13 would have set by changing the delay amount multiple times in the past as described below. That is, in order for the DLL control unit 13 to set the delay amount, the DLL control unit 13 temporarily sets the X value from the initial delay amount, generates the control signal dll_code, detects the phase difference between the input clock signal clk and the feedback signal fb_clk based on the phase signal up / down from the first phase detection unit 12, and if the phase difference is large, increases the X value and generates the control signal dll_code again, thereby performing feedback control to gradually approach the optimal delay amount and set the optimal X value (setting operation). After the X value is determined, the Y value is set based on the up / down phase signal from the first phase detection unit 12, and fine adjustment is performed to set the optimum control signal dll_code (Y value setting operation).

[0019] In contrast, in this embodiment, a temporary delay amount selection means is provided. When a delay operation is initiated, while a setting operation is performed first in the conventional system, in this embodiment, the input of the phase up / down signal from the first phase detection unit 12 is stopped first, and the temporary delay amount selection means starts a selection operation. The temporary delay amount selection means generates multiple replica delay signals (temporary delay signals) dfb_clk by delaying a feedback signal fb_clk, which has the same phase as the delay signal (output clock signal) dll_clk, by multiple different temporary delay amounts. From the multiple replica delay signals dfb_clk, the replica delay signal dfb_clk with the smallest temporary delay amount relative to the input clock signal clk is selected, and a selection operation is performed to set the delay amount based on the temporary delay amount of the replica delay signal dfb_clk. Here, the temporary delay amount indicates how much the replica delay signal dfb_clk is delayed relative to the feedback signal fb_clk in the replica delay line unit 21. This is not used to actually perform a delay operation in the delay line unit 14.

[0020] In this way, in this embodiment, multiple replica delay signals (temporary delay signals) dfb_clk are generated to predict the delay amount in advance, and the optimal delay amount can be set by a single selection operation, without the need for multiple setting operations in which the DLL control unit 13 generates control signals dll_code with different delay amounts as in the conventional method.

[0021] Such a temporary delay selecting means includes a temporary delay generating unit 20 provided after the replica unit 15 and before the first phase detecting unit 12, and a selecting unit 25 provided after the temporary delay generating unit 20 and before the DLL control unit 13. A feedback signal fb_clk and an input clock signal clk are input to the temporary delay generating unit 20. The temporary delay generating unit 20 includes a replica delay line unit 21 and a second phase detecting unit 22.

[0022] A feedback signal fb_clk is input to the replica delay line unit 21. The replica delay line unit 21 generates multiple replica delay signals dfb_clk by delaying the input feedback signal fb_clk by different amounts, and transmits each of the multiple replica delay signals dfb_clk to the second phase detection unit 22. The second phase detection unit 22 receives the multiple replica delay signals dfb_clk and one input clock signal clk. The second phase detection unit 22 detects the phase difference between each replica delay signal dfb_clk and the input clock signal clk. The second phase detection unit 22 outputs multiple state signals cdl indicating this phase difference to the selection unit 25, and the selection unit 25 selects the optimal state signal cdl from the multiple state signals cdl.

[0023] Specific configurations of the replica delay line unit 21 and the second phase detection unit 22 will be described with reference to FIG. 2. The replica delay line unit 21 has a configuration that simulates the delay line unit 14, i.e., the same configuration as the delay line unit 14, and is composed of multiple NAND gates connected in series. Two adjacent NAND gates form a set of delay elements 23, which are also connected in series, with multiple delay elements 23a to 23x connected in series. Each replica delay signal dfb_clk extracted from a node nd between the delay elements 23 has a different temporary delay amount depending on how many delay elements 23 the feedback signal fb_clk has passed through. The replica delay signal dfb_clk closest to the input side has a small temporary delay amount, and the temporary delay amount of the replica delay signal dfb_clk increases with each delay element 23 the feedback signal fb_clk passes through.

[0024] For example, the replica delay signal dfb_clk6 output from the delay element 23b adjacent to the delay element 23a is delayed by one delay element 23 from the replica delay signal dfb_clk4 output from the delay element 23a. In this case, the tentative delay amount that can be set by the delay elements 23 configured in the replica delay line unit 21 is set to be longer than one clock cycle (1tCK). By setting it in this way, even if the delay amount is large, the tentative delay amount can be set sufficiently and stably. Note that another NAND gate is provided between the node nd and the second phase detection unit 22, and each replica delay signal dfb_clk is output to the second phase detection unit 22 via this other NAND gate.

[0025] The second phase detection unit 22 is composed of a plurality of D flip-flop circuits DFF, and each D flip-flop circuit DFF receives the input clock signal clk and each replica delay signal dfb_clk. For example, the input clock signal clk and the replica delay signal dfb_clk2 are input to the D flip-flop circuit DFF1, and the input clock signal clk and the replica delay signal dfb_clk4 are input to the D flip-flop circuit DFF2. Each D flip-flop circuit DFF detects whether the replica delay signal dfb_clk is high or low at the rising edge of the input clock signal clk, and outputs the detected signals collectively as a plurality of state signals cdl. The plurality of state signals cdl are input to the selection unit 25.

[0026] Specific operations of the replica delay line unit 21 and the second phase detection unit 22 will be described with reference to FIG. 3. FIG. 3 shows the input clock signal clk, the feedback signal fb_clk, and the replica delay signals dfb_clk2 to dfb_clk8 generated by the replica delay line unit 21 side by side. As described above, the replica delay signals dfb_clk2 to dfb_clk8 are each delayed by a different temporary delay amount relative to the feedback signal fb_clk by the delay element 23. In this state, at the rising timing of the input clock signal clk (rising edge, indicated by the dotted line in FIG. 3), the logic states of the replica delay signals dfb_clk2 to dfb_clk8 are low, high, high, and low, respectively. Therefore, the state signals cdl2 to cdl8 output from the D flip-flop circuits DFF1 to DFF4 indicate "L," "H," "H," and "L." These state signals cdl are all input to the selector 25 at once.

[0027] The selector 25 then selects the state signal cdl whose logic state has changed from high to low among the multiple state signals cdl input collectively, in order of decreasing temporary delay. That is, when the state signal cdlx indicates a high level and the next state signal cdly indicates a low level, the selector 25 generates the control signal dll_code based on the state signal cdlx. In the example shown in FIG. 3, the state signals cdl2 to cdl8 are "L," "H," "H," and "L." The logic state change from high to low occurs between the state signal cdl6 and the state signal cdl8. When the high level drops to low, the state signal cdlx becomes the state signal cdl6. When the logic state is changed, the phase lead / lag between the input clock signal clk and the replica delay signal dfb_clk is inverted, resulting in a small phase difference with the input clock signal clk. Therefore, by having the selection unit 25 select either the state signal cdlx or cdly before or after the logical state is changed (in this embodiment, the state signal cdlx before the logical state is changed) as the selected temporary delay amount, the DLL control unit 13 can set an appropriate delay amount.

[0028] The selector 25 inputs the state signal cdl selected in this way to the DLL control unit 13. Then, the DLL control unit 13 sets the X value from the provisional delay amount indicated by this selected state signal cdl.

[0029] While the DLL control unit 13 is performing a selection operation by the temporary delay amount selection means, the phase signal up / down is not input from the first phase detection unit 12 and the setting operation that was previously performed is not performed, so the delay operation in the delay line unit 14 is essentially stopped, that is, the update of the control signal dll_code is stopped. Then, when the selection operation is completed, the replica delay line unit 21 and the second phase detection unit 22 are stopped, the input of the phase signal up / down from the first phase detection unit 12 is resumed, and the Y value setting operation is performed. As a result, the control signal dll_code is updated in the DLL control unit 13 and input to the delay line unit 14, and the delay operation that was previously stopped is performed.

[0030] As described above, in this embodiment, the temporary delay amount selector generates multiple replica delay signals dfb_clk, detects the phases of these signals collectively, and performs a selection operation to select the replica delay signal dfb_clk that is closest in phase to the input clock signal. During this selection operation, the first phase detector 12 does not input the phase signal up / down to the delay line unit 14, so the delay line unit 14 stops updating the control signal dll_code, and only after the selection operation is completed can it update the control signal dll_code to an appropriate value in one go. Therefore, compared to changing the control signal dll_code multiple times to gradually adjust the delay amount, it is possible to suppress the significant influence of jitter and prevent underflow and overflow from occurring.

[0031] Furthermore, in this embodiment, by providing the temporary delay amount generation unit 20, phase detection can be performed using the feedback signal fb_clk output from the replica unit 15 and the input clock signal clk, and the configuration is simple. Moreover, regardless of the configuration of the delay line unit 14, by providing the temporary delay amount generation unit 20 after the replica unit 15 as in this embodiment, the delay amount can be preferably detected in one go.

[0032] (Embodiment 2) This embodiment includes a temporary delay amount generating section 30 having a different configuration from the temporary delay amount generating section 20 of embodiment 1. In Fig. 4, the temporary delay amount generating section 30 includes a replica delay line section 31 and a phase detecting section 32. Note that in embodiment 2, the configuration of the control circuit 1 other than the temporary delay amount generating section 30 is the same as that of embodiment 1, and therefore will not be described.

[0033] The replica delay line unit 31 is configured with a plurality of delay element strings 34, each consisting of a delay element 33, connected in parallel. Each delay element string 34 is configured with a different number of delay elements 33 connected in series, with one or more delay elements 33 connected in series, and each delay element 33 is configured with two NAND gates connected in series. The replica delay signal dfb_clk, which is the output of each delay element string 34, has a different temporary delay amount depending on the number of delay elements 33, as in the first embodiment. The replica delay signal dfb_clk is input to each D flip-flop circuit DFF of the phase detection unit 32. The input clock signal clk is also input to the D flip-flop circuit DFF. Each D flip-flop circuit DFF outputs a status signal cdl indicating whether the replica delay signal dfb_clk is at high level or low level at the rising edge of the input clock signal clk.

[0034] In this case, too, the state signal cdl indicating whether the multiple replica delay signals dfb_clk are at high level or low level can be output collectively at the rising timing (rising edge) of the input clock signal clk. As shown in FIG. 5 , in this embodiment, the logic state of the state signal cdl10 is high level and the logic state of the state signal cdl12 is low level, so the selector 25 selects the state signal cdl10 and selects the temporary delay amount of the state signal cdl10 and inputs it to the DLL control unit 13.

[0035] As shown in the first and second embodiments, the temporary delay generating units 20 and 30 are not limited to any particular configuration, and may be configured to simultaneously set a plurality of replica delay signals and simultaneously detect the phase difference between the replica delay signals and the input clock signal.

[0036] (Variation) In the above-described embodiments, the delay elements are all NAND gates, but this is not a limitation. Other delay means may also be used. It is preferable that the delay line unit 14 and the replica delay line units 21 and 31 have the same components. Therefore, if the delay line unit 14 is made up of NAND gates, the delay elements of the replica delay line units 21 and 31 are preferably made up of NAND gates. However, if the delay line unit 14 is made up of inverters, the components of the replica delay line units 21 and 31 are preferably inverters. In the above-described embodiments, the selector 25 is provided upstream (externally) from the DLL control unit 13. However, the present invention is not limited to this. For example, the selector 25 may be provided inside the DLL control unit 13. Alternatively, for example, the selector 25 may be provided in the second phase detection unit 22, and the state signal cdl selected by the selector 25 may be input to the DLL control unit 13.

[0037] 6, the second phase detection unit 22 may be configured as a synchronizer by connecting two stages. Such a configuration makes it possible to more stably determine the logic state. In the above-described embodiment, the delay amount is set based on one state signal cdl that is at a high level when the logic state changes from a high level to a low level, but it may also be set based on the next state signal cdl that is at a low level.

[0038] In the above-described embodiment, the semiconductor memory device including the control circuit is a DRAM, but the present invention is not limited to this. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a flash memory, or another semiconductor memory device.

[0039] The above-described embodiments and modifications have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments and modifications are intended to include all design modifications and equivalents that fall within the technical scope of the present invention. [Explanation of symbols]

[0040] 1 Control circuit 11 Input Buffer 12 First phase detector 13 DLL control unit (control means) 14 Delay Line Section 15 Replica Section 16 output buffers 20, 30 temporary delay amount generating unit (temporary delay amount generating means) 21 Replica delay line section 22 Second phase detector 23 Delay Elements 25 Selection unit (selection means) 31 Replica delay line section 32 Phase detection section 33 Delay Elements 34 Delayed Element Sequence CK External clock signal clk Input clock signal dll_clk delayed signal (output clock signal) dfb_clk replica delayed signal (temporary delayed signal) dll_code control signal fb_clk feedback signal up / down phase signal

Claims

1. control means for generating a control signal indicative of the amount of delay; a delay line section that performs a delay operation to delay an input clock signal and generate an output clock signal in response to the control signal; a temporary delay amount selection means for receiving the output clock signal, delaying the output clock signal by a plurality of different temporary delay amounts to generate a plurality of temporary delay signals, and then selecting, from the plurality of temporary delay signals, the temporary delay signal having a phase closest to the phase of the input clock signal, and outputting a signal indicating the temporary delay amount of the selected temporary delay signal; The control circuit is characterized in that the control means sets the delay amount based on the output signal indicating the temporary delay amount.

2. 2. The control circuit according to claim 1, wherein the delay operation in the delay line section is stopped while the temporary delay amount selection means is performing the selection operation.

3. The temporary delay amount selection means a temporary delay amount generating means for generating a plurality of temporary delay signals by delaying the output clock signal by a plurality of different temporary delay amounts; a selection means for selecting, from the plurality of temporary delay signals, a temporary delay signal having a temporary delay amount close to the required delay amount, and outputting a signal indicating the temporary delay amount of the selected temporary delay signal; 3. The control circuit according to claim 1, further comprising:

4. the temporary delay amount generating means has a replica delay line section to which a feedback signal having the same phase as the output clock signal is input, and a phase detection section to which the input clock signal is input, the replica delay line unit generates the temporary delay signals having a plurality of different temporary delay amounts obtained by delaying the input feedback signal, 4. The control circuit according to claim 3, wherein the plurality of temporary delay signals are input to the phase detection unit.

5. 5. The control circuit according to claim 4, wherein the selection means is provided in the control means or the phase detection section.

6. 5. The control circuit according to claim 4, further comprising a replica section that receives the output clock signal from the delay line section and outputs the feedback signal to the replica delay line section.

7. 5. The control circuit according to claim 4, wherein the phase detection unit generates a state signal that detects the logical state of each of the temporary delay signals in response to the input clock signal as a signal indicating the temporary delay amount, and inputs the state signal to the selection means.

8. The control circuit according to claim 7, characterized in that the selection means sets the provisional delay amount based on the status signal of either one of the provisional delay signals or the next provisional delay signal when the logical state changes between one of the provisional delay signals and the next provisional delay signal when the status signals are compared in order of the least provisional delay amount.

9. 9. The control circuit according to claim 8, wherein the change in logic state is such that the logic state of the first temporary delayed signal is high and the logic state of the next delayed signal is low.

10. 4. The control circuit according to claim 3, wherein the maximum temporary delay that can be generated by said temporary delay generating means is a temporary delay that is greater than one clock cycle.

11. 5. The control circuit according to claim 4, wherein the replica delay line section has the same configuration as the delay line section.

12. 5. The control circuit according to claim 4, wherein the replica delay line section comprises a plurality of delay elements connected in series, each delaying the input clock signal by a predetermined amount.

13. 5. The control circuit according to claim 4, wherein the replica delay line section is provided with a delay element string in parallel, the delay element string being made up of a plurality of delay elements connected in series.

14. 5. The control circuit according to claim 4, wherein the phase detection section is configured by a synchronizer having a plurality of D flip-flop circuits arranged in two stages.

15. 2. A semiconductor memory device comprising the control circuit according to claim 1.

16. 16. The semiconductor memory device according to claim 15, wherein the semiconductor memory device is a dynamic random access memory.

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