Switch device and tripping latch circuit thereof

Abstract

The embodiment of the utility model provides switch equipment and a tripping latch circuit thereof. The tripping latch circuit comprises a signal transmission circuit and a feedback circuit. The signal transmission circuit comprises a tripping signal input end which is suitable for being coupled with a tripping signal input circuit so as to receive a tripping signal; the signal feedback end is suitable for receiving a feedback signal; the first control signal input end is suitable for receiving a first indication signal used for indicating whether the energy of the energy storage capacitor reaches a tripping completion energy threshold value or not; and the signal output end is suitable for being coupled with the tripping driving circuit so as to provide an output signal for the tripping driving circuit, and the signal transmission circuit is suitable for selectively transmitting the tripping signal to the signal output end to serve as the output signal based on the feedback signal and the first indication signal. The feedback circuit is coupled between the signal output end and the signal feedback end, and is suitable for generating a feedback signal based on a second indication signal and the output signal, wherein the second indication signal is used for indicating whether the energy of the energy storage capacitor reaches an energy threshold value required by tripping or not.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to the field of switching devices, and more specifically, to a switching device and its trip latching circuit. Background Technology

[0002] Trip latching circuits are used in switching equipment such as circuit breakers. When an overload or short circuit occurs in the circuit, the trip latching circuit receives and latches the trip signal, enabling the tripping mechanism to reliably execute the tripping action, thereby cutting off the circuit and preventing damage to the electrical equipment. Utility Model Content

[0003] In a first aspect of this disclosure, a trip latching circuit for a switching device is provided, comprising a signal transmission circuit and a feedback circuit. The signal transmission circuit includes: a trip signal input terminal adapted to be coupled to a trip signal input circuit to receive a trip signal from the trip signal input circuit; a signal feedback terminal adapted to receive a feedback signal; a first control signal input terminal adapted to receive a first indication signal indicating whether the energy of a storage capacitor has reached a trip completion energy threshold; and a signal output terminal adapted to be coupled to a trip drive circuit to provide an output signal to the trip drive circuit, wherein the signal transmission circuit is adapted to selectively transmit the trip signal to the signal output terminal as an output signal based on the feedback signal and the first indication signal. The feedback circuit is coupled between the signal output terminal and the signal feedback terminal and is adapted to generate a feedback signal based on a second indication signal indicating whether the energy of the storage capacitor has reached the energy threshold required for tripping and the output signal.

[0004] In some embodiments, the signal transmission circuit includes a first AND gate logic unit and a second AND gate logic unit. The first AND gate logic unit includes: a first input terminal coupled to a trip signal input terminal to receive a trip signal; a second input terminal coupled to a signal feedback terminal to receive a feedback signal; and a first output terminal adapted to output a first AND gate output signal. The second AND gate logic unit includes: a third input terminal coupled to a first output terminal to receive a first AND gate output signal; a fourth input terminal coupled to a first control signal input terminal to receive a first indication signal; and a second output terminal coupled to a signal output terminal to output a second AND gate output signal as an output signal.

[0005] In some embodiments, the feedback circuit includes a first OR gate logic unit. The first OR gate logic unit includes: a fifth input terminal coupled to a signal output terminal to receive an output signal; a sixth input terminal adapted to receive a second indication signal; and a third output terminal coupled to a signal feedback terminal to output a first OR gate output signal as a feedback signal.

[0006] In some embodiments, the feedback circuit further includes a resistor coupled between the signal output terminal and the fifth input terminal.

[0007] In some embodiments, the trip latch circuit further includes a driver coupled between the second output terminal and the signal output terminal, wherein when the enable terminal of the driver is in an active state, the second output terminal is connected to the signal output terminal.

[0008] In some embodiments, the trip latch circuit further includes: a first grounding circuit coupled to a path between the first output terminal and the third input terminal, a second grounding circuit coupled to a path between the second output terminal and the driver, and a third grounding circuit coupled to a path between the third output terminal and the second input terminal.

[0009] In a second aspect of this disclosure, a switching device is provided, characterized in that it includes a trip latch circuit according to a first aspect of this disclosure.

[0010] In some embodiments, the switching device further includes: a trip signal input circuit coupled to the trip signal input terminal of the signal transmission circuit to provide a trip signal; and a trip drive circuit coupled to the signal output terminal of the signal transmission circuit to receive an output signal.

[0011] In some embodiments, the trip signal input circuit includes a second OR gate logic unit. The second OR gate logic unit includes: a seventh input terminal adapted to receive a trip control signal from the controller; an eighth input terminal adapted to receive a timeout signal from the monitoring device; and a fourth output terminal coupled to the trip signal input terminal to output a second OR gate output signal as a trip signal.

[0012] In the trip latch circuit provided according to the embodiments of this disclosure, even if the trip signal input circuit provides a trip signal to the trip signal input terminal due to short-term interference, resulting in the output terminal outputting a trip signal, as the interference disappears, the trip signal input circuit immediately resumes outputting a low-level non-trip signal to the trip signal input terminal, and the output terminal then outputs a low-level non-trip signal instead of a trip signal. Furthermore, when the trip latch circuit outputs a trip signal due to short-term interference, as long as the trip signal input terminal receives a low-level non-trip signal, as the interference disappears, the output terminal immediately resumes outputting a low-level non-trip signal instead of a trip signal. When subjected to short-term interference, the trip drive circuit, after receiving the trip signal from the output terminal, has not yet had time to drive the trip mechanism to perform the trip action; that is, it receives a non-trip signal from the output terminal and no longer drives the trip mechanism to perform the trip action. This avoids erroneous tripping of the trip mechanism, improves the anti-interference capability of the trip circuit, and enhances the user experience.

[0013] It should be understood that the content described in this section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0015] Figure 1 A schematic circuit diagram of a tripping circuit for a switching device according to an embodiment of the present disclosure is shown, the tripping circuit employing a tripping latching circuit according to an embodiment of the present disclosure;

[0016] Figure 2 A circuit block diagram of a tripping circuit for a switching device according to another embodiment of the present disclosure is shown, the tripping circuit employing a tripping latching circuit according to another embodiment of the present disclosure; and

[0017] Figure 3 It shows Figure 2 A schematic circuit diagram of the trip latch circuit and the trip signal input circuit. Detailed Implementation

[0018] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0019] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0020] As mentioned earlier, trip latching circuits are used in switching equipment such as circuit breakers. When an overload or short circuit occurs in the circuit, the trip latching circuit receives and latches the trip signal, enabling the trip unit to reliably execute the tripping action and thus disconnect the circuit.

[0021] Figure 1A schematic circuit diagram of a tripping circuit for a switching device according to an embodiment of the present disclosure is shown. This tripping circuit incorporates a tripping latch circuit according to an embodiment of the present disclosure. Specifically, the tripping circuit includes a tripping latch circuit 100, a tripping signal input circuit 300, and a gate logic unit 71.

[0022] like Figure 1 As shown, the trip signal input circuit 300 generally includes an OR gate logic unit 36 ​​and an OR gate logic unit 35.

[0023] In some embodiments, such as Figure 1 As shown, the OR gate logic unit 36 ​​includes input terminal 361, input terminal 362, and output terminal 363. Input terminal 361 receives signals from the controller (also known as the MCU). The MCU samples the circuit current and outputs a high-level trip control signal to input terminal 361 when the current is abnormal. Input terminal 362 receives signals from an analog circuit that monitors the short-circuit current in the system. When the short-circuit current reaches a threshold, the analog circuit outputs a high-level trip control signal to input terminal 362. When either input terminal 361 or input terminal 362 receives a high-level trip control signal, output terminal 363 outputs a high-level trip control signal.

[0024] In some embodiments, such as Figure 1 As shown, the OR gate logic unit 35 includes input terminal 351, input terminal 352, and output terminal 353. Input terminal 351 is used to receive signals from a monitoring device, which monitors the operating status of the MCU. In some embodiments, an inverter 34 is coupled between the monitoring device and input terminal 351. When the MCU is working normally, the monitoring device outputs a high-level signal, which is inverted by the inverter 34 to become a low-level signal. When the MCU malfunctions, the monitoring device outputs a low-level timeout signal, which is inverted by the inverter 34 to become a high-level signal. Input terminal 352 is used to receive signals from the output terminal 363 of the OR gate logic unit 36. When either input terminal 351 or input terminal 352 receives a high-level signal, output terminal 353 outputs a high-level trip signal.

[0025] It should be noted that the implementation of the trip signal input circuit 300 is not limited to the examples above, as long as it can issue a high-level trip signal when the preset trip conditions are met.

[0026] In some embodiments, such as Figure 1As shown, the AND gate logic unit 71 includes input terminal 711, input terminal 712, and output terminal 713. Input terminal 711 is used to receive a signal from the trip signal input circuit 300. Specifically, input terminal 711 and output terminal 353 are coupled. Input terminal 712 is used to receive an indication signal indicating whether the energy of the energy storage capacitor has reached the energy threshold required for tripping. The energy storage capacitor powers the tripping mechanism, more specifically, the electromagnetic coil of the tripping mechanism. When the energy of the energy storage capacitor reaches the energy threshold required for tripping, it means that the energy storage capacitor has stored enough energy to ensure reliable tripping of the tripping mechanism, and input terminal 712 receives a high-level indication signal accordingly. Conversely, when the energy of the energy storage capacitor has not reached the energy threshold required for tripping, input terminal 712 receives a low-level indication signal. Output terminal 713 is coupled to the trip signal input terminal 107 of the trip latch circuit 100. When input terminal 712 receives a high-level indication signal, the high-level trip signal received at input terminal 711 is output from output terminal 713 and provided to the trip signal input terminal 107 of the trip latch circuit 100.

[0027] In some embodiments, such as Figure 1 As shown, the trip latch circuit 100 includes a signal transmission circuit and a feedback circuit. The signal transmission circuit includes an OR gate logic unit 15 and an AND gate logic unit 16.

[0028] In some embodiments, such as Figure 1 As shown, the OR gate logic unit 15 includes input terminal 151, input terminal 152, and output terminal 153. Input terminal 151 is used to receive feedback signals from the feedback circuit. Input terminal 152 is coupled to signal input terminal 107 to receive signals from output terminal 713. Based on the high-level feedback signal received at input terminal 151 and / or the high-level trip signal received at input terminal 152, output terminal 153 outputs a high-level trip signal.

[0029] In some embodiments, such as Figure 1As shown, the AND gate logic unit includes input terminal 161, input terminal 162, and output terminal 163. Output terminal 163 is coupled to input terminal 161. During the normal tripping process of the tripping mechanism, the energy stored in the energy storage capacitor gradually decreases due to discharge. When the energy decreases to the tripping completion energy threshold (the tripping completion energy threshold is less than the energy threshold required for tripping), it means that the tripping mechanism has reliably tripped. When the energy of the energy storage capacitor is greater than the tripping completion energy threshold, input terminal 162 receives a high-level indication signal. Conversely, when the energy of the energy storage capacitor reaches the tripping completion energy threshold, input terminal 162 receives a low-level indication signal. Based on the high-level indication signal received at input terminal 162, the high-level tripping signal received at input terminal 161 is output from output terminal 163. Output terminal 163 is adapted to be coupled to the signal output terminal 108 of the tripping latch circuit 100, and the signal output terminal 108 is used to couple to the tripping drive circuit and the feedback circuit.

[0030] In some embodiments, such as Figure 1 As shown, the feedback circuit is coupled between the signal output terminal 108 and the input terminal 151. The signal output from the signal output terminal 108 is transmitted to the input terminal 151 through the feedback circuit. The feedback circuit generates a high-level feedback signal based on the high-level trip signal output from the signal output terminal 108.

[0031] In some embodiments, such as Figure 1 As shown, the trip latch circuit 100 may also be configured with a driver 17, which is coupled between the output terminal 163 and the signal output terminal 108. The driver 17 includes an input terminal 171, an output terminal 172, and an enable terminal 173. The input terminal 171 is coupled to the output terminal 163, and the output terminal 172 is coupled to the signal output terminal 108. The enable terminal 173 controls the connection and disconnection between the input terminal 171 and the output terminal 172 according to the received power status monitoring signal. The power status monitoring signal is related to the power supply status of the monitoring device, MCU, and analog circuit. When the power supply to the monitoring device, MCU, and analog circuit is normal, the enable terminal 173 receives a high-level power status monitoring signal, the enable terminal 173 is activated, the input terminal 171 and the output terminal 172 are connected, and the output terminal 163 and the signal output terminal 108 are connected. The signal output from the output terminal 163 can be transmitted to the signal output terminal 108 through the driver 17.

[0032] When the trip drive circuit receives a high-level trip signal from the signal output terminal 108, the trip drive circuit drives the trip mechanism to perform a tripping action. In some embodiments, the trip drive circuit includes, for example, a switching device (which may be, but is not limited to, a MOS switch), an electromagnetic coil, and the aforementioned energy storage capacitor. When the trip drive circuit receives the trip signal, the MOS switch is turned on, the energy storage capacitor supplies power to the electromagnetic coil, and the magnetic field force generated by the electromagnetic coil causes the tripping mechanism to trip.

[0033] In the aforementioned tripping circuit, once the signal output terminal 108 outputs a high-level tripping signal, the tripping latch circuit 100 will maintain a high-level tripping signal output to the tripping drive circuit until the energy of the energy storage capacitor decreases to the tripping completion energy threshold. This ensures that the tripping drive circuit reliably drives the tripping mechanism to perform the tripping action. That is, before the energy of the energy storage capacitor decreases to the tripping completion energy threshold, the high-level tripping signal is latched by the tripping latch circuit 100 and is not affected by the signal output from the output terminal 713. After the energy of the energy storage capacitor decreases to the tripping completion energy threshold, the input terminal 162 receives a low-level non-tripping signal, and the output terminal 163 correspondingly outputs a low-level non-tripping signal, releasing the latching of the tripping signal. As mentioned earlier, when the energy of the energy storage capacitor decreases to the tripping completion energy threshold, the tripping mechanism has already tripped.

[0034] When a switching device with the above-mentioned trip latch circuit is subjected to a short-term interference at any position of the trip circuit, causing the trip latch circuit 100 to output a trip signal, the trip signal is latched by the trip latch circuit 100, which can easily lead to the tripping mechanism tripping erroneously.

[0035] Figure 2 A circuit block diagram of a tripping circuit for a switching device according to another embodiment of the present disclosure is shown, the tripping circuit employing a tripping latching circuit according to another embodiment of the present disclosure. Figure 3 It shows Figure 2 A schematic circuit diagram of the trip latch circuit and the trip signal input circuit. Figure 2 and Figure 3 The tripping circuit shown has good anti-interference capability, which can effectively prevent the tripping mechanism from tripping erroneously when the tripping circuit is subjected to short-term interference, thereby improving the user experience. The following section discusses... Figure 2 and Figure 3 The provided tripping circuit is explained.

[0036] The tripping circuit includes a tripping latch circuit 100, a tripping signal input circuit 300, and a tripping drive circuit 400. The tripping latch circuit 100 receives the tripping signal from the tripping signal input circuit 300 and outputs the tripping signal to the tripping drive circuit 400, causing the tripping drive circuit 400 to drive the tripping mechanism to trip.

[0037] In some embodiments, the trip signal input circuit 300 may have and Figure 1 The trip signal input circuit 300 shown has a largely the same structure. Figure 3In the illustrated embodiment, the trip signal input circuit 300 may include a second OR gate logic unit 31. The second OR gate logic unit 31 may include a seventh input terminal 311, an eighth input terminal 312, and a fourth output terminal 313. The seventh input terminal 311 is used to couple with a controller (which may be referred to as an MCU), and the eighth input terminal 312 is coupled with a monitoring device. When the MCU detects an abnormal circuit current, the MCU sends a high-level trip control signal, which is received by the seventh input terminal 311. When the MCU malfunctions, the eighth input terminal 312 receives a timeout signal from the monitoring device. This timeout signal can be converted into a high-level signal by an inverter and then provided to the eighth input terminal 312. When either the seventh input terminal 311 or the eighth input terminal 312 receives a high-level signal, the fourth output terminal 313 outputs a high-level second OR gate output signal, which serves as a high-level trip signal.

[0038] The trip latch circuit 100 includes a signal transmission circuit 10 and a feedback circuit 20. The signal transmission circuit 10 includes a trip signal input terminal 101, a signal feedback terminal 102, a first control signal input terminal 104, and a signal output terminal 103.

[0039] In some embodiments, the trip signal input terminal 101 is coupled to the trip signal input circuit 300, for example, as a signal input terminal of the trip latch circuit 100, to receive a signal from the trip signal input circuit 300. The signal can be a low-level non-trip signal or a high-level trip signal. In this embodiment, the trip signal input terminal 101 can be coupled to the fourth output terminal 313. The signal feedback terminal 102 is adapted to receive a feedback signal. The first control signal input terminal 104 is adapted to receive a first indication signal indicating whether the energy of the energy storage capacitor has reached the trip completion energy threshold. The signal output terminal 103 is coupled to the trip drive circuit 400, for example, as a signal output terminal of the trip latch circuit 100, to provide an output signal to the trip drive circuit 400. The signal transmission circuit 10 is adapted to selectively transmit the trip signal to the signal output terminal 103 as an output signal based on the feedback signal and the first indication signal.

[0040] In some embodiments, the feedback circuit 20 is coupled between the signal output terminal 103 and the signal feedback terminal 102. The feedback circuit 20 is adapted to generate a feedback signal based on a second indication signal indicating whether the energy of the energy storage capacitor has reached the energy threshold required for tripping and the aforementioned output signal, and to provide the feedback signal to the signal feedback terminal 102 of the signal transmission circuit 10.

[0041] Whether the signal transmission circuit 10 outputs a trip signal through the signal output terminal 103 depends on the signal received at the trip signal input terminal 101, the feedback signal received at the signal feedback terminal 102, and the first indication signal received at the first control signal input terminal 104. When the trip latch circuit 100 is operating normally, the feedback signal and the first indication signal do not affect the transmission of the trip signal; that is, when the trip signal input terminal 101 receives the trip signal, the signal output terminal 103 outputs the trip signal as the output signal. Conversely, when any of the signal received at the trip signal input terminal 101, the feedback signal, or the first indication signal changes, the signal output terminal 103 outputs a non-trip signal (a low-level signal) as the output signal.

[0042] For a trip circuit employing this trip latch circuit, when the trip latch circuit 100 is operating normally, if the trip signal input circuit 300 provides a trip signal to the trip signal input terminal 101 due to short-term interference, thereby causing the signal output terminal 103 to output a trip signal, as the interference disappears, the trip signal input circuit 300 immediately resumes outputting a non-trip signal to the trip signal input terminal 101, and the signal output terminal 103 then outputs a non-trip signal instead of a trip signal. Furthermore, when the trip latch circuit 100 internally experiences short-term interference causing the signal output terminal 103 to output a trip signal, as long as the trip signal input terminal 101 receives a non-trip signal, as the interference disappears, the signal output terminal 103 immediately resumes outputting a non-trip signal instead of a trip signal. When subjected to short-term interference, the trip drive circuit 400 receives a trip signal from the signal output terminal 103 but has not yet had time to drive the trip mechanism to perform the trip action. That is, it receives a non-trip signal from the signal output terminal 103 and no longer drives the trip mechanism to perform the trip action, thereby avoiding false tripping of the trip mechanism, improving the anti-interference capability of the trip circuit, and improving the user experience.

[0043] See also Figure 2 and Figure 3 An exemplary embodiment of the signal transmission circuit 10 and the feedback circuit 20 is shown. The signal transmission circuit 10 may include a first AND gate logic unit 11 and a second AND gate logic unit 12. The feedback circuit may include a first OR gate logic unit 21.

[0044] The first AND gate logic unit 11 includes a first input terminal 111, a second input terminal 112, and a first output terminal 113. The first input terminal 111 is coupled to a trip signal input terminal 101, which provides the received trip signal / non-trip signal to the first input terminal 111. In some embodiments, the first input terminal 111 serves as a signal input terminal 101. The second input terminal 112 is coupled to a signal feedback terminal 102 to receive a feedback signal. The first output terminal 113 is adapted to output a first AND gate output signal. When the first input terminal 111 receives a high-level trip signal and the second input terminal 112 receives a high-level feedback signal, the first AND gate logic unit 11 provides the high-level trip signal as the first AND gate output signal to the third input terminal 121 of the second AND gate logic unit 12.

[0045] The second AND gate logic unit 12 includes a third input terminal 121, a fourth input terminal 122, and a second output terminal 123. The third input terminal 121 is coupled to the first output terminal 113 to receive the first AND gate output signal. The fourth input terminal 122 is coupled to the first control signal input terminal 104 to receive a first indication signal. In some embodiments, the fourth input terminal 122 serves as the first control signal input terminal 104. When the energy of the energy storage capacitor is greater than the tripping completion energy threshold, the fourth input terminal 122 receives a high-level first indication signal. When the energy of the energy storage capacitor reaches the tripping completion energy threshold, the fourth input terminal 122 receives a low-level first indication signal. The second output terminal 123 is coupled to the signal output terminal 103 to output the second AND gate output signal as the output signal. In some embodiments, the second output terminal 123 serves as the signal output terminal 103. When the second AND gate logic unit 12 receives a high-level trip signal and a high-level first indication signal as the output signal of the first AND gate, the second AND gate logic unit 12 provides the high-level trip signal as the output signal of the second AND gate to the signal output terminal 103. Then, the signal output terminal 103 provides the high-level trip signal as the output signal to the trip drive circuit 400 and the feedback circuit 20.

[0046] The first OR gate logic unit 21 includes a fifth input terminal 211, a sixth input terminal 212, and a third output terminal 213. The fifth input terminal 211 is coupled to the signal output terminal 103 to receive the output signal output from the signal output terminal 103. The sixth input terminal 212 is adapted to receive a second indication signal. The third output terminal 213 is coupled to the signal feedback terminal 102 to output the first OR gate output signal as a feedback signal. When the fifth input terminal 211 receives a high-level tripping signal, and / or the sixth input terminal 212 receives a high-level second indication signal indicating that the energy of the energy storage capacitor has reached the energy threshold required for tripping, the third output terminal 213 outputs a high-level feedback signal. That is, when either the fifth input terminal 211 or the sixth input terminal 212 receives a high-level signal, the third output terminal 213 outputs a high-level feedback signal. The aforementioned energy threshold required for tripping is greater than the energy threshold required for tripping completion. When the energy of the energy storage capacitor does not reach the energy threshold required for tripping, the sixth input terminal 212 receives a low-level second indication signal indicating that the energy of the energy storage capacitor has not reached the energy threshold required for tripping. As mentioned above, for a normal tripping process, when the energy of the energy storage capacitor reaches the energy threshold required for tripping, it means that the energy storage capacitor has stored enough energy to ensure reliable tripping of the tripping mechanism. When the energy of the energy storage capacitor decreases to the tripping completion energy threshold due to discharge to the electromagnetic coil, it means that the tripping mechanism has reliably tripped.

[0047] In some embodiments, the trip latch circuit 100 may further include a driver 13 coupled between the second output terminal 123 and the signal output terminal 103. The driver 13 includes an input terminal 131, an output terminal 132, and an enable terminal 133. The input terminal 131 is coupled to the second output terminal 123, and the output terminal 132 is coupled to the signal output terminal 103. In some embodiments, the output terminal 132 serves as the signal output terminal 103. The enable terminal 133 controls the connection and disconnection between the input terminal 131 and the output terminal 132 according to the received power status monitoring signal. In some embodiments, the power status monitoring signal is related to the power supply status of the monitoring device, MCU, etc. When the power supply of the monitoring device, MCU, etc. is normal, the enable terminal 133 receives a high-level power status monitoring signal and is activated, so that the input terminal 131 and the output terminal 132 are connected, the second output terminal 123 and the signal output terminal 103 are connected, and the high-level trip signal output from the second output terminal 123 can be transmitted through the driver 13 to the signal output terminal 108 as an output signal.

[0048] In some embodiments, the feedback circuit 20 may further include a resistor 22 coupled between the signal output terminal 103 and the fifth input terminal 211.

[0049] In some embodiments, the trip latch circuit 100 may further include a first grounding circuit 18, a second grounding circuit 14, and a third grounding circuit 25. The first grounding circuit 18 is coupled to the path between the first output terminal 113 and the third input terminal 121. The second grounding circuit 14 is coupled to the path between the second output terminal 123 and the driver 13. The third grounding circuit 25 is coupled to the path between the third output terminal 213 and the second input terminal 112. By providing individual grounding circuits, uncertain voltage levels due to factors such as induction can be prevented when the pins are floating.

[0050] The following is a brief description of the configuration according to this disclosure. Figure 2 and Figure 3 The tripping process of the switching device in the tripping latch circuit 100 of the illustrated embodiment:

[0051] During the tripping initiation phase, either the MCU or the monitoring device sends a high-level signal to the second OR gate logic unit 31. Correspondingly, the fourth output terminal 313 provides a high-level tripping signal to the first input terminal 111 via the tripping signal input terminal 101. At this time, the energy of the energy storage capacitor reaches the energy threshold required for tripping, and the sixth input terminal 212 receives a high-level second indication signal. Therefore, the third output terminal 213 provides a high-level feedback signal to the second input terminal 112. Subsequently, the first output terminal 113 provides the high-level tripping signal as the first AND gate output signal to the third input terminal 121. At this time, the energy of the energy storage capacitor is greater than the tripping completion energy threshold, and the fourth input terminal 122 receives a high-level first indication signal via the first control signal input terminal 104. The second output terminal 123 then outputs the high-level tripping signal as the second AND gate output signal. The high-level trip signal output from the second output terminal 123 is provided to the signal output terminal 103 through the driver 13. The high-level trip signal is then provided as the output signal of the signal output terminal 103 to the trip drive circuit 400 and the feedback circuit 20.

[0052] During the intermediate stage of tripping, the energy of the storage capacitor is less than the energy threshold required for tripping but greater than the energy threshold for tripping completion. Although the sixth input terminal 212 receives a low-level second indication signal, the fifth input terminal 211 still receives a high-level tripping signal, and the third output terminal 213 maintains a high-level feedback signal. During the tripping process, the fourth output terminal 313 continuously provides a high-level tripping signal to the first input terminal 111, and correspondingly, the signal output terminal 103 maintains a high-level tripping signal.

[0053] At the end of the tripping phase, after the energy of the energy storage capacitor reaches the tripping completion energy threshold due to discharge, the fourth input terminal 122 receives a low-level first indication signal, and the second output terminal 123 outputs a second AND gate output signal as a low-level non-tripping signal. Correspondingly, the signal output terminal 103 outputs a low-level non-tripping signal as the output signal, and the tripping latch mechanism 100 no longer sends a high-level tripping signal to the tripping drive circuit 400. At this point, the tripping mechanism has completed the tripping process.

[0054] When the trip signal input circuit 300 outputs a high-level trip signal to the trip signal input terminal 101 due to a short-term interference, which in turn causes the signal output terminal 103 to output a high-level trip signal, as the interference disappears, the trip signal input circuit 300 immediately resumes outputting a low-level non-trip signal to the trip signal input terminal 101, and the signal output terminal 103 subsequently outputs a low-level non-trip signal instead of a trip signal. When subjected to short-term interference, the trip drive circuit 400, upon receiving the trip signal, has not yet had time to drive the trip mechanism to perform the tripping action; that is, it receives a low-level non-trip signal and no longer drives the trip mechanism to perform the tripping action, thus avoiding accidental tripping of the trip mechanism.

[0055] When the trip latch circuit 100 experiences a short-term interference, causing the signal output terminal 103 to output a high-level trip signal, as long as the trip signal input terminal 101 receives a low-level non-trip signal, the signal output terminal 103 immediately resumes outputting a low-level non-trip signal and ceases outputting a trip signal as the interference disappears. During short-term interference, the trip drive circuit 400, upon receiving the trip signal, has not yet had time to drive the trip mechanism to perform the tripping action; that is, it receives a non-trip signal and ceases driving the trip mechanism to perform the tripping action, thus preventing erroneous tripping of the trip mechanism.

[0056] According to embodiments of this disclosure, a switching device is also provided, the tripping circuit of which includes the tripping latch circuit 100 described above, thereby improving the anti-interference capability of the tripping circuit and thus enhancing the user experience.

[0057] In some embodiments, the tripping circuit of the switching device may further include the tripping signal input circuit 300 and the tripping drive circuit 400 described above. For detailed descriptions of the signal input circuit 300 and the drive circuit 400, please refer to the description above, which will not be repeated here.

[0058] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A trip latch circuit (100) for switching equipment, characterized in that, include: Signal transmission circuit (10), including: The trip signal input terminal (101) is adapted to be coupled to the trip signal input circuit (300) to receive a trip signal from the trip signal input circuit (300); The signal feedback terminal (102) is adapted to receive feedback signals; The first control signal input terminal (104) is adapted to receive a first indication signal used to indicate whether the energy of the energy storage capacitor has reached the tripping completion energy threshold; and A signal output terminal (103) is adapted to be coupled to a trip drive circuit (400) to provide an output signal to the trip drive circuit (400), wherein the signal transmission circuit (10) is adapted to selectively transmit the trip signal to the signal output terminal (103) as the output signal based on the feedback signal and the first indication signal; and A feedback circuit (20) is coupled between the signal output terminal (103) and the signal feedback terminal (102), and is adapted to generate the feedback signal based on a second indication signal for indicating whether the energy of the energy storage capacitor has reached the energy threshold required for tripping and the output signal.

2. The trip latch circuit (100) according to claim 1, characterized in that, The signal transmission circuit (10) includes: The first AND gate logic unit (11) includes: The first input terminal (111) is coupled to the trip signal input terminal (101) to receive the trip signal; The second input terminal (112) is coupled to the signal feedback terminal (102) to receive the feedback signal; and The first output terminal (113) is adapted to output the first AND gate output signal; and the second AND gate logic unit (12) includes: The third input terminal (121) is coupled to the first output terminal (113) to receive the output signal of the first AND gate; The fourth input terminal (122) is coupled to the first control signal input terminal (104) to receive the first indication signal; and The second output terminal (123) is coupled to the signal output terminal (103) to output the second AND gate output signal as the output signal.

3. The trip latch circuit (100) according to claim 2, characterized in that, The feedback circuit (20) includes a first OR gate logic unit (21), which includes: The fifth input terminal (211) is coupled to the signal output terminal (103) to receive the output signal; The sixth input terminal (212) is adapted to receive the second indication signal; and The third output terminal (213) is coupled to the signal feedback terminal (102) to output the first OR gate output signal as the feedback signal.

4. The trip latch circuit (100) according to claim 3, characterized in that, The feedback circuit (20) also includes a resistor (22) coupled between the signal output terminal (103) and the fifth input terminal (211).

5. The trip latch circuit (100) according to claim 3, characterized in that, The trip latch circuit (100) further includes a driver (13) coupled between the second output terminal (123) and the signal output terminal (103). When the enable terminal of the driver (13) is in an active state, the second output terminal (123) is connected to the signal output terminal (103).

6. The trip latch circuit (100) according to claim 5, characterized in that, The trip latch circuit (100) also includes: A first grounding circuit (18) coupled to the path between the first output terminal (113) and the third input terminal (121), A second grounding circuit (14) coupled to the path between the second output terminal (123) and the driver (13), and A third grounding circuit (25) coupled to the path between the third output terminal (213) and the second input terminal (112).

7. A switching device, characterized in that, Includes a trip latch circuit (100) according to any one of claims 1 to 6.

8. The switching device according to claim 7, characterized in that, Also includes: A trip signal input circuit (300) is coupled to the trip signal input terminal (101) of the signal transmission circuit (10) to provide the trip signal; as well as The trip drive circuit (400) is coupled to the signal output terminal (103) of the signal transmission circuit (10) to receive the output signal.

9. The switching device according to claim 8, characterized in that, The trip signal input circuit (300) includes a second OR gate logic unit (31), which includes: The seventh input terminal (311) is adapted to receive the trip control signal issued by the controller; The eighth input terminal (312) is adapted to receive a timeout signal from the monitoring device; and The fourth output terminal (313) is coupled to the trip signal input terminal (101) to output a second OR gate output signal as the trip signal.

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