Device manufacturing method and device

Abstract

To provide a method of manufacturing a device capable of suppressing deterioration of characteristics.SOLUTION: A method of manufacturing a device includes forming a conductive film using a non-superconducting material on a second surface of a substrate having a first surface and the second surface opposite to the first surface, forming a through hole penetrating the substrate by etching the substrate from the first surface after forming the conductive film, forming a through electrode using a superconducting material in the through hole by an electrolytic plating method using the conductive film exposed in the through hole as a seed layer, and removing the conductive film after forming the through electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a device manufacturing method and a device. [Background technology]

[0002] There is known a device having a through electrode that penetrates between the first and second surfaces of a substrate to conduct circuits provided on the first and second surfaces. It is known that such through electrodes are formed by injection molding (see, for example, Patent Document 1). It is also known that through electrodes are formed by electrolytic plating (see, for example, Patent Documents 2-4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0005887 [Patent Document 2] International Publication No. 2023 / 085366 [Patent Document 3] Special Publication No. 2020-522128 [Patent Document 4] US Patent Application Publication No. 2022 / 0359415 Summary of the Invention [Problem to be solved by the invention]

[0004] When forming a through electrode made of a superconducting material by electroplating, a conductive film made of a non-superconducting material may be used as the seed layer. In this case, a portion of the through electrode is made of the non-superconducting material, which may increase the electrical resistance of the through electrode even at low temperatures and cause deterioration of its characteristics.

[0005] One aspect of the present invention aims to suppress deterioration of characteristics. [Means for solving the problem]

[0006] In one aspect, a method for manufacturing a device includes the steps of: forming a conductive film using a non-superconducting material on a second surface of a substrate having a first surface and a second surface opposite the first surface; after forming the conductive film, etching the substrate from the first surface to form a through hole that penetrates the substrate; forming a through electrode in the through hole using a superconducting material by an electrolytic plating method using the conductive film exposed in the through hole as a seed layer; and after forming the through electrode, removing the conductive film.

[0007] In one embodiment, the device comprises a substrate having a first surface and a second surface opposite the first surface, a through electrode formed of a superconducting material and extending through the substrate from the first surface to the second surface, and wiring provided on the second surface and connected to the through electrode and formed of a superconducting material different from the through electrode, wherein the through electrode protrudes from the second surface and the wiring is in contact with at least a side surface of the through electrode. [Effects of the Invention]

[0008] One aspect is that deterioration of characteristics can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a device according to a first embodiment. [Figure 2] 2(a) to 2(c) are cross-sectional views (part 1) illustrating a method for manufacturing a device according to the first embodiment. [Figure 3] 3(a) to 3(c) are cross-sectional views (part 2) illustrating the method for manufacturing the device according to the first embodiment. [Figure 4] 4(a) and 4(b) are cross-sectional views (part 3) illustrating the method for manufacturing the device according to the first embodiment. [Figure 5] 5(a) to 5(c) are cross-sectional views (part 1) showing a method for manufacturing a device according to a comparative example. [Figure 6]6(a) to 6(c) are cross-sectional views (part 2) showing a method for manufacturing a device according to a comparative example. [Figure 7] FIG. 7(a) is a cross-sectional view of a device according to Example 2, and FIG. 7(b) is a plan view of the vicinity of a through electrode in Example 2 as viewed from the -Z direction. [Figure 8] 8(a) to 8(c) are cross-sectional views (part 1) showing a method for manufacturing a device according to the second embodiment. [Figure 9] 9(a) to 9(c) are cross-sectional views (part 2) showing a method for manufacturing a device according to the second embodiment. [Figure 10] FIG. 10(a) is a cross-sectional view of a device according to Example 3, and FIG. 10(b) is a plan view of the vicinity of a through electrode in Example 3 as viewed from the -Z direction. [Figure 11] 11(a) to 11(c) are cross-sectional views showing a method for manufacturing a device according to the third embodiment. [Figure 12] FIG. 12 is a cross-sectional view of the device according to the fourth embodiment. [Figure 13] 13(a) and 13(b) are cross-sectional views showing a method for manufacturing a device according to the fourth embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a device according to a modification of the fourth embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a device according to Example 5. [Figure 16] FIG. 16 is a cross-sectional view of a device according to a modification of the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Examples of interposers will be described in Examples 1 to 3. Examples of quantum bit devices will be described in Examples 4 and 5. [Example]

[0011] FIG. 1 is a cross-sectional view of a device 100 according to a first embodiment. Directions parallel to an upper surface 11 of a substrate 10 and perpendicular to each other are defined as the X-axis direction and the Y-axis direction. The thickness direction of the substrate 10 is defined as the Z-axis direction. As shown in FIG. 1, the substrate 10 has an upper surface 11 and a lower surface 12, and a through-hole 13 is provided therein, penetrating from the upper surface 11 to the lower surface 12. The substrate 10 is, for example, a silicon (Si) substrate. The thickness of the substrate 10 is, for example, 300 μm to 500 μm. The diameter of the through-hole 13 is, for example, 50 μm to 100 μm.

[0012] An insulating film 14 is provided on the upper surface 11 of the substrate 10. An insulating film 15 is provided on the lower surface 12 of the substrate 10. A through electrode 30 is provided in the through hole 13. The through electrode 30 is provided so as to completely fill the through hole 13. An upper surface 31 of the through electrode 30 is substantially flush with an upper surface of the insulating film 14. A lower surface 32 of the through electrode 30 is substantially flush with a lower surface of the insulating film 15. The insulating films 14 and 15 are, for example, silicon oxide (SiO2) films. The insulating films 14 and 15 have thicknesses of, for example, 50 nm to 100 nm. The through electrode 30 is made of a superconducting material that exhibits superconductivity at a temperature below a predetermined temperature (for example, below 10 K). The through electrode 30 is made of, for example, tin (Sn).

[0013] An insulating film 17 is provided on the insulating film 14 and the through electrode 30. A wiring 40 is provided on the insulating film 17. The wiring 40 is connected to the through electrode 30 by a via wiring 41 that penetrates the insulating film 17. An insulating film 19 is provided on the insulating film 17 to cover the wiring 40. A terminal electrode 45 is provided on the insulating film 19. The terminal electrode 45 is connected to the wiring 40 by a via wiring 43 that penetrates the insulating film 19. The insulating films 17 and 19 are, for example, silicon oxide (SiO2) films. The insulating films 17 and 19 have thicknesses of, for example, 100 nm to 300 nm. The wiring 40, via wiring 41, via wiring 43, and terminal electrode 45 are made of a superconducting material. The wiring 40, via wiring 41, via wiring 43, and terminal electrode 45 are, for example, made of titanium nitride (TiN). The wiring 40 and terminal electrode 45 have thicknesses of, for example, 50 nm to 150 nm.

[0014] Wiring 42 is provided on the insulating film 15 and the through electrode 30. At least a portion of the wiring 42 is in contact with the lower surface 32 of the through electrode 30, thereby connecting to the through electrode 30. An insulating film 18 is provided on the insulating film 15, covering the wiring 42. A terminal electrode 46 is provided on the insulating film 18. The terminal electrode 46 is connected to the wiring 42 by a via wiring 44 that penetrates the insulating film 18. A bump electrode 47 is provided on the terminal electrode 46. The insulating film 18 is, for example, a silicon oxide (SiO2) film. The thickness of the insulating film 18 is, for example, 100 nm to 300 nm. The wiring 42, the via wiring 44, and the terminal electrode 46 are made of a superconducting material. The wiring 42, the via wiring 44, and the terminal electrode 46 are made of, for example, titanium nitride (TiN). The thickness of the wiring 42 and the terminal electrode 46 is, for example, 50 nm to 150 nm. The bump electrode 47 is made of a superconducting material. The bump electrode 47 is made of, for example, indium (In).

[0015] The substrate 10 is not limited to a silicon substrate, but may be a glass substrate, a quartz substrate, a sapphire substrate, an alumina substrate, a silicon carbide substrate, or the like. If the substrate 10 is formed of an insulating inorganic material, the insulating films 14 and 15 may not be provided. The through electrode 30 may be formed of a superconducting material other than tin (Sn), such as zinc (Zn), cadmium (Cd), lead (Pb), indium (In), or ruthenium (Ru). The insulating films 14, 15, 17, 18, and 19 are not limited to silicon oxide films, but may be silicon nitride films, aluminum oxide films, aluminum nitride films, or the like. The wiring 40, the via wiring 41, the wiring 42, the via wiring 43, the via wiring 44, the terminal electrode 45, and the terminal electrode 46 may be formed of a superconducting material other than titanium nitride (TiN). For example, it may be formed of aluminum (Al), vanadium (V), niobium (Nb), tantalum (Ta), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN).

[0016] [Manufacturing method] 2(a) to 4(b) are cross-sectional views showing a manufacturing method of the device 100 according to the first embodiment. As shown in FIG. 2(a), a substrate 10, which is a silicon substrate having a thickness of, for example, 300 μm to 400 μm, is heated in an oxygen atmosphere to form insulating films 14 and 15, which are silicon oxide films, on an upper surface 11 and a lower surface 12. The insulating films 14 and 15 have a thickness of, for example, 100 nm. Thereafter, a metal mask layer 60 is formed on the insulating film 14. The metal mask layer 60 is, for example, an aluminum (Al) layer and is formed by sputtering. The metal mask layer 60 has a thickness of, for example, 500 nm. A conductive film 61 is formed on the insulating film 15. The conductive film 61 is, for example, a copper (Cu) film. The conductive film 61 is formed by forming a Cu film having a thickness of about 100 nm by sputtering, and then forming a Cu film having a thickness of about 1 μm to 2 μm by electroplating. An adhesive layer such as a titanium (Ti) layer may be formed between the insulating film 15 and the conductive film 61. The thickness of the adhesive layer may be 20 nm, for example. Either the metal mask layer 60 or the conductive film 61 may be formed first.

[0017] As shown in FIG. 2(b), the metal mask layer 60 and the insulating film 14 are etched using a resist mask layer (not shown) formed on the metal mask layer 60 as a mask, thereby forming openings 62 in the metal mask layer 60 and the insulating film 14. The metal mask layer 60 and the insulating film 14 are etched, for example, by reactive ion etching (RIE). Next, the substrate 10 is etched using the metal mask layer 60 as a mask, thereby forming through-holes 13 that penetrate from the upper surface 11 to the lower surface 12. The through-holes 13 are formed, for example, by deep reactive ion etching (Deep-RIE) using the Bosch process. The diameter of the through-holes 13 is, for example, 50 μm to 100 μm. Next, the insulating film 15 exposed at the bottom of the through-holes 13 is removed, for example, by reactive ion etching. This exposes the conductive film 61 in the through-holes 13.

[0018] 2(c), the metal mask layer 60 is removed by, for example, wet etching. Thereafter, a superconducting film is embedded in the through-hole 13 by electrolytic plating using the conductive film 61 as a seed layer, to form the through electrode 30 made of the superconducting film. For example, the through electrode 30 is made of tin (Sn). The upper surface 31 of the through electrode 30 is made to be substantially flush with the upper surface of the insulating film 14.

[0019] The reason why Cu, a non-superconducting material, is used for the conductive film 61 that will serve as the seed layer is as follows. First, Cu, a non-superconducting material, has high electrical conductivity. Second, Cu, a non-superconducting material, has a low tendency to ionize, and is therefore less likely to be dissolved in a plating solution. Third, Cu, a non-superconducting material, can be formed into a film using a plating method, making it easy to form a thick film. Fourth, Cu, a non-superconducting material, can be easily removed by wet etching or chemical mechanical polishing (CMP). For these reasons, Cu, a non-superconducting material, is used for the conductive film 61 that will serve as the seed layer.

[0020] As shown in FIG. 3(a), an insulating film 17 is formed on the insulating film 14 so as to cover the upper surface 31 of the through electrode 30. The insulating film 17 is formed, for example, by chemical vapor deposition (CVD). The insulating film 17 is, for example, a silicon oxide film, and has a thickness of, for example, 200 nm. Thereafter, the conductive film 61 is removed by wet etching or CMP. As a result, the lower surface 32 of the through electrode 30 and the lower surface of the insulating film 15 become substantially flush with each other. The insulating film 17 is provided to protect the through electrode 30 during the process of removing the conductive film 61.

[0021] As shown in FIG. 3(b), a superconducting film is formed on the insulating film 15 by, for example, sputtering, and then the superconducting film is patterned by, for example, reactive ion etching, to form wiring 42 on the insulating film 15. At least a portion of the wiring 42 is in contact with the lower surface 32 of the through electrode 30, thereby connecting to the through electrode 30. The wiring 42 is made of, for example, titanium nitride (TiN). The thickness of the wiring 42 is, for example, 100 nm. In this way, the through electrode 30 and the wiring 42 are made of different superconducting materials.

[0022] As shown in FIG. 3(c), an insulating film 18 is formed on the insulating film 15 so as to cover the wiring 42. The insulating film 18 is formed, for example, by a CVD method. The insulating film 18 is, for example, a silicon oxide film, and has a thickness of 200 nm, for example. A through hole 48 is formed in the insulating film 17, for example, by a reactive ion etching method, reaching the through electrode 30. A via wiring 41 connecting to the through electrode 30 is formed in the through hole 48. A wiring 40 is formed on the insulating film 17. The via wiring 41 and the wiring 40 are formed, for example, by a sputtering method and an etching method. The via wiring 41 and the wiring 40 are formed of, for example, titanium nitride (TiN). The thickness of the wiring 40 is, for example, 100 nm.

[0023] As shown in FIG. 4(a), an insulating film 19 is formed on the insulating film 17 so as to cover the wiring 40. The insulating film 19 is formed, for example, by a CVD method. The insulating film 19 is, for example, a silicon oxide film, and has a thickness of, for example, 200 nm. Next, a through hole 49 is formed in the insulating film 19, for example, by a reactive ion etching method, so as to reach the wiring 40. A via wiring 43 connected to the wiring 40 is formed in the through hole 49. A terminal electrode 45 connected to the via wiring 43 is formed on the insulating film 19. The via wiring 43 and the terminal electrode 45 are formed, for example, by a sputtering method and an etching method. The via wiring 43 and the terminal electrode 45 are formed, for example, from titanium nitride (TiN).

[0024] As shown in FIG. 4(b), a through hole 50 reaching the wiring 42 is formed in the insulating film 18 using, for example, reactive ion etching. A via wiring 44 connecting to the wiring 42 is formed in the through hole 50. A terminal electrode 46 connecting to the via wiring 44 is formed on the insulating film 18. The via wiring 44 and the terminal electrode 46 are formed using, for example, sputtering and etching. The via wiring 44 and the terminal electrode 46 are formed from, for example, titanium nitride (TiN). Then, a bump electrode 47 is formed on the terminal electrode 46. The bump electrode 47 is formed from, for example, indium (In). In this way, the device 100 according to Example 1 is formed.

[0025] [Comparative Example] 5(a) to 6(c) are cross-sectional views showing a method for manufacturing a device according to a comparative example. As shown in FIG. 5(a), insulating films 14 and 15 are formed on an upper surface 11 and a lower surface 12 of a silicon substrate 10 by heating the substrate 10 in an oxygen atmosphere. Then, a conductive film 90 and a metal mask layer 91 are formed on the insulating film 15. The conductive film 90 is, for example, a gold (Au) film. The metal mask layer 91 is, for example, an aluminum (Al) layer. The conductive film 90 and the metal mask layer 91 are formed by, for example, sputtering or vacuum deposition.

[0026] 5(b), a resist mask layer (not shown) formed on the metal mask layer 91 is used as a mask to etch the metal mask layer 91, the conductive film 90, and the insulating film 15 to form an opening 92. Next, the substrate 10 is etched using the metal mask layer 91 as a mask to form a through hole 13 that penetrates from the lower surface 12 to the upper surface 11. Next, the insulating film 14 exposed at the bottom of the through hole 13 is removed by etching.

[0027] As shown in FIG. 5(c), the metal mask layer 91 is removed by, for example, wet etching.

[0028] 6(a), a non-superconducting film 93 is formed on a conductive film 90 by electrolytic plating. The non-superconducting film 93 is made of, for example, copper (Cu). Since a through-hole 13 is formed in the substrate 10, the non-superconducting film 93 may enter the through-hole 13.

[0029] 6(b), a superconducting film 94 is embedded in the through-hole 13 by electrolytic plating using the non-superconducting film 93 as a seed layer. The superconducting film 94 is made of, for example, tin (Sn).

[0030] 6(c), after forming an insulating film 17 on the insulating film 14 so as to cover the upper surface of the superconducting film 94, the non-superconducting film 93 and the conductive film 90 formed on the insulating film 14 are removed by, for example, CMP. As a result, a through electrode 95 including the non-superconducting film 93 and the superconducting film 94 is formed in the through hole 13. Thereafter, the same steps as those described with reference to FIGS. 3(b) to 4(b) are performed.

[0031] In the comparative example, as shown in Figures 5(b) to 6(a), after forming a through hole 13 in the substrate 10, a non-superconducting film 93 is formed on the lower surface 12 of the substrate 10. For this reason, a part of the non-superconducting film 93 may enter the through hole 13. Therefore, as shown in Figures 6(b) and 6(c), when a superconducting film 94 is formed in the through hole 13 by electrolytic plating using the non-superconducting film 93 as a seed layer, a through electrode 95 including the non-superconducting film 93 and the superconducting film 94 may be formed.

[0032] Non-superconducting film 93 does not exhibit superconductivity at extremely low temperatures (for example, 10 K or less). Therefore, if non-superconducting film 93 is included in through electrode 95, the electrical resistance of through electrode 95 increases even at extremely low temperatures, which may deteriorate the characteristics of the device.

[0033] On the other hand, according to Example 1, as shown in FIG. 2(a), a conductive film 61 is formed on the lower surface 12 (second surface) of the substrate 10 using a non-superconducting material (e.g., Cu). After the conductive film 61 is formed, the substrate 10 is etched from its upper surface 11 (first surface) to form a through-hole 13 penetrating from the upper surface 11 to the lower surface 12, as shown in FIG. 2(b). As shown in FIG. 2(c), a through electrode 30 is formed in the through-hole 13 using a superconducting material (e.g., Sn) by electroplating using the conductive film 61 exposed in the through-hole 13 as a seed layer. As shown in FIG. 3(a), after the through electrode 30 is formed, the conductive film 61 is removed. This prevents the through electrode 30 from containing a non-superconducting material. This prevents the electrical resistance of the through electrode 30 from increasing at cryogenic temperatures, thereby suppressing deterioration of the device characteristics.

[0034] 3(a), before removing the conductive film 61, an insulating film 17 that covers the through electrode 30 is formed on the upper surface 11 of the substrate 10. This makes it possible to prevent damage to the through electrode 30 when removing the conductive film 61.

[0035] In addition, in Example 1, as shown in Fig. 3(b), wiring 42 connected to the through electrode 30 is formed on the lower surface 12 of the substrate 10 using a superconducting material. As shown in Fig. 3(c), wiring 40 connected to the through electrode 30 is formed on the upper surface 11 of the substrate 10 using a superconducting material. Since the inclusion of non-superconducting material in the through electrode 30 is suppressed, an increase in electrical resistance between the wiring 40 and the wiring 42 at cryogenic temperatures is suppressed.

[0036] In Example 1, the conductive film 61 used as a seed layer is formed to contain copper (Cu), which is a non-superconducting material. This results in a conductive film 61 with high electrical conductivity and low ionization tendency. That is, the conductive film 61 has low electrical resistance and is not easily dissolved in a plating solution, making it suitable for use as a seed layer in an electrolytic plating method. Furthermore, the conductive film 61 can be formed by a plating method and can be removed by a wet etching method or a CMP method, making it easy to form and remove the conductive film 61. From this perspective, the conductive film 61 may be formed to contain gold (Au) or silver (Ag), which are non-superconducting materials, in addition to copper (Cu).

[0037] Although the first embodiment has been described with reference to an example in which the through electrode 30 contains tin (Sn), the through electrode 30 may contain other superconducting materials as long as they can be deposited by electrolytic plating. For example, the through electrode 30 may contain tin (Sn), zinc (Zn), cadmium (Cd), lead (Pb), indium (In), or ruthenium (Ru). [Example]

[0038] FIG. 7(a) is a cross-sectional view of a device 200 according to Example 2. FIG. 7(b) is a plan view of the vicinity of a through electrode 30 in Example 2 as viewed from the -Z direction. As shown in FIG. 7(a), in Example 2, an insulating film 16 is provided on the sidewall surface of a through hole 13. The insulating film 16 is, for example, a silicon oxide (SiO2) film having a thickness of 50 nm to 100 nm. The through electrode 30 protrudes in the -Z direction from the lower surface of the insulating film 15. That is, the lower surface 32 of the through electrode 30 is located further in the -Z direction than the lower surface of the insulating film 15 and the upper surface 51 of the wiring 42. The lower surface 32 of the through electrode 30 is flush with the lower surface 52 of the wiring 42. The wiring 42 connected to the through electrode 30 is in contact with the side surface 33 of the through electrode 30. The other configurations are the same as those in Example 1, and therefore will not be described.

[0039] As shown in FIG. 7( b), the lower surface 32 of the through electrode 30 has a circular planar shape. Although not shown, the upper surface 31 of the through electrode 30 also has a circular planar shape. The wiring 42 does not cover the lower surface 32 of the through electrode 30, but is in contact with the side surface 33 of the through electrode 30. The wiring 42 has a planar shape, such as a hexagonal shape, around the through electrode 30. The upper surface 31 and the lower surface 32 of the through electrode 30 are not limited to being circular, and may have other planar shapes such as an elliptical shape. The shape of the wiring 42 around the through electrode 30 may be a planar shape such as a polygonal shape, a circle, or an elliptical shape.

[0040] [Manufacturing method] 8(a) to 9(c) are cross-sectional views showing a manufacturing method of a device 200 according to Example 2. As shown in FIG. 8(a), a substrate 10, for example a silicon substrate, is heated in an oxygen atmosphere to form insulating films 14 and 15 on an upper surface 11 and a lower surface 12. Next, a metal mask layer 60 is formed on the insulating film 14. A superconducting film 63 and a conductive film 61 are formed in this order on the insulating film 15. The superconducting film 63 is, for example, a titanium nitride (TiN) film, and is formed by sputtering. The thickness of the superconducting film 63 is, for example, 100 nm.

[0041] 8(b), the metal mask layer 60 and the insulating film 14 are etched using a resist mask layer (not shown) formed on the metal mask layer 60 as a mask, thereby forming an opening 62 in the metal mask layer 60 and the insulating film 14. Next, the substrate 10 is etched using the metal mask layer 60 as a mask, thereby forming a through hole 13 that penetrates from the upper surface 11 to the lower surface 12. The insulating film 15 located at the bottom of the through hole 13 is removed using, for example, reactive ion etching.

[0042] 8(c), the substrate 10 is heated in an oxygen atmosphere to form an insulating film 16 on the sidewall surface of the through-hole 13. Next, the superconducting film 63 located on the bottom surface of the through-hole 13 is removed by, for example, reactive ion etching. As a result, the conductive film 61 is exposed in the through-hole 13.

[0043] As shown in FIG. 9(a), after removing the metal mask layer 60, a superconducting film is embedded in the through-hole 13 by electrolytic plating using the conductive film 61 as a seed layer, thereby forming the through electrode 30 made of the superconducting film.

[0044] As shown in FIG. 9( b), an insulating film 17 is formed on the insulating film 14 so as to cover the upper surface 31 of the through electrode 30. Next, the conductive film 61 is removed by wet etching or CMP. When the superconducting film 63 is a TiN film, the superconducting film 63 is less soluble in the etching solution for the conductive film 61, which is a Cu film, and is harder than the conductive film 61. Therefore, when the conductive film 61 is removed by wet etching or CMP, the superconducting film 63 can be used as a stopper layer. The lower surface 32 of the through electrode 30 and the lower surface of the superconducting film 63 are flush with each other. From the viewpoint of having the superconducting film 63 function as a stopper layer when the conductive film 61 is removed, it is preferable that the superconducting film 63 be made of a superconducting material that is less soluble in the etching solution and is hard. For example, the superconducting film 63 is preferably formed of titanium nitride (TiN), vanadium (V), niobium (Nb), tantalum (Ta), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN).

[0045] As shown in FIG. 9(c), the superconducting film 63 is patterned by, for example, reactive ion etching to form wiring 42 on the insulating film 15. The wiring 42 is made of a superconducting material different from that of the through electrode 30. At least a portion of the wiring 42 is in contact with the side surface 33 of the through electrode 30, thereby connecting to the through electrode 30. The lower surface 32 of the through electrode 30 is located farther from the substrate 10 than the upper surface 51 of the wiring 42, and is flush with the lower surface 52 of the wiring 42. Thereafter, steps similar to those described in FIGS. 3(c) to 4(b) of Example 1 are carried out. As a result, the device 200 according to Example 2 is formed.

[0046] According to the second embodiment, as shown in FIG. 8(a), before forming the conductive film 61, a superconducting film 63 (first superconducting film) is formed on the lower surface 12 of the substrate 10. The conductive film 61 is formed on the superconducting film 63. As a result, as explained in FIG. 9(b), the superconducting film 63 can be used as a stopper layer when removing the conductive film 61. This improves ease of manufacture. From the viewpoint of using the superconducting film 63 as a stopper layer, the superconducting film 63 is preferably formed to contain TiN, V, Nb, Ta, VN, NbN, or TaN.

[0047] 9(b) and 9(c), after removing the conductive film 61, the superconducting film 63 (first superconducting film) is patterned to form the wiring 42 connected to the through electrode 30. This allows the wiring 42 to be formed using the superconducting film 63, which can be used as a stopper layer when removing the conductive film 61, thereby improving ease of manufacturing. In this case, as shown in FIG. 7(a), the through electrode 30 protrudes in the −Z direction from the lower surface 12 (second surface) of the substrate 10. The wiring 42, which is made of a superconducting material different from that of the through electrode 30, contacts the side surface 33 of the through electrode 30. Furthermore, the lower surface 32 of the through electrode 30 (the tip surface protruding from the lower surface 12 of the substrate 10) is flush with the lower surface 52 of the wiring 42 (the surface opposite to the lower surface 12 of the substrate 10). [Example]

[0048] FIG. 10(a) is a cross-sectional view of a device 300 according to Example 3. FIG. 10(b) is a plan view of the vicinity of a through electrode 30 in Example 3 as viewed from the -Z direction. As shown in FIG. 10(a), in Example 3, an insulating film 16 is provided on the sidewall surface of a through hole 13. Wiring 53 is provided on the insulating film 15. The wiring 53 is made of a superconducting material. The wiring 53 is made of, for example, titanium nitride (TiN), vanadium (V), niobium (Nb), tantalum (Ta), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN). The thickness of the wiring 53 is, for example, 100 nm to 300 nm. At least a portion of the wiring 53 contacts the side surface 33 and the lower surface 32 of the through electrode 30 that protrude in the -Z direction beyond the lower surface of the insulating film 15, thereby covering the through electrode 30. The wiring 53 includes a first layer 54 and a second layer 55, and is connected to the through electrode 30 by the first layer 54 contacting the side surface 33 of the through electrode 30 and the second layer 55 contacting the lower surface 32 of the through electrode 30. Therefore, the lower surface 32 of the through electrode 30 is located in the -Z direction with respect to the lower surface of the insulating film 15 and the upper surface 56 of the wiring 53. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0049] 10(b), in Example 3, as in Example 2, the lower surface 32 of the through electrode 30 has a circular planar shape, and the wiring 53 has a planar shape, such as a hexagonal shape, around the through electrode 30. Note that the lower surface 32 of the through electrode 30 may have another planar shape, such as an elliptical shape. The wiring 53 may have another planar shape, such as a polygonal shape, a circular shape, or an elliptical shape.

[0050] [Manufacturing method] 11(a) to 11(c) are cross-sectional views showing a method for manufacturing a device 300 according to Example 3. As shown in Fig. 11(a), first, the steps described in Fig. 8(a) to Fig. 9(b) of Example 2 are carried out.

[0051] 11(b), a superconducting film 64 is formed on the superconducting film 63 to cover the through electrode 30. The superconducting film 64 is, for example, a titanium nitride (TiN) film, and is formed by sputtering. The thickness of the superconducting film 64 is, for example, 100 nm.

[0052] As shown in FIG. 11( c), the superconducting films 63 and 64 are patterned by, for example, reactive ion etching, to form wiring 53 including a first layer 54 and a second layer 55 on the insulating film 15. The wiring 53 is made of a different superconducting material from that of the through electrode 30. At least a portion of the wiring 53 is formed to cover the through electrode 30 protruding from the lower surface 12 of the substrate 10. That is, the wiring 53 is connected to the through electrode 30 by having the first layer 54 contact the side surface 33 of the through electrode 30 and the second layer 55 contact the lower surface 32 of the through electrode 30. The lower surface 32 of the through electrode 30 is located farther from the lower surface 12 of the substrate 10 than the upper surface 56 of the wiring 53. Thereafter, steps similar to those described with reference to FIGS. 3( c) to 4(b) of Example 1 are performed. As a result, a device 300 according to Example 3 is formed.

[0053] According to the third embodiment, as shown in FIG. 11(a), before forming the conductive film 61, a superconducting film 63 (first superconducting film) is formed on the lower surface 12 of the substrate 10 (see also FIG. 8(a) of the second embodiment). As shown in FIG. 11(b), after removing the conductive film 61, a superconducting film 64 (second superconducting film) is formed on the superconducting film 63 to cover the through electrode 30. As shown in FIG. 11(c), the superconducting film 63 and the superconducting film 64 are patterned to form the wiring 53 connected to the through electrode 30. This increases the contact area between the through electrode 30 and the wiring 53, thereby improving the connection reliability between the through electrode 30 and the wiring 53. In this case, as shown in FIG. 10(a), the through electrode 30 protrudes in the −Z direction from the lower surface 12 (second surface) of the substrate 10. The wiring 53, which is made of a superconducting material different from that of the through electrode 30, contacts the side surface 33 and the lower surface 32 (the tip surface protruding from the lower surface 12 of the substrate 10) of the through electrode 30. [Example]

[0054] FIG. 12 is a cross-sectional view of a device 400 according to Example 4. As shown in FIG. 12, Example 4 does not include via wiring 44, terminal electrode 45, terminal electrode 46, and bump electrode 47, as compared to FIG. 1 of Example 1. Instead, a quantum bit 70 is provided on insulating film 19. The quantum bit 70 is connected to wiring 40 through via wiring 43. The quantum bit 70 is an element that forms a coherent two-level system using superconductivity. For example, the quantum bit 70 includes a Transmon quantum bit circuit in which a Josephson device and a capacitor are connected in parallel. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0055] [Manufacturing method] 13(a) and 13(b) are cross-sectional views showing a method for manufacturing a device 400 according to Example 4. As shown in Fig. 13(a), first, the steps described with reference to Fig. 2(a) to Fig. 3(c) of Example 1 are carried out.

[0056] As shown in FIG. 13(b), an insulating film 19 is formed on the insulating film 17 so as to cover the wiring 40. Next, a via wiring 43 is formed in the insulating film 19. Next, a quantum bit 70 connected to the via wiring 43 is formed on the insulating film 19. When the quantum bit 70 includes a Josephson element, it is formed by a commonly known method using, for example, oblique vacuum deposition. In this way, the device 400 according to the fourth embodiment is formed.

[0057] [Variations] 14 is a cross-sectional view of a device 410 according to a modification of Example 4. As shown in FIG. 14, in this modification of Example 4, quantum bits 70 are not provided on insulating film 19, but instead are provided on insulating film 18, connecting to wiring 42 through via wiring 44. The other configurations are the same as in Example 4, and therefore a description thereof will be omitted. Device 410 according to the modification of Example 4 is obtained by forming via wiring 44 in insulating film 18, and then forming quantum bits 70 connected to via wiring 44 on insulating film 18.

[0058] According to Example 4 and its modifications, after carrying out the same steps as those shown in Figures 2(a) to 3(c) of Example 1, quantum bits 70 connected to through electrodes 30 are formed on the upper surface 11 or the lower surface 12 of the substrate 10. Since the inclusion of non-superconducting materials in the through electrodes 30 is suppressed, deterioration of the characteristics of devices including quantum bits 70 can be suppressed. [Example]

[0059] FIG. 15 is a cross-sectional view of a device 500 according to a fifth embodiment. As shown in FIG. 15 , in the fifth embodiment, a chip 80 and a chip 81 are flip-chip mounted on the upper surface 11 of the substrate 10 in the device 100 of the first embodiment by bump electrodes 83. At least one of the chips 80 and 81 is a quantum chip having quantum bits. For example, both the chips 80 and 81 may be quantum chips, or one may be a quantum chip and the other a control chip. The device surfaces of the chips 80 and 81 on which circuits such as quantum bits are formed may be the surfaces facing the substrate 10, or may be the surfaces opposite the substrate 10.

[0060] The device 500 according to the fifth embodiment is formed by performing the steps of FIGS. 2(a) to 4(b) of the first embodiment and then flip-chip mounting the chips 80 and 81 on the upper surface 11 of the substrate 10.

[0061] [Variations] Fig. 16 is a cross-sectional view of a device 510 according to a modification of Example 5. As shown in Fig. 16, in the modification of Example 5, chips 80 and 81 are flip-chip mounted on the upper surface 11 of a substrate 10, and a chip 82 is also flip-chip mounted on the lower surface 12 by bump electrodes 47. For example, chips 80 and 81 are quantum chips, and chip 82 is a control chip. However, other cases are also possible as long as at least one of chips 80 to 82 is a quantum chip.

[0062] A device 510 according to a modification of the fifth embodiment is formed by carrying out the steps of the first embodiment shown in FIGS. 2(a) to 4(b), and then flip-chip mounting chips 80 and 81 on the upper surface 11 of the substrate 10, and flip-chip mounting chip 82 on the lower surface 12.

[0063] According to the fifth embodiment and its modifications, after carrying out the same steps as those shown in Figures 2(a) to 4(b) of the first embodiment, one or more chips 80 to 82 are mounted on at least one of the upper surface 11 and the lower surface 12 of the substrate 10. At least one of the chips 80 to 82 is a quantum chip. Since the inclusion of non-superconducting material in the through electrode 30 is suppressed, deterioration of the characteristics of the device including the quantum chip can be suppressed.

[0064] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims.

[0065] In addition, the following supplementary notes are provided in relation to the above description. (Appendix 1) A method for manufacturing a device, comprising: a step of forming a conductive film using a non-superconducting material on a second surface of a substrate having a first surface and a second surface opposite the first surface; a step of forming a through hole penetrating the substrate by etching the substrate from the first surface after forming the conductive film; a step of forming a through electrode in the through hole using a superconducting material by electroplating using the conductive film exposed in the through hole as a seed layer; and a step of removing the conductive film after forming the through electrode. (Appendix 2) A method for manufacturing a device as described in Appendix 1, further comprising the step of forming a first superconducting film on the second surface before forming the conductive film, wherein the step of forming the conductive film includes forming the conductive film on the first superconducting film. (Appendix 3) A method for manufacturing a device according to Appendix 2, further comprising the step of forming wiring connected to the through electrode by patterning the first superconducting film after removing the conductive film. (Appendix 4) A method for manufacturing a device according to Appendix 2, further comprising the steps of: after removing the conductive film, forming a second superconducting film on the first superconducting film to cover the through electrode; and forming wiring connected to the through electrode by patterning the first superconducting film and the second superconducting film. (Appendix 5) The method for manufacturing a device according to appendix 1, further comprising the step of forming an insulating film covering the through electrode on the first surface before removing the conductive film. (Appendix 6) A method for manufacturing a device according to appendix 1, further comprising the steps of: forming a first wiring on the second surface using a superconducting material to connect to the through electrode; and forming a second wiring on the first surface using a superconducting material to connect to the through electrode. (Supplementary Note 7) A method for manufacturing a device according to Supplementary Note 1 or 2, further comprising the step of forming a quantum bit connected to the through electrode on the first surface or the second surface. (Appendix 8) A method for manufacturing a device described in Appendix 1 or 2, further comprising a step of mounting one or more chips on at least one of the first surface and the second surface, wherein at least one of the one or more chips is a quantum chip. (Appendix 9) The method for manufacturing a device according to appendix 1 or 2, wherein the conductive film contains copper, gold, or silver. (Appendix 10) The method for manufacturing a device according to appendix 1 or 2, wherein the through electrode contains tin, zinc, cadmium, lead, indium, or ruthenium. (Appendix 11) The method for manufacturing a device according to appendix 2, wherein the first superconducting film contains titanium nitride, vanadium, niobium, tantalum, vanadium nitride, niobium nitride, or tantalum nitride. (Appendix 12) A device comprising: a substrate having a first surface and a second surface opposite the first surface; a through electrode formed of a superconducting material and extending through the substrate from the first surface to the second surface; and wiring provided on the second surface and connected to the through electrode and formed of a superconducting material different from the through electrode, wherein the through electrode protrudes beyond the second surface and the wiring is in contact with at least a side surface of the through electrode. (Appendix 13) The device described in Appendix 12, characterized in that the tip surface of the through electrode protruding from the second surface is on the same plane as the surface of the wiring opposite the second surface. (Appendix 14) The device according to appendix 12, wherein the wiring is in contact with the side surface of the through electrode and a tip surface of the through electrode that protrudes beyond the second surface. [Explanation of symbols]

[0066] 10...substrate, 11...upper surface, 12...lower surface, 13...through hole, 14...insulating film, 15...insulating film, 16...insulating film, 17...insulating film, 18...insulating film, 19...insulating film, 30...through electrode, 31...upper surface, 32...lower surface, 33...side surface, 40...wiring, 41...via wiring, 42...wiring, 43...via wiring, 44...via wiring, 45...terminal electrode, 46...terminal electrode, 47...bump electrode, 48...through hole, 49...through hole, 50...through hole, 51...upper surface, 52...lower surface , 53...wiring, 54...first layer, 55...second layer, 56...top surface, 60...metal mask layer, 61...conductive film, 62...opening, 63...superconducting film, 64...superconducting film, 70...qubit, 80...chip, 81...chip, 82...chip, 83...bump electrode, 90...conductive film, 91...metal mask layer, 92...opening, 93...non-superconducting film, 94...superconducting film, 95...through electrode, 100, 200, 300, 400, 410, 500, 510...device

Claims

1. forming a conductive film on a second surface of a substrate having a first surface and a second surface opposite to the first surface, using a non-superconducting material; forming a through-hole penetrating the substrate by etching the substrate from the first surface after forming the conductive film; forming a through electrode in the through hole using a superconducting material by electrolytic plating using the conductive film exposed in the through hole as a seed layer; and removing the conductive film after forming the through electrode.

2. forming a first superconducting film on the second surface before forming the conductive film; 2. The method for manufacturing a device according to claim 1, wherein the step of forming the conductive film forms the conductive film on the first superconducting film.

3. 3. The method for manufacturing a device according to claim 2, further comprising the step of forming wiring connected to the through electrode by patterning the first superconducting film after removing the conductive film.

4. After removing the conductive film, forming a second superconducting film on the first superconducting film to cover the through electrode; The method for manufacturing a device according to claim 2, further comprising the step of forming wiring connected to the through electrode by patterning the first superconducting film and the second superconducting film.

5. The method for manufacturing a device according to claim 1 or 2, further comprising the step of forming a quantum bit connected to the through electrode on the first surface or the second surface.

6. further comprising the step of mounting one or more chips on at least one of the first surface and the second surface; 3. The method for manufacturing a device according to claim 1, wherein at least one of the one or more chips is a quantum chip.

7. 3. The method for manufacturing a device according to claim 1, wherein the conductive film contains copper, gold, or silver.

8. 3. The method for manufacturing a device according to claim 1, wherein the through electrode contains tin, zinc, cadmium, lead, indium, or ruthenium.

9. 3. The method of claim 2, wherein the first superconducting film comprises titanium nitride, vanadium, niobium, tantalum, vanadium nitride, niobium nitride, or tantalum nitride.

10. a substrate having a first surface and a second surface opposite the first surface; a through electrode formed of a superconducting material and extending from the first surface to the second surface through the substrate; a wiring provided on the second surface and connected to the through electrode, the wiring being made of a superconducting material different from the through electrode; the through electrode protrudes from the second surface, The device is characterized in that the wiring is in contact with at least a side surface of the through electrode.

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