LLC converter control circuit and LLC converter

Abstract

To provide an LLC converter control circuit capable of accurately detecting a current value even in a region where an output current is minute.SOLUTION: An LLC converter control circuit 100 includes a current detection circuit 110 that outputs a zero cross signal ZC, and a synchronization signal generation circuit 120 that outputs a first signal Va indicating a value obtained by performing an exclusive OR operation on values of a first drive signal VgH and the zero cross signal ZC. The LLC converter control circuit 100 also includes an edge delay circuit 130 that outputs a delay signal Vd that is a signal obtained by delaying the first signal Va. The LLC converter control circuit 100 also includes a ramp voltage generation circuit 140 that charges and discharges a capacitor Ct with a feedback current Ifb based on a change in the level of the delay signal Vd and outputs a ramp voltage Vct. Further, the LLC converter control circuit 100 includes a drive signal generation circuit 160 that generates the first drive signal VgH and the second drive signal VgL based on the ramp voltage Vct.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an LLC converter control circuit and an LLC converter. [Background technology]

[0002] Conventionally, techniques related to control devices for switching circuits for LLC converters have been proposed. Patent Document 1 discloses a control device for a resonant converter. The control device for a resonant converter disclosed in Patent Document 1 charges and discharges a capacitor using a feedback current, and controls the half-bridge of the LLC converter according to the charging and discharging times. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-83186 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in an LLC converter, the phase difference between the periodic square wave voltage and the zero-cross signal due to the load current is 0° at maximum output current, meaning there is no phase difference between the periodic square wave voltage and the zero-cross signal. However, when there is no load, the phase difference is 90°, and the zero-cross signal lags behind the periodic square wave voltage. As a result, the slope of the sawtooth wave (ramp voltage) used to generate the drive signal changes by a maximum of two times when the phase difference is 90°. In addition, the change due to the slope of the feedback current also changes by a maximum of two times. Under light loads, the change due to the slope of this feedback current is only two times, making it difficult to accurately detect the output current due to the feedback current.

[0005] The present disclosure has been made in view of the problems inherent in the conventional technology, and an object of the present disclosure is to provide an LLC converter control circuit that enables accurate detection of current values ​​even in a region where the output current is very small. [Means for solving the problem]

[0006] An LLC converter control circuit according to an embodiment of the present disclosure controls a high-side drive signal for driving a high-side switch and a low-side drive signal for driving a low-side switch based on a resonant current conversion voltage obtained by converting into voltage a current flowing through a resonant circuit in which a high-side switch and a low-side switch are alternately turned on and off. The LLC converter control circuit includes: a current detection circuit that compares the resonant current conversion voltage with a GND potential and outputs a zero-cross signal whose voltage level changes at the timing when the resonant current conversion voltage switches to a positive potential or a negative potential; a synchronization signal generation circuit that outputs a first signal indicating a value obtained by exclusive-ORing a first drive signal for generating the high-side drive signal and values ​​of the zero-cross signal; an edge delay circuit that outputs a delayed signal that is a signal obtained by delaying the first signal by a predetermined time; a ramp voltage generation circuit that charges and discharges a capacitor with a current supplied from a feedback terminal based on a level change of the delayed signal and outputs a ramp voltage; and a drive signal generation circuit that generates first and second drive signals for generating the high-side drive signal and the low-side drive signal based on the ramp voltage.

[0007] An LLC converter according to another aspect of the present disclosure includes the above-described LLC converter control circuit, an input power supply, a half-bridge circuit consisting of a high-side switch and a low-side switch, a resonant circuit in which a primary winding of a transformer and a resonant capacitor are connected in series between the output of the half-bridge circuit and GND, a first diode, a second diode, and an output capacitor that rectify and smooth the secondary winding of the transformer, an output voltage detection circuit that detects the output voltage, and a resonant current detection circuit that detects the current flowing through the resonant circuit. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide an LLC converter control circuit that enables accurate detection of a current value even in a region where the output current is very small. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of an LLC converter according to this embodiment. [Figure 2] FIG. 2 is a diagram for explaining a comparative example of an LLC converter control circuit. [Figure 3] FIG. 3 is a diagram showing the configuration of the LLC converter control circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the configuration of the LLC converter control circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram for explaining the operation of the LLC converter control circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram for explaining the operation of the LLC converter control circuit according to the first embodiment. [Figure 7A] FIG. 7A is a diagram for explaining the operation of the LLC converter control circuit in the comparative example. [Figure 7B] FIG. 7B is a diagram for explaining the operation of the LLC converter control circuit in the comparative example. [Figure 8] FIG. 8 is a diagram for explaining the operation of the LLC converter control circuit according to the first embodiment. [Figure 9] FIG. 9 is a diagram for explaining the operation of the LLC converter control circuit according to the first embodiment. [Figure 10] FIG. 10 is a diagram showing the relationship between the output current and the feedback current in the LLC converter according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing the configuration of an LLC converter control circuit according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing the configuration of an LLC converter control circuit according to the second embodiment. [Figure 13] FIG. 13 is a diagram for explaining the operation of the comparative example of the LLC converter control circuit. [Figure 14] FIG. 14 is a diagram for explaining the operation of the LLC converter control circuit according to the second embodiment. [Figure 15] FIG. 15 is a diagram for explaining the operation of the LLC converter control circuit according to the second embodiment. [Figure 16] FIG. 16 is a diagram for explaining the operation of the LLC converter control circuit according to the second embodiment. [Figure 17] FIG. 17 is a diagram showing the relationship between the output current and the feedback current in the LLC converter according to the second embodiment. [Figure 18] FIG. 18 is a diagram showing the relationship between the output current and the feedback current when the input voltage is changed in the LLC converter according to the second embodiment. [Figure 19] FIG. 19 is a diagram for explaining the operation of the LLC converter control circuit according to the third embodiment. [Figure 20] FIG. 20 is a diagram for explaining the operation of the LLC converter control circuit according to the third embodiment. [Figure 21] FIG. 21 is a diagram showing the configuration of an LLC converter control circuit according to the third embodiment. [Figure 22] FIG. 22 is a diagram showing the configuration of an LLC converter control circuit according to the third embodiment. [Figure 23] FIG. 23 is a diagram illustrating another configuration example of the LLC converter control circuit according to the third embodiment. [Figure 24] FIG. 24 is a diagram illustrating another configuration example of the LLC converter control circuit according to the third embodiment. [Figure 25] FIG. 25 is a diagram illustrating another configuration example of the LLC converter control circuit according to the third embodiment. [Figure 26] FIG. 26 is a diagram illustrating another configuration example of the LLC converter control circuit according to the third embodiment. [Figure 27] FIG. 27 is a diagram for explaining the operation of the LLC converter control circuit according to the third embodiment. [Figure 28] FIG. 28 is a diagram for explaining the operation of the LLC converter control circuit according to the third embodiment. [Figure 29] FIG. 29 is a diagram showing the relationship between the output current and the feedback current in the LLC converter according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, LLC converters 10 and LLC converter control circuits 100 according to several embodiments of the present disclosure will be described in detail with reference to the drawings. The same or equivalent parts in the drawings of the LLC converters 10 and LLC converter control circuits 100 according to the embodiments will be designated by the same reference numerals, and their description will be omitted.

[0011] (LLC Converter 10 Configuration) FIG. 1 is a diagram showing the configuration of an LLC converter 10 provided with an LLC converter control circuit 100 according to this embodiment.

[0012] The LLC converter 10 includes an input power supply Vin and a half-bridge circuit connected to the input power supply Vin and configured with a high-side switch QH and a low-side switch QL. The LLC converter 10 also includes a resonant circuit in which a primary winding of a transformer T and a resonant capacitor Cr are connected in series between an output HB of the half-bridge circuit and GND.

[0013] The LLC converter 10 also includes a first diode Ds1 and a second diode Ds2 that rectify and smooth the secondary winding of the transformer T, and an output capacitor Co. The LLC converter 10 also includes an output voltage detection circuit 200 that detects the output voltage Vo. The LLC converter 10 also includes a resonant current detection circuit 300 that detects the current flowing through the resonant circuit.

[0014] The LLC converter 10 further includes an LLC converter control circuit 100 that controls the high-side switch QH and the low-side switch QL. The LLC converter control circuit 100 controls the high-side drive signal VgsH and the low-side drive signal VgsL based on the feedback current Ifb of the output voltage detection circuit 200 and the voltage Vres of the resonant current detection circuit 300.

[0015] The voltage Vres represents a voltage obtained by converting a current flowing through a resonant circuit that resonates by alternately turning on and off the high-side switch QH and the low-side switch QL. The high-side drive signal VgsH and the low-side drive signal VgsL are signals that drive the high-side switch QH and the low-side switch QL. The LLC converter 10 controls the output voltage Vo based on the high-side drive signal VgsH and the low-side drive signal VgsL. As described above, the voltage Vres is a signal obtained by converting a current flowing through the resonant circuit into a voltage, and corresponds to a resonant current conversion voltage.

[0016] (Configuration of LLC converter control circuit) Fig. 2 is a diagram for explaining a comparative example of an LLC converter control circuit. Fig. 3 and Fig. 4 are diagrams showing the configuration of an LLC converter control circuit 100a according to a first embodiment. Note that when it is not necessary to distinguish between the LLC converter control circuits 100a to 100e shown in the following embodiments, they will be simply referred to as "LLC converter control circuit 100."

[0017] The LLC converter control circuit shown in FIG. 2 as a comparative example includes a current detection circuit 110, a synchronization signal generation circuit 120, a ramp voltage generation circuit 140, a comparison circuit 150, a drive signal generation circuit 160, and a dead time generation circuit 170.

[0018] The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and outputs a zero-cross signal ZC that is High (high level) when the voltage Vres is positive and Low (low level) when the voltage Vres is negative. That is, the current detection circuit 110 compares the voltage Vres with the GND potential and outputs a zero-cross signal ZC whose voltage level changes at the timing when the voltage Vres switches to a positive potential or a negative potential.

[0019] The synchronization signal generation circuit 120 inputs the first drive signal VgH output from the drive signal generation circuit 160 and the zero-cross signal ZC of the current detection circuit 110 to a circuit that performs an exclusive OR operation, and generates a first signal Va.

[0020] The ramp voltage generating circuit 140 charges the capacitor Ct with the feedback current Ifb flowing through the FB terminal starting from the time when the first signal Va output from the synchronization signal generating circuit 120 goes low, and discharges the capacitor Ct at the timing when the first signal Va goes high, thereby outputting the ramp voltage Vct.

[0021] The comparator circuit 150 compares the ramp voltage Vct with the reference voltage Vp, and outputs a second signal Vb that goes high when the ramp voltage Vct exceeds the reference voltage Vp.

[0022] The drive signal generation circuit 160 is configured as a T-FF that receives the second signal Vb as an input, uses the first drive signal VgH as its Q output, and uses the second drive signal VgL as its NQ output. The drive signal generation circuit 160 also toggles between the first drive signal VgH and the second drive signal VgL at the rising edge (rising timing) of the second signal Vb, which is the comparison result of the comparison circuit 150.

[0023] The dead time generation circuit 170 generates a high-side drive signal VgsH and a low-side drive signal VgsL by delaying the rising timing of the first drive signal VgH and the second drive signal VgL, and outputs them to the VGH terminal and VGL terminal, respectively.

[0024] (First embodiment) The LLC converter control circuit 100a according to the first embodiment shown in FIGS. 3 and 4 further includes an edge delay circuit 130 in addition to the configuration of the comparative example shown in FIG.

[0025] The edge delay circuit 130 outputs a delayed signal Vd, which is a signal obtained by delaying the first signal Va by a predetermined time. As shown in FIG. 4, when the first signal Va generated by the synchronization signal generation circuit 120 is Low (low level), the edge delay circuit 130 charges a capacitor C2 with a current Icc2 from a constant current source. The edge delay circuit 130 also outputs a delayed signal Vd, which is obtained by delaying the first signal Va until the charged voltage reaches a threshold voltage Vth2. In other words, the edge delay circuit 130 delays the falling time of the first signal Va output from the synchronization signal generation circuit 120.

[0026] As a result, the LLC converter control circuit 100a according to the first embodiment delays the time when charging of the voltage of the capacitor Ct provided in the ramp voltage generation circuit 140 starts from the time when the resonant current crosses zero. That is, the ramp voltage generation circuit 140 charges and discharges the current supplied from the feedback terminal FB to and from the capacitor Ct based on the level change of the delay signal Vd, and outputs the ramp voltage Vct.

[0027] This increases the amount of change in the feedback current Ifb near no load in the LLC converter 10 according to the first embodiment. As a result, the LLC converter control circuit 100a can accurately determine an extremely light load state based on the amount of change in the feedback current Ifb.

[0028] 5 and 6 are waveform examples showing the operation of the LLC converter control circuit 100a according to the first embodiment when the load 20 is at a rated load and when there is no load.

[0029] (Operation under rated load) 5, the operation in the case of a rated load will be described. The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-cross signal ZC. At time t0, the high-side drive signal VgsH is turned off.

[0030] Next, at time t1, the zero-cross signal ZC output from the resonant current detection circuit 110 changes from high to low. Also, at time t1, the edge delay circuit 130 starts charging the capacitor C2 with a preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 starts rising from time t1.

[0031] Next, at time t2, the voltage Ramp2 becomes higher than a preset threshold voltage Vth2, and the feedback current Ifb starts to charge the capacitor Ct provided in the ramp voltage generation circuit 140. The ramp voltage Vct (voltage Ramp3) of the ramp voltage generation circuit 140 starts to rise from time t2.

[0032] The preset threshold voltage Vth2 is determined in advance so as to delay the rise time t2 of the ramp voltage Vct from the zero cross time tz (time t1) shown in FIG. 5 by a time Tsf.

[0033] Next, at time t3, the ramp voltage Vct becomes higher than the predetermined reference voltage Vp, the low-side drive signal VgsL becomes Low, and the low-side switch QL is controlled to be turned off.

[0034] Next, at time t4, the zero-cross signal ZC of the current detection circuit 110 for the resonant current changes from low to high. Also, at time t4, the edge delay circuit 130 starts charging the capacitor C2 with the preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 starts rising again from time t4.

[0035] At time t5, the voltage Ramp2 becomes higher than the threshold voltage Vth2, and the feedback current Ifb starts charging the capacitor Ct provided in the ramp voltage generation circuit 140. The ramp voltage Vct of the ramp voltage generation circuit 140 also starts rising again from time t5. At time t6, the ramp voltage Vct becomes higher than the predetermined reference voltage Vp, the high-side drive signal VgsH goes low, and the high-side switch QH is controlled to be turned off.

[0036] (Operation under no load) Next, operation under no load will be described with reference to Fig. 6. The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and outputs the zero-cross signal ZC. At time t0, the high-side drive signal VgsH is turned off.

[0037] Next, at time t1, the zero-cross signal ZC output from the resonant current detection circuit 110 changes from high to low. Also, at time t1, the edge delay circuit 130 starts charging the capacitor C2 with a preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 starts rising from time t1.

[0038] Next, at time t2, the voltage Ramp2 becomes higher than a preset threshold voltage Vth2, and the feedback current Ifb starts to charge the capacitor Ct provided in the ramp voltage generation circuit 140. The ramp voltage Vct (voltage Ramp3) of the ramp voltage generation circuit 140 starts to rise from time t2.

[0039] The preset threshold voltage Vth2 is determined in advance so as to delay the rise time t2 of the ramp voltage Vct from the zero cross time tz (time t1) shown in FIG. 6 by a time Tsf.

[0040] Next, at time t3, the ramp voltage Vct becomes higher than the predetermined reference voltage Vp, the low-side drive signal VgsL becomes Low, and the low-side switch QL is controlled to be turned off.

[0041] Next, at time t4, the zero-cross signal ZC of the current detection circuit 110 for the resonant current changes from low to high. Also, at time t4, the edge delay circuit 130 starts charging the capacitor C2 with the preset current Icc2. The voltage Ramp2 of the edge delay circuit 130 starts rising again from time t4.

[0042] At time t5, the voltage Ramp2 becomes higher than the threshold voltage Vth2, and the feedback current Ifb starts charging the capacitor Ct provided in the ramp voltage generation circuit 140. The ramp voltage Vct of the ramp voltage generation circuit 140 also starts rising again from time t5. At time t6, the ramp voltage Vct becomes higher than the predetermined reference voltage Vp, the high-side drive signal VgsH goes low, and the high-side switch QH is controlled to be turned off.

[0043] Figures 7A and 7B are waveforms showing operation at rated load and no load in the comparative example of Figure 2. Specifically, Figures 7A and 7B are waveforms showing the half-bridge voltage Vhb, voltage Vres, zero-cross signal ZC, and sawtooth lamp voltage Vct generated by feedback current Ifb at the maximum output current at rated load and at no load.

[0044] In FIG. 7A, the phase difference between the half-bridge voltage Vhb and the zero-cross signal ZC in the LLC converter 10 due to the load current is 0° at the maximum output current, and there is no phase difference between the half-bridge voltage Vhb and the zero-cross signal ZC.

[0045] On the other hand, in FIG. 7B, the phase difference between the half-bridge voltage Vhb and the zero-cross signal ZC in the LLC converter 10 due to the load current is 90° when there is no load, and the zero-cross signal ZC lags behind the half-bridge voltage Vhb.

[0046] Therefore, in the conventional technology shown in the comparative example, the slope of the sawtooth wave for generating the drive signal changes by a maximum of two times, as shown in Figures 7A and 7B, and therefore the change in feedback current Ifb also changes by a maximum of two times.

[0047] Next, a description will be given of the operation of the LLC converter control circuit 100a according to the first embodiment. Figures 8 and 9 show waveforms illustrating the operation of the LLC converter control circuit 100a according to the first embodiment at the maximum output current and when there is no load.

[0048] As shown in FIG. 7A above, at the maximum output current, the phase difference between the half-bridge voltage Vhb and the zero-cross signal ZC is 0°. Therefore, in the conventional technology shown as a comparative example, the sawtooth ramp voltage Vct generated by the feedback current Ifb is generated at the time when the zero-cross signal ZC inverts (see FIG. 7A). Therefore, if the feedback current at no load is Ifb0, the feedback current Ifb is 1 / 2 × Ifb0.

[0049] On the other hand, as shown in FIG. 8, in the operating waveforms of the LLC converter control circuit 100a according to the first embodiment, the sawtooth ramp voltage Vct generated by the feedback current Ifb is generated after a time Tsf has elapsed since the zero-cross signal ZC is inverted.

[0050] For example, the slope of the sawtooth wave increases by the amount of delay compared to conventional technology. If the time Tsf is Tsw (operating cycle) / 8, the slope of the sawtooth wave increases by 4 / 3 times compared to conventional control. Therefore, the feedback current is 2 / 3 x Ifb0.

[0051] Furthermore, when there is no load as shown in Fig. 9, the phase difference between the half-bridge voltage Vhb and the zero-cross signal ZC is 90°. In the conventional technology shown in Fig. 7B, the sawtooth wave ramp voltage Vct generated by the feedback current Ifb is generated at the time when the zero-cross signal ZC inverts (see Fig. 7B).

[0052] On the other hand, in the operating waveforms of the LLC converter control circuit 100a according to the first embodiment, the sawtooth ramp voltage Vct generated by the feedback current Ifb is generated after the time Tsf has elapsed from the time when the zero-cross signal ZC is inverted.

[0053] As a result, the slope of the sawtooth wave in the LLC converter control circuit 100a according to the first embodiment increases by the amount of delay compared to the prior art. For example, if the operating cycle is Tsw and the time Tsf is Tsw / 8, the slope of the sawtooth wave increases by two times. Therefore, if the feedback current in the no-load state of the prior art is Ifb0, the feedback current in the no-load state of the LLC converter control circuit 100a according to the first embodiment is 2×Ifb0.

[0054] Therefore, in the conventional technology shown in FIG. 7A, the change in feedback current Ifb from no load to maximum load is doubled, whereas in the LLC converter control circuit 100a according to the first embodiment, the change in feedback current Ifb is tripled.

[0055] Furthermore, in the configuration of the first embodiment, when the time Tsf is increased to approach 1 / 4Tsw, the amount of change in the feedback current Ifb increases from light load to no load, so that light load to no load can be detected with high accuracy.

[0056] 10 is a diagram showing the relationship between the output current Io and the feedback current Ifb in the LLC converter 10 according to the first embodiment. Specifically, the graph shows the results of a simulation of the change in the feedback current Ifb due to the output current Io.

[0057] As shown in FIG. 10, when time Tsf=0×Tsw (operation cycle), the sawtooth wave ramp voltage Vct has no delay from the zero cross signal ZC, and therefore exhibits the characteristics of the conventional control method.

[0058] On the other hand, as shown in Figure 10, increasing the time Tsf increases the feedback current Ifb under light load conditions. Furthermore, as the time Tsf increases, the change in feedback current Ifb due to the output current Io increases when switching from no load to a light load, and the slope becomes steeper. Therefore, the LLC converter control circuit 100a according to the first embodiment can accurately detect a light load condition based on the feedback current Ifb.

[0059] (Second embodiment) As described above, one specific embodiment has been described, but the above-described embodiment is merely an example and is not intended to limit the scope of the present invention. For example, the above-described embodiment illustrates a configuration in which the time Tsf is determined by a predetermined threshold value. Here, we will further describe an LLC converter control circuit 100b according to a second embodiment, which is capable of precisely adjusting the time Tsf in the LLC converter control circuit 100, and which has a configuration different from that of the first embodiment.

[0060] 11 and 12 are diagrams showing the configuration of an LLC converter control circuit 100b according to the second embodiment. As shown in Fig. 11 and 12, the LLC converter control circuit 100b according to the second embodiment differs from the LLC converter control circuit 100a according to the first embodiment in that it includes a negative current period detection circuit 180.

[0061] As described above, the edge delay circuit 130 of the LLC converter control circuit 100a according to the first embodiment generates the delay signal Vd using a predetermined threshold voltage Vth2. On the other hand, the LLC converter control circuit 100b according to the second embodiment generates the threshold voltage Vth2 using the negative current period detection circuit 180.

[0062] The negative current period detection circuit 180 measures the period during which the current flowing through the switch is negative after the switch is switched, based on the first drive signal VgH of the drive signal generation circuit 160 and the zero-cross signal ZC generated by the current detection circuit 110. Further, the negative current period detection circuit 180 generates and outputs a threshold voltage Vth2 corresponding to the negative period. Specifically, the negative current period detection circuit 180 generates a threshold voltage Vth2 corresponding to the time Tn from when the first drive signal VgH becomes Low until the zero-cross signal ZC becomes Low.

[0063] Also, the edge delay circuit 130 delays the falling edge of the first signal Va by a time Ts corresponding to the time of the threshold voltage Vth2. Here, in the example shown in FIG. 12, if K = Ts / Tn, then the threshold voltage Vth2 = Icc1×Tn / C1. Also, since Ts = C2×Vth2 / Icc2, K = (Icc1 / Icc2)×(C2 / C1).

[0064] The LLC converter control circuit 100b according to the second embodiment is characterized in that the currents Icc1, Icc2, the capacitors C1, C2 are set within the range of 0 < K < 1, and the rising and falling edges of the first signal Va are delayed by a time Ts proportional to the time Tn.

[0065] For example, when setting K = 0.5, it is possible to set the desired K by setting Icc1 = Icc2 and C1 = 2×C2. Or, it is possible to set the desired K by setting C1 = C2 and Icc2 = 2×Icc1.

[0066] FIG. 13 is a diagram for explaining an operation example in the conventional circuit configuration shown in FIG. 2 as a comparative example of the LLC converter control circuit.

[0067] The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-cross signal ZC. At time t0, the ramp voltage Vct of the capacitor Ct becomes higher than the predetermined reference voltage Vp, the second signal Vb goes high, the first drive signal VgH goes low, and the second drive signal VgL goes high. Also, the first signal Va goes high, turning on the transistor Q40 of the ramp voltage generation circuit 140, causing the ramp voltage Vct to become zero and the second signal Vb to go low.

[0068] Next, at time t1, the zero-cross signal ZC output from the resonant current current detection circuit 110 changes from High to Low. The first signal Va also changes to Low, turning off the transistor Q40. The ramp voltage generation circuit 140 also starts charging the capacitor Ct with the feedback current Ifb. Furthermore, the ramp voltage Vct starts rising from time t1.

[0069] At time t3, the voltage of the capacitor Ct becomes higher than the predetermined reference voltage Vp, the second signal Vb becomes High, the second drive signal VgL becomes Low, and the first drive signal VgH becomes High.

[0070] At time t4, the zero-cross signal ZC output from the current detection circuit 110 for the resonant current changes from low to high. The first signal Va also changes to low, turning off the transistor Q40. The feedback current Ifb starts charging the capacitor Ct. The ramp voltage Vct starts rising from time t4.

[0071] At time t6, the voltage of capacitor Ct becomes higher than the predetermined reference voltage Vp, the second signal Vb becomes High, the first drive signal VgH becomes Low, and the second drive signal VgL becomes High. Also, the first signal Va becomes High, turning on transistor Q40, the ramp voltage Vct becomes zero, and the second signal Vb becomes Low.

[0072] 14 is a waveform diagram showing the operation of the LLC converter control circuit 100b according to the second embodiment. The current detection circuit 110 compares the voltage Vres at the IS terminal with the GND potential and sends out a zero-cross signal ZC.

[0073] At time t0, the second signal Vb goes high, the first drive signal VgH goes low, and the second drive signal VgL goes high. Also, the transistor Q1 of the negative current period detection circuit 180 turns off, the capacitor C1 starts to charge with the current Icc1, and the voltage Ramp1 starts to rise from time t0.

[0074] At time t0, the first signal Va goes high, turning on the transistor Q2. The voltage Ramp2 goes to zero. The delay signal Vd goes high, turning on the transistor Q40 of the ramp voltage generating circuit 140. The ramp voltage Vct goes to zero, and the second signal Vb goes low.

[0075] At time t1, the zero-cross signal ZC of the resonant current current detection circuit 110 changes from High to Low. Also at time t1, the sample and hold SH1 samples and holds the Ramp1 voltage at the negative edge of the zero-cross signal ZC to generate the threshold voltage Vth2.

[0076] The threshold voltage Vth2 is proportional to the time Tn during which the current IdL is negative. The first signal Va also goes low, turning off the transistor Q2. This causes the edge delay circuit 130 to begin charging the capacitor C2 with the preset current Icc2. The voltage Ramp2 begins to rise from time t1.

[0077] At time t2, voltage Ramp2 reaches threshold voltage Vth2. Furthermore, delay signal Vd goes low, turning off transistor Q40, and capacitor Ct begins to be charged by feedback current Ifb. Furthermore, ramp voltage Vct begins to rise from time t2.

[0078] Here, the time Ts is proportional to the time Tn because the relationship is Tn:Ts=C1 / Icc1:C2 / Icc2.

[0079] At time t3, the ramp voltage Vct, which is the voltage of capacitor Ct, becomes higher than the predetermined reference voltage Vp, causing the second signal Vb to go High, the second drive signal VgL to go Low, and the first drive signal VgH to go High. The first signal Va also goes High, turning on transistor Q2. Furthermore, the voltage Ramp2 goes to zero. The delay signal Vd also goes High, turning on transistor Q40. Furthermore, the ramp voltage Vct goes to zero, causing the second signal Vb to go Low.

[0080] At time t4, the zero-cross signal ZC of the current detection circuit 110 for the resonant current changes from low to high, the first signal Va changes to low, and the transistor Q2 turns off. The edge delay circuit 130 also starts charging the capacitor C2 with a preset current Icc2. The voltage Ramp2 starts rising from time t4.

[0081] At time t5, voltage Ramp2 becomes equal to threshold voltage Vth2. Delay signal Vd goes low, turning off transistor Q40, and capacitor Ct begins to be charged by feedback current Ifb. Ramp voltage Vct begins to rise from time t5.

[0082] Furthermore, as described above, the time Ts is proportional to the time Tn because the relationship is Tn:Ts=C1 / Icc1:C2 / Icc2.

[0083] At time t6, the second signal Vb goes high, the first drive signal VgH goes low, and the second drive signal VgL goes high. Also, the transistor Q1 turns off, the capacitor C1 starts to charge with the current Icc1, and the voltage Ramp1 starts to rise from time t6.

[0084] Furthermore, the first signal Va goes High, turning on the transistor Q2. Furthermore, the voltage Ramp2 goes to zero. Furthermore, the delay signal Vd goes High, turning on Q40. The ramp voltage Vct goes to zero, and the second signal Vb goes Low.

[0085] As described above in the description of the first embodiment, FIGS. 7A and 7B are diagrams for explaining the sawtooth waveform of the conventional lamp voltage Vct when the output current Io is at its maximum and zero.

[0086] 7A, the phase difference between the half-bridge voltage Vhb and the current flowing through the half-bridge-connected resonant circuit at the maximum output current is 0°. Therefore, at the maximum output current, the voltage Vres crosses zero when the half-bridge switches are switched, and the ramp voltage Vct of the ramp voltage generation circuit 140 rises when the switches are switched.

[0087] 7B, when there is no load and the output current Io is zero, the phase difference between the half-bridge voltage Vhb and the current flowing through the half-bridge-connected resonant circuit is 90°. Therefore, when there is no load, the voltage Vres reaches zero crossing at the midpoint of the time when the half-bridge switches are switched. Therefore, the ramp voltage Vct of the ramp voltage generating circuit 140 rises half the on-period after the switches are switched.

[0088] 15 and 16 are diagrams for explaining the sawtooth wave of the lamp voltage Vct when the output current Io is at its maximum and when it is zero in the LLC converter control circuit 100b according to the second embodiment.

[0089] 15, the phase difference between the half-bridge voltage Vhb and the current flowing through the half-bridge-connected resonant circuit at the maximum output current is 0°. Therefore, at the maximum output current, the voltage Vres crosses zero when the half-bridge switch is switched. As a result, there is no period in which a negative current flows after the switch is switched, and the ramp voltage Vct of the ramp voltage generation circuit 140 rises when the switch is switched.

[0090] 16, the phase difference between the half-bridge voltage Vhb and the current flowing through the half-bridge-connected resonant circuit when there is no load is 90°. Therefore, when there is no load, the high-side switch QH is off and the low-side switch QL is on, and a negative current flows through the QL switch during a time Tn from time t0 to time t1. In the LLC converter control circuit 100b according to the second embodiment, the ramp voltage Vct of the ramp voltage generation circuit 140 rises at time t2, which is a time Ts proportional to the time Tn from time t1.

[0091] That is, as shown in Figure 16, in the operating waveform when Ts = 0.5 x Tn, the ramp voltage Vct rises with a delay of 1 / 4 of the time TonL from the zero-cross signal ZC. Therefore, the slope of the sawtooth wave is twice as large as that of the prior art shown in Figure 7B. Therefore, the slope of the sawtooth wave changes by up to four times, and the change in the feedback current Ifb also changes by up to four times.

[0092] FIG. 17 is a diagram showing the relationship between the output current and feedback current in the LLC converter 10 according to the second embodiment. The characteristics shown in FIG. 17 are the results of a simulation of the change in feedback current Ifb due to the output current Io in the LLC converter control circuit 100b according to the second embodiment. Here, K is Ts / Tn. The solid line K=0 indicates the characteristic obtained when Ts / Tn is 0, which means there is no delay, and thus represents the characteristic obtained using the conventional control method.

[0093] As shown in Figure 17, increasing the K value increases the feedback current Ifb under light load conditions. Furthermore, from no load to very light load (area A), the change in feedback current Ifb due to output current Io increases and the slope becomes steeper.

[0094] Therefore, in the LLC converter control circuit 100b according to the second embodiment, the amount of change in the feedback current Ifb relative to the output current becomes large (the slope becomes steeper) under an extremely light load, which enables the LLC converter control circuit 100b according to the second embodiment to accurately detect an extremely light load state using the feedback current Ifb.

[0095] (Third embodiment) Next, a third embodiment will be described. In the following description, when the same reference numerals as those in the first and / or second embodiment are used, they indicate the same configuration as the first and / or second embodiment, and the preceding description will be referred to unless otherwise specified. Here, the configuration of LLC converter control circuits 100c to 100e according to the third embodiment that generate a proportional voltage proportional to the switching period will be described, focusing on the configuration that differs from that of the first and / or second embodiment.

[0096] FIG. 18 is a diagram showing the simulation results when the input voltage is changed in response to changes in the feedback current Ifb relative to the output current Io when K=0.5 in the LLC converter control circuit 100b according to the second embodiment described above.

[0097] Because the frequency of the LLC converter 10 varies greatly depending on the input voltage, the range of variation of the feedback current Ifb relative to the output current Io differs depending on the input voltage. Therefore, in an LLC converter 10 where the input voltage changes, it is difficult to detect a light load state using only the feedback current Ifb.

[0098] The LLC converter control circuit 100c according to the third embodiment suppresses fluctuations in the feedback current Ifb relative to the input voltage by using a proportional voltage Vpp proportional to the period as the voltage compared with the ramp voltage Vct, which enables the LLC converter control circuit 100c according to the third embodiment to accurately detect a light load state regardless of the input voltage.

[0099] 19 and 20 are diagrams for explaining the proportional voltage Vpp of the LLC converter control circuit 100c according to the third embodiment. As shown in Fig. 19, the LLC converter control circuit 100c according to the third embodiment generates a proportional voltage Vpp that is proportional to the time that the first drive signal VgH of the drive signal generation circuit 160 is low. Therefore, the feedback current Ifb is not affected by changes in the operating cycle (frequency) and is therefore not affected by the input voltage.

[0100] For example, as shown in FIG. 20, the proportional voltage Vpp, which is compared with the ramp voltage Vct by the comparator circuit 150, varies up and down depending on the operating cycle. That is, the proportional voltage Vpp is proportional to the cycle, so the voltage increases as the cycle lengthens and decreases as the cycle shortens. Therefore, the slope of the ramp voltage Vct is the current value of the feedback current Ifb, and the slope remains constant regardless of whether the cycle lengthens or shortens. Therefore, in the LLC converter control circuit 100c according to the third embodiment, the current value of the feedback current Ifb remains constant.

[0101] Figures 21 and 22 are diagrams showing the configuration of an LLC converter control circuit 100c according to the third embodiment, and Figures 23 to 26 are diagrams showing the configurations of LLC converter control circuits 100d and 100e as other configuration examples according to the third embodiment.

[0102] The LLC converter control circuits 100c, 100d, and 100e according to the third embodiment differ from the LLC converter control circuit 100b according to the second embodiment in that they include a cycle detection circuit 190.

[0103] Like the negative current period detection circuit 180 described above, the period detection circuit 190 includes a sample and hold SH2 and generates a proportional voltage Vpp according to the period of the first drive signal VgH or the second drive signal VgL. Specifically, in the example shown in Fig. 22, the sample and hold SH2 samples and holds the voltage Vch at the positive edge of the second drive signal VgL to generate the proportional voltage Vpp.

[0104] In the example shown in Figure 22, the period detection circuit 190 delays the rising edge of the second drive signal VgL using a delay circuit, discharges the voltage Vch, and samples the voltage Vch at the rising edge of the second drive signal VgL to generate a proportional voltage Vpp that is proportional to the period.

[0105] In addition, the LLC converter control circuit 100d shown in FIG. 24 and the LLC converter control circuit 100e shown in FIG. 26 are configured to use the voltage Ramp1 charged by the period detection circuit 190 as the voltage to be sampled and held by the negative current period detection circuit 180.

[0106] Also, as shown in FIG. 26, the period detection circuit 190 may delay the rising edge of the first drive signal VgH using a delay circuit to discharge the voltage Vch, and sample the voltage Vch at the rising edge of the first drive signal VgH to generate a proportional voltage Vpp that is proportional to the period.

[0107] As a result, the LLC converter control circuits 100d and 100e according to the third embodiment share a portion of the negative current period detection circuit 180 and the period detection circuit 190, thereby making it possible to reduce the circuit scale.

[0108] FIG. 27 is a waveform diagram for explaining the operation of the LLC converter control circuit 100d according to the third embodiment.

[0109] At time t0, when the ramp voltage Vct of the ramp voltage generation circuit 140 exceeds the proportional voltage Vpp, the second signal Vb output from the comparison circuit 150 goes High. As a result, the second drive signal VgL of the drive signal generation circuit 160 goes Low and the first drive signal VgH goes High.

[0110] Since the zero-cross signal ZC of the current detection circuit 110 is low, the first signal Va goes high. In the ramp voltage generation circuit 140, the transistor Q40 turns on and discharges the capacitor Ct. In the comparison circuit 150, the ramp voltage Vct falls below the proportional voltage Vpp, and the second signal Vb goes low.

[0111] Then, as the second drive signal VgL goes low, the transistor Q1 of the cycle detection circuit 190 turns off, and the voltage Ramp1 starts to rise.

[0112] At time t1, when the voltage Vres becomes positive, the zero-cross signal ZC output from the current detection circuit 110 goes high. Also, the first signal Va output from the synchronization signal generation circuit 120 goes low. This turns off the transistor Q2 of the edge delay circuit 130, and the voltage Ramp2 begins to rise.

[0113] Furthermore, when the first signal Va, which is the output of the synchronization signal generating circuit 120, goes low, the negative current period detecting circuit 180 samples and holds the voltage of Ramp1 and outputs the threshold voltage Vth2.

[0114] At time t2, when Ramp2 of the edge delay circuit 130 becomes equal to or greater than the threshold voltage Vth2, the delay signal Vd goes low. This also turns off the transistor Q40 of the ramp voltage generation circuit 140, causing the ramp voltage Vct to start rising. Here, the triangular wave ramp voltage Vct generated by the feedback current Ifb rises with a delay of time Ts from the zero crossing.

[0115] At time t3, when the ramp voltage Vct output from the ramp voltage generation circuit 140 exceeds the proportional voltage Vpp, the second signal Vb output from the comparison circuit 150 goes High, causing the first drive signal VgH of the drive signal generation circuit 160 to go Low and the second drive signal VgL to go High.

[0116] Since the zero-cross signal ZC of the synchronization signal generation circuit 120 is high, the first signal Va goes high. In the ramp voltage generation circuit 140, the transistor Q40 turns on and discharges the capacitor Ct. In addition, in the comparison circuit 150, the ramp voltage Vct falls below the proportional voltage Vpp, and the second signal Vb goes low.

[0117] At time t4, the delay circuit of the period detection circuit 190 turns on the transistor Q1 with a delayed signal after the first drive signal VgH goes high, and the voltage Ramp1 is discharged.

[0118] At time t5, when the voltage Vres becomes negative, the zero-cross signal ZC output from the current detection circuit 110 goes low. Also, the first signal Va output from the synchronization signal generation circuit 120 goes low. Also, the transistor Q2 of the edge delay circuit 130 turns off, and the voltage Ramp2 starts to rise.

[0119] At time t6, when the voltage Ramp2 of the edge delay circuit 130 becomes equal to or greater than the threshold voltage Vth2, the delay signal Vd goes low. Also, the transistor Q40 of the ramp voltage generation circuit 140 turns off, and the ramp voltage Vct starts to rise. The triangular-wave ramp voltage Vct generated by the feedback current Ifb rises with a delay of time Ts from the zero crossing.

[0120] 28 is a diagram showing a comparative example of the operation under no load in the LLC converter control circuit 100 according to the second and third embodiments. In Fig. 28, (a) and (b) in the upper row show the operating waveforms of the LLC converter control circuit 100b according to the second embodiment, and (c) and (d) in the lower row show the operating waveforms of the LLC converter control circuit 100c according to the third embodiment.

[0121] In the LLC converter control circuit 100b according to the second embodiment, as shown in (a), the lamp voltage Vct, which is a sawtooth wave at a frequency fa [Hz], is compared with a predetermined reference voltage Vp to determine the off timing.

[0122] When the input voltage becomes higher than in state (a) and the operating frequency becomes fb [Hz], which is twice fa [Hz], the feedback current Ifb must also be doubled so that the slope of the ramp voltage Vct doubles, as in state (b). This is also true when the load current is large.

[0123] On the other hand, in the LLC converter control circuit 100c according to the third embodiment, a means for generating a proportional voltage Vpp proportional to the period is added, and the ramp voltage Vct and the proportional voltage Vpp are compared.

[0124] As shown in (c), the LLC converter control circuit 100c according to the third embodiment compares the sawtooth ramp voltage Vct at a frequency of fa [Hz] with the generated proportional voltage Vpp to determine the off timing. When the input voltage increases and the operating frequency becomes fb [Hz], twice the frequency of fa [Hz], as shown in (d), the period is halved. Therefore, as shown in (d), the generated proportional voltage Vpp is halved, and the slope of the ramp voltage Vct remains the same. Therefore, when there is no load, the feedback current Ifb remains the same regardless of the operating frequency.

[0125] Next, the relationship between the output current Io and feedback current Ifb of the LLC converter control circuit 100 according to the third embodiment will be described. As explained above in connection with the second embodiment, Fig. 18 shows the relationship between the output current Io and feedback current Ifb when K = 0.5 for the LLC converter control circuit 100b according to the second embodiment in Fig. 12. Fig. 29 shows the relationship between the output current Io and feedback current Ifb when K = 0.5 for the LLC converter control circuits 100c, 100d, and 100e according to the third embodiment.

[0126] In Fig. 18, the feedback current Ifb fluctuates depending on the input voltage. On the other hand, in the waveform shown in Fig. 29, the fluctuation of the feedback current Ifb due to the input voltage is suppressed, and the fluctuation range converges as the output current Io decreases. Therefore, the LLC converter control circuits 100c, 100d, and 100e according to the third embodiment can accurately detect a light load regardless of the input voltage.

[0127] (Other embodiments) Although the embodiments have been described in detail with reference to the drawings, the present embodiments are not limited to the contents described in the above embodiments. Furthermore, the components described above include those that can be easily imagined by a person skilled in the art and those that are substantially the same. Furthermore, the configurations described above can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the configurations can be made without departing from the spirit of the embodiments.

[0128] The features of the LLC converter control circuit 100 and the LLC converter 10 will be described below.

[0129] An LLC converter control circuit 100 according to a first embodiment controls a high-side drive signal VgsH for driving a high-side switch QH and a low-side drive signal VgsL for driving a low-side switch QL based on a resonant current conversion voltage. The resonant current conversion voltage corresponds to a voltage Vres obtained by converting a current flowing through a resonant circuit in which the high-side switch QH and the low-side switch QL are alternately turned on and off. The LLC converter control circuit 100 includes a current detection circuit 110 that compares the resonant current conversion voltage with a ground potential and outputs a zero-crossing signal ZC whose voltage level changes when the resonant current conversion voltage switches to a positive or negative potential. The LLC converter control circuit 100 also includes a synchronization signal generation circuit 120 that outputs a first signal Va indicating a value obtained by exclusive-ORing the values ​​of a first drive signal VgH for generating the high-side drive signal VgsH and the zero-crossing signal ZC. The LLC converter control circuit 100 also includes an edge delay circuit 130 that outputs a delayed signal Vd obtained by delaying the first signal Va by a predetermined time. The LLC converter control circuit 100 also includes a ramp voltage generation circuit 140 that charges and discharges a current supplied from a feedback terminal FB to a capacitor Ct based on a change in the level of the delay signal Vd, and outputs a ramp voltage Vct. The LLC converter control circuit 100 also includes a drive signal generation circuit 160 that generates a first drive signal VgH and a second drive signal VgL for generating a high-side drive signal VgsH and a low-side drive signal VgsL based on the ramp voltage Vct.

[0130] This configuration increases the amount of change in the feedback current Ifb near no load in the LLC converter control circuit 100. As a result, the LLC converter control circuit 100 can accurately determine an extremely light load state based on the amount of change in the feedback current Ifb.

[0131] The LLC converter control circuit 100 according to the second aspect may further include a negative current period detection circuit 180 that generates a threshold voltage Vth2 corresponding to the time from when the value of the first drive signal VgH changes to when the value of the zero-cross signal ZC changes. The edge delay circuit 130 may generate a delayed signal Vd by delaying the first signal Va by a time proportional to the threshold voltage Vth2.

[0132] With this configuration, the LLC converter control circuit 100 experiences a large change in the feedback current Ifb relative to the output current under an extremely light load (the slope becomes steeper), which enables the LLC converter control circuit 100 to more accurately detect an extremely light load state using the feedback current Ifb.

[0133] The LLC converter control circuit 100 according to the third aspect may further include a period detection circuit 190 and a comparison circuit 150. The period detection circuit 190 may generate a proportional voltage Vpp proportional to the switching period of the resonant circuit based on the second drive signal VgL. The comparison circuit 150 may compare the proportional voltage Vpp with the ramp voltage Vct. Furthermore, the drive signal generation circuit 160 may switch the states of the first drive signal VgH and the second drive signal VgL at the rising edge of the comparison result of the comparison circuit 150.

[0134] With this configuration, the comparator circuit 150 of the LLC converter control circuit 100 can accurately detect a light load regardless of the input voltage by comparing the lamp voltage Vct with the proportional voltage Vpp that is proportional to the switching period.

[0135] The LLC converter control circuit 100 according to the fourth aspect may further include a period detection circuit 190, a negative current period detection circuit 180, and a comparison circuit 150. The period detection circuit 190 may generate a proportional voltage Vpp proportional to the switching period of the resonant circuit based on the second drive signal VgL. The negative current period detection circuit 180 may generate a threshold voltage Vth2 corresponding to the time from when the value of the second drive signal VgL changes to when the value of the zero-crossing signal ZC changes. The edge delay circuit 130 may generate a delayed signal Vd by delaying the first signal Va by a time proportional to the threshold voltage Vth2. The comparison circuit 150 may compare the proportional voltage Vpp with the ramp voltage Vct. The drive signal generation circuit 160 may switch the states of the first drive signal VgH and the second drive signal VgL at the rising edge of the comparison result of the comparison circuit 150.

[0136] With this configuration, the comparator circuit 150 of the LLC converter control circuit 100 can accurately detect a light load regardless of the input voltage by comparing the lamp voltage Vct with a proportional voltage Vpp that is proportional to the switching period. Also, the LLC converter control circuit 100 can reduce the circuit size by sharing parts of the negative current period detection circuit 180 and the period detection circuit 190.

[0137] The LLC converter control circuit 100 according to the fifth aspect may further include a period detection circuit 190, a negative current period detection circuit 180, and a comparison circuit 150. The period detection circuit 190 may generate a proportional voltage Vpp proportional to the switching period of the resonant circuit based on the first drive signal VgH. The negative current period detection circuit 180 may generate a threshold voltage Vth2 corresponding to the time from when the value of the first drive signal VgH changes to when the value of the zero-crossing signal ZC changes. The edge delay circuit 130 may generate a delayed signal Vd by delaying the first signal Va by a time proportional to the threshold voltage Vth2. The comparison circuit 150 may compare the proportional voltage Vpp with the ramp voltage Vct. The drive signal generation circuit 160 may switch the states of the first drive signal VgH and the second drive signal VgL at the rising edge of the comparison result of the comparison circuit 150.

[0138] With this configuration, the comparator circuit 150 of the LLC converter control circuit 100 can accurately detect a light load regardless of the input voltage by comparing the lamp voltage Vct with a proportional voltage Vpp that is proportional to the switching period. Also, the LLC converter control circuit 100 can reduce the circuit size by sharing parts of the negative current period detection circuit 180 and the period detection circuit 190.

[0139] An LLC converter 10 according to a sixth aspect includes the above-described LLC converter control circuit 100 and an input power supply Vin. The LLC converter 10 also includes a half-bridge circuit configured with a high-side switch QH and a low-side switch QL. The LLC converter 10 also includes a resonant circuit in which a primary winding of a transformer T and a resonant capacitor are connected in series between the output of the half-bridge circuit and GND. The LLC converter 10 also includes a first diode Ds1, a second diode Ds2, and an output capacitor Co that rectify and smooth the secondary winding of the transformer T, an output voltage detection circuit 200 that detects the output voltage Vo, and a resonant current detection circuit 300 that detects the current flowing through the resonant circuit.

[0140] This configuration increases the amount of change in the feedback current Ifb near no load in the LLC converter 10. As a result, the LLC converter control circuit 100 can accurately determine an extremely light load state based on the amount of change in the feedback current Ifb. [Explanation of symbols]

[0141] 10 LLC Converter 100, 100a, 100b, 100c, 100d, 100e LLC converter control circuit 110 Current detection circuit 120 Synchronous signal generation circuit 130 Edge Delay Circuit 140 Lamp voltage generation circuit 150 Comparison circuit 160 Drive signal generation circuit 170 Dead Time Generator 180 Negative current period detection circuit 190 Period detection circuit C1, C2, Ct, Ch capacitors ZC Zero cross signal Ifb Feedback current VgH 1st drive signal VgL Second drive signal VgsH High-side drive signal VgsL Low-side drive signal Io output current Vin Input power supply SH1, SH2 Sample and Hold Q1, Q2, Q3, Q40 transistors

Claims

1. an LLC converter control circuit that controls a high-side drive signal that drives a high-side switch and a low-side drive signal that drives a low-side switch based on a resonant current-converted voltage obtained by converting a current flowing through a resonant circuit in which a high-side switch and a low-side switch are alternately turned on and off, a current detection circuit that compares the resonant current conversion voltage with a GND potential and outputs a zero-cross signal whose voltage level changes at the timing when the resonant current conversion voltage switches to a positive potential or a negative potential; a synchronization signal generating circuit that outputs a first signal indicating a value obtained by exclusive-ORing a first drive signal for generating the high-side drive signal and the zero-cross signal; an edge delay circuit that outputs a delayed signal that is a signal obtained by delaying the first signal by a predetermined time; a ramp voltage generating circuit that charges and discharges a capacitor with a current supplied from a feedback terminal based on a change in the level of the delay signal, and outputs a ramp voltage; a drive signal generation circuit that generates the first drive signal and the second drive signal for generating the high-side drive signal and the low-side drive signal based on the ramp voltage; An LLC converter control circuit comprising:

2. a negative current period detection circuit that generates a threshold voltage corresponding to the time from when the value of the first drive signal changes to when the value of the zero-cross signal changes, 2. The LLC converter control circuit according to claim 1, wherein the edge delay circuit generates the delayed signal by delaying the first signal by a time proportional to the threshold voltage.

3. Further comprising a period detection circuit and a comparison circuit, the period detection circuit generates a proportional voltage proportional to the switching period of the resonant circuit based on the second drive signal; the comparison circuit compares the proportional voltage with the ramp voltage; 3. The LLC converter control circuit according to claim 2, wherein the drive signal generation circuit switches the states of the first drive signal and the second drive signal at a rising edge of the comparison result of the comparison circuit.

4. The power supply circuit further includes a period detection circuit, a negative current period detection circuit, and a comparison circuit, the period detection circuit generates a proportional voltage proportional to the switching period of the resonant circuit based on the second drive signal; the negative current period detection circuit generates a threshold voltage corresponding to the time from when the value of the second drive signal changes to when the value of the zero-cross signal changes; the edge delay circuit generates the delayed signal by delaying the first signal by a time proportional to the threshold voltage; the comparison circuit compares the proportional voltage with the ramp voltage; 2. The LLC converter control circuit according to claim 1, wherein the drive signal generation circuit switches the states of the first drive signal and the second drive signal at a rising edge of the comparison result of the comparison circuit.

5. The power supply circuit further includes a period detection circuit, a negative current period detection circuit, and a comparison circuit, the period detection circuit generates a proportional voltage proportional to the switching period of the resonant circuit based on the first drive signal; the negative current period detection circuit generates a threshold voltage corresponding to a time from when the value of the first drive signal changes to when the value of the zero-cross signal changes; the edge delay circuit generates the delayed signal by delaying the first signal by a time proportional to the threshold voltage; the comparison circuit compares the proportional voltage with the ramp voltage; 2. The LLC converter control circuit according to claim 1, wherein the drive signal generation circuit switches the states of the first drive signal and the second drive signal at a rising edge of the comparison result of the comparison circuit.

6. an LLC converter control circuit according to any one of claims 1 to 5; an input power supply; a half-bridge circuit configured with the high-side switch and the low-side switch; the resonant circuit in which a primary winding of a transformer connected between the output of the half-bridge circuit and GND and a resonant capacitor are connected in series; a first diode, a second diode, and an output capacitor for rectifying and smoothing the secondary winding of the transformer; an output voltage detection circuit for detecting an output voltage; a resonant current detection circuit for detecting a current flowing through the resonant circuit; An LLC converter comprising:

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