Semiconductor structure and method of manufacturing the same

Abstract

To provide a semiconductor structure having excellent writing efficiency, and to provide a method of manufacturing the semiconductor structure.SOLUTION: In a semiconductor structure including a substrate SB and a memory element 100, the memory element is disposed on the substrate and includes a floating gate 110, a tunnel dielectric layer 150, a control gate structure 200, an inter-gate oxide layer 130, an erase gate 120, and a word line 140. The floating gate is disposed on the substrate. The tunnel dielectric layer is disposed between the floating gate and the substrate. A control gate structure is disposed on the floating gate, wherein the control gate structure includes a high-k dielectric layer and a metal gate, and wherein a width at a top portion of the control gate structure is greater than a width at a bottom portion of the control gate structure. The inter-gate oxide layer is disposed between the floating gate and the control gate structure. The erase gate is disposed on one side of the floating gate.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to semiconductor structures and methods for fabricating the same, and more particularly, the present invention relates to embedded flash memory devices and methods for fabricating the same. [Background technology]

[0002] In conventional methods for forming embedded flash (E-flash) memory devices, it is difficult to form a control gate using a high-k metal gate (HKMG) process. Therefore, in the above-mentioned methods, a relatively large doped region is disposed in the substrate to replace the function of the control gate, which reduces the write efficiency of the final embedded flash memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,340,349 [Patent Document 2] U.S. Patent No. 9,659,953 [Patent Document 3] U.S. Patent No. 9,082,837 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a semiconductor structure with relatively good write efficiency. [Means for solving the problem]

[0005] Some embodiments of the present invention provide a semiconductor structure including a substrate and a memory element. The memory element is disposed on the substrate and includes a floating gate, a tunnel dielectric layer, a control gate structure, an inter-gate oxide layer, an erase gate, and a word line. The floating gate is disposed on the substrate. The tunnel dielectric layer is disposed between the floating gate and the substrate. The control gate structure is disposed on the floating gate, where the control gate structure includes a high-k dielectric layer and a metal gate, and the width of the control gate structure at an upper portion is greater than the width of the control gate structure at a bottom portion. The inter-gate oxide layer is disposed between the floating gate and the control gate structure. The erase gate is disposed on one side of the floating gate. The word line is disposed on the other side of the floating gate.

[0006] The present invention provides a method for fabricating a semiconductor structure, and the semiconductor structure fabricated by this method provides a semiconductor structure with relatively good write efficiency.

[0007] Another embodiment of the present invention provides a method for fabricating a semiconductor structure, the method comprising: forming a memory material layer on a substrate, the memory material layer including, in order, a floating gate, an erase gate, a first nitride layer, a first oxide layer, a second nitride layer, and a second oxide layer; forming a first trench in the memory material layer, the first trench exposing a portion of the first nitride layer; forming a second trench in the memory material layer, the second trench overlapping the first trench to form an opening, the second trench exposing a portion of the floating gate; forming an inter-gate oxide layer in the opening; forming a dummy gate structure including a high-k dielectric layer in the opening; and replacing the dummy gate structure with a control gate structure including a metal gate to form a memory element, the control gate structure having a width greater at a top portion than at a bottom portion of the control gate structure. [Effects of the Invention]

[0008] Based on the above, the present invention provides a novel semiconductor structure and a manufacturing method thereof. By forming a control gate structure including a high-k dielectric layer and a metal gate in the memory device, the write efficiency of the memory device of the present invention can be improved compared to conventional embedded flash memory devices. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a schematic diagram of a method flow for fabricating a semiconductor structure according to one embodiment of the present invention. [Figure 1B] 1 is a schematic diagram of a method flow for fabricating a semiconductor structure according to one embodiment of the present invention. [Figure 1C] 1 is a schematic diagram of a method flow for fabricating a semiconductor structure according to one embodiment of the present invention. [Figure 1D] 1 is a schematic diagram of a method flow for fabricating a semiconductor structure according to one embodiment of the present invention. [Figure 1E] 1 is a schematic diagram of a method flow for fabricating a semiconductor structure according to one embodiment of the present invention. [Figure 1F] 1 is a schematic diagram of a method flow for fabricating a semiconductor structure according to one embodiment of the present invention. [Figure 2A] 1 is a schematic local cross-sectional view of a semiconductor structure according to one embodiment of the present invention; [Figure 2B] 2 is a schematic local cross-sectional view of a control gate structure according to one embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] In order to explain the present invention in detail, examples are given below in conjunction with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. Furthermore, the drawings of the present invention are for illustrative purposes only, and specific elements in the drawings are not drawn to scale. In the following description, the same elements will be designated by the same reference numerals for ease of understanding.

[0011] 1A to 1F are schematic diagrams of a method flow for manufacturing a semiconductor structure in accordance with a first embodiment of the present invention.

[0012] Referring to FIGS. 1A to 1F, in this embodiment, the semiconductor structure 10 can be formed through the following steps, but the present invention is not limited thereto.

[0013] Step (1) is performed: a memory material layer is formed on a substrate SB.

[0014] 1A, in some embodiments, the substrate SB may be a semiconductor substrate, although the present invention is not limited thereto. The material of the substrate SB may be, for example, an elemental semiconductor, a compound semiconductor, an alloy semiconductor, or other suitable material. For example, the material of the substrate SB may include silicon, germanium, indium antimonide, indium arsenide, indium phosphide, gallium nitride, gallium arsenide, gallium antimonide, lead telluride, or a combination thereof. In other embodiments, the substrate SB may be a silicon-on-insulator (SOI) substrate.

[0015] In this embodiment, the substrate SB includes a memory device region A1, a high-voltage device region A2, and a logic device region A3. Here, a memory material layer is formed in the memory device region A1 of the substrate SB. Note that, before forming the memory material layer on the substrate SB, a dielectric layer IL1, a local oxidation of silicon (LOCOS) structure LO, and a shallow trench isolation structure STI may be formed on the substrate SB first. In this embodiment, the dielectric layer IL1 located in the memory device region A1 may be formed as a tunnel dielectric layer after subsequent processes. The dielectric layer IL1 located in the high-voltage device region A2 may be formed as a gate dielectric layer after subsequent processes, as will be described in detail in the following embodiments. The silicon local oxidation structure LO is, for example, disposed in the memory device region A1 and adjacent to the dielectric layer IL1. In some embodiments, the silicon local oxidation structure LO may be formed via a thermal oxidation process, but the present invention is not limited thereto. The shallow trench isolation structure STI may include, for example, a shallow trench isolation structure STI1, a shallow trench isolation structure STI2, and a shallow trench isolation structure STI3. Here, the shallow trench isolation structure STI1 is used, for example, to separate the memory device region A1 from the high-voltage device region A2, the shallow trench isolation structure STI2 is used, for example, to separate the high-voltage device region A2 from the logic device region A3, and the shallow trench isolation structure STI3 is used, for example, to separate the logic device region A3 from another device region (not shown). In some embodiments, the shallow trench isolation structures STI can be formed by first performing an etching process to form a plurality of trenches in the substrate SB, and then performing a chemical vapor deposition process to form an insulating material in the plurality of trenches, although the present invention is not limited thereto.

[0016] The memory material layer may include, for example, a floating gate 110, an erase gate 120, a first oxide layer OL1, a first nitride layer NL1, a second oxide layer OL2, a second nitride layer NL2, and a third oxide layer OL3, but the present invention is not limited thereto.

[0017] The floating gate 110 is disposed on, for example, the dielectric layer IL1. In some embodiments, the material of the floating gate 110 includes polysilicon, although the invention is not limited thereto.

[0018] The erase gate 120 is, for example, disposed on one side of the floating gate 110. In some embodiments, the material of the erase gate 120 includes polysilicon, although the invention is not limited thereto.

[0019] The memory material layer may further include a conductive material layer CL located in the memory element region A1 and the high-voltage element region A2. The conductive material layer CL is disposed on the dielectric layer IL1. The conductive material layer CL located in the memory element region A1 may be formed as a word line material layer after subsequent processing, and the conductive material layer CL located in the high-voltage element region A2 may be formed as a gate material layer after subsequent processing. In some embodiments, the conductive material layer CL may include polysilicon, but the present invention is not limited thereto. In other embodiments, the conductive material layer CL, the floating gate 110, and the erase gate 120 may belong to the same layer.

[0020] The first oxide layer OL1 is, for example, disposed on the floating gate 110. In this embodiment, the first oxide layer OL1 covers the floating gate 110. In some embodiments, the material of the first oxide layer OL1 includes silicon oxide, but the present invention is not limited thereto.

[0021] The first nitride layer NL1 is disposed on the first oxide layer OL1, for example. In some embodiments, the material of the first nitride layer NL1 includes silicon nitride, but the invention is not limited thereto. Note that the first nitride layer NL1 is also disposed in the logic element region A3 and covers the dielectric layer IL1, but the invention is not limited thereto.

[0022] The second oxide layer OL2 is disposed, for example, on the first nitride layer NL1. In this embodiment, the second oxide layer OL2 covers the first nitride layer NL1 and the erase gate 120. In some embodiments, the material of the second oxide layer OL2 includes silicon oxide, although the invention is not limited thereto. Note that the second oxide layer OL2 is also disposed in the high-voltage element region A2 and the logic element region A3, although the invention is not limited thereto.

[0023] The second nitride layer NL2 is disposed on the second oxide layer OL2, for example. In some embodiments, the material of the second nitride layer NL2 includes silicon nitride, but the invention is not limited thereto. Note that the second nitride layer NL2 is also disposed in the high-voltage element region A2 and the logic element region A3, but the invention is not limited thereto.

[0024] The third oxide layer OL3 is disposed on the second nitride layer NL2, for example. In some embodiments, the material of the third oxide layer OL3 includes silicon oxide, but the invention is not limited thereto. The third oxide layer OL3 may also be disposed in the high-voltage element region A2 and the logic element region A3, but the invention is not limited thereto.

[0025] Step (2) is performed: a first groove R1 is formed in the memory material layer.

[0026] 1B , in some embodiments, an etching process can be performed to form a first trench R1 in the memory material layer. In this embodiment, the first trench R1 exposes a portion of the first nitride layer NL1. Specifically, the etching process can be performed to sequentially remove the third oxide layer OL3, the second nitride layer NL2, and a portion of the second oxide layer OL2. Because the material of the second oxide layer OL2 and the material of the first nitride layer NL1 have different etching selectivities, the first nitride layer NL1 can be used as an etch stop layer in this etching process.

[0027] In addition, in the process of forming the first groove R1, the third oxide layer OL3, the second nitride layer NL2, and the second oxide layer OL2 located in the logic element region A3 can also be removed simultaneously, but the present invention is not limited to this.

[0028] Step (3) is performed: a second groove R2 is formed in the memory material layer.

[0029] Continuing to refer to FIG. 1B , in some embodiments, an etching process can be performed to form a second trench R2 in the memory material layer. In this embodiment, the second trench R2 and the first trench R1 overlap in the normal direction Z of the substrate SB to form an opening OP. Specifically, the second trench R2 is formed by performing an etching process on the first nitride layer NL1 exposed by the first trench R1. In this embodiment, the width of the second trench R2 in the direction X is smaller than the width of the first trench R1 in the direction X. In this embodiment, the second trench R2 exposes a portion of the first oxide layer OL1. Specifically, the above etching process can be performed to remove the first nitride layer NL1. Because the material of the first nitride layer NL1 and the material of the first oxide layer OL1 have different etching selectivities, the first oxide layer OL1 can be used as an etch stop layer in this etching process.

[0030] Step (4) is performed: an inter-gate oxide layer 130 is formed in the opening OP.

[0031] 1C , in some embodiments, an appropriate deposition process can be performed to form an inter-gate oxide layer 130 on the floating gate 110, although the present invention is not limited thereto. The inter-gate oxide layer 130 can include, for example, a composite structure. In this embodiment, the inter-gate oxide layer 130 includes three dielectric layers stacked sequentially. For example, the inter-gate oxide layer 130 can include an oxide-nitride-oxide (ONO) composite layer, although the present invention is not limited thereto. In other embodiments, the inter-gate oxide layer 130 can include a single-layer structure, and the material thereof can be silicon oxide.

[0032] Step (5) is performed: a dummy gate structure 200a is formed in the opening OP.

[0033] With continued reference to FIG. 1C, in some embodiments, but not limited to, a method for forming a dummy gate structure 200a in an opening OP includes the following steps.

[0034] First, a high-k dielectric layer 210 is formed on the sidewall of the opening OP. In some embodiments, the high-k dielectric layer 210 can be formed by a suitable deposition process, but the present invention is not limited thereto. The material of the high-k dielectric layer 210 can include, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (YO3), zirconium oxide (ZrO2), or other suitable high-k materials. In this embodiment, the material of the high-k dielectric layer 210 is hafnium oxide, but the present invention is not limited thereto. Note that in this embodiment, the high-k dielectric layer 410 is simultaneously formed in the logic element region A3 during the process of forming the high-k dielectric layer 210, but the present invention is not limited thereto. Furthermore, before forming the high-k dielectric layer 410, a buffer layer (not shown) can be formed in the logic element region A3 to buffer the high-k dielectric layer 410 from the substrate SB.

[0035] Next, a bottom barrier layer 220 is formed on the high-k dielectric layer 210. In some embodiments, the bottom barrier layer 220 can be formed by performing an appropriate deposition process, but the present invention is not limited thereto. The material of the bottom barrier layer 220 can include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In this embodiment, the bottom barrier layer 220 has a multi-layer structure. Specifically, the bottom barrier layer 220 can include a first bottom barrier layer 222 and a second bottom barrier layer 224, where the material of the first bottom barrier layer 222 can be titanium nitride and the material of the second bottom barrier layer 224 can be tantalum nitride, but the present invention is not limited thereto. Note that in this embodiment, during the process of forming the bottom barrier layer 220, a bottom barrier layer 420 including a first bottom barrier layer 422 and a second bottom barrier layer 424 is simultaneously formed in the logic element region A3, but the present invention is not limited thereto.

[0036] Then, a dummy gate 230a is formed on the bottom barrier layer 220. In some embodiments, the dummy gate 230a can be formed by performing an appropriate deposition process, but the present invention is not limited thereto. The material of the dummy gate 230a can include, for example, polysilicon. Note that in this embodiment, the process of forming the dummy gate 230a simultaneously forms a dummy gate 430a in the logic element region A3, but the present invention is not limited thereto.

[0037] In some embodiments, the method may further include removing a portion of the dummy gate 230a to form a groove, where the bottom of the groove is substantially flush with the bottom of the second nitride layer NL2. Then, a first sacrificial layer SA1 and a second sacrificial layer SA2 are sequentially formed in the groove, where the first sacrificial layer SA1 is made of silicon nitride and the second sacrificial layer SA2 is made of silicon oxide. In this embodiment, the first sacrificial layer SA1 and the second sacrificial layer SA2 are also formed in the logic element region A3, but the present invention is not limited thereto.

[0038] At this point, the fabrication of the dummy gate structure 200a is completed. Although the above method has been described as an example of the method for fabricating the dummy gate structure 200a in this embodiment, the method for fabricating the dummy gate structure of the present invention is not limited to this.

[0039] Step (6) is performed: A part of the dummy gate structure 200a is removed to form a dummy gate structure 200b.

[0040] 1D , in some embodiments, an etching process may be performed to remove a portion of the high-k dielectric layer 210, a portion of the bottom barrier layer 220, and a portion of the dummy gate 230a to form a dummy gate structure 200b. Note that the first sacrificial layer SA1 and the second sacrificial layer SA2 are also removed during this etching process. In this embodiment, the remaining second nitride layer NL2 and third oxide layer OL3 are also removed during this etching process, exposing a portion of the second oxide layer OL2.

[0041] It should be noted that the method further includes subsequent steps after forming the dummy gate structure 200b.

[0042] First, a patterning process is performed on the second oxide layer OL2, the conductive material layer CL, and the dielectric layer IL1 to form the word lines 140 and the tunnel dielectric layer 150 in the memory element region A1. Here, the word lines 140 are part of the conductive material layer CL, and the tunnel dielectric layer 150 is part of the dielectric layer IL1. Simultaneously with the patterning process, a high-voltage element 300 is formed in the high-voltage element region A2. Specifically, the high-voltage element 300 includes, for example, a gate 302, a gate oxide layer 304, and a gap wall 306. Here, the gate 302 is part of the conductive material layer CL, the gate oxide layer 304 is part of the dielectric layer IL1, and the gap wall 306 is part of the dielectric layer IL2. The second oxide layer OL2 that has been subjected to the patterning process can be formed as the dielectric layer 310.

[0043] An appropriate deposition process may then be performed to form sidewalls 440 in logic element region A3, which flank high-k dielectric layer 410, bottom barrier layer 420, and dummy gate 430a.

[0044] A suitable deposition process is then performed to form a conformal dielectric layer IL2 in the memory device region A1, the high-voltage device region A2, and the logic device region A3. In some embodiments, the material of the dielectric layer IL2 includes silicon nitride, but the invention is not limited thereto. The dielectric layer IL2 can be used, for example, as a gap wall for subsequent devices, which will be described in detail in the following embodiments.

[0045] Then, a suitable deposition or spin-coating process is performed to form the dielectric layer IL3. In this embodiment, the dielectric layer IL3 exposes portions of the dielectric layer IL2 located in the memory device region A1, the high-voltage device region A2, and the logic device region A3, respectively, and has an upper surface that is substantially flush with these dielectric layers IL2. In some embodiments, the material of the dielectric layer IL3 includes silicon oxide, although the present invention is not limited thereto.

[0046] Step (7) is performed: the dummy gate structure 200b is replaced with the control gate structure 200 to form the memory element 100.

[0047] Referring to FIG. 1E, in some embodiments, but not limited to, a method for replacing the dummy gate structure 200b with the control gate structure 200 includes the following steps.

[0048] First, a planarization process is performed to remove a portion of the dielectric layer IL3 and a portion of the dielectric layer IL2 to expose the dummy gate 230a.

[0049] Next, a metal gate replacement process (RMG) is performed to replace the dummy gate 230a with the metal gate 230. In this embodiment, the metal gate 230 includes a work function metal layer 232, an upper barrier layer 234, and a low-resistance material layer 236, in that order, although the present invention is not limited thereto. The material of the work function metal layer 232 may include, for example, a binary composite metal. For example, the material of the work function metal layer 232 may include titanium aluminum (TiAl), zirconium aluminum (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), hafnium aluminum (HfAl), or other suitable composite metals. In this embodiment, the material of the work function metal layer 232 is aluminum titanium, although the present invention is not limited thereto. The material of the upper barrier layer 234 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In this embodiment, the material of the upper barrier layer 234 is a combination of titanium and titanium nitride, but the present invention is not limited thereto. The material of the low-resistivity material layer 236 may include, for example, aluminum (Al), tungsten (W), copper (Cu), or a combination thereof. In this embodiment, the material of the low-resistivity material layer 236 is aluminum, but the present invention is not limited thereto.

[0050] At this point, the fabrication of replacing the dummy gate structure 200b with the control gate structure 200 is completed. Although the manufacturing method of replacing the dummy gate structure 200b with the control gate structure 200 in this embodiment has been described above as an example, the manufacturing method of the replacement dummy gate structure and control gate structure of the present invention is not limited to this.

[0051] At the same time as performing the above metal gate replacement process, the dummy gate 430a located in the logic element region A3 is replaced with a metal gate 430 to form the logic element 400. In detail, the metal gate 430 may include, for example, a work function metal layer 432, an upper barrier layer 434, and a low resistance material layer 436, in that order, but the present invention is not limited thereto.

[0052] Step (8) is performed: forming an interconnect structure 500 on the substrate SB, where the interconnect structure 500 is electrically connected to the memory device 100, the high-voltage device 300, and the logic device 400;

[0053] Referring to FIG. 1F, in this embodiment, the interconnect structure 500 includes a dielectric layer IL4 and a plurality of conductive vias V.

[0054] In some embodiments, the dielectric layer IL4 can be formed by a chemical vapor deposition process, a spin-coating process, or other suitable process, but the invention is not limited thereto. The material of the dielectric layer IL4 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, polyimide, or other suitable material, but the invention is not limited thereto.

[0055] The plurality of conductive vias V may be disposed within, for example, the dielectric layer IL4 and may each penetrate, for example, the dielectric layer IL4. In some embodiments, the plurality of conductive vias V may be formed by performing a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, or other suitable process, but the invention is not limited thereto. In this embodiment, the plurality of conductive vias V includes conductive vias V1, V2, and V3. The conductive via V1 may be electrically connected to, for example, the control gate structure 200 of the memory element 100. The conductive via V2 may further penetrate, for example, the dielectric layer 310 and be electrically connected to, for example, the gate 302 of the high-voltage element 300. The conductive via V3 may be electrically connected to, for example, the metal gate 430 of the logic element 400. The material of the plurality of conductive vias V may include, for example, a suitable conductive material. For example, the material of the plurality of conductive vias V may include, for example, copper, titanium, tungsten, tantalum, titanium nitride, tantalum nitride, polysilicon, or a combination thereof, but the invention is not limited thereto.

[0056] At this point, the method for fabricating the semiconductor structure 10 in this embodiment is completed, but the method for fabricating the semiconductor structure 10 provided by the present invention is not limited thereto. In this embodiment, the semiconductor structure 10 includes a memory device 100, which is a type of embedded flash (E-flash) memory device. Forming the control gate structure 200 can relatively improve the write efficiency of the memory device 100.

[0057] 2A is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention, and FIG. 2B is a schematic cross-sectional view of a control gate structure according to an embodiment of the present invention. Hereinafter, the structure of the semiconductor structure 10 in this embodiment will be briefly introduced with reference to FIG. 1F, FIG. 2A, and FIG. 2B, but the present invention is not limited thereto.

[0058] 1F and 2A, the semiconductor structure 10 in this embodiment includes a substrate SB and a memory device 100. As shown in FIG.

[0059] The substrate SB is, for example, a silicon substrate, but the present invention is not limited thereto. In this embodiment, the substrate SB includes a memory device region A1, a high-voltage device region A2, and a logic device region A3. The high-voltage element region A2 is located between the memory element region A1 and the logic element region A3 in the direction X, but the present invention is not limited thereto. The remaining description of the substrate SB can refer to the above embodiment and will not be described again here.

[0060] The memory device 100 is disposed on, for example, a substrate SB and is located in a memory device region A1 of the substrate SB. The memory device 100 is, for example, a type of embedded flash (E-flash) memory device. In this embodiment, the memory device 100 includes a floating gate 110, a tunnel dielectric layer 150, a control gate structure 200, an inter-gate oxide layer 130, an erase gate 120, and a word line 140.

[0061] The floating gate 110 is disposed on, for example, a substrate SB. The floating gate 110 may be used to store hot electrons, for example, and may have the function of storing data. The remaining description of the floating gate 110 can refer to the above embodiment, and will not be described again here.

[0062] The tunnel dielectric layer 150 is, for example, disposed on the substrate SB, and is, for example, located between the floating gate 110 and the substrate SB. The tunnel dielectric layer 150 may, for example, be used to tunnel hot electrons when a corresponding voltage is applied to the memory element 100. The remaining description of the tunnel dielectric layer 150 can refer to the above embodiment, and will not be described again here.

[0063] The control gate structure 200 is disposed on, for example, the floating gate 110. For example, hot electrons can tunnel to the floating gate 110 by applying a voltage to the control gate structure 200. Referring to Figures 2A and 2B, in this embodiment, a width WT of a top portion 200T of the control gate structure 200 in the direction X is greater than a width WB of a bottom portion 200B of the control gate structure in the direction X. Specifically, since the control gate structure 200 is disposed in an opening OP formed by the first groove R1 and the second groove R2, the control gate structure 200 may include a top portion 200T and a bottom portion 200B having different widths.

[0064] 2A and 2B simultaneously, the control gate structure 200 in this embodiment includes a high-k dielectric layer 210, a bottom barrier layer 220, a work function metal layer 232, an upper barrier layer 234 and a low resistance material layer 236.

[0065] The high-k dielectric layer 210 is, for example, conformally disposed on the sidewall of the opening OP and has, for example, a neckline shape. In this embodiment, the material of the high-k dielectric layer 210 is hafnium oxide, but the present invention is not limited thereto. The remaining description of the high-k dielectric layer 210 can refer to the above embodiment and will not be described again here.

[0066] The bottom barrier layer 220 is, for example, conformally disposed on the high-k dielectric layer 210 and has, for example, a neckline shape. In this embodiment, the bottom barrier layer 220 includes a first bottom barrier layer 222 and a second bottom barrier layer 224, where the material of the first bottom barrier layer 222 is titanium nitride and the material of the second bottom barrier layer 224 is tantalum nitride, but the present invention is not limited thereto. The remaining description of the bottom barrier layer 220 can refer to the above embodiment and will not be described again here.

[0067] The work function metal layer 232 is disposed on the bottom barrier layer 220, and has a U-shape, for example. In this embodiment, the material of the work function metal layer 232 is aluminum titanium, but the present invention is not limited thereto. The remaining description of the work function metal layer 232 can refer to the above embodiment, and will not be described again here.

[0068] The upper barrier layer 234 is disposed on the work function metal layer 232, and has a U-shape, for example. In this embodiment, the material of the upper barrier layer 234 is a combination of titanium and titanium nitride, but the present invention is not limited thereto. The remaining description of the upper barrier layer 234 can be referred to in the above embodiment, and will not be described again here.

[0069] The low-resistance material layer 236 is disposed on the upper barrier layer 234, for example, and is filled in the opening OP, for example. In this embodiment, the material of the low-resistance material layer 236 is aluminum, but the present invention is not limited thereto. The remaining description of the low-resistance material layer 236 can refer to the above embodiment, and will not be described again here.

[0070] In this embodiment, the work function metal layer 232, the upper barrier layer 234 and the low resistance material layer 236 can be formed as a metal gate 230, but the present invention is not limited thereto.

[0071] The inter-gate oxide layer 130 is disposed, for example, between the floating gate 110 and the control gate structure 200. The inter-gate oxide layer 130 can be used, for example, to electrically insulate the floating gate 110 and the control gate structure 200 from each other. In this embodiment, the inter-gate oxide layer 130 includes an oxide-nitride-oxide (ONO) composite layer, but the present invention is not limited thereto. The remaining description of the inter-gate oxide layer 130 can refer to the above embodiment, and will not be described again here.

[0072] The erase gate 120 is disposed, for example, on one side of the floating gate 110. The erase gate 120 may have a function of erasing hot electrons accumulated in the floating gate 110. The remaining description of the erase gate 120 can refer to the above embodiment, and will not be described again here.

[0073] The word line 140 is disposed, for example, on the other side of the floating gate 110. By applying a write voltage or a read voltage to the word line 140, a corresponding write operation or a read operation can be performed on the memory device 100, but the present invention is not limited thereto. The remaining description of the word line 140 can refer to the above embodiment, and will not be described again here.

[0074] The gap wall 160 is disposed, for example, on one side of the word line 140 away from the floating gate 110. In this embodiment, the gap wall 160 is part of the dielectric layer IL2, but the present invention is not limited thereto.

[0075] In this embodiment, the semiconductor structure 10 further includes a high voltage device 300 and a logic device 400 .

[0076] The high-voltage element 300 is disposed, for example, in the high-voltage element region A2. In this embodiment, the high-voltage element 300 is a type of transistor. For example, the high-voltage element 300 includes a gate 302, a gate oxide layer 304, and gap walls 306, where the gate oxide layer 304 is disposed between the gate 302 and the substrate SB, and the gap walls 306 are disposed on both sides of the gate 302, but the present invention is not limited thereto. The remaining description of the high-voltage element 300 can refer to the above embodiment, and will not be described again here.

[0077] The logic element 400 is disposed within the logic element region A3, for example. In this embodiment, the logic element 400 is a type of transistor. For example, the logic element 400 includes a high-k dielectric layer 410, a bottom barrier layer 420, a metal gate 430, sidewalls 440, and gap walls 450. Here, the high-k dielectric layer 410 is disposed on a substrate SB, the bottom barrier layer 420 is disposed on the high-k dielectric layer 410, and the metal gate 430 is disposed on the bottom barrier layer 420, but the present invention is not limited thereto. The bottom barrier layer 420 includes, for example, a first bottom barrier layer 422 and a second bottom barrier layer 424. The metal gate 430 includes, for example, a work function metal layer 432, an upper barrier layer 434, and a low-resistance material layer 436. The sidewalls 440 are disposed on both sides of the high-k dielectric layer 410, the bottom barrier layer 420, and the metal gate 430. The gap wall 450 is disposed, for example, on one side of the sidewall 440, away from the metal gate 430. The remaining description of the logic device 400 can refer to the above embodiment, and will not be described again here.

[0078] In this embodiment, the semiconductor structure 10 may further include an interconnect structure 500 .

[0079] 2A and 2B simultaneously, the interconnect structure 500 includes, for example, a dielectric layer IL4 and a plurality of conductive vias V. The plurality of conductive vias V are disposed, for example, in the dielectric layer IL4 and each penetrate, for example, the dielectric layer IL4. In this embodiment, the plurality of conductive vias V include conductive vias V1, V2, V3, V4, and V5. The conductive via V1 is, for example, electrically connected to the control gate structure 200 of the memory element 100. The conductive via V2 is, for example, electrically connected to the gate 302 of the high-voltage element 300. The conductive via V3 is, for example, electrically connected to the metal gate 430 of the logic element 400. The conductive via V4 is, for example, electrically connected to the erase gate 120 of the memory element 100. The conductive via V5 is, for example, electrically connected to the word line 140 of the memory element 100.

[0080] In summary, the semiconductor structure and fabrication method provided by the present invention can improve the write efficiency of the memory element of the present invention compared to conventional embedded flash memory elements by forming a control gate structure including a high-k dielectric layer and a metal gate in the memory element.

[0081] Furthermore, in the semiconductor structure manufacturing method provided by the present invention, the high-k dielectric layer and the metal gate can be formed in the same process as the remaining film layers in the logic element region, meaning that no additional processes are required to form the high-k dielectric layer and the metal gate, and therefore the semiconductor structure manufacturing method of the present invention does not require additional manufacturing costs. [Industrial Applicability]

[0082] The semiconductor structure and fabrication method of the present invention can be applied to an embedded flash memory device and fabrication method thereof. [Explanation of symbols]

[0083] 10: Semiconductor structure 100: Memory element 110: Floating Gate 120:Erase Gate 130: Gate oxide layer 140: Word line 150: Tunnel dielectric layer 160, 306, 450: Gap wall 200: Control gate structure 200a, 400a: Dummy gate structure 200B: Bottom part 200T: Upper part 210, 410: High-k dielectric layer 220, 420: bottom barrier layer 222, 422: first bottom barrier layer 224, 424: second bottom barrier layer 230, 430: Metal gate 230a, 430a: Dummy gate 232: Work function metal layer 234: Upper barrier layer 236:Low resistance material layer 300: High voltage element 302: Gate 304: Gate oxide layer 310: Dielectric layer 400: Logic elements 440: Side wall 500: Interconnection Structure A1: Memory element area A2: High voltage element area A3: Logic element area CL: Conductive material layer IL1, IL2, IL3, IL4: dielectric layers LO: Locally oxidized silicon structure NL1: First nitride layer NL2: second nitride layer OL1: First oxide layer OL2: second oxide layer OL3: Third oxide layer OP: Opening R1: First groove R2: Second groove SA1: First sacrificial layer SA2: Second sacrificial layer SB:Substrate STI, STI1, STI2, STI3: shallow separation structure V, V1, V2, V3, V4, V5: Conductivity WB, WT: width X: Direction Z: Normal direction

Claims

1. A substrate; a memory element disposed on the substrate, a floating gate disposed on the substrate; a tunnel dielectric layer disposed between the floating gate and the substrate; a control gate structure disposed on the floating gate, the control gate structure including a high-k dielectric layer and a metal gate, the control gate structure having a width at a top portion thereof greater than a width at a bottom portion thereof; an inter-gate oxide layer disposed between the floating gate and the control gate structure; an erase gate disposed on one side of the floating gate; a word line disposed on the other side of the floating gate; the memory element including Semiconductor structure.

2. The control gate structure comprises: a bottom barrier layer disposed on the high-k dielectric layer; further comprising: The semiconductor structure of claim 1 .

3. The metal gate is a work function metal layer disposed on the bottom barrier layer; an upper barrier layer disposed on the work function metal layer; a low resistance material layer disposed on the upper barrier layer; Including, The semiconductor structure of claim 2 .

4. The bottom barrier layer comprises: a first bottom barrier layer, the material of which includes titanium nitride; a second bottom barrier layer disposed on the first bottom barrier layer, the second bottom barrier layer being made of tantalum nitride; Including, The semiconductor structure of claim 2 .

5. high voltage and logic devices disposed on the substrate; a first isolation structure disposed in the substrate and positioned between the high voltage element and the memory element; a second isolation structure located between the logic element and the high voltage element; further comprising: The semiconductor structure of claim 1 .

6. forming a memory material layer over a substrate, the memory material layer including a floating gate, an erase gate, a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer, and a third oxide layer; forming a first trench in the memory material layer, the first trench exposing a portion of the first nitride layer; forming a second trench in the layer of memory material, the second trench and the first trench overlapping to form an opening, the second trench exposing a portion of the floating gate; forming an inter-gate oxide layer in the opening; forming a dummy gate structure in the opening, the dummy gate structure including a high-k dielectric layer; and replacing the dummy gate structure with a control gate structure including a metal gate to form a memory element; a width at a top portion of the control gate structure is greater than a width at a bottom portion of the control gate structure; A method for manufacturing a semiconductor structure.

7. forming the dummy gate structure in the opening, forming the high-k dielectric layer on the sidewalls of the opening; forming a bottom barrier layer on the high-k dielectric layer; forming a dummy gate on the bottom barrier layer; Including, The method of manufacturing a semiconductor structure according to claim 6.

8. the memory material layer further includes a word line material layer, and in the step of forming the dummy gate on the bottom barrier layer, the word line material layer is patterned to form a word line. The method of manufacturing a semiconductor structure according to claim 7.

9. forming the bottom barrier layer on the high-k dielectric layer, forming a first bottom barrier layer on the high-k dielectric layer, wherein a material of the first bottom barrier layer comprises titanium nitride; forming a second bottom barrier layer on the first bottom barrier layer, wherein a material of the second bottom barrier layer comprises tantalum nitride; Including, The method of manufacturing a semiconductor structure according to claim 7.

10. The step of replacing the dummy gate structure with the control gate structure including the metal gate includes: removing the dummy gate; forming a work function metal layer on the bottom barrier layer; forming an upper barrier layer on the work function metal layer; forming a low resistance material layer on the upper barrier layer; Including, The method of manufacturing a semiconductor structure according to claim 7.

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