transistor

Abstract

To provide a field effect transistor (FET) which is used in a microfabricated semiconductor integrated circuit and has a small off-current.SOLUTION: The field-effect transistor includes a flaky oxide semiconductor having a thickness of 1 nm or more and 30 nm or less and formed substantially perpendicularly to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate having a stripe shape and a width of 10 nm or more and 100 nm or less formed to cover the gate insulating film. In this structure, since the gate covers three sides of the thin piece-like oxide semiconductor, electrons injected from the source and the drain can be efficiently removed, a region between the source and the drain can be substantially depleted, and the off-state current can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor and a semiconductor device using the same. [Background technology]

[0002] Conventionally, field effect transistors (FETs) used in semiconductor integrated circuits have been silicon These have been formed from semiconductors such as (for example, see Non-Patent Document 1). Field-effect transistors using oxide semiconductors with a capacitance of 2.5 eV or more have been reported. In particular, by extremely reducing the donor concentration in the semiconductor layer, the off-state current can be reduced to a level lower than that of a normal semiconductor layer. It has become clear that the concentration can be reduced to a level that cannot be measured by the method (for example, Patent Document See 1).

[0003] For example, in a silicon FET, the off-state current per 1 μm of channel width is typically 1× 10 -15 A / μm or more, whereas indium-gallium-zinc oxide (In- FETs using Ga-Zn oxide semiconductors are 1×10 -18 A / μm or less This is because the band gap is large and thermally excited carriers are extremely small in intrinsic semiconductors. This is because the concentration is low, and if the band gap is 3 eV or more, the theoretical off-state potential is The lower limit of the flow is 1×10 -31 A / μm or less.

[0004] Such an FET with extremely low off-state current is configured with one FET and one capacitor. If used in dynamic random access memory (1T1C type DRAM), The refresh interval can be made long enough. Ideally, refresh should be semi-permanent. Data can be retained without the need for a manual reset (see Patent Document 2).

[0005] In addition, a gain cell type memory ( If this method is used in a semiconductor memory device (see Patent Document 3), it can be made semi-permanently non-volatile. The gain cell type memory that has been used up to now does not require a large-capacity capacitor, so it is suitable for 1T1C type DRs. It has been considered as a way to compensate for the shortcomings of AM, but in many cases, it is difficult to reduce the off-current sufficiently. It was never put into practical use because it was not possible to [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent Publication No. 2011 / 0148455 [Patent Document 2] US Patent Publication No. 2011 / 0156027 [Patent Document 3] U.S. Patent No. 7,468,901 [Non-patent literature]

[0007] [Non-Patent Document 1] Hisamoto et al. “A Folded-channel MOSFET for Deep-sub-tenth Micron Era”, IEDM Tech. Dig., pp.1032―1034, 1998. Summary of the Invention [Problem to be solved by the invention]

[0008] However, as a result of the research of the present inventors, it has been found that such an extremely low off-current can be obtained when the channel length is This can be achieved only when the channel length is sufficiently long, but when the channel length is 100 nm or less, It was found that this was difficult to achieve due to the effects.

[0009] The reason for this will be explained using Figure 10. Figure 10(A) shows the case where the channel length is sufficiently long. The oxide semiconductor film 201a is provided with a source 204a and a drain 202b that are in ohmic contact with the oxide semiconductor film 201a. However, if the work function of the gate 203a is 5 By setting the potential at 0.2 eV or more, the electrons are removed from the oxide semiconductor 201a. As a result, a depleted region 206a without electrons can be formed over a wide area.

[0010] The presence of the depleted region 206a reduces the current between the source 204a and the drain 205a. This can prevent electrons from entering the gate, resulting in an extremely low off-state current. In this case, the thinner the gate insulating film 202a is and the higher the dielectric constant is, and the work function of the gate 203a is, the better. The larger the number, the more effective it is.

[0011] FIG. 10B shows the case where only the channel length is shortened without changing the thickness of the oxide semiconductor. In this case, the lower part of the oxide semiconductor 201b (the opposite side of the gate insulating film 202b) ), the gate action does not reach, and the electron concentration cannot be reduced sufficiently. In the compound semiconductor 201b, a depleted region 206b is formed on the gate 203b side. As a result, the source 204b and the drain 204c are not Therefore, the current between the electrodes 205b cannot be sufficiently blocked.

[0012] This problem can be solved by making the oxide semiconductor 201b as thin as possible. However, if the thickness is less than 1 nm, the semiconductor characteristics of the oxide semiconductor 201b may deteriorate. In particular, when the oxide semiconductor 201b has a certain crystal structure, a problem may occur in the performance. In some cases, the required crystallinity may not be obtained.

[0013] Even with silicon FETs, the channel length becomes shorter, which leads to an increase in off-state current and a decrease in the sub-channel current. The deterioration of threshold characteristics is known as the short channel effect, but in oxide semiconductors, This is because in silicon FETs, the source and channel formation regions, or The drain and channel forming regions can be separated by a PN junction, but the oxide In semiconductors, a PN junction is formed to separate the channel from the source or drain. This is because it is difficult to do so.

[0014] Generally, in a silicon FET, for example, the source and drain are made of high-concentration N-type. In this case, the channel forming region is also made P-type with an appropriate concentration. This prevents electrons from being injected into the channel from the source or drain. If the concentration of P-type impurities in the hole formation region is high, the effect of preventing electron injection becomes stronger. Therefore, in a silicon FET, if the channel length is shortened, the impurities in the channel formation region The short channel effect can be suppressed by increasing the concentration.

[0015] In contrast, in many cases, oxide semiconductors can be doped to become semiconducting, as in silicon. It is difficult to control the conductivity type of the material. For example, N-type semiconductors can be made from oxides containing zinc, such as zinc oxide. Therefore, it is not possible to fabricate a P-type semiconductor. A technique of forming a highly doped P-type region cannot be adopted.

[0016] In order to advance miniaturization, it is essential to shorten the channel length, and even with a short channel It is desirable to obtain a sufficiently low off-state current. One of the objectives of the present invention is to provide a FET that can avoid an increase in off-state current due to the use of a multi-layer structure. Another object of one embodiment of the present invention is to provide a sufficiently miniaturized FET. Another object of one embodiment of the present invention is to provide a semiconductor device including an FET. An object of one aspect of the present invention is to provide a method for manufacturing a FET or a semiconductor device. The present invention solves at least one of the above problems. [Means for solving the problem]

[0017] In one aspect of the present invention, the thickness is 1 nm or more and 30 nm or less, preferably 3 nm or more and 5 nm or less. , the height is at least one time the minimum feature size, and it is approximately perpendicular to the insulating surface. a thin oxide semiconductor formed on the substrate; and a gate insulating film formed on the thin oxide semiconductor. The stripe-shaped film formed covering the gate insulating film has a width of 10 nm to 100 nm, preferably It is an FET having a gate of 10 nm or more and 30 nm or less. "Approximately perpendicular" means that the angle is between 70° and 110° relative to the target surface. say.

[0018] In one embodiment of the present invention, the thickness is 1 nm or more and 30 nm or less, preferably 3 nm or more and 5 nm or less. The height is equal to or greater than the minimum processed line width, and the flake-like oxide is formed almost perpendicular to the insulating surface. a source and a drain in contact with at least three sides of the oxide semiconductor; The FET has a gate insulating film formed over the semiconductor. The spacing between the lines is 10 nm or more and 100 nm or less, preferably 10 nm or more and 30 nm or less. It is recommended to use ET.

[0019] In the above, the oxide semiconductor may be indium oxide, zinc oxide, or tin oxide. In addition, binary metal oxides, such as In-Zn oxides and Sn-Zn oxides, are also suitable. , Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide Alternatively, an In—Sn-based oxide or an In—Ga-based oxide may be used. For example, In-Ga oxides are oxides containing indium (In) and gallium (Ga), It means an oxide containing 5 atomic % or more, and other elements may also be included.

[0020] For example, when using an In-Zn oxide, indium (In) and zinc (Zn) are mixed as In / Zn=0.5 to 50, preferably In / Zn=1 to 20, more preferably In / Zn= An oxide semiconductor can be formed using an oxide target containing 1.5 to 15% of the oxide. The target used for forming the In-Zn oxide has an atomic ratio of In:Zn:O. When the ratio is x:y:z, it is recommended that z>1.5x+y. This can improve the mobility of the FET.

[0021] Similarly, oxide semiconductors include ternary metal oxides such as In-Ga-Zn oxide and I n-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al -Ga-Zn oxides, Sn-Al-Zn oxides, etc. can be used. Furthermore, a quaternary metal oxide, such as an In-Sn-Ga-Zn oxide, may also be used.

[0022] Here, for example, In-Ga-Zn oxide is a compound of indium (In) and gallium (Ga It means oxides containing 3.3 atomic percent or more of zinc (Zn) and other elements. In the case of In-Sn-Ga-Zn oxides, indium (I Contains 2.5 atomic percent or more of tin (Sn), gallium (Ga), and zinc (Zn) It means an oxide, and other elements may be included.

[0023] In addition, the oxide semiconductor may have a crystalline region. The crystals preferably have a c-axis that is approximately perpendicular to the oxide semiconductor surface. The area where the gate is provided on the surface or the area covered by the gate has crystallinity. It is preferable to do so.

[0024] Such crystals can be triangular, hexagonal, equilateral triangular, or equilateral hexagonal when viewed perpendicular to the ab plane. A phase in which metal atoms are arranged in layers in the c-axis direction, or The metal atoms and oxygen atoms may be arranged in layers. An oxide semiconductor having crystals that are nearly perpendicular is called C-Axis Aligned Crystal. It is called Line Oxide Semiconductor (CAAC-OS).

[0025] In addition, in the above, a part of the oxide semiconductor has a region containing nitrogen, boron, or phosphorus. In particular, these regions may be formed automatically by means of ion implantation or the like using the gate as a mask. The oxide semiconductor may be formed in a self-aligned manner. Metal elements that have the ability to absorb electrons, such as copper, or elements that have the ability to form peroxides, The metal element may be contained in an amount of 0.1 atomic % to 5 atomic %.

[0026] In the above, the gate insulating film is made of silicon oxide, tantalum oxide, hafnium oxide, or oxide. aluminum oxide, yttrium oxide, lanthanum oxide, hafnium silicate, silicon oxynitride, It may include one or more materials selected from silicon nitride.

[0027] In the above, the gate insulating film contains 50 atomic % or more of elements other than oxygen. is selected from silicon, tantalum, hafnium, aluminum, yttrium, and lanthanum It may also be made of oxides of one or more elements.

[0028] In this specification, the term "metal element" refers to rare gas elements, hydrogen, boron, carbon, nitrogen, and Group 16 elements ( Oxygen, etc.), Group 17 elements (fluorine, etc.), silicon, phosphorus, germanium, arsenic, antimony, etc. Oxides are all elements other than metals. This refers to compounds in which the atomic percentage is 50 atomic % or more.

[0029] Another embodiment of the present invention is a memory using one or more of the above-described FETs. Examples of the memory include a T1C type RAM and a gain cell type memory. An embodiment is a central processing unit (CPU) having a register formed using the above-described FET. , or other semiconductor circuits such as semiconductor integrated circuits (LSI). [Effects of the Invention]

[0030] In the above structure, the gate covers three surfaces of the thin oxide semiconductor. The source and drain are efficiently removed from the oxide semiconductor. Most of the area between the gate and gate electrodes can be made into a depleted region, thereby reducing the off-current. [Brief explanation of the drawings]

[0031] [Figure 1] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 2] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 3] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 4] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 5] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 6] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 7] 1A and 1B illustrate an example of a FET according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate an example of a method for manufacturing a FET according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate an example of a method for manufacturing a FET according to one embodiment of the present invention. [Figure 10] FIG. 1 is a diagram illustrating an example of a conventional FET. [Figure 11] 1A and 1B are diagrams illustrating one embodiment of the present invention. [Figure 12] 1A and 1B are diagrams illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a diagram illustrating a comparison of the characteristics of a FET according to an embodiment of the present invention and a conventional FET. [Figure 14] 1A to 1C are diagrams illustrating application examples of one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating application examples of one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments.

[0033] (Embodiment 1) 1 to 4 show conceptual diagrams of the shape of the FET of this embodiment. FIG. 1 is a perspective view of the FET. 2 is a cross-sectional view taken along plane X, FIG. 3 is a cross-sectional view taken along plane Y, and FIG. 4 is a cross-sectional view taken along plane Z. The FET shown in FIG. 4 is in contact with the insulating surface 100 and has a thickness t of 1 nm or more and 30 nm or less, preferably Preferably, the thickness is 3 nm or more and 5 nm or less, and the height h is 5 nm or more and 100 nm or less, preferably 10 The oxide semiconductor 101 has a flake shape with a thickness of 50 nm or more.

[0034] The oxide semiconductor 101 preferably has a crystalline structure, and is preferably the above-described CAAC-OS. In this case, the oxide semiconductor 101 preferably has at least a plurality of surfaces other than the bottom surface. However, it is preferable to arrange multiple crystals so that they are perpendicular to each other. To obtain a suitable crystalline state, after forming a thin amorphous oxide semiconductor, It is preferable to perform the heat treatment in an atmosphere.

[0035] A source 104 and a drain 105 are provided in contact with a part of the oxide semiconductor 101. The source 104 and the drain 105 are made of aluminum, magnesium, chromium, copper, or tantalum. Metallic materials such as tantalum, titanium, molybdenum, tungsten, or these metallic materials The alloy material layer may be, for example, a layer of Cu. - Layers of Mg-Al alloy materials can be used, or their metal nitrides can be used. good.

[0036] Then, the oxide semiconductor 101, the source 104, and the drain 105 are covered with the oxide semiconductor 10 The gate insulating film 102 is provided in contact with the gate insulating film 102. The gate insulating film 102 may be a single layer or It has a laminated structure of two or more layers, and is made of silicon oxide, tantalum oxide, hafnium oxide, and aluminum oxide. titanium, yttrium oxide, lanthanum oxide, hafnium silicate, silicon oxynitride, silicon nitride The insulating film may be formed using a material selected from the group consisting of conductors.

[0037] The gate 103 is formed to cover the gate insulating film 102. The gate 103 is striped, and in this embodiment, In the FET, it is formed so as to overlap with a part of the source 104 and the drain 105. The channel length can be defined as the distance L1 between the source 104 and the drain 105 (FIGS. 2 and 3). See 3).

[0038] The channel width is defined as the sum of the lengths of the three faces of the oxide semiconductor 101 (approximately 2h + t). Since h can be increased independently of the minimum processing line width of the circuit, The width can be made sufficiently large compared to the channel length, which increases the on-current of the FET. .

[0039] The gate 103 has a single layer or a laminated structure of two or more layers, and is made of platinum, palladium, osmium, or a metal selected from tungsten, molybdenum, titanium, or or their nitrides, metal nitrides or metal oxynitrides containing indium, Metal nitrides, metal oxynitrides, p-type silicon, etc. can be used. It is preferable to form a material having a potential of 5.2 eV or more facing the gate insulating film 102. For example, indium nitride is suitable because it has a work function of 5.6 electron volts.

[0040] Many of these materials with large work functions have high resistivity. A material with a large conductivity is formed on the gate insulating film 102, and a material with a good conductivity is formed on the gate insulating film 102. The material (conductor) should be formed to an appropriate thickness. For materials with better conductivity, There are no restrictions on functions.

[0041] As shown in FIG. 4, the oxide semiconductor 101 is surrounded on three sides by the gate 103. Therefore, electrons injected into the oxide semiconductor 101 from the source and drain are efficiently This allows for efficient removal of the depletion region 106 between the source and drain, thereby reducing the off-current. In addition, the channel width of the FET can be increased regardless of the area occupied by the FET. It is possible to create high-speed semiconductor circuits while maintaining a high degree of integration.

[0042] (Embodiment 2) FIG. 5 shows the FET of this embodiment. FIG. 5(A) is a cross-sectional view taken along the X plane corresponding to FIG. 2. 5B is a cross-sectional view taken along the Y plane corresponding to FIG. 3. The cross section on the Z plane corresponding to 4 is the same as FIG.

[0043] The FET of this embodiment has an oxide semiconductor 101 in contact with an insulating surface 100. A source 104 and a drain 105 are provided in contact with a part of the compound semiconductor 101. The oxide semiconductor 101, the source 104, and the drain 105 are covered with the insulating film. The gate insulating film 102 is provided in contact with the gate electrode 101. In this embodiment, the gate 103 is connected to the source 104 and the drain 106. This FET differs from the FET shown in the first embodiment in that it is formed so as not to overlap with the gate 105 .

[0044] In the FET shown in FIG. 5, the gate 103 does not overlap with the source 104 or the drain 105. However, it is also possible to have a structure in which only one of the two overlaps. The channel length is defined by the distance L2 between the source 104 and the drain 105. The source 104 and the gate 103 or the drain 105 and the gate 103 do not overlap. The offset region shown in Figure 5(B) has a width x of 1. 103 and the source 104 and between the gate 103 and the drain 105. In this case, it is preferable that the thickness is 10 nm or more.

[0045] Generally, when an offset region is provided between the source and drain, the on-current decreases. In the FET of this embodiment, the channel width W is the minimum load of the circuit, similar to the FET of the first embodiment. It can be made large regardless of the line width, and the on-current is large enough that the reduction due to the offset region You can offset the difference.

[0046] In particular, the width x of the offset region is 10 nm or more and 30 nm or less, preferably 10 nm or less. If the thickness is 20 nm or less, the decrease in on-current is sufficiently small. By providing the set region, the depletion region 106 can be widened, and the short channel effect can be further improved. Furthermore, the parasitic The capacity can be reduced.

[0047] Even if the gate insulating film is thin, the gate 103 and source The leakage current between the source 104 or the gate 103 and the drain 105 in the off state can be reduced. In this case, the leakage current is mainly due to the tunnel effect, so in the following, As shown in FIG. 5, the depletion region 106 is connected between the gate 103 and the source 104. Or it extends to about the middle between the gate 103 and the drain 105 .

[0048] In this situation, for example, the tunnel current between the source 104 and the gate 103 is depleted. Two barriers must be overcome: the region 106 and the gate insulating film 102. The barrier height of the depleted region 106 seen from the outside is half the band gap of the oxide semiconductor 101. For example, if the band gap of an oxide semiconductor is 3.2 eV, For example, it is 1.6 electron volts.

[0049] This is because the barrier height of silicon oxide, a typical insulator (about 4 electron volts or less) Although the tunnel current is small compared to the barrier length, a long barrier is necessary to reduce the tunnel current. Since the depletion region 106 is sufficiently wide, it is as effective as or more effective than the Therefore, if the barrier is long, the tunnel current can be reduced sufficiently.

[0050] For example, since the FET of the first embodiment does not have an offset region, the source 10 The tunnel current between the gate 103 and the transistor 4 is determined by the thickness of the gate insulating film 102 . Therefore, the tunnel current is set to be equal to or smaller than the current flowing between the source and drain. To achieve this, the physical thickness of the gate insulating film 102 needs to be 5 nm or more. If the thickness of the gate insulating film 102 is less than 5 nm, the contribution of the tunnel current becomes large, and the tunnel Therefore, it becomes impossible to reduce the off-state current including the current.

[0051] In particular, in the FET of the first embodiment, the overlapping area between the source 104 and the gate 103 is large. Therefore, in reality, the physical thickness of the gate insulating film 102 is required to be 10 nm or more. In this way, when the gate insulating film 102 becomes thicker, the on-current (i.e., the switching The switching speed decreases.

[0052] On the other hand, in the FET of this embodiment, (1) as shown in FIG. 5(B), The sum of the distance y from the edge of the gate 103 to the edge of the gate insulating film 102 and the thickness of the gate insulating film 102 is 5 nm or more. or (2) the distance from the edge of the depletion region 106 to the gate 103 is 5 nm. It is sufficient to satisfy one of the following conditions:

[0053] For example, if the distance y is 5 nm, even if the thickness of the gate insulating film 102 is 0, the OFF state The tunnel current between the source 104 and the gate 103 can be sufficiently blocked. In the on state, if the thickness of the gate insulating film 102 is not finite, the FET cannot operate normally. Therefore, in reality, the thickness of the gate insulating film 102 is 0.5 nm or more and less than 5 nm, preferably 0.5 nm or more and less than 5 nm. It should be between 0.5nm and 2nm.

[0054] The thickness of the gate insulating film 102 may be determined taking into consideration the magnitude of the leakage current in the on-state. In order to reduce power consumption, it is desirable to make the gate insulating film 102 thicker. When operation is required, it is desirable to make the gate insulating film thin. For example, in memory If the on-state period is less than 1 / 10,000 of the off-state period, the gate insulating film can be made thin. Even if the power consumption is reduced, it will not increase significantly.

[0055] (Embodiment 3) FIG. 6 shows the FET of this embodiment. FIG. 6(A) is a cross-sectional view taken along the X plane corresponding to FIG. 2. 6(B) is a cross-sectional view taken along the Y plane corresponding to FIG. 3. The cross section of the FET of this embodiment taken along the Z plane corresponding to the insulating surface 10 is the same as that of FIG. The oxide semiconductor 101 is in contact with the surface of the semiconductor layer 100.

[0056] A source 104 and a drain 105 are provided in contact with a part of the oxide semiconductor 101. Then, the oxide semiconductor 101, the source 104, and the drain 105 are covered with the oxide semiconductor The gate insulating film 102 is provided in contact with the gate insulating film 101. A gate 103 is formed covering the source 104 and the drain 105. This is the same as the FET shown in the second embodiment in that it is formed so as not to overlap with the FET 05.

[0057] The FET of this embodiment has an N-type region 107 and an N-type region 10 The FET of the second embodiment differs from the FET of the first embodiment in that it has an N-type region 107 and an N-type region 108. The gate 103, the source 104, and the drain 105 are used as masks, and nitrogen, boron, phosphorus, etc. are ionized. The N-type region 107 and the N-type region 108 may be introduced into the oxide semiconductor 101 by ion implantation or other means. and the concentration of nitrogen, boron or phosphorus in the N-type region 108 is 1×10 18cm -3 1x or more 10 22 cm -3 Less than 1 × 10 18 cm -3 More than 1×10 20 cm -3 below It would be best to do so.

[0058] The FET shown in FIG. 6 has a structure with two N-type regions, but it is also possible to use a structure with only one of them. In the FET shown in FIG. 6, the channel length is substantially equal to the gate width L 3. The FET of this embodiment has a larger on-state current than the FET of the second embodiment. In addition, the gate 103 and the source 104 or the drain 106 can be formed more precisely than in the FET of the first embodiment. The parasitic capacitance with 105 can be reduced.

[0059] (Fourth embodiment) FIG. 7 shows the FET of this embodiment. FIG. 7(A) is a cross-sectional view taken along the X plane corresponding to FIG. 2. 7B is a cross-sectional view taken along the Y plane corresponding to FIG. 3. The cross section of the FET of this embodiment taken along the Z plane corresponding to the insulating surface 10 is the same as that of FIG. The oxide semiconductor 101 is in contact with the surface of the semiconductor layer 100.

[0060] A source 104 and a drain 105 are provided in contact with a part of the oxide semiconductor 101. The gate insulating film 102 covers a part of the oxide semiconductor 101. The end of 102 may contact the source 104 or the drain 105 .

[0061] Furthermore, a gate 103 is formed to cover the gate insulating film 102. A sidewall insulator 109 and a sidewall insulator 110 are provided in contact with the end portion. The source 104 and the sidewall insulator 110 are provided to contact the drain 105. The sidewall insulators 109 and 110 are formed so that the source 104 and drain 105 are Prevent contact with the gate 103.

[0062] The FET of this embodiment has an N-type region 107 and an N-type region 10 The N-type regions 107 and 108 are formed by using the gate 103 as a mask. , boron, phosphorus, or the like may be introduced into the oxide semiconductor 101 by means of ion implantation or the like. The concentration of nitrogen, boron, or phosphorus in the N-type region 107 and the N-type region 108 is 1×10 18 cm -3 More than 1×10 22 cm -3 Less than 1 × 10 18 cm -3 More than 1×10 20 cm -3 The following would be appropriate.

[0063] In the FET shown in FIG. 7, the channel length can be substantially defined by the gate width L4. In this type of FET, the source 104 or the drain 105 of the oxide semiconductor 101 is heavily doped. The portions where the N-type region 107 is formed are the N-type region 108. The ON current can be made larger than that of the FET of the first embodiment, and the gate 103 and the source 104 or the drain 105 can be reduced.

[0064] The characteristics (drain voltage) of the FET shown in Fig. 7 and the planar FET shown in Fig. 10(C) Flow (I D ) gate potential (V G The results of the calculation of the dependence are shown below. In the FET shown, L4 = t = x1 = x2 = 30 nm, and h = 50 nm. In the FET shown in FIG. 7, the channel length is 30 nm and the channel width is 130 nm. In the FET shown in FIG. 10(C), L5=x1=x2=30 nm, and the oxide semiconductor 20 The thickness d of 1c was set to 30 nm and the channel width was set to 130 nm.

[0065] In the FET shown in FIG. 7 and the FET shown in FIG. 10(C), the gate insulating film 102 and The relative dielectric constant of the gate insulating film 102 and the gate insulating film 202c is 4.1. The thickness of gate 103 and gate 203c is 5 nm, and the work function of gate 103 and gate 203c is 5.5 electron volts. The band gap of the oxide semiconductor 101 and the oxide semiconductor 201c is set to 3.15 electrons. The electron affinity of the oxide semiconductor 101 and the oxide semiconductor 201c is 4.6 eV. The relative dielectric constant of the oxide semiconductor 101 and the oxide semiconductor 201c is set to 15, the N-type region 107, The resistivity of the N-type region 108, the N-type region 207, and the N-type region 208 is set to 0.3 Ω·cm, Work functions of the source 104 and the source 204c and the drain 105 and the drain 205c was set to 4.6 electron volts.

[0066] The calculations were performed using the Synopsys, Inc. device simulator, Sen The calculation results are shown in Figure 13(A). The potential at the gate is 0 V, and the potential at the drain is +1 V. In FIG. 13(A), structure A is the same as that shown in FIG. Structure B is that of the FET shown in FIG.

[0067] As is clear from the figure, the FET with structure A is unable to sufficiently reduce the off-state current, and Even if the potential of the gate is -3V, the drain current is 10 -14 A or higher. In contrast, structure B So, when the gate potential is -1V, the drain current is 10 -18 A or less, The off-state current can be reduced.

[0068] The same calculation was performed with different FET sizes. For the FET shown in Figure 7, L4 = x1 = x2 = 30 nm, t = 5 nm, h = 15 nm. That is, in the FET shown in Figure 7, The channel length is 30 nm and the channel width is 35 nm. In the ET, L5=x1=x2=30 nm, d=5 nm, and the channel width was 35 nm. The results are shown in Figure 13(B). The source potential was 0 V and the drain potential was +1 V. be.

[0069] In FIG. 13(B), structure A is that of the FET shown in FIG. 10(C), and structure B is that of the FET shown in FIG. The oxide semiconductor 201c is thinned (relative to the channel length) to Although the off-state current of the FET with structure A is decreasing, it is still larger than that of structure B. For example, when the gate potential is 0V, the drain current is 10 -20 A or below In contrast, in structure A, the drain current is 10 -18 It is about A level.

[0070] The ratio of the channel length to the thickness t of the oxide semiconductor 101 or the oxide semiconductor 201c (L / t ) is 1 in FIG. 13(A) and 6 in FIG. 13(B). As shown in FIG. 13B, the oxide semiconductor 201c exhibited relatively good characteristics. The channel length remains the same, but the thinning reduces the short channel effect. is.

[0071] In the FET of structure B, the oxide semiconductor 101 is relatively thinned, resulting in a short channel. In addition, the channel effect can be mitigated. Even in a structure where L / t is 2 or less, sufficient characteristics can be obtained with the FET of Structure B. It is a sign.

[0072] (Embodiment 5) A method for fabricating an FET according to this embodiment will be described with reference to FIGS. 8 and 9. , which show three cross sections in each manufacturing process of the FET, are shown in Fig. In the following explanation, the known semiconductor manufacturing technology or Patent Document 1, Patent Document 2, See reference 2.

[0073] First, as shown in FIG. 8(A), a thin oxide semiconductor 101 is formed on an insulating surface 100. The thickness t of the oxide semiconductor is 1 nm or more and 30 nm or less, preferably 3 nm or more and 5 nm or less. , the height h is set to 5 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. The width w can be any value, but in order to increase the degree of integration, it is recommended to set it to twice the minimum processing line width F. When a plurality of FETs are provided in one oxide semiconductor 101, This is not the case.

[0074] The oxide semiconductor 101 shown in FIG. 8A is a thin rectangular parallelepiped and has six faces. One of the surfaces (bottom surface) is included in the insulating surface 100. 0. Hereafter, this surface is called the α-surface. Furthermore, the other four surfaces are part of the surface ( The two faces with larger areas are called β faces, and The other two planes are called gamma planes.

[0075] Note that although the oxide semiconductor 101 is depicted as a perfect rectangular parallelepiped in FIG. For example, the oxide semiconductor 101 may have a corner in any cross section. It may be a curved surface with a specific radius of curvature. In this case, the boundaries between the α, β, and γ planes are not clearly distinguishable. Also, the base may be wider than the α-face, or the base may be narrower than the α-face. It may be narrower.

[0076] After the oxide semiconductor 101 is formed, heat treatment may be performed at a temperature of 250° C. to 750° C. The heat treatment is preferably carried out in ultra-dry air with an extremely low water vapor concentration (dew point of -60°C or less, preferably or -80°C or below), high-purity oxygen gas, high-purity nitrogen gas (both with a purity of 6N or above) above (impurity concentration is 1 ppm or less), preferably 7N or above (impurity concentration is 0.1 ppm or less) It is preferable to carry out the treatment under a )) atmosphere or a high vacuum environment of 1 Pa or less.

[0077] When heat treatment is performed in such an atmosphere, hydrogen is released from the oxide semiconductor 101. In particular, acids with a band gap of 3 electron volts or more and an electron affinity of 4 electron volts or more In oxide semiconductors, it acts as a donor, so lowering its concentration reduces the off-current of the FET. This is preferable for making it smaller.

[0078] Depending on the material of the oxide semiconductor 101, the above heat treatment may result in a crystal having a c-axis perpendicular to each plane. It may have a crystalline structure.

[0079] When the oxide semiconductor 101 is heat-treated in a reducing atmosphere such as a high vacuum, hydrogen is simultaneously In oxide semiconductors, oxygen vacancies also act as donors, so It is preferable to supplement the above, and for this purpose, it is preferable to subsequently perform a heat treatment in an oxidizing atmosphere. I wish.

[0080] In addition, in order to suppress the increase in carrier (electron in this case) concentration due to oxygen vacancies, The compound semiconductor 101 contains 0.1 atomic % to 5 atomic % of nickel or copper, which has the property of absorbing electrons. It may be allowed to have.

[0081] Next, a gate insulating film 102 is formed to cover the oxide semiconductor 101. Thickness and dielectric constant are important factors in determining transistor characteristics, and The thickness is preferably 20 nm or less, more preferably 0.5 nm or more and 10 nm or less. As explained above, if an offset region of appropriate length is provided, the tunnel current can be suppressed. Therefore, the physical thickness of the gate insulating film 102 can be set to 2 nm or less.

[0082] The gate insulating film 102 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. known materials such as ammonium, hafnium oxide, lanthanum oxide, zirconium oxide, and tantalum oxide Just use

[0083] Thereafter, a first conductive material film is formed to cover the gate insulating film 102. The portion of the material film that is in contact with the gate insulating film 102 has a work function of 5.2 eV or more. Materials (e.g., platinum-based precious metals such as platinum, osmium, and palladium, indium nitride, or Indium oxynitride (In-ON), indium gallium oxynitride (In-Ga-ON) ), indium zinc oxynitride (In-Zn-ON), indium gallium zinc oxynitride (I It is preferable to use n-Ga-Zn-ON, etc. In addition, other parts of the first conductive material film The main components are highly conductive metal materials such as aluminum, copper, titanium, and tungsten. It may be made of any material.

[0084] Furthermore, a first insulating material film is formed on the first conductive material film. Silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. may be used for the .

[0085] Then, as shown in FIG. 8(B), the first conductive material film and the first insulating material film are etched. The oxide semiconductor 101 is then formed in a stripe pattern, covering part of the α-plane and part of the β-plane. A gate 103 and a barrier insulator 111 on the gate 103 are formed.

[0086] Thereafter, the gate 103 and the barrier insulator 111 are masked by means of ion implantation or the like. Phosphorus is implanted into the oxide semiconductor 101. Nitrogen or boron may be implanted instead of phosphorus. In either case, the oxide semiconductor 101 exhibits N-type conductivity. If necessary, ions are implanted. After that, the material may be heat-treated at 250 to 750° C. The optimum temperature and atmosphere for the heat treatment are Depends on the element being implanted.

[0087] When the height h of the oxide semiconductor 101 exceeds 100 nm, the oxide semiconductor 101 Since these ions may not be uniformly implanted, the height of the oxide semiconductor 101 is set to 100 n. It is preferable that the offset region be set to m or less. In this case, this ion implantation step is omitted.

[0088] Thereafter, a second insulating film is formed on the gate insulating film 102, the gate 103, and the barrier insulating film 111. The second insulating material film is formed from the same material as the first insulating material film or The first insulating material film may be selected from the same materials as those mentioned above, but the second insulating material film is selected from the same materials as those mentioned above, but the first insulating material film is selected from the same materials as those mentioned above, and the second insulating material film is selected from the same materials as those mentioned above. It is preferable that the second insulating material film is different from the gate insulating film 102 by etching. Preferably the characteristics are similar.

[0089] Thereafter, the gate 103 and the burr are removed by anisotropic etching, as shown in FIG. 9(A). The sidewall insulators 109 and 110 are formed on the side surfaces of the insulating layer 111. The thickness of the gate insulating film 102 is set to 5 nm or more, preferably 10 nm or more. That is, the sidewall insulators 109 and 110 and the portions not covered by the gate 103 are also etched. Then, the oxide semiconductor 101 is exposed.

[0090] At this time, as shown in FIG. 9(A), the oxide semiconductor 101 (the N-type region 107 and the N-type region 108) may also have its upper portion etched (over-etching). The etching rate ratio between the insulating material film and the oxide semiconductor 101 cannot be made sufficiently large. is.

[0091] In particular, when the second insulating material film is made of silicon oxide or silicon oxynitride, dry etching is required. The etching rate of the tin oxide semiconductor containing indium or the oxide semiconductor containing zinc is Since the oxide semiconductor 101 is not much different from a semiconductor, it is inevitably etched.

[0092] This is not limited to the FET used in this embodiment, but also applies to the planar FET shown in FIG. In particular, in the planar FET shown in FIG. 10(C), As described above, in order to sufficiently reduce the off-state current, the oxide semiconductor 201c needs to be extremely thin. In this case, the allowable range of etching conditions becomes stricter, and If it comes off, most of the oxide semiconductor except for the part covered by the sidewall insulator and gate 203c will be The body 201c may also be lost.

[0093] On the other hand, in the FET of this embodiment, for example, the height of the oxide semiconductor 101 can be made sufficiently large. Therefore, even if the oxide semiconductor 101 is etched to some extent, the fabrication of the FET will not fail. There is nothing to do.

[0094] Generally, when etching a surface with a certain extent, the etching rate varies depending on the area. In the planar FET shown in FIG. 10(C), The oxide semiconductor 201c is overetched sufficiently with respect to the thickness of the oxide semiconductor 201c. It is extremely difficult to make the size smaller, which is a major factor in reducing yield.

[0095] In the FET of this embodiment, the oxide semiconductor 101 is over-etched. It is enough to make the height h small enough, not the thickness t of 01, and the height h is several times the thickness t. Or even more, the etching conditions are milder and the yield is higher.

[0096] Next, a second conductive material film is formed and etched to form a second conductive material film as shown in FIG. 9(B). The source 104 and the drain 105 are formed. The source 104 and the drain 105 are formed by exposing the acid In FIG. 9B, the source 104 and the drain 105 are formed in contact with the oxide semiconductor 101. are formed so as to contact the α-, β-, and γ-planes of the oxide semiconductor 101, but are not necessarily There is no need to contact the surface.

[0097] The oxide semiconductor 101 absorbs water and deteriorates when exposed to the air. To prevent this, use an appropriate insulating material with barrier properties (silicon nitride, aluminum oxide, In the above-described FET, a film of oxide semiconductor may be formed. Most of the body 101 is covered by a gate 103, a source 104, and a drain 105. This structure makes it more durable than planar FETs.

[0098] (Embodiment 6) In the above embodiment, an example in which an FET is formed on an insulating surface has been shown. However, if a part of the surface is conductive, A FET may be formed on the surface of the silicon substrate, which allows electrical connection to the underlying layer. Figure 11 shows an example of such a FET and a semiconductor circuit (memory cell) that uses it.

[0099] Figure 11 shows a random access memory (RAM) consisting of one transistor and one capacitor. The same circuit is shown as an example of a RAM structure. When it is configured with a silicon semiconductor, it is called a 1T1C type DRAM. Because the off-state current is large, data is rewritten (refreshed) every few tens of milliseconds. Because it is necessary.

[0100] However, as mentioned above, in FETs using oxide semiconductors, the off-state current is higher than that of silicon semiconductors. Since it can be made much smaller than a FET using a conductor, refresh is practically unnecessary. In this case, it is inappropriate to call it DRAM, so in the following it will simply be called RAM. Alternatively, to distinguish it from RAMs of other structures, it is called 1T1C type RAM.

[0101] The configuration of the memory cells and other circuits of the RAM shown in FIG. The conductor circuit is a transistor using a single crystal silicon semiconductor formed on the surface of a silicon semiconductor substrate. a driver circuit section 114 having a transistor, a cell transistor 115 of a memory cell, The capacitor 116 of the memory cell and the bit line 112 provided between the memory cell and the driver circuit section The bit line 113 may be made of various conductive materials. 3 is electrically connected to the driver circuit section 114.

[0102] The cell transistor of the memory cell is provided with an FE having an offset region as shown in the second embodiment. T is used. The manufacturing method and detailed structure thereof can also be referred to in embodiment 5. A cross-sectional view corresponding to the cross-sectional view shown in FIG. 5(B) is shown, but cross-sectional views in other planes are not shown in the embodiment. 2. It should be noted that the present invention is not limited to the FET shown in the second embodiment, and other embodiments may also be used. The FET shown in FIG.

[0103] The FET includes an interlayer insulator 112 and a conductive region 113 that electrically connects to a bit line 113. a, an oxide semiconductor 101, a gate insulating film 102, a gate 103, a source 10 4 and the drain 105. A part of the oxide semiconductor 101 and a part of the source 104 are It contacts the conductive region 113a. The surface of the conductive region 113a is preferably flat. On the other hand, the drain 105 is not in contact with the conductive region 113a. The capacitor 116 is connected via a connecting electrode 117 .

[0104] The capacitor 116 is composed of a lower electrode 118, a capacitor insulating film 119, and an upper electrode 120. The capacitor configuration is not limited to this, and various known stacked capacitors may be used. The structure of the capacitor can be applied. The material, thickness, size, etc. of the capacitor can be the same as those of various known stacked capacitors. Cut.

[0105] (Embodiment 7) In this embodiment, the FET of the second embodiment is applied to a so-called gain cell type memory. The FET used is not limited to that of the second embodiment, but may be that of the first embodiment. Alternatively, the third to fifth embodiments may be used.

[0106] A gain cell type memory is, for example, a memory described in Patent Document 3, and typically has the following structure: Two transistors (write and read transistors) and one capacitor Others consist of three transistors, one transistor and one diode, Some consist of a diode and one capacitor, etc.

[0107] The circuit diagram of a memory cell consisting of two transistors and one capacitor is shown in Figure 12(B ) that is, the gate of the write transistor 127 is connected to the write word line, One electrode of the capacitor 126 is connected to the read word line, and the other electrode of the write transistor 127 is connected to the The source of the read transistor 128 is connected to the bit line, and the source of the write transistor 127 is connected to the bit line. The drain of the capacitor 126 and the other electrode of the capacitor 126 are connected to the gate of the read transistor 128. The drain of the read transistor 128 is connected to the power supply line.

[0108] In addition, even in the case of gain cell type memory, when it is configured with FETs using silicon semiconductors, Because it required frequent refreshing, it is usually called a gain-cell DRAM. do.

[0109] In the gain cell type memory, the capacitance of the capacitor 126 is sufficiently smaller than that of the DRAM capacitor. In DRAM, the required capacitance of the capacitor is In the gain cell type memory, the capacitance is determined by the relative ratio of the parasitic capacitances of the read transistor. It is determined by the relative ratio to the gate capacitance of the capacitor 128.

[0110] If the capacitance of the capacitor 126 can be reduced, the time required for charging and discharging the capacitor, i.e., the switching time, can be reduced. In DRAM, the charging and discharging of the capacitor is the rate limiting factor, which reduces the operating speed. While there are limitations on the design rule, gain cell type memories have become more flexible with the shrinking of design rules. The gate capacitance of the transistor 128 and the capacitance of the capacitor 126 decrease at the same rate. , a memory with extremely fast response can be created.

[0111] Specifically, if the design rule is reduced to 1 / 10 (the dimensions of the FET are 1 / 3 of the length, width, and height), 10), the capacitance of capacitor 126 will be 1 / 10, and the on-resistance of the FET will also be 1 / 1 0, the time required for switching is 1 / 100. On the other hand, in DRAM, Even if the on-resistance of T becomes 1 / 10, the capacitance of the capacitor does not change, so the switching In other words, the time required for the gain cell type memory is 10 times faster than that required for the DRAM. It is possible to achieve twice the speed.

[0112] Although gain cell memory is expected to have such excellent characteristics, it is necessary to sufficiently reduce the off-current of the FET. Generally, the design rule is 1 / 10, so it has not been put to practical use. However, the FET off-state current does not become 1 / 10 of the original value. As a result, leakage current may increase.

[0113] For example, if an FET uses a PN junction in the off state to insulate the source and drain, As the band width decreases, leakage due to band-to-band tunneling at the PN junction becomes significant. In semiconductors with a small band gap (less than 1.5 eV), the influence of thermally excited carriers is also negligible. If the off-state current cannot be suppressed, it is difficult to reduce the capacitance of the capacitor.

[0114] The write transistor 127 of the gain cell type memory is a FE using a known silicon semiconductor. When using only T, the effect of using two transistors disappears. If the capacitance of the bottom 126 is about 10 fF like a normal DRAM, In a FET using a semiconductor, the leakage current when off is at least 10 -14 A, so 1 second The charge stored in the capacitor 126 disappears in about this time. Therefore, a refresh operation is required more than ten times per second.

[0115] It is not possible to use a capacitor of the same capacity to provide one more transistor than in DRAM. The capacitance of the capacitor must be reduced because it is not worth the cost. If the capacitance of the capacitor is reduced in relation to the relative ratio with the parasitic capacitance of However, in a gain cell memory, even if the capacitance of the capacitor is reduced to 1 / 10, the data can still be read. It can be seen.

[0116] However, FETs using silicon semiconductors have a relatively large off-state current, which If the capacity of the Pacita becomes 1 / 10, the refresh interval will also become 1 / 10. In addition to increasing power consumption, memory access is also restricted. If the number is 100, the refresh interval will be 1 / 100, which is not practical. Since there was no means to sufficiently reduce the leakage current of the write transistor 127, Such a gain cell type memory was never put to practical use.

[0117] When the write transistor 127 is formed of a FET using an oxide semiconductor for the channel, When the off-current is sufficiently small, the gain cell type memory This makes the memory cell highly promising. The gate capacitance of the transistor 127 and the readout transistor 128 can be reduced to the same level. Therefore, it is necessary to provide capacitors with special shapes (stack type or trench type) like DRAM. This allows for greater design freedom and simplifies the process. This makes it a usable memory.

[0118] For example, the off-state current is reduced to one millionth (10 -20 A grade) If so, even if the capacitor were one thousandth of that of DRAM, the refresh interval would be The off-state current is smaller, e.g., 1 0 -24 If it's A or below, you only need to refresh it once every few days.

[0119] When writing, as mentioned above, the data is written to a capacitor with a capacity significantly smaller than that of DRAM. Since it is a charge, the characteristics of the write transistor 127 do not need to be so excellent to be practical. For example, the capacitance of the capacitor 126 is However, if the capacitance is 1 / 1000 of the capacitance of the DRAM capacitor, the write transistor 127 will also be turned on. The transistor current (or mobility) can be one thousandth of that of a DRAM transistor.

[0120] If the mobility of the write transistor 127 is 1 / 1 of that of a transistor using a silicon semiconductor, Even with a mobility of 100, writes can be performed 10 times faster than with regular DRAM. As mentioned above, high speed becomes more noticeable as design rules become smaller.

[0121] Note that the off-current of the write transistor 127 becomes sufficiently small, and the refresh is substantially If refreshing is no longer necessary, the aspect of non-volatile memory will become stronger. For example, not only as RAM, but also as a gain cell type memory, it is possible to apply it to a memory having a NAND structure. The NAND structure also makes it possible to increase the degree of integration.

[0122] An outline of the gain cell type memory of this embodiment is shown in FIG. 128 has a gate 121, a source 123, and a drain 122. The drain 122 is connected to a power supply It functions as a line or is connected to a power supply line, and preferably extends in the word line direction. The source 123 is connected to the source 104 of the write transistor 127 .

[0123] The write transistor 127 uses the FET described in the second embodiment. The FETs described in the first, third to fifth embodiments may also be used. The drawing shown in FIG. 12(A) corresponds to FIG. 5(B).

[0124] The write transistor 127 is formed by overlaying an interlayer insulator 112 with an oxide semiconductor 101, a gate insulating film 102, and a gate insulating film 104. The insulating film 102, the gate 103, the source 104, and the drain 105 are The gate 103 is connected to the gate 121 of the read transistor 128. The gate 121 of the read transistor 128 functions as a gate line or part thereof. The drain 105 of the write transistor 127 is electrically connected to the drain 105 of the write transistor It is preferable that the gate 103 and the source 104 of the transistor 127 are not electrically connected. .

[0125] A bit line is connected to the source 104. A read word line 124 is provided through the gate insulating film 102. The line 124, the drain 105, and the gate insulating film 102 form a capacitor 126. The output word line 124 is connected to the drain 103 via the side of the oxide semiconductor 101. 5It is shaped to cover from above.

[0126] Therefore, if the width of the read word line 124 is L6, the area of ​​the capacitor 126 (read The area of ​​the overlapping portion of the output word line 124 and the drain 105 is greater than (2h+t)×L6. On the other hand, the gate area of ​​the gate 121 of the read transistor 128 is L6×L6 The height h of the oxide semiconductor can be increased without being restricted by the minimum processing line width of the circuit. As a result, the capacitance of the capacitor 126 can be adjusted to the gate of the read transistor 128. This means that when reading data, This means that errors are less likely to occur.

[0127] The memory cell having the structure shown in FIG. 12(A) can be fabricated as follows. , the gate 121 of the read transistor 128 and the source 123, the drain 122 is formed, and the interlayer insulating film 112 is formed thereon. The surface is planarized to expose the gate 121 .

[0128] Then, a thin oxide semiconductor 101 is formed, and a readout transistor is formed on the interlayer insulator 112. A contact hole is formed that reaches the source 123 of the oxide semiconductor 128. The source 104 and the drain 105 are formed by covering a part of the MOSFET 101. The drain 105 is The gate 121 of the output transistor 128 and the source 104 are connected to the source 123. Do so.

[0129] Then, the gate insulating film 102 is formed. Then, the gate insulating film 102 is covered with a gate insulating film. 103, the read word line 124 is formed. Then, a contact that reaches the source 104 is formed. Holes are drilled and bit lines 125 are formed.

[0130] The gain cell type memory described in this embodiment differs from the DRAM in that it is By utilizing the fact that the signal amplification process and the circuit for it are not required, It can be used as a register (a memory device that temporarily stores data).

[0131] A register in a normal semiconductor circuit is made up of a flip-flop circuit using six transistors. Therefore, the area occupied by the register increases, but the gate The cancellation type memory is formed by two transistors and one capacitor, and also by two The transistors are arranged three-dimensionally, so they occupy a smaller area than conventional resistors.

[0132] In addition, registers that use flip-flop circuits lose data when the power supply is interrupted. However, the gain cell type described in this embodiment cannot restore the original state even after recovery. Memory can retain data for a certain period of time, so the original state can be restored quickly after power is restored. It can be reproduced.

[0133] By utilizing this characteristic, even if there is only a short period of time when the semiconductor circuit is not performing calculations, Power consumption is reduced by stopping the power supply and then supplying it again when calculations are required. For example, in the image processing and output circuit, the image is The data is processed and sent in less than 1 millisecond, and the remaining 16 milliseconds The power supply to the circuit may be turned off for a period of time longer than 1 second. The force can be reduced.

[0134] In a CPU, which is a larger semiconductor circuit, multiple circuits each perform calculations, but However, not all circuits are performing calculations, and many circuits are simply waiting. By not supplying power to such circuits, power consumption can be significantly reduced. The register of the path is configured using the gain cell type memory described in this embodiment. , it can instantly supply and cut off power to a circuit.

[0135] (Embodiment 8) The following describes an example of using the memory described in the sixth or seventh embodiment with reference to FIG. 14 is a block diagram showing an example of the configuration of a microprocessor. The microprocessor shown in FIG. 14 includes a CPU 301, a main memory 302, a clock controller 303, and a controller 303, cache controller 304, serial interface 305, / O port 306, terminal 307, interface 308, cache memory 309, etc. Of course, the microprocessor shown in FIG. 14 is a simplified representation of its configuration. This is just one example, and actual microprocessors have a wide variety of configurations depending on their applications. There are.

[0136] To make the CPU 301 operate at a higher speed, a memory with a correspondingly high speed is required. However, it is necessary to use a high-speed, large-capacity memory with an access time that matches the operating speed of the CPU 301. Therefore, the use of large-capacity main memory is generally costly. In addition to the main memory 302, there is also a memory such as an SRAM, which is a memory with a smaller capacity but higher speed than the main memory 302. The cache memory 309 is interposed between the CPU 301 and the main memory 302 . When the CPU 301 accesses the cache memory 309, the main memory 302 This allows high-speed operation regardless of the speed of the

[0137] In the microprocessor shown in FIG. 14, the above-mentioned memory is used as the main memory 302. The above configuration allows for a highly integrated microprocessor and a highly reliable microprocessor. A processor can be implemented.

[0138] The main memory 302 stores programs executed by the CPU 301. For example, at the beginning of execution, the program stored in the main memory 302 is The downloaded program is downloaded to the cache memory 309. The data is not limited to those stored in the internal memory 302, but may be downloaded from other external memories. The cache memory 309 stores the program executed by the CPU 301. It not only stores data but also functions as a work area, temporarily storing the calculation results of the CPU 301. Store.

[0139] The number of CPUs is not limited to one, but multiple CPUs may be provided. By doing so, the operating speed can be improved. In this case, the processing speed between CPUs If it is done bit by bit, it may cause problems when looking at the overall process, so each slave CP The processing speed of U may be balanced by the master CPU.

[0140] Although a microprocessor is used as an example here, the above-mentioned memory may be a microprocessor. Its use is not limited to the main memory of a display device. It is also suitable for use as a video RAM, which is used for image processing circuits, and as a large-capacity memory. In addition, it is also used as a large-capacity or small-sized memory in various system LSIs. You can be there.

[0141] (Embodiment 9) In this embodiment, a semiconductor device having the memory described in the sixth or seventh embodiment is used. An example of a semiconductor device will be described. The semiconductor device includes a memory according to one embodiment of the present invention. In particular, in the case of a portable semiconductor device, the present invention If miniaturization can be achieved by using a memory according to one aspect, usability for users will be improved. The following benefits can be obtained.

[0142] A memory according to one aspect of the present invention is used in a display device, a notebook personal computer, a recording medium, Image playback devices equipped with DVD (Digital Versatile Disc) Used for devices that have a display that can play back recording media such as SC and display the images It is possible.

[0143] Another example of a semiconductor device in which the memory according to one embodiment of the present invention can be used is a mobile phone. Talk, portable game consoles, personal digital assistants, e-books, video cameras, digital still cameras, Goggle-type display (head-mounted display), navigation system, sound Sound reproduction devices (car audio, digital audio players, etc.), copiers, fax machines printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these semiconductor devices are shown in FIG.

[0144] FIG. 15A shows a portable game machine, which includes a housing 401, a housing 402, a display unit 403, and a display unit 404, microphone 405, speaker 406, operation keys 407, stylus 408, etc. The memory according to one aspect of the present invention is an integrated circuit for controlling the operation of a portable game machine. The present invention can be applied to an integrated circuit for controlling the operation of a portable game machine. By using the memory according to one embodiment, a compact portable game machine can be provided. The portable game machine shown in FIG. 15(A) has two display units 403 and 404. However, the number of display units that the portable game machine has is not limited to this.

[0145] FIG. 15B shows a mobile phone, which includes a housing 411, a display unit 412, an audio input unit 413, an audio output unit 414, and a microphone. The light receiving unit 416 receives the signal from the input unit 414, the operation keys 415, and the light receiving unit 416. By converting light into an electrical signal, an external image can be captured. Such a memory can be used in an integrated circuit for controlling the operation of a mobile phone. By using a memory according to one embodiment of the present invention in an integrated circuit for controlling driving of a computer, It is possible to provide a compact mobile phone.

[0146] FIG. 15C shows a portable information terminal, which includes a housing 421, a display unit 422, operation keys 423, and the like. The portable information terminal shown in FIG. 15(C) may have a modem built into the housing 421. The memory according to one embodiment of the present invention is used in an integrated circuit for controlling the operation of a mobile information terminal. The present invention relates to an integrated circuit for controlling the operation of a portable information terminal. By using a memory, a compact portable information terminal can be provided. [Explanation of symbols]

[0147] 100 Insulating Surface 101 Oxide Semiconductor 102 Gate insulating film Gate 103 104 Source 105 Drain 106 Depletion region 107 N-type region 108 N-type region 109 Sidewall insulator 110 Sidewall insulator 111 Barrier insulators 112 Interlayer insulation 113 bit lines 113a Conductive region 114 Driver circuit section 115 Cell Transistor 116 Capacitor 117 Connecting electrode 118 Lower electrode 119 Capacitor insulating film 120 Upper electrode Gate 121 122 Drain 123 Source 124 read word line 125 bit lines 126 Capacitor 127 Write transistor 128 readout transistor 201a Oxide Semiconductor 201b Oxide semiconductor 201c Oxide Semiconductor 202a Gate insulating film 202b Gate insulating film 202c Gate insulating film Gate 203a Gate 203b Gate 203c 204a Source 204b Source 204c Source 205a Drain 205b Drain 205c Drain 206a Depletion region 206b Depletion region 207 N-type region 208 N-type region 301 CPU 302 main memory 303 Clock Controller 304 Cache Controller 305 serial interface 306 I / O ports 307 Terminal 308 Interface 309 Cache Memory 401 Case 402 Case 403 Display section 404 Display section 405 Microphone 406 Speaker 407 Operation Key 408 Stylus 411 Case 412 Display section 413 Audio input section 414 Audio output unit 415 Operation Key 416 Light receiving section 421 Case 422 Display section 423 Operation Key

Claims

[Claim 1] an oxide semiconductor layer; a gate insulating film having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a first side surface of the oxide semiconductor layer, and a region in contact with a second side surface of the oxide semiconductor layer; a gate having a region in contact with an upper surface of the gate insulating film, a region in contact with a first side surface of the gate insulating film, and a region in contact with a second side surface of the gate insulating film; a source and a drain electrically connected to the oxide semiconductor layer, In a region where the gate and the oxide semiconductor layer overlap, a thickness of a region of the oxide semiconductor layer sandwiched by the gate insulating film is smaller than a height of the oxide semiconductor layer; the gate insulating film has a region that overlaps with the oxide semiconductor layer but does not overlap with the gate.

Images