Differential signal output circuit and differential clock generation circuit

Abstract

To provide a differential signal output circuit capable of suppressing characteristic deterioration of a differential output signal caused by noise mixing into a power supply line, and a differential clock generation circuit applying the same.SOLUTION: The differential signal output circuit includes an internal power supply circuit that generates an internal power supply voltage in which an influence of noise mixed into a power supply line is suppressed based on a power supply voltage supplied to the power supply line, an output circuit that receives supply of the internal power supply voltage and operates, and a drive circuit that receives supply of the internal power supply voltage and drives the pair of MOSFETs based on a differential input signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to a differential signal output circuit and a differential clock generation circuit. [Background technology]

[0002] The following techniques are known as techniques related to differential signal output circuits. For example, Patent Document 1 describes a vibrating device including an oscillator circuit that generates an oscillation signal by oscillating a vibrating element, and an output buffer circuit that outputs a clock signal based on the oscillation signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-84161 Summary of the Invention [Problem to be solved by the invention]

[0004] ECL (Emitter-Coupled Logic) is a method for implementing logic circuits that include differential amplifier circuits composed of bipolar transistors. ECL achieves high speeds by operating bipolar transistors in a non-saturated state. In ECL, the emitters of a pair of transistors that make up the input differential pair are coupled to each other and connected to a negative power supply through a constant current source. Because ECL requires a negative power supply, it is difficult to apply it to general applications. Subsequently, PECL (Positive ECL), which uses a positive power supply, and LVPECL (Low Voltage PECL), which can be driven at a lower voltage, were developed, and these are now used in high-performance computing applications such as mainframes and supercomputers, as well as in communications infrastructure.

[0005] In a differential signal output circuit realized using a more common CMOS process, the input signal is fed to the power supply voltage V DD However, when noise is introduced into the power supply line, the phase noise characteristics and phase jitter characteristics of the differential output signal deteriorate.

[0006] The disclosed technology has been made in consideration of the above points, and aims to provide a differential signal output circuit that can suppress deterioration of the characteristics of differential output signals caused by noise being mixed into power supply lines, and a differential clock generation circuit that applies the same. [Means for solving the problem]

[0007] The differential signal output circuit according to the disclosed technology includes an internal power supply circuit that generates an internal power supply voltage, based on a power supply voltage supplied to a power supply line, in which the influence of noise entering the power supply line is suppressed; an output circuit that includes a pair of MOSFETs that output a differential output signal and operates upon receiving the supply of the internal power supply voltage; and a drive circuit that receives the supply of the internal power supply voltage and drives the pair of MOSFETs based on a differential input signal.

[0008] The internal power supply circuit may include an operational amplifier circuit that receives a voltage corresponding to the power supply voltage and outputs the internal power supply voltage. The internal power supply circuit may include a low-pass filter provided on an input path of a voltage corresponding to the power supply voltage. The internal power supply circuit may be configured to change the level of the internal power supply voltage. The differential signal output circuit may further include a control circuit that generates a control voltage based on the differential output signal. The drive circuit may drive the pair of MOSFETs so that the low level of the differential output signal becomes a level corresponding to the control voltage. The pair of MOSFETs may form a source follower.

[0009] The differential clock generation circuit according to the disclosed technology includes the above-described differential signal output circuit, an oscillation circuit that outputs an oscillation signal having a constant frequency, and a conversion circuit that converts the oscillation signal into a differential signal and outputs the converted signal as the differential input signal. [Effects of the Invention]

[0010] According to the disclosed technology, a differential signal output circuit capable of suppressing deterioration of the characteristics of a differential output signal due to noise mixed into a power supply line, and a differential clock generation circuit to which the same is applied, are provided. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an example of a configuration of a differential signal output circuit according to an embodiment of the disclosed technique; [Figure 2] 1 is a diagram illustrating an example of a specific configuration of an internal power supply circuit and an output circuit according to an embodiment of the disclosed technique; [Figure 3] FIG. 1 is a diagram illustrating an example of a configuration of a differential signal output circuit according to a comparative example. [Figure 4] FIG. 10 is a block diagram showing an example of a configuration of a differential signal output circuit according to another embodiment of the disclosed technology. [Figure 5] FIG. 10 is an equivalent circuit diagram showing an example of a specific configuration of a differential signal output circuit according to another embodiment of the disclosed technique. [Figure 6] 10 is a time chart showing an example of an operation waveform of each part of a differential signal output circuit according to another embodiment of the disclosed technique. [Figure 7A] 10A and 10B are diagrams illustrating results of SSB phase noise and RMS phase jitter obtained by simulation for a differential signal output circuit according to another embodiment of the disclosed technique. [Figure 7B] 10A and 10B are diagrams illustrating the results of SSB phase noise and RMS phase jitter obtained by simulation for a differential signal output circuit according to a comparative example. [Figure 8] FIG. 10 is a block diagram illustrating an example of a configuration of a differential clock generation circuit according to another embodiment of the disclosed technology. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and redundant description will be omitted.

[0013] [First embodiment] 1 is a block diagram showing an example of the configuration of a differential signal output circuit 10 according to a first embodiment of the disclosed technique. The differential signal output circuit 10 receives a differential input signal S in_A , S in_B Differential output signal S according to out_A , S out_B The differential signal output circuit 10 includes an internal power supply circuit 11, a drive circuit 12, and an output circuit 13. The differential signal output circuit 10 may be formed on a semiconductor substrate. A termination circuit (not shown) is connected to output terminals 14A and 14B of the differential signal output circuit 10. A differential input signal S in_A and S in_B Similarly, the logic levels of the differential output signal S out_A and S out_B The logic levels of are opposite to each other.

[0014] The internal power supply circuit 11 is connected to the power supply line via a power supply voltage V DD Based on the internal supply voltage V IPS Generates the internal power supply voltage V IPS is a voltage where the influence of noise mixed into the power supply line is suppressed. The noise suppression by the internal power supply circuit 11 is realized by the filter function that the internal power supply circuit 11 has. The internal power supply voltage V IPS is, for example, the power supply voltage V DD Alternatively, the voltage may be a voltage obtained by lowering the level of the voltage by a predetermined level.

[0015] The output circuit 13 outputs a differential output signal S out_A , S out_B The output circuit 13 receives the internal power supply voltage V from the internal power supply circuit 11. IPSThe drive circuit 12 operates by receiving the internal power supply voltage V IPS is supplied to the differential input signal S in_A , S in_B A pair of MOSFETs constituting the output circuit 13 are driven based on the above.

[0016] 2 is a diagram showing an example of a specific configuration of the internal power supply circuit 11 and the output circuit 13. The internal power supply circuit 11 has a resistive element 81, a current source 82, and an operational amplifier circuit 84. One end of the resistive element 81 is connected to a power supply line, and the other end is connected to the current source 82. A constant current generated by the current source 82 flows through the resistive element 81, causing a voltage drop across the resistive element 81. A node n0, which is the connection point between the resistive element 81 and the current source 82, is connected to a power supply voltage V DD A voltage is generated by dropping the level of the voltage drop across the resistor element 81.

[0017] The non-inverting input terminal of the operational amplifier circuit 84 is connected to the node n0 via the low-pass filter 83. The inverting input terminal of the operational amplifier circuit 84 is connected to its own output terminal. The operational amplifier circuit 84 forms a voltage follower and outputs a voltage of the same level as the voltage generated at the node n0 as the internal power supply voltage V IPS The internal power supply voltage V IPS is the internal power supply line L IPS are supplied to.

[0018] Noise that has entered the power supply line is removed by the low-pass filter 83. Furthermore, noise can also be suppressed by the power supply voltage fluctuation removal function provided in the operational amplifier circuit 84. Therefore, even if noise has entered the power supply line, the internal power supply circuit 11 can generate the internal power supply voltage V with the influence of noise suppressed. IPS The power supply voltage fluctuation elimination function provided in the operational amplifier circuit 84 can be evaluated by an index value called PSRR (Power Supply Rejection Ratio).

[0019] The output circuit 13 outputs a differential output signal Sout_A , S out_B The output circuit 13 has p-channel MOSFETs (hereinafter referred to as p-MOS) 71, 72, 73, 74, and 75. The p-MOSs 71, 72, and 73 each have a source connected to the internal power supply voltage V IPS The internal power supply line L IPS and the gate is connected to the bias voltage V BIAS is supplied. The drain of p-MOS 71 is connected to the sources of p-MOSs 74 and 75. The drain of p-MOS 72 is connected to output terminal 14A. The drain of p-MOS 73 is connected to output terminal 14B. p-MOSs 71, 72, and 73 each function as a constant current source. The drain of p-MOS 74 is connected to output terminal 14A, and the drain of p-MOS 75 is connected to output terminal 14B. p-MOSs 74 and 75 are turned on and off complementarily in response to a drive signal supplied from drive circuit 12.

[0020] The output current of the p-MOS 71 is, for example, 15 mA, and the output currents of the p-MOSs 72 and 73 are, for example, 6 mA each. For example, when the p-MOS 74 is in the ON state and the p-MOS 75 is in the OFF state, the differential output signal S out_A is high level, and the differential output signal S out_B In this case, a current (21 mA) that is the sum of the output current (15 mA) of p-MOS 71 and the output current (6 mA) of p-MOS 72 flows through the resistor element (not shown) of the termination circuit connected to output terminal 14A, and a high-level differential output signal S out_A The output current (6 mA) of the p-MOS 73 flows through a resistor element (not shown) of the termination circuit connected to the output terminal 14B, and a low-level differential output signal S out_B will be output.

[0021] The drive circuit 12 is connected to, for example, an internal power supply line L IPS and a CMOS inverter (not shown) connected between the internal power supply voltage V IPS It operates by receiving power from

[0022] 3 is a diagram showing an example of the configuration of a differential signal output circuit 10X according to a comparative example. The differential signal output circuit 10X according to the comparative example differs from the differential signal output circuit 10 according to the embodiment of the disclosed technique described above in that it does not have an internal power supply circuit. In the differential signal output circuit 10X according to the comparative example, the drive circuit 12 and the output circuit 13 receive a power supply voltage V DD It operates by receiving power from

[0023] In the differential signal output circuit 10 according to the comparative example, when noise is mixed into the power supply line, the noise is superimposed on the drive signal supplied from the drive circuit 12 to the output circuit 13, and as a result, the differential output signal S out_A , S out_B This may result in a deterioration in the phase noise characteristics and phase jitter characteristics of the optical fiber.

[0024] On the other hand, according to the differential signal output circuit 10 according to the embodiment of the disclosed technique, the output circuit 13 and the drive circuit 12 output the internal power supply voltage V IPS As a result, even if noise is mixed into the power supply line, the drive circuit 12 can supply the output circuit 13 with a drive signal in which the influence of noise is suppressed. As a result, the differential output signal S output from the output circuit 13 OUT_A , S OUT_B That is, according to the differential signal output circuit 10 of this embodiment, it is possible to suppress deterioration of the phase noise characteristics and phase jitter characteristics of the differential output signal S OUT_A , S OUT_B It is possible to suppress the deterioration of the characteristics.

[0025] Furthermore, the differential signal output circuit 10 according to the embodiment of the disclosed technique can be realized using a more general CMOS process, and can be manufactured in a larger number of fabricators than when a bipolar process is used.

[0026] [Second embodiment] 4 is a block diagram showing an example of the configuration of a differential signal output circuit 10A according to a second embodiment of the disclosed technique. The differential signal output circuit 10A includes an internal power supply circuit 11A, a drive circuit 12A, an output circuit 13A, and a control circuit 15A.

[0027] The output circuit 13A outputs a differential output signal S out_A , S out_B The control circuit 15A has a pair of MOSFETs that output a differential output signal S out_A , S out_B Based on the control voltage V X The driver circuit 12A generates a differential output signal S out_A , S out_B The low level of the control voltage V X The differential input signal S in_A , S in_B A pair of MOSFETs constituting the output circuit 13 are driven based on the above.

[0028] 5 is an equivalent circuit diagram showing an example of a specific configuration of the differential signal output circuit 10A. The drive circuit 12A has four CMOS inverters 21, 22, 23, and 24. The CMOS inverter 21 has a p-MOS 31 and an n-channel MOSFET (hereinafter referred to as n-MOS) 32. The p-MOS 31 has a source connected to the internal power supply line L IPS The drain of the p-MOS 31 is connected to the drain of the n-MOS 32, and the drain is connected to the drain of the n-MOS 32. The source of the n-MOS 32 is connected to the ground line. The gate of the p-MOS 31 and the gate of the n-MOS 32 are connected to each other, and these are used as the input terminal of the CMOS inverter 21. The drain of the p-MOS 31 and the drain of the n-MOS 32 are connected to each other, and these are used as the output terminal of the CMOS inverter 21. The CMOS inverter 21 converts the differential input signal S in_A The signal S is the inverted logic level of 1_A Output.

[0029] The CMOS inverter 22 has a p-MOS 33 and an n-MOS 34. The p-MOS 33 has a source connected to the internal power supply line L IPSThe drain of the p-MOS 33 is connected to the drain of the n-MOS 34, and the drain is connected to the drain of the n-MOS 34. The source of the n-MOS 34 is connected to the ground line. The gate of the p-MOS 33 and the gate of the n-MOS 34 are connected to each other, and these are used as the input terminal of the CMOS inverter 22. The drain of the p-MOS 33 and the drain of the n-MOS 34 are connected to each other, and these are used as the output terminal of the CMOS inverter 22. The CMOS inverter 22 converts the differential input signal S in_B The signal S is the inverted logic level of 1_B Output.

[0030] The CMOS inverter 23 has a p-MOS 35 and an n-MOS 36. The p-MOS 35 has a source connected to the internal power supply line L IPS The drain of the p-MOS 35 is connected to the drain of the n-MOS 36, and the drain of the n-MOS 36 is connected to the node n1. The gate of the p-MOS 35 and the gate of the n-MOS 36 are connected to each other, and these are used as the input terminal of the CMOS inverter 23. The drain of the p-MOS 35 and the drain of the n-MOS 36 are connected to each other, and these are used as the output terminal of the CMOS inverter 23. The CMOS inverter 23 converts the signal S 1_A The signal S is the inverted logic level of 2_A Output.

[0031] The CMOS inverter 24 has a p-MOS 37 and an n-MOS 38. The p-MOS 37 has a source connected to the internal power supply line L IPS The drain of the p-MOS 37 is connected to the drain of the n-MOS 38, and the drain of the n-MOS 38 is connected to the node n1. The gate of the p-MOS 37 and the gate of the n-MOS 38 are connected to each other, and these are used as the input terminal of the CMOS inverter 24. The drain of the p-MOS 37 and the drain of the n-MOS 38 are connected to each other, and these are used as the output terminal of the CMOS inverter 24. The CMOS inverter 24 converts the signal S 1_B The signal S is the inverted logic level of 2_B Output.

[0032] The output circuit 13A has n-MOSs 41 and 42. The drain of the n-MOS 41 is connected to the internal power supply line L IPS , its source is connected to the output terminal 14A, and its gate is connected to the output terminal of the CMOS inverter 23. The n-MOS 41 receives the signal S output from the CMOS inverter 23. 2_A A differential output signal S with a logic level according to out_A The differential output signal S out_A is output from output terminal 14A and transmitted to a termination circuit (not shown).

[0033] The drain of n-MOS42 is connected to the internal power supply line L IPS , its source is connected to the output terminal 14B, and its gate is connected to the output terminal of the CMOS inverter 24. The n-MOS 42 receives the signal S output from the CMOS inverter 24. 2_B A differential output signal S with a logic level according to out_B The differential output signal S out_B is output from the output terminal 14B and transmitted to a termination circuit (not shown). The n-MOSs 41 and 42 constitute a source follower, and the signal S 2_A , S 2_B and the same phase differential output signal S out_A , S out_B Output.

[0034] The control circuit 15A has resistance elements 51, 52, 53, 54, an operational amplifier circuit 55, capacitors 56, 57, and a p-MOS 58. One end of the resistance element 51 is connected to the output terminal 14B, and the other end is connected to one end of the resistance element 52. The other end of the resistance element 52 is connected to the output terminal 14A. The resistance values ​​of the resistance elements 51 and 52 are the same, and a differential output signal S is output from the connection point between these elements. out_A and the differential output signal S out_B The intermediate voltage V C will be output.

[0035] The inverting input terminal of the operational amplifier circuit 55 is connected to the connection point between the resistor element 51 and the resistor element 52, and the inverting input terminal is supplied with an intermediate voltage V CA reference voltage V having a constant voltage level is input to the non-inverting input terminal of the operational amplifier circuit 55. REF is input. The output terminal of the operational amplifier circuit 55 is connected to one terminal of the resistor element 53. The other terminal of the resistor element 53 is connected to one terminal of the capacitor 56 and the gate of the p-MOS 58. The other terminal of the capacitor 56 is connected to the ground line. The drain of the p-MOS 58 is connected to the ground line, and the source is connected to one terminal of the resistor element 54, one terminal of the capacitor 57, and the node n1. The other terminal of the resistor element 54 is connected to the internal power supply line L IPS The other end of the capacitor 57 is connected to the ground line. The control circuit 15A outputs the differential output signal S out_A , S out_B The intermediate voltage V C The level of the reference voltage V REF The control voltage V X Generates a control voltage V X is output from the source of the p-MOS 58 and supplied to the node n1.

[0036] The internal power supply circuit 11A differs from the internal power supply circuit 11 according to the first embodiment in that the resistance value of the resistive element 81 is variable. IPS It is possible to change the level of

[0037] 6 is a time chart showing an example of the operating waveforms of the components of the differential signal output circuit 10A. The inverters 21 and 22 in the front stage of the drive circuit 12A respectively convert the differential input signal S in_A , S in_B The signal S is the inverted logic level of 1_A , S 1_B The signal S is output. 1_A , S 1_B The high level of the internal power supply line L IPS The internal power supply voltage V IPS The signal S 1_A , S 1_B The low level of is approximately the same as the level of the ground voltage supplied to the ground line.

[0038] The inverters 23 and 24 at the rear stage of the drive circuit 12A respectively convert the signal S 1_A , S 1_B The signal S is the inverted logic level of 2_A , S 2_B The signal S is output. 2_A , S 2_B The high level of the internal power supply voltage V IPS is approximately the same level as the signal S 2_A , S 2_B The low level of the control voltage V X It is roughly the same level as the

[0039] The n-MOSs 41 and 42 of the output circuit 13A receive the signal S 2_A , S 2_B and the same phase differential output signal S out_A , S out_B The output circuit 13A outputs a differential output signal S out_A , S out_B That is, the differential output signal S out_A , S out_B The high level of the internal power supply voltage V IPS The gate-source voltage V GS_H The differential output signal S out_A , S out_B The low level of the control voltage V X The gate-source voltage V GS_L The control voltage V X The level of the differential output signal S out_A and S out_B The intermediate voltage V C The level is the reference voltage V REF That is, the differential output signal S out_A , S out_BThe low level of the differential output signal S is set by feedback control by the control circuit 15A. out_A , S out_B When the low level of is set, the differential output signal S out_A , S out_B The amplitude (difference between high and low levels) of the differential output signal S out_A , S out_B The low level and amplitude of the reference voltage V REF It can be adjusted by the level of the reference voltage V REF The level of the differential output signal S out_A , S out_B The amplitude may be set to, for example, 0.75 V, which is the LVPECL standard.

[0040] According to the differential signal output circuit 10A of this embodiment, similarly to the differential signal output circuit 10 according to the first embodiment, the output circuit 13A and the drive circuit 12A output the internal power supply voltage V IPS Therefore, the differential output signal S OUT_A , S OUT_B It is possible to suppress the deterioration of the characteristics.

[0041] 7A and 7B show the power supply voltage V DD at 100KHz, 50mV P-P 7A and 7B are diagrams showing the results of simulations of SSB phase noise and RMS phase jitter when noise from the differential signal output circuit 10A is superimposed. FIG. 7A shows the results for the differential signal output circuit 10A having the configuration shown in FIG. 5. FIG. 7B shows the results for a differential signal output circuit according to a comparative example, which has a configuration in which the internal power supply circuit 11A is removed from the differential signal output circuit 10A having the configuration shown in FIG. 5. In the differential signal output circuit according to the comparative example, the drive circuit and the output circuit receive the power supply voltage V DD It operates by receiving power from

[0042] In the differential signal output circuit 10A according to the second embodiment of the disclosed technology, the SSB phase noise was approximately −100 dBc / Hz (offset frequency: 100 kHz), and the RMS phase jitter was 0.16 pS (integral range: 12 kHz-20 MHz). In the differential signal output circuit according to the comparative example, the SSB phase noise was approximately −60 dBc / Hz (offset frequency: 100 kHz), and the RMS phase jitter was 16.4 pS (integral range: 12 kHz-20 MHz). As such, it was confirmed that the differential signal output circuit 10A according to the second embodiment of the disclosed technology can reduce the SSB phase noise by approximately −40 dBc / Hz and reduce the RMS phase jitter by approximately two orders of magnitude compared to the differential signal output circuit according to the comparative example.

[0043] Furthermore, in the differential signal output circuit 10A according to the second embodiment, the internal power supply circuit 11A outputs the internal power supply voltage V IPS The level of the differential output signal S OUT_A , S OUT_B The user can change the high level of the differential output signal S by setting the resistance value of the resistor element 81 of the internal power supply circuit 11A. OUT_A , S OUT_B The high level can be set to any level.

[0044] Moreover, according to the differential signal output circuit 10A of the second embodiment, the differential output signal S out_A , S out_B Since the differential signal output circuit 10A outputs the differential signal in a voltage format, it is possible to output a differential output signal at a constant level regardless of the configuration of the termination circuit. Furthermore, the differential signal output circuit 10A can be realized using a more general CMOS process, and can be manufactured in a wider range of fabricators than when a bipolar process is used.

[0045] [Third embodiment] 8 is a block diagram showing an example of the configuration of a differential clock generation circuit 200 according to the third embodiment of the disclosed technique. The differential clock generation circuit 200 is configured to include the differential signal output circuit 10 according to the first embodiment or the differential signal output circuit 10A according to the second embodiment. The differential clock generation circuit 200 has an oscillation circuit 201, a level shifter 202, a signal conversion circuit 203, and the differential signal output circuit 10 (or the differential signal output circuit 10A).

[0046] A crystal oscillator 210 is connected to the oscillation circuit 201. The oscillation circuit 201 generates a sinusoidal oscillation signal S having a constant frequency. OSC The level shifter 202 outputs a sinusoidal oscillation signal S OSC is shaped into a square wave and the amplitude and signal level are adjusted. SQ The signal conversion circuit 203 outputs the single-ended signal S SQ The output signal of the signal conversion circuit 203 is converted into a differential signal and output. in_A , S in_B The differential signal output circuit 10 (or the differential signal output circuit 10A) receives the differential input signal S in_A , S in_B Differential output signal S according to out_A , S out_B The differential output signal S out_A , S out_B are terminated by a termination circuit (not shown) and supplied as differential clock signals to a subsequent circuit (not shown). Although the above description has been given of a configuration using a crystal oscillator 210, it is also possible to configure a differential clock generation circuit using a piezoelectric element or an oscillator element.

[0047] The following additional notes are further disclosed regarding the first to third embodiments described above. (Appendix 1) an internal power supply circuit that generates an internal power supply voltage, based on a power supply voltage supplied to a power supply line, in which the influence of noise entering the power supply line is suppressed; an output circuit including a pair of MOSFETs for outputting a differential output signal, the output circuit being operated by receiving the internal power supply voltage; a drive circuit that receives the internal power supply voltage and drives the pair of MOSFETs based on a differential input signal; A differential signal output circuit comprising:

[0048] (Appendix 2) The internal power supply circuit has an operational amplifier circuit to which a voltage corresponding to the power supply voltage is input and which outputs the internal power supply voltage. 2. A differential signal output circuit according to claim 1.

[0049] (Appendix 3) The internal power supply circuit has a low-pass filter provided on an input path of a voltage corresponding to the power supply voltage. 3. A differential signal output circuit according to claim 1 or 2.

[0050] (Appendix 4) The internal power supply circuit is configured so that the level of the internal power supply voltage can be changed. 4. A differential signal output circuit according to claim 1.

[0051] (Appendix 5) a control circuit that generates a control voltage based on the differential output signal; The drive circuit drives the pair of MOSFETs so that the low level of the differential output signal becomes a level corresponding to the control voltage. 5. A differential signal output circuit according to claim 1.

[0052] (Appendix 6) The pair of MOSFETs constitute a source follower. 6. A differential signal output circuit according to claim 5.

[0053] (Appendix 7) A differential signal output circuit according to any one of Supplementary Note 1 to Supplementary Note 6; an oscillation circuit that outputs an oscillation signal having a constant frequency; a conversion circuit that converts the oscillation signal into a differential signal and outputs the converted signal as the differential input signal; 1. A differential clock generation circuit comprising: [Explanation of symbols]

[0054] 10, 10A, 10X differential signal output circuit 11, 11A internal power supply circuit 12, 12A drive circuit 13, 13A output circuit 14A, 14B output terminals 15A control circuit 81 Resistor element 82 Current source 83 Low-pass filter 84 Operational Amplifier Circuit 200 Differential Clock Generation Circuit 201 Oscillator Circuit 202 Level Shifter 203 Signal conversion circuit 210 Crystal Oscillator

Claims

1. an internal power supply circuit that generates an internal power supply voltage, based on a power supply voltage supplied to a power supply line, in which the influence of noise entering the power supply line is suppressed; an output circuit including a pair of MOSFETs for outputting a differential output signal, the output circuit being operated by receiving the internal power supply voltage; a drive circuit that receives the internal power supply voltage and drives the pair of MOSFETs based on a differential input signal; A differential signal output circuit comprising:

2. The internal power supply circuit has an operational amplifier circuit to which a voltage corresponding to the power supply voltage is input and which outputs the internal power supply voltage.

2. The differential signal output circuit according to claim 1.

3. The internal power supply circuit has a low-pass filter provided on an input path of a voltage corresponding to the power supply voltage.

2. The differential signal output circuit according to claim 1.

4. The internal power supply circuit is configured so that the level of the internal power supply voltage can be changed.

2. The differential signal output circuit according to claim 1.

5. a control circuit that generates a control voltage based on the differential output signal; The drive circuit drives the pair of MOSFETs so that the low level of the differential output signal becomes a level corresponding to the control voltage.

2. The differential signal output circuit according to claim 1.

6. The pair of MOSFETs constitute a source follower.

6. The differential signal output circuit according to claim 5.

7. a differential signal output circuit according to any one of claims 1 to 6; an oscillation circuit that outputs an oscillation signal having a constant frequency; a conversion circuit that converts the oscillation signal into a differential signal and outputs the converted signal as the differential input signal; 1. A differential clock generation circuit comprising:

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