Dynamic Compensation Clamp for Current-Mode Control

Abstract

The present invention relates to a voltage clamping circuit, particularly a compensation circuit used in current mode control in a switching voltage regulator. The voltage regulator circuit includes an amplifier having an input coupled to a feedback voltage terminal and a reference voltage terminal. A comparator has a first comparator input coupled to the amplifier output and a second comparator input and a comparator output. A current sense circuit provides a current sense output proportional to the output current. A waveform generator is coupled between the second comparator input and ground. A first latch input is coupled to the comparator output. A clock generator is coupled between the second latch input and ground. A clamp circuit has a first clamp input coupled to the current sense output, a second clamp input coupled to a fixed voltage source, and a clamp output coupled to the first comparator input. The clamp circuit limits the first comparator input voltage to a clamp voltage that varies in response to the current sense output.

Description

[Technical Field]

[0001] This description relates to voltage clamping circuits, particularly compensation circuits used in current-mode control in switching voltage regulators, etc. When a switching voltage regulator includes a current-mode control loop, the switching voltage regulator can generate significant voltage spikes on the output voltage line when recovering from a voltage dropout or overcurrent condition. [Background technology]

[0002] Voltage spikes can be caused by using a fixed voltage compensation clamp on the voltage control loop error amplifier when the output voltage drops below a specified output voltage, and then by a relatively large change in the control loop compensation voltage when recovering from a dropout or overcurrent condition. Traditional solutions to the problem of output voltage overshoot when recovering from a dropout condition include responding and limiting the output voltage by controlling the high-side and low-side drive transistors. However, this can lead to sustained oscillations in the output voltage due to an inherent race condition between the output voltage and the compensation loop. Summary of the Invention

[0003] In a first example, a voltage regulator circuit includes an amplifier having first and second amplifier inputs and an amplifier output. The first amplifier input is coupled to a feedback voltage terminal and the second amplifier input is coupled to a reference voltage terminal. A comparator has first and second comparator inputs and a comparator output. The first comparator input is coupled to the amplifier output.

[0004] A current sense circuit has a current sense input and a current sense output, the current sense input is coupled to the output voltage terminal and the current sense output is coupled to the second comparator input, and the current sense circuit is configured to provide a voltage at the current sense output that is proportional to the current being delivered to the output voltage terminal.

[0005] A waveform generator is coupled between the second comparator input and a ground terminal. The waveform generator may be configured to provide a waveform signal at the switching frequency. A latch has first and second latch inputs and first and second latch outputs. The first latch input is coupled to the comparator output. A clock generator is coupled between the second latch input and the ground terminal. The clock generator may be configured to provide a clock signal at the switching frequency.

[0006] A voltage clamp circuit has first and second voltage clamp inputs and a voltage clamp output. The first voltage clamp input is coupled to the current sense output. The second voltage clamp input is coupled to a fixed voltage source. The voltage clamp output is coupled to the first comparator input. The voltage clamp circuit can be configured to limit the voltage at the first comparator input to a clamp voltage that varies in response to the voltage at the current sense output.

[0007] In a second example, a method for controlling a voltage converter circuit includes connecting a first field effect transistor (FET) in series with a second FET between an input voltage terminal and a ground terminal, an inductor coupled between a switching terminal and an output voltage terminal, the output voltage terminal providing an output voltage, and the first and second FETs connected at the switching terminal.

[0008] A compensation current is generated at the compensation terminal. The compensation current, proportional to the difference between the reference voltage and a voltage proportional to the output voltage, generates a compensation voltage that tracks the current through the inductor. A waveform signal and a clock signal, which are in phase and have the same frequency, are each generated. The compensation voltage is limited to not exceed a clamping voltage. The clamping voltage is equal to the sum of the maximum voltage of the waveform signal, the minimum compensation voltage required to trigger switching of the first and second FETs, and a current sense voltage proportional to the current through the inductor.

[0009] The compensation voltage is compared to a comparison voltage using a comparator having a comparator output, the comparison voltage being equal to the sum of a maximum voltage of the waveform signal and a minimum compensation voltage required to trigger switching of the first and second FETs, and the first and second FETs are controlled in response to the comparator output. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows a schematic diagram for an example switching voltage regulator with a fixed voltage clamp on a compensation signal.

[0011] [Figure 2] 1 illustrates a timing diagram of a compensation voltage signal and an output voltage signal in an example switching voltage regulator having a fixed voltage clamp circuit.

[0012] [Figure 3] 1 shows a voltage versus time graph for a signal of an example dynamic voltage clamp circuit.

[0013] [Figure 4] 1 shows a schematic diagram for an example switching voltage regulator with a dynamic voltage clamp circuit. DETAILED DESCRIPTION OF THE INVENTION

[0014] In this description, the same reference numbers indicate the same or similar features (in function and / or structure).The drawings are not necessarily drawn to scale.

[0015] Switching voltage regulators that include current-mode control loops can generate significant voltage spikes at their output voltage terminals when the switching voltage regulator recovers from a dropout or overcurrent condition. One common condition that can cause a large voltage spike at the output voltage terminal is the recovery of the voltage regulator after the output voltage terminal has been shorted to ground.

[0016] A second common condition that can cause large voltage spikes at the output voltage terminals is when a switching voltage regulator attempts to deliver more current than the load it can provide. This condition can produce a droop in the output voltage. A third condition that can cause large voltage spikes at the output voltage terminals is when the input voltage drops below the specified nominal output voltage. In this case, while the switching voltage regulator is operating at its maximum operable duty cycle, the output voltage V OUT follows the input voltage.

[0017] 1 is a schematic diagram of an example switching voltage regulator 100. An input voltage source 102 supplies an input voltage V IN A transistor 104 is coupled between an input voltage source 102 and a switching terminal 105. A transistor 106 is coupled between the switching terminal 105 and a ground terminal. In this example, transistor 104 operates as a high-side switch of the switching voltage regulator 100, and transistor 106 operates as a low-side switch of the switching voltage regulator 100. A voltage between the switching terminal 105 and an output voltage terminal V O An inductor 110 is connected between the current I L flows through the inductor 110. The capacitor C O 126 and resistor R O 128 is the output voltage terminal V O 130 and a ground terminal. O 126 and resistor R O 128 represent the load capacitance and load resistance of the output, respectively.

[0018] Output voltage terminal V O A resistor 132 is coupled between 130 and an output voltage feedback terminal 133. A resistor 136 is coupled between the output voltage feedback terminal 133 and a ground terminal. Resistors 132 and 136 are connected to the output voltage V O The voltage at the output voltage feedback terminal 133 is V FBThe inverting input of amplifier 134 is coupled to output voltage feedback terminal 133 and is connected to voltage V FB A reference voltage source 138 is coupled between the non-inverting input of amplifier 134 and ground and receives a voltage V REF Provides voltage V REF is the output voltage V O 130 is at a specified nominal output voltage, the voltage V at the output voltage feedback terminal 133 FB is the reference voltage that is set equal to

[0019] In at least one example, amplifier 134 is a transconductance amplifier. Amplifier 134 is configured to generate a voltage V at output voltage feedback terminal 133. FB is the reference voltage V REF At its output, V FB and V REF A clamp circuit 140 is connected between the output of amplifier 134 and ground. The purpose of clamp circuit 140 is to provide a signal proportional to the difference between the compensation voltage V COMP 135 is the specified fixed clamp voltage V Clamp The clamp circuit 140 may be a Zener diode or any other type of circuit that provides a fixed maximum voltage and can pull down voltages higher than the fixed maximum voltage to the fixed maximum voltage.

[0020] Output voltage terminal V O A current sense circuit 118 is coupled between 130 and a first non-inverting input of the comparator 112. The current sense circuit 118 senses the current flowing through the inductor 110 and provides a voltage proportional to the current through the inductor 110 to the first non-inverting input of the comparator 112. A slope compensation generator 116 is coupled between the second non-inverting input of the comparator 112 and ground. The slope compensation generator 116 provides a slope compensation waveform at the frequency of the switching voltage regulator. In at least one example, the slope compensation waveform is a sawtooth waveform.

[0021] The current sense signal provided by current sense circuit 118 is summed with a slope compensation waveform from slope compensation generator 116 to provide a non-inverting input to comparator 112. The output of amplifier 134 is coupled to the inverting input of comparator 112, at which signal V COMP Provide 135. Resistor R COMP 120 is connected to the output of amplifier 134 and capacitor C COMP 122. The capacitor C COMP The second terminal of the capacitor C122 is coupled to the ground terminal. O_EA 124 is coupled between the output of amplifier 134 and ground. Resistor R COMP 120, Capacitor C COMP 122, and capacitor C O_EA 124 forms a Type II compensation filter commonly used in current mode control circuits.

[0022] Capacitor C COMP 122 sets the crossover frequency of the Type II compensation filter. Resistor R COMP 120 is capacitor C COMP 122, which provides a zero for the Type II compensation filter. O_EA 124 typically has a small capacitance value (e.g., 10 pF) and is used primarily to filter out high frequency noise rather than to provide stability to the control loop. The stability of the control loop is primarily determined by the capacitance of capacitor C COMP 122 and resistor R COMP Provided by 120.

[0023] Although comparator 112 is shown as having three inputs, it may also be shown as having a summing terminal connected to a single non-inverting input, in which case the current sense signal from current sense circuit 118 is summed with the slope compensation waveform from slope compensation generator 116, and the summed signal is provided as the non-inverting input to comparator 112. Comparator 112 then couples this summed signal to the compensation voltage V COMP 135 and provides the output signal to the reset input of latch 108. In at least one example, latch 108 is an RS flip-flop.

[0024] A clock generator 114 is coupled between the set input of latch 108 and a ground terminal. Clock generator 114 provides a clock signal having the same frequency as the switching frequency of switching voltage regulator 100. In at least one example, the clock signal is a square wave signal. The clock signal generated by clock generator 114 is at the same frequency and in phase with the slope compensation waveform generated by slope compensation generator 116.

[0025] The Q output of latch 108 is coupled to the control terminal of transistor 104 to control the on / off of transistor 104. The QN output of latch 108, which is an inverted version of the Q output, is coupled to the control terminal of transistor 106 to control the on / off of transistor 106. In some examples, additional first and second drive stages (not shown) are coupled between the Q output of latch 108 and the control terminal of transistor 104 and between the QN output of latch 108 and the control terminal of transistor 106, respectively, to ensure that adequate drive is provided to transistors 104 and 106, respectively, to turn them on.

[0026] Switching voltage regulators that use peak current-mode control can experience problems when the switching duty cycle exceeds 50%, which can result in subharmonic oscillations that can destabilize the control loop. To allow current-mode controlled voltage regulators to operate at any duty cycle, including those greater than 50%, some type of slope compensation may be included to help avoid subharmonic oscillations.

[0027] The slope compensation signal provided by slope compensation generator 116 in switching voltage regulator 100 helps avoid subharmonic oscillations and ensure that the switching voltage regulator remains stable over the entire duty cycle. The slope compensation signal may be a sawtooth waveform having the same frequency as the switching frequency of the voltage regulator. When the slope compensation signal from slope compensation generator 116 is turned on, it is summed with the output of current sense circuit 118 to generate a compensation voltage V COMP Compared to 135.

[0028] When transistor 104 turns on, the slope compensation signal begins to increase, eventually tripping comparator 112 and providing a logic high at its output. The logic high signal provided at the reset input of latch 108 resets latch 108, which pulls down the gate voltage of transistor 104. As a result, latch 108 remains reset, and transistor 104 remains off until it turns on again in the next cycle, and then the cycle repeats.

[0029] The current through inductor 110 increases such that the voltage at the output of current sense circuit 118 is a compensation voltage V COMP When the output of comparator 112 becomes high enough to be higher than 135, the output of comparator 112 resets latch 108. A continuously running clock signal provided by clock generator 114 is provided to the set input of latch 108. This clock signal may be a square wave signal or may have some other waveform. This clock signal triggers the turning on of transistor 104. A rising edge of the clock signal sets latch 108. Transistor 104 then turns on and the current through inductor 110 begins to increase. The slope compensation signal provided by slope compensation generator 116 also begins to increase.

[0030] The sum of the slope compensation signal and the output voltage of the current sense circuit 118 is the compensation voltage V COMPWhen the input voltage Vout equals 135, the output of comparator 112 goes high, resetting latch 108. Resetting latch 108 turns off transistor 104. This control loop regulates the peak current through inductor 110. The cycle then repeats, beginning with the rising edge of the clock signal from clock generator 114. Transistor 104 then turns on and remains on until the current through inductor 110 is high enough to turn transistor 104 off.

[0031] A clamp circuit 140 is coupled between the output of amplifier 134 and ground. Clamp circuit 140 generates a compensation voltage V COMP An upper limit or clamp voltage V above which 135 cannot rise. Clamp As long as switching voltage regulator 100 is operating under nominal control conditions, the compensation voltage V COMP 135 reflects the magnitude of the current through inductor 110. During this control state, the compensation voltage V COMP 135 and the current sense voltage at the output of the current sense circuit 118 track each other. COMP The higher 135, the higher the current through inductor 110.

[0032] However, there are conditions that can cause the voltage regulator control loop to go open loop, and the voltage regulation control loop is no longer closed loop and is no longer under control. COMP The voltage shifts to either the high-side or low-side voltage rail depending on whether the output voltage is lower or higher, respectively, than its specified nominal value. Examples of conditions that can cause the voltage regulator control loop to go open include the output voltage terminal being shorted to ground, the voltage regulator attempting to deliver more current to the load than it can supply and causing the output voltage level to collapse, and the input voltage being at or below the specified nominal output voltage.

[0033] The voltage regulator control loop operates on a reference voltage, V REF138 and this is coupled to the output voltage V formed by resistors 132 and 136. O The output feedback voltage V is provided by a resistor divider on 130 FB 133. Ideally, the output feedback voltage V FB 133 is always the reference voltage V REF 138. The output feedback voltage V FB 133 is the reference voltage V REF If it is lower than 138, the compensation voltage V COMP 135 begins to increase. Without the clamp circuit 140, the compensation voltage V COMP 135 rises to the upper supply rail voltage and remains at that voltage, creating an open loop condition in the voltage control loop.

[0034] The clamp voltage V that sets the upper limit of the compensation voltage VCOMP135 Clamp should be set high enough so as not to affect the performance of the switching voltage regulator during normal operation. However, the clamp voltage V Clamp is set high enough so as not to affect the performance of the switching voltage regulator under all normal conditions. Clamp is typically set well above the voltage when the voltage control loop is closed.

[0035] Output feedback voltage V FB 133 is the reference voltage V REF If the voltage drops below 138V for a long enough time, the compensation voltage V COMP 135 rises to the clamp voltage and remains there as long as the voltage regulator is in that state. When coming out of that state, a long recovery period may be required for the voltage regulator control loop to regain full control. This recovery period is maintained by the capacitor C COMP 122 and C O_EA During the recovery period, the output voltage V O 130 can significantly overshoot. In one example, the output voltage V O130 overshoots 60% above the specified nominal voltage.

[0036] In this case, the output voltage V O The overshoot on 130 occurs when the compensation voltage V COMP 135 is in dropout state, the clamp voltage V Clamp Then, the input voltage V IN 102 rises sufficiently above the specified nominal output voltage and the dropout condition ends, the output voltage V O 130 may overshoot. This is because the compensation voltage V COMP 135 is the clamp voltage V Clamp From the output voltage V O This is because the voltage regulator control loop has not yet recovered and taken over control, due to the recovery time required to return to the voltage required to accurately control 130.

[0037] Clamp voltage V Clamp If is set to a fixed value, the fixed value should be set high enough so that the clamp does not disturb the voltage control loop during normal operation. COMP 135 also depends on the magnitude of the current through inductor 110 and the duty cycle of the switching voltage regulator. In one example, the compensation voltage V during regulated operation COMP The voltage range of 135 varied from 0.6V to 1.6V.

[0038] Therefore, V Clamp If V is set to a single fixed clamping voltage, that clamping voltage must be set high enough so as not to interfere with normal operation under any conditions. For example, the compensation voltage V COMP If 135 operates at around 800 mV during normal operation, that voltage can charge up to about 2.1 V when a dropout condition occurs. Then, when the voltage regulator comes out of dropout, the compensation voltage V COMP135 must work to drop from 2.1V to 800mV before the voltage control loop regains control. This recovery time can take tens or hundreds of microseconds. During this recovery time, the output voltage V OUT may overshoot significantly. The compensation voltage V COMP The recovery time required for a voltage change of 135 is the output voltage V O This causes the 130 overshoot problem.

[0039] 2 shows a timing diagram 200 of the compensation voltage and output voltage in an example switching voltage regulator with a fixed voltage clamp circuit. Curve 210 shows the compensation voltage V COMP 135. Curve 220 is a plot of the output voltage V O 130 is a plot of voltage versus time.

[0040] At 222, the input voltage V IN 102 is the specified nominal output voltage V OUT(nom) The output voltage V OUT The input voltage V IN 102 is the specified nominal output voltage V OUT(nom) When the output feedback voltage V FB 133 is the reference voltage V REF 138, which causes the compensation voltage V COMP 135 rises to the upper clamp voltage at 212. During the period from 222 to 224, the voltage control loop is out of control and the output voltage V OUT is not properly regulated, and the input voltage V IN In a step-down regulator, the output voltage V OUT The maximum voltage that can be reached is the input voltage V IN is equal to.

[0041] At 224, the input voltage V INrecovers and the switching voltage regulator comes out of dropout. The output voltage V OUT rises, but the specified nominal output voltage V OUT(nom) Instead, the output voltage V OUT is the specified nominal output voltage V OUT(nom) When a switching voltage regulator comes out of dropout, it overshoots to a peak voltage significantly above V COMP 135 begins to drop from the clamp voltage at 214. However, the compensation voltage V COMP A recovery time is required for 135 to discharge from the clamp voltage to the steady state value at 216. The time between 214 and 216 is the recovery time.

[0042] Compensation voltage V COMP When 135 reaches its steady state value, the voltage control loop regains control and the output voltage V OUT is 228, and the specified nominal output voltage V OUT(nom) In this case, the compensation voltage V COMP The 135 must discharge from 2.1V to 0.65V, which requires a recovery time of over 150 microseconds. During this recovery time, the output voltage V OUT The output voltage overshoots the specified nominal output voltage of 5V by more than 3V. This overshoot problem occurs during the recovery time when the clamp voltage and compensation voltage V COMP This was due to the large voltage difference between the steady state voltage of 135 and the

[0043] One solution to the overshoot problem is to dynamically adjust the clamp voltage to changing conditions rather than setting it to a fixed voltage. COMP 135. The switching voltage regulator circuit provides appropriate information to determine and generate a dynamic compensation clamp voltage that limits the amount of voltage discharge required to regulate the output voltage V O Helps limit overshoot of 130.

[0044] Clamp voltage V Clamp is the compensation voltage VCOMP This allows the voltage clamp to have no effect on circuit performance during normal operation, but to provide a compensation voltage V when the switching voltage regulator goes into dropout. COMP This helps ensure that the compensation voltage V COMP However, it can recover from dropout more quickly. COMP can recover more quickly because it tolerates a smaller fluctuation than a fixed voltage clamp circuit (e.g., 100mV instead of 1-2V).

[0045] Compensation voltage V COMP The clamp voltage V Clamp is the compensation voltage V COMP The clamp voltage V is dynamically adjusted to track and keep just above Clamp By setting OUT Then, when the switching voltage regulator goes into dropout, the compensation voltage V COMP does not require significant discharge to regain control of the voltage control loop, so the compensation voltage V COMP recovers from dropout conditions more quickly.

[0046] This depends on the current flowing through the inductor 110, which is sensed by the current sense circuit 118, to determine the clamp voltage V Clamp To trigger switching in the voltage regulator, a minimum compensation voltage V COMP 135 is required. In one example, this minimum compensation voltage V COMP_Offset However, in other systems, V COMP_Offset When operating at or near a 100% duty cycle, the maximum voltage V of the slope compensation signal from the slope compensation generator 116 is MAX_Slope_Compcan be determined for any given system. In one example system, V MAX_Slope_Comp was determined to be 340 mV. However, V MAX_Slope_Comp The magnitude of may be different in other systems.

[0047] Compensation voltage clamp base voltage V Base_Clamp is the minimum compensation voltage V COMP_Offset The maximum slope compensation voltage V MAX_Slope_Comp In some examples, a safety margin voltage V may be added to ensure that the clamping of the compensation voltage does not interfere with the normal operation of the voltage regulator. margin When the safety margin voltage is added, the base voltage V of the compensation voltage clamp Base_Clamp is the minimum compensation voltage V COMP_Offset , the maximum slope compensation voltage V when operating at 100% duty cycle MAX_Slope_Comp , and the safety margin voltage V margin is equal to the sum of

[0048] To determine the clamp voltage, the inductor current ripple is sensed and the base voltage V of the compensation voltage clamp is Base_Clamp In at least one example system, the sensed inductor current signal is added to the base voltage V of the compensation voltage clamp. Base_Clamp The inductor current signal is rectified before being added to the compensation voltage V. Rectifying the inductor current signal can improve performance because it is the peak inductor current that is regulated. COMP should be kept above this peak. Ideally, the clamp voltage V Clamp tracks the peak inductor current because no information is needed from the rest of the slope compensation waveform. Therefore, the base voltage V of the compensation voltage clamp Base_Clamp A more accurate clamp voltage can be determined by rectifying the sensed inductor current signal before adding it to

[0049] 3 shows a voltage versus time graph 300 for a signal of an exemplary dynamic voltage clamp circuit. COMP_Offset which is the minimum compensation voltage V required to trigger switching in the voltage regulator. COMP 135. Voltage 320 is the maximum voltage of the slope compensation signal from slope compensation generator 116 when the voltage regulator is operating at 100% duty cycle, V MAX_Slope_Comp Voltage 330 is a safety margin voltage V that may be added to ensure that the clamp on the compensation voltage never interferes with the normal operation of the voltage regulator. margin Voltage V margin The addition of 330 is optional and may vary depending on the system. margin 330 can be zero.

[0050] Voltage 340 is V Base_Clamp and this means that V COMP_Offset 310, V MAX_Slope_Comp 320, and safety margin voltage V margin 330. Curve 350 is the sum of the current sense voltage V ISENSE 1. Curve 360 ​​is a plot of the voltage vs. time of the compensation voltage V COMP 135 is the upper limit or clamp voltage above which V cannot rise. Clamp 1 is a plot of voltage versus time for the clamping voltage V Clamp 360 is the base voltage of the compensation voltage clamp, V Base_Clamp 340 and the current sensing voltage V ISENSE The sum of 350 and clamp voltage V Clamp 360 is set by the clamp circuit 140.

[0051] Clamp voltage V Clamp 360 is a fixed value V Base_Clamp 340, the sensed inductor current V ISENSE Equal to the value scaled by 350. Clamp voltage V Clamp 360 maintains the compensation voltage V so as not to interfere with the normal operation of the voltage regulator in any way. COMPThe clamp voltage V Clamp 360 indicates that the voltage regulator is in an open loop state and generates a compensation voltage V COMP 135 is the clamp voltage V Clamp It is set slightly higher than required so that if a rise to 360 occurs, a large voltage must be discharged to regain control and regulate the output voltage.

[0052] Clamp voltage V Clamp 360 is the compensation voltage V COMP It follows and slightly exceeds 135. Clamp voltage V Clamp 360 depends on the sensed inductor current. When the voltage regulator operates at a lower output current and the inductor current is lower, the clamp voltage V Clamp Similarly, when the voltage regulator operates at a higher output current and the inductor current is higher, the clamp voltage V Clamp 360 is the higher voltage.

[0053] 4 is a schematic diagram illustrating an example switching voltage regulator 400 with a dynamic voltage clamp circuit. An input voltage source 102 supplies an input voltage V IN Transistor 104 is coupled between input voltage source 102 and switching terminal 105 and acts as a high-side switch of the voltage regulator. Transistor 106 is coupled between switching terminal 105 and ground and acts as a low-side switch of the voltage regulator. Inductor 110 is coupled between switching terminal 105 and output voltage terminal V O 130. Current I L flows through the inductor 110. The capacitor C O 126 and resistor R O 128 is the output voltage terminal V O 130 and the ground terminal. O 126 and resistor R O 128 represent the load capacitance and load resistance on the output side, respectively.

[0054] Output voltage terminal V O A resistor 132 is coupled between 130 and an output voltage feedback terminal 133. A resistor 136 is coupled between the output voltage feedback terminal 133 and a ground terminal. Resistors 132 and 136 are coupled to the output voltage V O 130. The voltage at the output voltage feedback terminal 133 is V FB The inverting input of amplifier 134 is coupled to output voltage feedback terminal 133 and is connected to voltage V FB A reference voltage source 138 is coupled between the non-inverting input of amplifier 134 and ground and receives a reference voltage V REF Provides voltage V REF is a reference voltage representing the specified nominal output voltage of switching voltage regulator 400.

[0055] In at least one example, amplifier 134 is a transconductance amplifier. Amplifier 134 generates a voltage V at output voltage feedback terminal 133. FB is the reference voltage V REF At its output, V FB and V REF A clamp circuit 140 is connected between the output of amplifier 134 and ground. The purpose of clamp circuit 140 is to provide a signal proportional to the difference between the compensation voltage V COMP 135 is a dynamically generated clamping voltage V Clamp The clamping voltage V Clamp is the fixed voltage and the sensed inductor current V ISENSE Equals the sum of 350 scaled.

[0056] The current detection circuit 118 detects the voltage at the output terminal V O 130 and the first non-inverting input of comparator 112. Current sense circuit 118 senses the current flowing through inductor 110 and generates a voltage V proportional to the current through inductor 110. ISENSE350. A slope compensation generator 116 is coupled between the second non-inverting input of the comparator 112 and the ground terminal. The slope compensation generator 116 provides a slope compensation waveform at the frequency of the switching voltage regulator.

[0057] The current sense signal V from the current sense circuit 118 ISENSE 350 is summed with the slope compensation waveform from slope compensation generator 116 and forms the non-inverting input to comparator 112. The output of amplifier 134 is coupled to the inverting input of comparator 112, at which signal V COMP Provide 135. Resistor R COMP 120 is connected to the output of amplifier 134 and capacitor C COMP 122. The capacitor C COMP The second terminal of the capacitor C122 is connected to the ground terminal. O_EA 124 is coupled between the output of amplifier 134 and ground. Resistor R COMP 20. Capacitor C COMP 122, and capacitor C O_EA 124 forms a Type II compensation filter commonly used in current mode control circuits.

[0058] Capacitor C COMP 122 sets the crossover frequency of the Type II compensation filter. Resistor R COMP 120 is the capacitor C COMP 122 to provide a zero for the Type II compensation filter. O_EA 124 typically has a small capacitance value (e.g., 10 pF) and is used primarily to filter out high frequency noise rather than providing control loop stabilization. Control loop stability is primarily determined by capacitor C COMP 122 and resistor R COMP Provided by 120.

[0059] Although comparator 112 is shown as having three inputs, it may also be shown as having a sum terminal provided as the non-inverting input to comparator 112, in which case the current sense signal VISENSE 350 is the slope compensation wave V from the slope compensation generator 116 SLOPE_COMP and coupled to a single non-inverting input to a comparator 112. The comparator 112 converts this summed signal into a compensation voltage V COMP 135 and provides an output signal to the reset input of latch 108. In at least one example, latch 108 is an RS flip-flop.

[0060] A clock generator 114 is coupled between the set input of latch 108 and a ground terminal. The clock generator provides a square wave signal having the same frequency as the switching frequency of switching voltage regulator 400. The square wave signal generated by clock generator 114 is coupled to a slope compensation waveform V generated by slope compensation generator 116. SLOPE_COMP It has the same frequency as and is in phase with

[0061] The Q output of latch 108 is coupled to the control terminal of transistor 104 to control the on / off of transistor 104. The QN output of latch 108, which is an inverted version of the Q output, is coupled to the control terminal of transistor 106 to control the on / off of transistor 106. In some examples, additional first and second drive stages (not shown) are coupled between the Q output of latch 108 and the control terminal of transistor 104 and between the QN output of latch 108 and the control terminal of transistor 106, respectively, to ensure that adequate drive is provided to transistors 104 and 106 with sufficient current to turn them on, respectively.

[0062] The clamp circuit 140 includes a buffer amplifier 442, a summer 446, a rectifier 448, an amplifier 450, and a transistor 452. The rectifier 448 may be omitted in some exemplary systems. The buffer amplifier 442 outputs a signal V ISENSE 350. The output of buffer amplifier 442 is coupled to a first input of summer 446, which receives V ISENSE 350. The second input of summer 446 receives a constant voltage VBase_Clamp 340, which is V COMP_Offset 310, V MAX_Slope_Comp 320, and safety margin voltage V margin Equals a sum of 330.

[0063] The output of summer 446 is coupled to the input of rectifier 448. The output of rectifier 448 is coupled to the inverting input of amplifier 450. Rectifier 448 is omitted in some example systems, in which case the output of summer 446 is coupled directly to the inverting input of amplifier 450. Rectifying the inductor current can improve performance. This reduces the peak inductor current to V Base_Clamp Adding to 340 gives the most accurate clamp voltage V Clamp Ideally, the clamp voltage V Clamp 360 tracks the peak inductor current, which is provided by rectifying the inductor current sense signal, although rectifying the inductor current sense signal is not required.

[0064] In this description, the terms "terminal," "node," "interconnect," "lead," and "pin" are used interchangeably. Unless specifically stated otherwise, these terms generally refer to an interconnection between, or termination of, device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0065] In this description, "ground" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description.

[0066] In this description, the term "coupled" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a control signal to cause device B to perform a certain action, then (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0067] Although operations may be described in a particular order in this description, some operations may be optional and need not be performed in that particular order to achieve a particular result. In some instances, multitasking or parallel processing may be advantageous. Also, the separation of various system components in the above examples does not necessarily require such separation in all examples.

[0068] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. 1. A voltage regulator circuit, comprising: an amplifier having first and second amplifier inputs and an amplifier output, the first amplifier input coupled to a feedback voltage terminal and the second amplifier input coupled to a reference voltage terminal; a comparator having first and second comparator inputs and a comparator output, the first comparator input coupled to the amplifier output; a current sense circuit having a current sense input and a current sense output, the current sense input coupled to an output voltage terminal and the current sense output coupled to the second comparator input, the current sense circuit configured to provide a current sense voltage at the current sense output that is proportional to a current delivered to the output voltage terminal; a waveform generator coupled between the second comparator input and a ground terminal, the waveform generator being configurable to provide a waveform signal at a switching frequency; a latch having first and second latch inputs and first and second latch outputs, the first latch input coupled to the comparator output; a clock generator coupled between the second latch input and the ground terminal, the clock generator being configurable to provide a clock signal at the switching frequency; a voltage clamp circuit having first and second voltage clamp inputs and a voltage clamp output, the first voltage clamp input coupled to the current sense output, the second voltage clamp input coupled to a fixed voltage source, and the voltage clamp output coupled to the first comparator input, the voltage clamp circuit being configurable to limit the voltage at the first comparator input to a clamp voltage that varies in response to the current sense voltage; a voltage regulator circuit comprising:

2. 2. The voltage regulator circuit of claim 1, wherein the waveform signal is a sawtooth waveform.

3. 2. The voltage regulator circuit of claim 1, wherein the waveform signal and the clock signal are in phase.

4. 2. The voltage regulator circuit of claim 1, wherein the latch is a flip-flop, the first latch input is a reset input, and the second latch input is a set input.

5. 2. The voltage regulator circuit of claim 1, wherein the fixed voltage source provides a fixed voltage that is the sum of a maximum voltage of the waveform signal and a minimum voltage at the first comparator input required to trigger switching in the latch.

6. 2. The voltage regulator circuit of claim 1, further comprising: a resistor and a first capacitor coupled in series between the first comparator input and the ground terminal; a second capacitor coupled between the first comparator input and the ground terminal; a voltage regulator circuit comprising:

7. 7. A voltage regulator circuit according to claim 6, the amplifier is a first amplifier, the amplifier output is a first amplifier output, and the voltage clamp circuit is a buffer having a buffer input and a buffer output, the buffer input coupled to the current sense output; an adder having first and second adder inputs and an adder output, the first adder input coupled to the buffer output and the second adder input coupled to the fixed voltage source; a second amplifier having third and fourth amplifier inputs and a second amplifier output, the third amplifier input coupled to the summer output and the fourth amplifier input coupled to the first comparator input; a transistor coupled between the fourth amplifier input and a ground terminal; a voltage regulator circuit comprising:

8. 8. The voltage regulator circuit of claim 7, further comprising a rectifier circuit coupled between the summer output and the third amplifier input.

9. 8. A voltage regulator circuit as recited in claim 7, wherein the fixed voltage source provides a fixed voltage that is the sum of a maximum voltage of the waveform signal and a minimum voltage at the first comparator input required to trigger switching in the latch.

10. 2. The voltage regulator circuit of claim 1, a first transistor coupled between an input voltage source and a switching terminal, the first transistor having a first control terminal coupled to the first latch output; a second transistor coupled between the switching terminal and the ground terminal and having a second control terminal coupled to the second latch output; a voltage regulator circuit further comprising:

11. 11. The voltage regulator circuit of claim 10, further comprising an inductor coupled between the switching terminal and the output voltage terminal.

12. 12. The voltage regulator circuit of claim 11, further comprising: a first resistor coupled between the output voltage terminal and the feedback voltage terminal; a second resistor coupled between the feedback voltage terminal and the ground terminal; a voltage regulator circuit comprising:

13. 1. A method for controlling a voltage converter circuit, comprising: connecting a first field effect transistor (FET) in series with a second FET between an input voltage terminal and a ground terminal; coupling an inductor between a switching terminal and an output voltage terminal, the output voltage terminal providing an output voltage, the first and second FETs being connected at the switching terminal; generating a current at a compensation terminal, said current being proportional to the difference between a reference voltage and a voltage proportional to said output voltage, said current generating a compensation voltage that tracks the current through said inductor; generating a waveform signal and a clock signal, each having the same frequency and being in phase; limiting the compensation voltage to not exceed a clamping voltage, the clamping voltage being equal to the sum of a maximum voltage of the waveform signal, a minimum compensation voltage required to trigger switching of first and second FETs, and a current sense voltage proportional to the current through the inductor; comparing the compensation voltage to a comparison voltage using a comparator having a comparator output, the comparison voltage being equal to the sum of the maximum voltage of the waveform signal and the minimum compensation voltage required to trigger switching of the first and second FETs; controlling the first and second FETs in response to the comparator output; A method comprising:

14. 14. The method of claim 13, wherein limiting the compensation voltage comprises: providing the current sense voltage to a first input of a summer circuit having a summer output; providing a constant voltage to a second input of the summing circuit, the constant voltage comprising a maximum voltage of the waveform signal and a minimum compensation voltage required to trigger switching of the first and second FETs; coupling the summer output to a first input of an amplifier and coupling the compensation terminal to a second input of the amplifier; coupling a transistor between the compensation terminal and a ground terminal, and coupling an output of the amplifier to a control terminal of the transistor; A method comprising:

15. 15. The method of claim 14, wherein limiting the compensation voltage further comprises coupling an input of a rectifier circuit to the summer output and coupling an output of the rectifier circuit to the first input of the amplifier.

16. 15. The method of claim 14, wherein the current sense voltage is buffered using a buffer amplifier before being provided to the first input of the summing circuit.

17. 14. The method of claim 13, further comprising filtering the compensation voltage with a compensation filter.

18. 18. The method of claim 17, wherein the compensation filter includes at least one pole and one zero.

19. 14. The method of claim 13, wherein the waveform signal is a sawtooth waveform.

20. 20. The method of claim 19, wherein the voltage converter circuit is a step-down converter circuit.

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