Power semiconductor element test equipment

Abstract

It is difficult to select and change the switch circuit board that supplies the test current to the semiconductor device 117 under test. [Solution] A plurality of switch circuit boards 201 are arranged in a connector 213 of a motherboard 207. A semiconductor device to be tested is connected to a connection member 205 having a connection portion. A switch circuit and a conductor plate 204 are mounted on the switch circuit board 201. The conductor plate 204 has a portion that protrudes from the switch circuit board 201. An opening 216 is arranged above the protruding portion. A connection member 205 is inserted through the opening 216, and the connection member 205 is fitted into the protruding portion to connect. A test current is supplied to the semiconductor device to be tested via the switch circuit.

Description

[Technical Field]

[0001] The present invention relates to an electric element testing apparatus and an electric element testing method for performing power cycle tests on electric elements such as SiC, IGBT, MOS-FET, GaN-FET, bipolar transistor, and resistor element.

[0002] Provided is an electric element testing device and an electric element testing method that can efficiently reproduce stresses similar to failure modes in the actual use environment and actual use state of semiconductor elements, and can evaluate and test power semiconductor elements and the like with high accuracy. [Background technology]

[0003] The lifespan of a power semiconductor element can be attributed to thermal fatigue caused by heat generation in the power semiconductor element itself, thermal fatigue caused by temperature changes in the external environment of the power semiconductor element, and voltage fatigue caused by the voltage applied to the gate insulating film of the power semiconductor element.

[0004] Generally, life tests for power semiconductor devices are conducted by repeatedly turning current on and off. The test is carried out by applying voltage to the emitter terminal (source terminal), collector terminal (drain terminal), etc. of the power semiconductor device, passing a test current, and applying a periodic on / off signal (operation / non-operation signal) to the gate terminal.

[0005] During testing, the current applied to semiconductor elements is large, at several hundred amperes. This requires low-resistance connection wiring to avoid heat generation and voltage drop. In addition, there are many types of tests, and the connection wiring must be changed depending on the type of test. Changing the connection wiring, etc., required a long time. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2017-17822 Summary of the Invention [Problem to be solved by the invention]

[0007] The constant current applied to test semiconductor elements such as transistors is several hundred amperes or more, so the connecting wiring must be made of thick wire with low resistance. Thick connection wiring is hard and inflexible, and changing the connection of thick connection wiring to correspond to test items takes a long time. [Means for solving the problem]

[0008] The semiconductor device testing device of the present invention separates the area (space) within the semiconductor device testing device where the transistors 117 to be tested are arranged from the area where the circuit board is arranged, where the test current for the transistors 117, etc. is generated, the control signal is generated, and the test results are acquired. A partition wall is provided for separation.

[0009] In this specification, the drawings, etc., plugs and other components used in the connection portion will be described as connection plugs or fork plugs. However, they are not limited to connection plugs or fork plugs, and any component of any shape, configuration, or structure may be used as long as it is detachable and can achieve electrical connection.

[0010] The transistor to be tested is connected to a circuit board having a switch circuit, etc., by inserting a connection plug (fork plug) 205 through an opening 216 provided in a partition wall 214 and electrically contacting the connection plug (fork plug) 215 with a conductor plate 204 on the circuit board. [Effects of the Invention]

[0011] Partitions 214 and 215 are provided to separate the area (space) within the semiconductor element testing equipment where transistors 117, etc. are placed from the placement area of ​​the circuit board where test currents for the transistors 117, etc. are generated, control signals are generated, and test results are obtained.

[0012] A shield plate, a shield film, or the like that absorbs noise is formed or placed on the partition wall 214, etc. The shield plate, etc. can suppress malfunctions of the power supply device, the test circuit, and the test semiconductor element. A fork plug 205 is inserted through an opening 216 provided in the partition wall 214, and the fork plug 205 is connected to a conductor plate 204 on the circuit board.

[0013] Which semiconductor element 117 to be tested is connected to the test circuit can be easily changed by changing the position of fork plug 205 inserted into opening 216. Furthermore, because fork plug 205 can be electrically connected to conductor plate 204 with an appropriate pressure, there is no need to manage the tightening torque as with nuts, etc.

[0014] The work of connecting or changing the connection of the connection wiring 211 for each test item is easy because it is done by changing the position of the fork plug 205, and the time required to change the connection of the connection wiring 211 and the power supply wiring 212 can be significantly reduced. In addition, no work space is required for changing the connection of the wiring, and no wiring space is required for the connection wiring 211. Therefore, the semiconductor device testing apparatus can be made smaller. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention; [Figure 2] 1 is a configuration diagram of a semiconductor device testing device according to the present invention; [Figure 3] 1A and 1B are explanatory diagrams and an equivalent circuit diagram of a semiconductor element to be tested; [Figure 4] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention; [Figure 5] 1 is an explanatory diagram and a configuration diagram of a semiconductor device testing device according to the present invention; [Figure 6] 1 is an explanatory diagram and a configuration diagram of a semiconductor device testing device according to the present invention; [Figure 7] 1A and 1B are explanatory and structural diagrams of a heat pipe portion of the present invention; [Figure 8] 1A and 1B are explanatory and structural diagrams of a heat pipe portion of the present invention; [Figure 9] 1A and 1B are explanatory and structural diagrams of a mounting portion of a semiconductor element according to the present invention; [Figure 10] 1A and 1B are explanatory and structural diagrams of a mounting portion of a semiconductor element according to the present invention; [Figure 11] 1A and 1B are explanatory and structural diagrams of a mounting portion of a semiconductor element according to the present invention; [Figure 12] 1A and 1B are explanatory and structural diagrams of a mounting portion of a semiconductor element according to the present invention; [Figure 13] 3 is an explanatory diagram of an electrical connection portion of the semiconductor device testing apparatus of the present invention. [Figure 14] 1A and 1B are explanatory and configuration diagrams of an electrical connection portion of a semiconductor device testing apparatus according to the present invention; [Figure 15] 1A and 1B are explanatory and configuration diagrams of an electrical connection portion of a semiconductor device testing apparatus according to the present invention; [Figure 16] 1A and 1B are explanatory and configuration diagrams of an electrical connection portion of a semiconductor device testing apparatus according to the present invention; [Figure 17] 1 is an explanatory diagram and a block diagram of a semiconductor device testing apparatus according to the present invention; [Figure 18] 1 is an explanatory diagram and a configuration diagram of a semiconductor device testing device according to the present invention; [Figure 19] 1 is a timing chart of a test method for a semiconductor device according to the present invention; [Figure 20] 2 is an explanatory diagram of an electric circuit section of the semiconductor device testing apparatus of the present invention. [Figure 21] 2 is an explanatory diagram of an electric circuit section of the semiconductor device testing apparatus of the present invention. [Figure 22] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 23] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 24] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 25] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 26] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 27] 1A and 1B are a block diagram and a timing chart of a semiconductor element device according to the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, a testing apparatus and a testing method for an electric element according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the embodiments described in the specification, the IGBT will be mainly used as an example of a power semiconductor element as an electric element.

[0017] The present invention is not limited to IGBTs, but can be applied to various semiconductor elements such as SiC transistors, MOSFETs, JFETs, thyristors, diodes, thermistors, and posistors.

[0018] Furthermore, the present invention is not limited to semiconductor elements, and it goes without saying that the present invention can also be applied to electrical elements other than semiconductors, such as resistor elements, capacitors, coils, quartz elements, and ZNR.

[0019] In each drawing for explaining the mode for carrying out the invention, elements having the same function or similarity are given the same reference numerals. Matters unnecessary for the explanation are omitted from the drawings. In addition, the drawings may be simplified or schematic to facilitate the explanation. Explanations may also be omitted in the specification. The embodiments of the present invention can be combined and modified with each other.

[0020] Figure 2 is a diagram illustrating the configuration and explanation of the semiconductor device testing apparatus of the present invention. As shown in Figure 2(a), the semiconductor device testing apparatus of the present invention has a housing 210, a chiller (cooling / warming device) 136, a heating / cooling plate 134, and a circulating water pipe 135 that circulates water between the heating / cooling plate 134 and the chiller 136. Transistors 117 to be tested and the like are placed in close contact with the heating / cooling plate 134.

[0021] The control circuit 133 sets test conditions by changing the current Id, gate voltage Vg, and voltage Vce so that the temperature information Tj of the transistor 117 to be tested reaches a predetermined value, and then performs the test.

[0022] If the temperature information Tj changes or changes to a predetermined value, it is determined that the transistor 117 has deteriorated or its characteristics have changed, and the test of the transistor 117 is stopped or the control method is changed.

[0023] For example, a change in the temperature information Tj is used to determine or judge a change in the characteristics of the transistor 117. Also, the change in the characteristics, reliability, and lifespan of the transistor 117 are evaluated based on the time it takes for the voltage Vce to reach a predetermined voltage, the time it takes for the transistor 117 to break down, etc.

[0024] In the semiconductor testing method of the present invention, the external conditions are changed in response to the deterioration or characteristic changes of transistor 117. For example, if transistor 117 generates heat, the water temperature is lowered. Lowering the water temperature or reducing the current flowing through transistor 117 prevents the deterioration and characteristic changes of transistor 117 from progressing, thereby extending the lifespan of transistor 117. Therefore, the lifespan and reliability characteristics of transistor 117 under specified set conditions can be quantitatively measured and determined.

[0025] The temperature of the transistor 117 is maintained at a specified or predetermined value by heating or cooling the circulating water in the chiller 136. The temperature of the transistor, etc. is periodically changed in accordance with the test conditions, and the transistor is cooled or heated to a constant value. Temperature information Tj of the test transistor is measured, and the chiller 136 is controlled to maintain the measured temperature information Tj at a constant value.

[0026] The chiller 136 keeps the temperature of equipment, etc. constant by circulating the heat medium while managing the liquid temperature of water or heat medium. The chiller 136 is often used mainly for cooling, but it can also heat as well as cool. The chiller 136 is configured to be able to control various temperatures.

[0027] 2(b), the partition wall 217 has an opening 216 for inserting a connection structure 218, which will be described in Figures 7, 9, 11, etc. The partition wall 215 has a hole for inserting a power supply wiring 212.

[0028] The control rack 131 has a power supply device 132 that supplies a test current and a test voltage to the semiconductor device 117, and a control circuit 133 that controls the semiconductor device 117 and the like or sets test conditions.

[0029] The control circuit 133 sets test conditions by changing the current Id, gate voltage Vg, and voltage Vce so that the temperature information Tj of the semiconductor element 117 becomes a predetermined value, and then performs the test. The control circuit 133 controls the power supply device 132, which supplies a test voltage or current to the semiconductor device 117 under test.

[0030] If the temperature information Tj changes or changes to a predetermined value, it is determined that the semiconductor element 117 has deteriorated or its characteristics have changed, and the test of the semiconductor module 117 and the semiconductor element 117 is stopped or the test method or control method is changed.

[0031] The temperature of the semiconductor element 117 is maintained at a specified or predetermined value by heating or cooling the circulating water of the chiller 136. The temperature of the semiconductor element, etc. is periodically changed in accordance with the test conditions, and the semiconductor element is cooled or heated to a constant value. Temperature information Tj of the semiconductor element 117 is measured, and the chiller 136 is controlled so as to maintain the measured temperature information Tj at a constant value.

[0032] The semiconductor device testing apparatus and semiconductor device testing method of the present invention can accommodate a wide variety of semiconductor devices 117 and semiconductor modules 117, as shown in Fig. 3, for example. The semiconductor device 117 in Fig. 3 has P, O, and N electrode terminals to which a large current is applied or output. 3A and 3B are a schematic view and an equivalent circuit diagram of a semiconductor device, respectively. 3A and 3B show a configuration including one transistor 117 and a diode Di.

[0033] 3(b1) and 3(b2) show a configuration including a transistor 117 (transistor 117m, transistor 117s) and a diode Di (diode Dim, diode Dis).

[0034] 3(c1)(c2) shows a configuration in which a plurality of transistors are connected together to perform testing by connecting the terminals of a semiconductor element having a transistor 117 (transistor 117m or transistor 117s) and a diode Di (diode Dim or diode Dis).

[0035] 3(d1) and 3(d2) show a configuration having a transistor 117 (transistor 117m, transistor 117s) and a diode D (diode Ds, diode Dm) having a terminal independent of the terminal of the transistor.

[0036] Figures 3(e1) and (e2) show a configuration in which multiple transistors are connected together to perform testing by connecting the terminals of a semiconductor element having a transistor 117 (transistor 117m or transistor 117s) and a diode D (diode Dm or diode Ds) having a terminal independent of the terminal of the transistor. In the following embodiment, the semiconductor device 117 shown in Fig. 3 will be mainly used as an example for explanation. Fig. 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention.

[0037] 1 shows one power supply device 121. The number of power supply devices 121 is not limited to one. For example, the semiconductor device testing apparatus of the present invention may have two or more power supply devices 121. The more power supply devices 121 there are, the more diverse the current waveforms Id that can be generated. In the embodiment of the present invention, the power supply device 121 is described, but the power supply device 121 is not limited to one that outputs a constant current.

[0038] For example, a power supply device 121 capable of setting a maximum (limit) voltage is used. An example is a device that functions to output a predetermined constant current at the set maximum voltage under certain conditions. Another example is a configuration in which the output terminal voltage can be set to a predetermined maximum voltage when a constant current is output.

[0039] The power supply device 132 outputs a large constant current for testing the transistor 117. The power supply device 132 supplies power (current, voltage) in synchronization with a control signal from the control circuit board (controller) 111. The power supply device 132 can set the maximum voltage value to be output. The switch circuit 122 (SWa) has a function of turning on (supply, application) and off (shutoff, open) the supply of the constant current output by the power supply device 132. The semiconductor device testing apparatus of the present invention is not limited to having one power supply device 132. Two or more power supply devices 132 may be provided.

[0040] In the embodiment of the present invention, a fork plug will be described as an example of the connection plug 205. Fork plugs 205 are connected to one end of each connection wiring 211 and each power supply wiring 212, such as fork plug 205e connected to the collector terminal of transistor 117 and fork plug 205d connected to one terminal of power supply device 132, and are then connected to conductor plate 204.

[0041] Although the present specification and drawings describe the conductor plate 204 as a plate, it is not limited to a plate and may be rod-shaped. Any shape may be used as long as it can be joined to a structure such as the fork plug 205. For example, it may be a structure such as a socket or connector. Furthermore, the conductor plate 204 may be shaped like a fork plug, and the fork plug 205 may be connected to the fork plug. The present invention is not limited to this. For example, the fork plug 205d may be omitted and the power supply wiring 212 may be electrically connected directly to the conductor plate 204c.

[0042] The present invention may have any configuration as long as a fork plug 205 is formed or placed on at least one terminal of the transistor 117 to be tested, and an electrical connection is made between the fork plug 205 and a connection object such as a conductor plate 204.

[0043] The fork plug 205 will be described as being inserted into a component or structure that separates spaces, such as the partition wall 214. However, this is not limiting. For example, the fork plug 205c may be connected to the conductive plate 204b, inserted through the partition wall 214, and electrically connected to one terminal (emitter terminal e) of the transistor 117.

[0044] The partitions 214, 215, and 217 of the semiconductor device testing apparatus of the present invention may be of any shape as long as they divide or separate spaces or regions, and may have a wide variety of configurations or structures such as a wall, plate, mesh, film, or foil.

[0045] The fork plug 205 may have any configuration, structure, form, style, or method that allows electrical connection to an object such as the conductive plate 204 by press-fitting, pressure welding, insertion, crimping, clamping, or the like. It goes without saying that the above matters also apply to other embodiments described in this specification and the drawings, and can also be combined with other embodiments.

[0046] The test current Id to be passed through the transistor 117 is supplied by operating the power supply device 132. The power supply device 132 is controlled to operate / not operate (on / off) by a signal from the control circuit board (controller) 111. The power supply device 132 also switches between outputting and not outputting the current Id. The timing of the device control circuit board 209 is controlled by the control circuit board (controller) 111.

[0047] In Fig. 1, the transistor 117 to be tested will be described as having a diode Di as shown in Fig. 3(a). It goes without saying that the semiconductor element testing apparatus and semiconductor element testing method of the present invention can also be applied to semiconductor elements 117 having multiple transistors in one package as shown in Fig. 3(b) and Fig. 3(d), and semiconductor modules 117 in which multiple transistor elements are connected as shown in Fig. 3(c) and Fig. 3(e).

[0048] The following description will be given assuming that the emitter terminal e of the transistor 117 is grounded. The gate terminal g of the transistor 117 is connected to the gate driver circuit 113.

[0049] In the sample connection circuit 203, a gate driver circuit 113, a variable resistance circuit 125, a constant current circuit 118, and an operational amplifier (buffer circuit) 116 are arranged or formed.

[0050] The sample connection circuit 203 is separated from the device control circuit board 209 and electrically connected by a connector 208 so that it can be placed near the transistor 117 to be tested.

[0051] The sample connection circuit 203 is connected to the transistor 117 via a connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminal g of the transistor 117 are arranged so that the distance between them is short, 30 mm or less. If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise etc. will be superimposed on the gate terminal g, causing the transistor 117 to malfunction.

[0052] 1, a test signal is applied to the gate terminal g of the transistor 117 from the gate driver circuit 113. The gate driver circuit 113 has an operational amplifier circuit.

[0053] 5, the device control circuit board 209 is placed in room B of a housing 210 of the semiconductor device tester. The housing 210 incorporates a power supply unit 132, a drive circuit system, a heating / cooling plate 134, and the like.

[0054] The sample connection circuit 203 is placed in the C1 chamber of the housing 210 of the semiconductor device testing device in order to be located close to the transistor 117 to be tested. The sample connection circuit 203 is connected to a connector 208 placed on the side of the housing 210. Wiring connected to the connection pin 206 of the connector 208 is connected to a device control circuit board 209 in the B chamber.

[0055] The sample connection circuit 203 is connected to a device control circuit board 209 by connection pins 206 of a connector 208. The sample connection circuits 203 are individually arranged corresponding to the transistors 117 to be tested, and the sample connection circuits 203 are configured so as to be easily detachable by connectors 202, etc.

[0056] A constant current circuit 118 supplies a constant current Ic to a diode Di arranged or formed between the channels of the transistor 117. An operational amplifier circuit 116 buffers (lowers the output impedance of) the terminal voltage of the diode Di and outputs it as a voltage Vi. The voltage Vi is converted from analog to digital by a temperature measurement circuit 115.

[0057] The terminal voltage Vi of the diode Di is applied to the temperature measurement circuit 115. The temperature measurement circuit 115 obtains temperature information Tj of the transistor 117 from the terminal voltage Vi and transfers it to the control circuit board 111. The temperature information is output from the connector 213 of the device control circuit board 209 to the motherboard 207 and sent to the control circuit board 111.

[0058] The gate driver circuit 113 applies a set frequency (on-off cycle) and a set on-voltage to the gate terminal of the transistor 117. As an example, as shown in FIG. 27(b), the on-off cycle of the transistor 117 is t cycle, and the on time is ton.

[0059] The transistor 117 is activated / deactivated (on / off) by the Vg signal voltage output from the gate driver circuit 113, and a current Id flows between the channels of the transistor 117 while the transistor 117 is on.

[0060] The gate driver circuit 113 has a variable resistance circuit 125. The resistance value Vr of the variable resistance circuit 125 is configured so that it can be set to a constant voltage or a voltage that changes over time between 0 (Ω) and 500 (Ω).

[0061] A resistor R (not shown) may be disposed between the gate terminal g and the emitter terminal e or collector terminal c of the transistor 117. By adjusting the value of the resistor R, the slope angles of the rising and falling voltage waveforms of the gate signal can be adjusted.

[0062] The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate voltage signal applied to the gate terminal g of the transistor 117. By separately adjusting the rise time Tr and the fall time Td, the on-time and on-characteristics of the transistor 117 are controlled to predetermined values.

[0063] As described above, the semiconductor device testing apparatus and testing method of the present invention can control, adjust, or set the resistance value of the variable resistance circuit connected to the gate terminal of transistor 117 or the rise time / fall time of gate driver circuit 113.

[0064] 1 and other figures, the resistance value Vr of the variable resistance circuit 125 of the gate driver circuit 113 is variable, but this is not limiting. For example, it goes without saying that the variable resistance circuit 125 may be an external resistor, and this resistor may be connected to the gate terminal of the transistor 117 by a connector (not shown) or the like.

[0065] The constant current circuit 118 supplies a predetermined constant current Ic. The constant current Ic is applied to the diode Di. When the temperature of the transistor 117 changes, the terminal voltage of the diode Di changes. By monitoring the terminal voltage of the diode Di, the temperature change of the transistor 117 can be measured or observed.

[0066] The diode Di may be a diode of another semiconductor chip mounted on the semiconductor chip on which the transistor 117 is formed. The diode Di may utilize a parasitic diode that is formed secondarily when the transistor 117 is formed.

[0067] In order to prevent the transistor 117 from generating heat due to the constant current Ic, the constant current Ic is set to a current value that is sufficiently smaller than the constant current Id that flows through the channel of the transistor 117 .

[0068] Specifically, the constant current Ic is set to 1 / 1000 or less of the current Id that is passed through the transistor 117 during testing. Preferably, the current Ic that is passed through the transistor 117 is set to 1×10 of the current Id. 6 1 or more of 1 x 10 4 The constant current Ic should be between 0.1mA and 100mA.

[0069] The channel current Id is changed, and the diode Di voltage (the voltage between the collector and emitter terminals of the transistor 117) is measured to determine the temperature coefficient K. The determined temperature coefficient K is stored in the temperature measurement circuit 115 or the controller 111.

[0070] The temperature coefficient K is determined by heating the transistor 117 to a predetermined temperature using the heating / cooling plate 134, passing a constant current Ic through the diode Di, and measuring the terminal voltage. By varying the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage of the diode Di relative to the temperature of the transistor 117 can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be determined from the terminal voltage of the diode Di relative to the temperature.

[0071] The constant current Ic is passed through the diode Di when the channel current Id is not flowing. In other words, when the transistor 117 is not turned on, the constant current Ic is passed and the voltage across the diode Di is measured. An operational amplifier circuit (buffer circuit) 116 outputs a terminal voltage Vi (terminal c-terminal e) of the diode Di.

[0072] The operational amplifier circuit 116 is not limited to one configured with an operational amplifier element, but may be any circuit having an output impedance lower than the input impedance. The temperature measurement circuit 115 obtains temperature information Tj of the transistor 117 being tested from the stored temperature coefficient K and voltage Vi.

[0073] The obtained temperature information Tj is sent to a control circuit board (controller) 111. When the temperature information Tj becomes equal to or exceeds a predetermined set value, the control circuit board (controller) 111 determines that the transistor 117 is in a predetermined stress state or a deteriorated state, and changes the control of the test or stops the test.

[0074] In the embodiment shown in FIG. 1 and other figures, the switch circuits Ssa124a and Ssb124b are indicated by the symbols for the switch circuits. The switch circuits 124 such as the switch circuits Ssa124a and Ssb124b can be used as switch circuits as long as they have a small resistance (on-resistance) when closed (on). Examples of such switch circuits include transistors, mechanical relays, phototransistors, photodiode switches, and photoMOS relays.

[0075] 4A and 4B are an equivalent circuit diagram and an explanatory diagram of a semiconductor device testing apparatus according to a first embodiment of the present invention. In this embodiment, the switch circuit Ssa 124a and the switch circuit Ssb 124b use power MOSFETs 124, as shown in FIG. 4B. MOSFETs are preferable because the voltage (Vsd) between their channels is small.

[0076] The channel voltage (Vsdb) of the power MOSFET 124b when it is on is selected to be equal to or lower than the channel voltage (Vsda) of the power MOSFET 124a when it is on. In other words, the channel voltage (Vsdb) of the power MOSFET 124b when it is on is set to be smaller than the channel voltage (Vsda) of the power MOSFET 124a when it is on. This is to ensure a stable flow of the current Im when the switch circuit 124b is turned on and the terminals of the power supply device 132 are short-circuited. When the switch circuit 124 a is turned on, the test current Id output by the power supply device 132 is supplied to the transistor 117 .

[0077] The switch circuit 124 is mounted or formed on the switch circuit board 201. The switch circuit 124 is connected to a conductor plate 204. The conductor plate 204 is, for example, a copper plate having a thickness of 5 mm and a width of 50 mm. The length of the conductor plate 204 is, for example, 250 mm. 5 and 13 show the fork plug 205 and the connection (contact) state between the fork plug 205 and the conductive plate 204. FIG.

[0078] Fig. 13(a) is a diagram showing a state in which a conductor plate 204 is attached to a switch circuit board (printed circuit board) 201 on which a switch circuit and the like are formed, and a fork plug 205 is connected to the conductor plate 204, as viewed from above. Fig. 13(b) is an explanatory diagram showing a state in which the fork plug 205 is clamped at one end of the conductor plate 204. 1, two conductive plates 204 are attached to the switch circuit board 201. The conductive plates 204 and the switch circuit board 201 are fastened together with screws.

[0079] Electrical connection is achieved by mechanically fitting fork plug 205 and conductor plate 204. When the U-shaped portion of fork plug 205 is inserted into conductor plate 204, the U-shaped portion expands slightly or makes proper contact, resulting in a good joint between fork plug 205 and conductor plate 204. 13, a connection bolt 219 is attached to the fork plug 205. A connection wire 211 is connected to the connection bolt 219 or the like.

[0080] A cross section taken along line AA' in Figure 13(a) is shown in Figure 13(b). The conductive plate 204 and the fork plug 205 make contact at contact parts 220a and 220b formed on the fork plug 205. The contact parts 220 are made of phosphor bronze and nickel alloy, and have spring properties. The surface of the contact parts 220 is gold-plated or silver-plated. The plating improves the electrical stability of the connection parts 220.

[0081] As shown in FIGS. 5 and 6, the fork plug 205 and the conductor plate 204 are electrically connected by inserting the fork plug 205 through an opening 216 in the partition wall 214 .

[0082] 5 shows the arrangement of each component of the semiconductor device testing apparatus of the present invention. The housing 210 of the semiconductor device testing apparatus has multiple sections. The lower part of the housing is separated into chambers A and B. The power supply unit 132 is placed in chamber A. Chambers A and B are separated by a partition wall 215. Chambers C1 and C2 are separated by a partition wall 217.

[0083] The power supply device 132, switch circuit board 201, and transistor 117 generate large noises due to repeated operation / non-operation. The noise can cause malfunctions of the circuit boards, etc. Malfunctions can be prevented by providing electrostatic and electromagnetic shields to the partition walls of each chamber.

[0084] Electrostatic shielding and electromagnetic shielding are realized by attaching or forming conductive plates, conductive plates, conductive films, metal plates, metal films, or wire mesh around the periphery of each chamber or on the surface of or inside the partition wall.

[0085] In the C1 chamber, the heating / cooling plate 134, the circulating water pipe 135, etc. shown in FIG. 2 are arranged, and the transistor 117 to be tested is arranged in close contact with the heating / cooling plate 134.

[0086] Water leak sensors (not shown) are installed around the heating and cooling plate in chamber C1. If the circulating water (cooling medium) leaks, the water leak sensors will activate and stop the semiconductor device testing equipment or issue an alarm.

[0087] A drainage groove (not shown) is formed around the periphery of the heating / cooling plate 134. When circulating water (cooling medium) leaks from the heating / cooling plate, the circulating water (cooling medium) flows into the drainage groove and is discharged outside the semiconductor device testing apparatus. The heating / cooling plate 134 is mounted on a tray (not shown), and the tray is configured to be detachable from the partition wall 214 . As described above, the partition wall 214 is configured so that even if the circulating water pipe 135 or the like is damaged, the circulating water (cooling medium) or the like will not leak into the lower chambers A and B.

[0088] A partition wall 215 is formed between chamber A, in which the power supply unit 132 is disposed, and chamber B, in which the drive circuit system is disposed. An electrostatic shield plate or an electromagnetic shield plate is disposed on the partition wall 215, which blocks noise from the power supply unit 132 and prevents the noise from being applied to the drive circuit system in chamber B.

[0089] In this embodiment of the present invention, a fork plug 205 is inserted from chamber C2 and connected to the conductive plate 204 in chamber B. An opening 216 into which the fork plug 205 is inserted is formed in the partition wall 214.

[0090] In this embodiment of the present invention, the fork plug 205 is inserted from the top to the bottom. However, the present invention is not limited to this. For example, the conductor plate 204 may be placed in the C2 chamber, and the fork plug 205 may be inserted from the B chamber to electrically connect the fork plug 205 and the conductor plate 204.

[0091] 13(c), a connector 213 is attached to a motherboard 207. A control circuit board 111, a device control circuit board 209, and a switch circuit board 201 are attached to the connector 213 of the motherboard 207. The number of switch circuit boards 201 is prepared according to the number of transistors 117 to be tested. The number of switch circuit boards 201 can be easily adjusted by changing the number of switch circuit boards 201 attached to the motherboard 207.

[0092] Temperature information Tj, voltage Vi, a control signal for the variable resistance circuit 125, a control signal for the constant current circuit 118, etc. are transmitted to the motherboard 207. In addition, power supply wiring and ground wiring for each circuit are formed and supplied to each circuit board via a connector 213.

[0093] 13(c), the conductive plate 204 is disposed so as to protrude from the switch circuit board 201. A fork plug 205 is connected to this protruding portion.

[0094] The fork plug 205a is connected to the conductor plate 204a of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through an opening 216 in the partition wall 215.

[0095] 1 and 5, fork plug 205d is connected to conductor plate 204c of switch circuit board 201b. Power supply wiring 212 is connected to switch circuit board 201b through opening 216 in partition wall 215. Fork plug 205b is connected to conductor plate 204b of switch circuit board 201a. Power supply wiring 212 is connected to switch circuit board 201a through opening 216 in partition wall 215.

[0096] 1 and 4, a switch circuit 124a is disposed between the conductor plates 204d and 204c of the switch circuit board 201a, and electrically shorts the conductor plates 204d and 204c. By shorting the conductor plates 204d and 204c, the current Id output by the power supply device 132 is supplied to the transistor 117 as the test current Id.

[0097] 4, switch circuit 124b is disposed between conductor plate 204a and conductor plate 204b of switch circuit board 201b. When switch circuit 124b is turned on, a short circuit occurs between conductor plate 204a and conductor plate 204b. This short circuit causes current Id output by power supply device 132 to flow to ground as discharge current Im. Therefore, no voltage is applied across the channel of transistor 117, and no current flows through transistor 117, preventing overvoltage and overcurrent from being applied to electrical elements such as transistor 117.

[0098] Fork plug 205c is connected to conductive plate 204b. Fork plug 205b is connected to conductive plate 204a. Fork plug 205e is connected to conductive plate 204d. Fork plug 205d is connected to conductive plate 204c.

[0099] The fork plug 205 is made of a metal such as aluminum. The fork plug 205 has a nickel-plated base and a silver-plated surface. The fork plug 205 is formed with a thread so that the connection wiring 211 can be attached to the fork plug 205 with a connection bolt 219 .

[0100] 5 shows two switch circuit boards 201a and 201b. The switch circuit board 201 is connected to a connector 213 on the mother board 207.

[0101] 5 and 6, fork plug 205c is inserted through opening 216 in partition wall 214 provided between chamber C2 and chamber B, and is connected to conductive plate 204b. Fork plug 205e is inserted through opening 216 in partition wall 214 provided between chamber C2 and chamber B, and is connected to conductive plate 204d.

[0102] The current flowing through the transistor 117 to be tested is large, at several hundred amperes, so the thickness of the connection wiring 211 used is also large. Therefore, the large connection wiring 211 and power supply wiring 212 are hard. Therefore, it is not easy to change the connection of the connection wiring 211 and power supply wiring 212.

[0103] In the semiconductor device testing apparatus of the present invention, the fork plug 205 is inserted from the C2 chamber into any opening 216 in the partition wall 214. By changing the position of the opening 216 into which the fork plug 205 is inserted, connection to any switch circuit board 201 is possible. Therefore, changing the connection with the switch circuit board 201 to be used depending on the test conditions of the transistor 117 does not require changing the wiring of the connection wiring 211, but only requires changing the position of the opening 216 into which the fork plug 205 is inserted. Also, as shown in FIG. 13(c), the switch circuit board 201 only requires changing the position of the connector 213 that connects to the motherboard 207.

[0104] As described above, the switch circuit board 201 and the device control circuit board 209 connected to the motherboard 207 are arranged according to the test content of the electric elements 117 such as semiconductor elements and the number of electric elements 117 to be tested. In addition, the connection switching with the switch circuit board 201 etc. is performed by changing the position of the fork plug 205 inserted into the opening 216 of the partition wall 214.

[0105] 1, 4, 5, 6, 16, 18, etc., connection wiring 211b connected to transistor 117 is connected to fork plug 205c. Connection wiring 211a connected to transistor 117 is connected to fork plug 205e. By detaching fork plug 205c and fork plug 205e from conductor plate 204, semiconductor device 117 to be tested can be detached from the test circuit.

[0106] 4 and other figures, the number of switch circuit boards 201b that short-circuit the outputs of the power supply devices 132 may correspond to the number of the power supply devices 132. For example, if the semiconductor device tester has one power supply device 132, one switch circuit board 201b (switch circuit 124b) may be sufficient.

[0107] The number of switch circuit boards 201b required corresponds to the number of transistors 117 to be tested. For example, if there are 12 transistors 117 to be tested, it is preferable to prepare 12 switch circuit boards 201b. Specifically, the number of switch circuits prepared corresponds to the number of electric elements 117 to be tested.

[0108] It is advantageous in terms of cost if the switch circuit board 201a for testing the electric element 117 and the switch circuit board 201b for short-circuiting the output of the power supply device 132 are made to the same board specifications.

[0109] It is preferable that a plurality of transistors or the like be mounted as the switch circuits 124 on the switch circuit board 201. The greater the number of switch circuits 124, the smaller the impedance that short-circuits the two conductive plates 204 can be.

[0110] 14(a) and (b) illustrate the state in which the fork plug 205 is inserted into the opening 216 of the partition wall 214. Fig. 14(a) is a view from the front side of the partition wall 214, and Fig. 14(b) is a view from the back side of the partition wall 214.

[0111] 14, fork plug 205b and multiple fork plugs 205c (fork plugs 205c1 to 205c5) are connected to conductive plate 204b, for example. Fork plug 205e1 is connected to conductive plate 204d1, fork plug 205e2 is connected to conductive plate 204d2, fork plug 205e3 is connected to conductive plate 204d3, fork plug 205e4 is connected to conductive plate 204d4, and fork plug 205e5 is connected to conductive plate 204d5.

[0112] Large noise is generated by turning on and off the switch circuit 124 of the switch circuit board 201. As a countermeasure against this, although not shown in Fig. 13(c), a metal plate that functions as a shield is placed between the two switch circuit boards 201 and is earthed.

[0113] The heat generated by the switch circuit 124 is dissipated to the conductor plate 204. A heat sink (not shown) is attached to the switch circuit 124. The ground terminal of the switch circuit 124 is connected to the ground of the switch circuit board 201. The heat of the conductor plate 204 is also dissipated via the ground copper foil of the switch circuit board 201.

[0114] 1 and 4, conductive plates 204a and 204b are attached to switch circuit board 201b. Conductive plate 204a is connected to fork plug 205a. Fork plug 205a is connected to the output terminal of power supply device 132. Conductive plate 204b is connected to fork plug 205b. Fork plug 205b is connected to the ground terminal of power supply device 132.

[0115] When the switch circuit 124b is turned on (closed), the output terminals of the power supply device 132 are short-circuited, and a short-circuit current Im flows to ground. Therefore, the output current of the power supply device 132 is not supplied to the transistor 117. When the switch circuit 124b is open, the output current Id of the power supply device 132 is supplied to the transistor 117.

[0116] Conductive plates 204c and 204d are attached to switch circuit board 201a. Conductive plate 204c is connected to fork plug 205d. Fork plug 205d is connected to the output terminal of power supply device 132. Conductive plate 204d is connected to fork plug 205e. Fork plug 205e is connected to the collector terminal of transistor 117 to be tested.

[0117] 5 and 6, the switch circuit board 201b is disposed in the chamber B of the housing 210. The switch circuit board 201b is electrically connected to the transistor 117 to be tested by a fork plug 205 inserted from the chamber C2 through an opening 216 in the partition wall 214.

[0118] In the embodiment of FIG. 14, the conductor plate 204b is shared, and the fork plug 205b and the fork plugs 205c1 to 205c5 are electrically connected to the conductor plate 204b.

[0119] Fork plug 205e1 is electrically connected to conductive plate 204d1, fork plug 205e2 is electrically connected to conductive plate 204d2, fork plug 205e3 is electrically connected to conductive plate 204d3, fork plug 205e4 is electrically connected to conductive plate 204d4, etc. One fork plug 205e is electrically connected to one conductive plate 204d. Furthermore, a plurality of openings 216 are formed in one partition wall 214, and fork plugs 205 are inserted into the openings 216.

[0120] 14, the connection wiring 211 attached to the fork plug 205 becomes cumbersome. Also, the connection wiring 211 obstructs the insertion of the fork plug 205 into the opening 216, making it difficult to insert the fork plug 205 into the opening 216.

[0121] As shown in FIG. 15, the present invention separates the row positions of the fork plugs 205 that connect to a common conductor plate 204b from the row positions of the fork plugs 205 that connect to one or more conductor plates 204a.

[0122] Fig. 15 is a diagram for explaining the technical idea of ​​the present invention. In Fig. 15, as an example, a conductor plate 204b is arranged to connect three or more fork plugs 205b and 205d. A plurality of fork plugs 205b and a plurality of fork plugs 205d are attached to the conductor plate 204b.

[0123] Conductive plates 204a1 to 204a6 are arranged to connect fork plugs 205a and 205c, and fork plugs 205a and 205c are attached to the respective conductive plates 204a1 to 204a6.

[0124] The conductive plates 204a1 to 204a6 are arranged in a straight line. Furthermore, the conductive plates 204 are arranged so that the conductive plates 204b and 204a are substantially parallel to each other.

[0125] A terminal 226a of the transistor 117 is connected to the fork plug 205b via a connection wire 211b, and a terminal 226b of the transistor 117 is connected to the fork plug 205a via a connection wire 211a.

[0126] A first terminal of the switch circuit board 201 is connected to the fork plug 205d via a connection wire 211d, and a second terminal of the switch circuit board 201 is connected to the fork plug 205c via a connection wire 211c.

[0127] Fork plug 205a and fork plug 205c are electrically connected in common by conductor plate 204a, and fork plug 205b and fork plug 205d are electrically connected in common by conductor plate 204b.

[0128] The fork plugs 205 are inserted into the openings 216 arranged in a straight line. Therefore, the fork plugs 205 are arranged in a straight line, so that the connection wires 211 are arranged in parallel. The semiconductor elements 117 to be tested are also arranged in a straight line on the heating / cooling plate 134.

[0129] 16(a), an opening 216b is formed in the fork plug insertion plate 241a, and an opening 216b is formed in the fork plug insertion plate 241b. The opening 216b in the fork plug insertion plate 241a is arranged along the conductor plate 204b. The opening 216b in the fork plug insertion plate 241a is arranged along the conductor plate 204a.

[0130] The connection wiring 211a, the connection wiring 211b, the connection wiring 211c, and the connection wiring 211d are connected to the respective fork plugs 205, and the connection wirings 211 are arranged so as to be approximately parallel to each other.

[0131] By arranging the connection wiring 211 in a substantially parallel position, there is no crossing with the connection wiring 211 as shown in FIG. 14, and the fork plug 205 can be easily inserted into the opening 216 .

[0132] Therefore, it becomes easy to switch which of the transistors 117a to 117e is to be tested by inserting or not inserting the fork plug 205 into the opening 216.

[0133] As shown in FIG. 16(b), the fork plug insertion plate 241a and the fork plug insertion plate 241b are configured or formed so as to have a step of height H in the vertical direction.

[0134] Openings 216b are formed in the fork plug insertion plates 241a and 241b. An opening 216a is formed in the partition wall 214. The fork plug 205 is inserted into the openings 216a and 216b, and is supported by the openings 216a and 216b and the conductive plate 204. Therefore, the fork plug 205 is firmly supported.

[0135] 16, connection wiring 211b and connection wiring 211d are arranged in a lower position, and connection wiring 211a and connection wiring 211c are arranged in an upper position. Therefore, the wiring position space of connection wiring 211b and connection wiring 211d and connection wiring 211a and connection wiring 211c are different in the vertical direction, and no intersection of connection wirings 211 occurs. This makes it easy to attach and detach, insert, press-fit, etc. for fork plug 205 to be inserted into opening 216. It goes without saying that the matters explained above with reference to FIGS. 15, 16, etc. can be applied to other embodiments of the present invention, and can be combined with other embodiments.

[0136] 6 shows one transistor 117 for ease of illustration. A connection structure 218a is inserted into the opening 216a of the partition wall 217, and a connection structure 218b is inserted into the opening 216b of the partition wall 217.

[0137] 2(b), an opening 216 is formed in the partition wall 217. A connection structure 218a1 is inserted into the opening 216a1, and a connection structure 218b1 is inserted into the opening 216b1. A connection structure 218a2 is inserted into the opening 216a2, and a connection structure 218b2 is inserted into the opening 216b2. A connection structure 218an is inserted into the opening 216an, and a connection structure 218bn is inserted into the opening 216bn.

[0138] The connection structure 218a is connected to an element terminal 226a of the transistor 117, and the connection structure 218b is connected to an element terminal 226b of the transistor 117. A circulating water pipe 135 is incorporated into the heating / cooling plate .

[0139] A connector 202 is connected to a terminal of the transistor 117, and a signal wiring 222 connected to the connector 202 is connected to a sample connection circuit 203. A signal wiring 235 of the sample connection circuit 203 is connected to a device control circuit board 209 via a connector 208.

[0140] As shown in FIG. 6, the fork plug 205 and the conductor plate 204 are brought into contact with each other and electrically connected by inserting the fork plug 205 through an opening 216 in the partition wall 214 .

[0141] The partitions (partitions 214, 215, and 217) have the function of separating the chambers (chamber C1, chamber C2, chamber A, and chamber B) and the function of preventing outside air from flowing in. In particular, dry air is flowed into chamber C1 because condensation may occur in chamber C1 during testing at low temperatures. The dry air that has flowed into chamber C1 is discharged through opening 216 to other chambers or to the outside of housing 210.

[0142] A fixing screw 221 is attached to the other end of the connection structure 218, and the connection wiring 211 is connected to the connection structure 218. A fork plug 205 is attached to the other end of the connection wiring 211 as a connection member. Fixing screw 221 is not limited to a screw, and may be any type that can electrically connect connection wiring 211 to connection structure 218.

[0143] The sample connection circuit 203 is connected to a device control circuit board 209 by connection pins 206 of a connector 208. The sample connection circuits 203 are individually arranged corresponding to the respective transistors 117 to be tested, and the sample connection circuits 203 are configured to be easily removable.

[0144] 7A and 7B are explanatory diagrams of a connection structure 218 which is one embodiment of a semiconductor device testing apparatus according to the present invention. Fig. 7A is a diagram showing a schematic back surface, and Fig. 7B is a diagram showing a schematic side surface.

[0145] The heat pipe 223 is in close contact with the recess 234 on the surface of the connection structure 218. Heat conductive grease or heat dissipating silicone oil compound may be applied between the surface of the connection structure 218 and the heat pipe.

[0146] The heat pipe 223 is arranged so as to fit into the recess 234. By arranging the heat pipe 223 in the recess on the back surface, the risk of the heat pipe 223 being damaged is reduced. The heat pipe fitting 231 of the connection structure 218 is made of a material having a linear expansion coefficient smaller than that of the heat pipe 223 .

[0147] The connection structure 218 is heated during testing, and therefore the heat pipe 223 and the heat pipe fitting 231 are also heated, causing the heat pipe 223 and the heat pipe fitting 231 to expand due to the heating.

[0148] In the present invention, a material having a linear expansion coefficient smaller than that of the heat pipe 223 is used for the heat pipe fitting 231 of the connection structure 218. Alternatively, a material having a linear expansion coefficient larger than that of the heat pipe fitting 231 is used for the heat pipe 223 of the connection structure 218. The material of the heat pipe 223 expands more in the recess 234, so that the heat pipe 223 is more firmly fitted into the recess 234. Therefore, the heat pipe 223 will not come off.

[0149] Examples of materials for the heat pipe fitting 231 include copper (linear expansion coefficient 16.8), brass (linear expansion coefficient 19), iron (linear expansion coefficient 12.1), and stainless steel (SUS304) (linear expansion coefficient 17.3). Examples of materials for the heat pipe 223 include materials with a linear expansion coefficient greater than that of the heat pipe fitting 231, such as aluminum (linear expansion coefficient 23), tin (linear expansion coefficient 26.9), and lead (linear expansion coefficient 29.1). Among these, it is preferable to use copper (linear expansion coefficient 16.8) for the material of the heat pipe fitting 231 and aluminum (linear expansion coefficient 23) for the material of the heat pipe 223. The heat pipe fitting 231 can also be made of materials other than metal, such as carbon. The heat pipe 223 is a sealed container in which a small amount of liquid (working liquid) is vacuum sealed, and has a capillary structure (wick) on the inner wall. As the working fluid, in addition to pure water, methanol (methyl alcohol), acetone, sodium, mercury, a fluorocarbon-based refrigerant, or ammonia may be used. Wick materials include aluminum, copper, stainless steel, sintered alloy, wire mesh, foam metal, and ceramic.

[0150] The connection structure 218 mainly comprises a heat pipe fitting 231, a connection pressure part 232, and a connection holding part 233. Between the connection pressure part 232 and the connection holding part 233, an element terminal 226 of the semiconductor element is inserted.

[0151] 9 is an explanatory diagram illustrating the connection state between the transistor 117 and the connection structure 218. The transistor 117 is fixed in close contact with the heating / cooling plate 134a. The fixing is performed by pressing with a spring (not shown). If necessary, a heating / cooling plate is also placed above the transistor 117 so that the transistor 117 can be set to a predetermined temperature condition.

[0152] A connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is drawn out to the connector 202. A control signal Vg to be applied to the gate terminal g of the transistor 117 and a constant current Ic from a constant current circuit 118 are applied to the signal wiring 222.

[0153] The transistors 117 to be tested must be fixed in close contact with the heating and cooling plate 134, and are therefore difficult to remove. The transistor 117 mounting process begins with fixing a plurality of transistors 117 to be tested to the heating and cooling plate 134. Next, the transistor 117 to be tested is selected, and a connecting structure 218 is inserted through the opening 216 in the partition wall 217 and attached to the element terminals 226 of the semiconductor element 117.

[0154] That is, the selected transistor 117 is electrically connected to the element terminal 226 by inserting the connection structure 218 from the C2 chamber side into the opening 216 where the selected transistor 117 is located.

[0155] Electrical connection with the transistor 117 is easy because it is only necessary to select the position where the connection structure 218 is inserted. In addition, by changing the signal applied to the connection wiring 211 connected to the connection structure 218, the test conditions and test contents of the transistor 117 can be easily changed.

[0156] Element terminal 226 is clamped by applying pressure between contact portions 225a and 225b. Connection wiring 211 is connected to one end of connection structure 218, and constant current Id is applied from connection wiring 211 to transistor 117. Heat pipe 223 is arranged on the back side of connection structure 218.

[0157] A current of several hundred amperes (A) flows through element terminal 226. Even if there is a slight resistance at contact point 225, a current of several hundred amperes (A) generates a large amount of heat, overheating element terminal 226. When element terminal 226 overheats, transistor 117 overheats, causing it to deteriorate or break down.

[0158] In the present invention, heat generated at element terminal 226 is transferred to connection wiring 211 of connection structure 218 by heat pipe 223. Therefore, contact point 225 does not overheat. Cooling fan 227 is disposed below connection structure 218 to dissipate heat from heat pipe 223.

[0159] As shown in Fig. 8(a), heat dissipation fins 228 may be formed or arranged so as to be in close contact with the heat pipe 223. As shown in Fig. 8(b), a circulating water pipe 135 may be formed or arranged within the connection structure 218 to cool the connection structure 218.

[0160] 9, the transistor 117 (semiconductor element 117) has two element terminals 226, that is, element terminal 226a (P) and element terminal 226b (N). As shown in Fig. 10, the technical idea of ​​the present invention can be applied even if the element terminal 226 of the transistor 117 has three terminals, that is, element terminal 226a (P), element terminal 226b (N), and element terminal 226c.

[0161] FIG. 10 is an explanatory diagram illustrating the connection state between a semiconductor module 117 having three element terminals 226 (element terminal 226a(P), element terminal 226b(N), element terminal 226c(O)) such as those shown in FIGS. 3(b), (c), (d), and (e) and a connection structure 218.

[0162] 10, a heat pipe 223a is formed or arranged in connection structure 218a, and a heat pipe 223b is formed or arranged in connection structure 218b, whereas a heat pipe 223 is not formed or arranged in connection structure 218c. Connection structure 218c is connected to element terminal 226c. No large current flows through element terminal 226c(O) of transistor 117. There is no need to form a heat pipe 223 in connection structure 218c.

[0163] By forming connection structure 218c thinner than the other connection structures 218 (connection structure 218a, connection structure 218b), it becomes easier to connect connection structure 218 and element terminal 226 of transistor 117. Furthermore, since the space for arranging transistor 117 can be narrow, the number of transistors 117 that can be mounted on heating / cooling plate 134 can be increased.

[0164] 11(a), the connection structure 218 in this embodiment of the present invention mainly comprises a heat pipe fitting 231, a connection receiving portion 225, a connection pressure portion 232, and a connection holding portion 233. An element terminal 226 of a semiconductor element is inserted between the connection receiving portion 225 and the connection holding portion 233.

[0165] A spring 236 is inserted or placed in a spring hole 239 of the connection receiving portion 225 and the connection pressure portion 232. A positioning screw 237 is inserted or placed in a positioning screw hole 240 in the center of the connection receiving portion 225, and the connection receiving portion 225 and the connection pressure portion 232 are positioned relative to each other.

[0166] The spring 236 is a pressing means, a sliding means, or a positioning means. One example of the spring 236 is a coil spring. Other examples include a leaf spring, a spiral spring, a tone spring, and a disc spring. The spring 236 is preferably made of or configured from a metal material with good electrical conductivity, but may also be made of heat-resistant rubber, plastic, or ceramic material.

[0167] A coil spring 236 is disposed between the connection receiving portion 225 and the connection pressure portion 232. The connection pressure portion 232 is connected by one or more fixing screws 224b. By tightening or attaching the fixing screws 224b, pressure (pressure) is applied between the connection receiving portion 225 and the connection holding portion 233.

[0168] The element terminal 226 is sandwiched between the connection receiving portion 225 and the connection holding portion 233, and the pressure of the spring 236 causes the element terminal 226 to be sandwiched between the connection receiving portion 225 and the connection holding portion 233 with a predetermined pressure (predetermined pressing force).

[0169] The pressure (pressure) can be easily adjusted by changing the spring 236. The pressure (pressure) can also be adjusted or set by the degree of tightening of the fixing screw 224b. The heat pipe metal fitting 231 and the connection holder 233 are fixed with one or more fixing screws 224a.

[0170] The connection receiving portion 225 is disposed between the connection pressure portion 232 and the connection holding portion 233. The constituent material or at least the surface material of the connection receiving portion 225 is platinum, gold, silver, tungsten, copper, nickel, or an alloy of a combination thereof.

[0171] Similarly, the surface of the connection holder 233 that comes into contact with the element terminal 226 is made of platinum, gold, silver, tungsten, copper, nickel, or an alloy of any of these.

[0172] The connection holding portion 233 is fixed to the heat pipe fitting 231 with a fixing screw 224a. The connection pressure portion 232 is fixed to the connection holding portion 233 with a fixing screw 224b. The element terminals 226 of the semiconductor element are fixed by tightening or positioning the fixing screw 224b. The connection wiring 211 is fixed to the left end of the heat pipe fitting 231 with a fixing screw 221. 11(a) and 11(d) are explanatory diagrams for explaining the combined state of the connection holding portion 233, the connection receiving portion 225, and the connection pressure portion 232. FIG.

[0173] The connection holder 233 connects and fixes the heat pipe 223 and the heat pipe fitting 231 with screws 224a (not shown) inserted into the screw holes 238a1 and 238a2. The heat pipe 223 and the heat pipe fitting 231 are connected and fixed in close contact so as to ensure good thermal conductivity and electrical conductivity. The connection holding portion 233 is connected and fixed to the connection pressure portion 232 by screws 224b (not shown) inserted into the screw holes 238b1 and 238b2.

[0174] The connection receiving portion 225 has protrusions 251 formed on both ends, and the connection pressure portion 232 has grooves 252 formed on both ends. The protrusions 251 of the connection receiving portion 225 are fitted into the grooves 252 of the connection pressure portion 232. The protrusions 251 of the connection receiving portion 225 and the grooves 252 of the connection pressure portion 232 are configured to be in electrical contact with each other.

[0175] In order to improve the contact between the element terminals 226 and the connection receiving portions 225, it is preferable to form triangular or other irregularities on the surface of the connection receiving portions 225 as shown in FIG. 11(c). In the configuration of FIG. 11, the element terminal 226 is sandwiched between the flat surface of the connection pressure portion 232 and the flat surface of the connection holding portion 233 .

[0176] 12 shows a configuration in which the element terminal 226 is sandwiched between a pressing tool mounting plate 313 and a connection holder 233. Pressing tools 311a and 311b are attached to the pressing tool mounting plate 313. The pressing tool 311 is exemplified by a metal leaf spring. The pressing tool 311 may also be made of a non-conductive material such as a silicone resin material. The pressing tool 311 is fitted into the pressing tool mounting plate 313.

[0177] The element terminal 226 is clamped between the flat surfaces of the pressing tool 311 and the connection holder 233. When the pressing tool 311 presses, the element terminal 226 and the connection holder 233 are electrically connected.

[0178] 11(a), the spring (pressure fitting) 236 was inserted into the spring hole 239 of the contact part 225. If the spring (pressure fitting) 236, the contact part 225, and the connection pressure part 232 are made of conductive materials, electricity may flow from the element terminal 226 → contact part 225 → spring (pressure fitting) 236 → connection pressure part 232. In this case, if the resistance value of the spring (pressure fitting) 236 is high, current will flow through the spring (pressure fitting) 236, causing the spring to generate heat and burn out.

[0179] In the embodiment of the present invention shown in Figure 12, spring hole 312 is formed in insulating plate 312. Pressing tool 311 contacts element terminal 226, and spring 236 presses pressing tool mounting plate 313. Insulating plate 312 is disposed above pressing tool mounting plate 313, providing insulation between pressing tool mounting plate 313 and spring 236. Spring hole 239 is formed in insulating plate 312, and spring 236 is inserted into spring hole 239. The other configuration is the same as in Figure 11, so description will be omitted. The insulating plate 312 may be an insulating film, an insulating film, or an insulating gas such as air.

[0180] Fig. 12(b) is a side view of the pressing tool attachment plate 313. Pressing tools 311a and 311b are arranged and inserted into the pressing tool attachment plate 313. Fig. 12(c) is a view seen from direction A in Fig. 12(b).

[0181] Since the insulating plate 312 is made of an insulating material, even if the pressing tool mounting plate 313 is made of a conductive material such as metal, no current flows through the spring (pressure fitting) 236. Therefore, no current path is generated from the element terminal 226 to the contact portion 225 to the spring (pressure fitting) 236 to the connecting pressure portion 232.

[0182] The embodiment of Fig. 12(a) has a configuration in which insulation is achieved by an insulating plate 312. The insulating effect of the present invention is not limited to the configuration in which an insulating plate 312 is used, as in Fig. 12(a). For example, a configuration shown in Fig. 12(d) is exemplified.

[0183] 12(d) shows a configuration in which an insulating portion 315 made of a resin material or the like is arranged around the screw hole 238b of the connection pressure portion 232. Because the area around the screw hole 238b is insulated by the insulating portion 315, no current flows through the fixing screw 224b. Therefore, no current path is generated from the element terminal 226 to the contact portion 225 to the spring (pressure fitting) 236 to the connection pressure portion 232, and the spring (pressure fitting) 236 will not be burned. As described above, the present invention is configured such that insulating plate 312 is disposed on the side of spring 236 that applies pressure, so that current does not flow to pressing tool mounting plate 313 and contact portion 225 side.

[0184] When a current flows, it flows through pressing parts such as spring 236 and fixing screw 224b, causing the spring 236 and fixing screw 224b to burn out. Current is supplied to element terminal 226 via connection holding part 233, which has fewer electrically high resistance parts such as spring 236.

[0185] 17 is an equivalent circuit diagram and an explanatory diagram of the semiconductor element testing apparatus in the first embodiment of the present invention. The semiconductor module to be tested is shown in FIG. 3(d) by way of example, but is not limited to this.

[0186] 17, when the switch circuit 124b is turned on, the output of the power supply device 132 is short-circuited, and the current Id output by the power supply device 132 flows to the ground as a current Im'. Alternatively, when the switch circuit 124b is turned on, the charge stored between the terminals of the power supply device 132 is discharged.

[0187] When the switch circuits 124c and 124d are turned on at the same time, the current Im flows, the output of the power supply device 132 is short-circuited, and the charge of the power supply device 132 is discharged. In this configuration or method, the switch circuit 124b is not necessary.

[0188] It is also effective to stagger the timing at which switch circuit 124c and switch circuit 124d turn on. For example, when switch circuit 124c turns on before switch circuit 124d, the channel of transistor 117s is short-circuited. Next, when switch circuit 124d turns on, the channel of transistor 117m is short-circuited. Alternatively, when switch circuit 124d turns on before switch circuit 124c, the channel of transistor 117m is short-circuited. Next, when switch circuit 124c turns on, the channel of transistor 117s is short-circuited. As described above, by sequentially turning on the switch circuits 124, the occurrence of surge voltages and the like in the semiconductor element 117 can be further suppressed. When the switch circuit 124 a is turned on, the current Id output by the power supply device 132 is supplied to the transistor 117 . The fork plug 205 is inserted through the opening 216 in the partition wall 214 and is electrically connected to the switch circuit board 201 .

[0189] 20 and 21 are explanatory diagrams of the circuit section of the semiconductor device testing apparatus of the present invention and explanatory diagrams of the circuit operation. As shown in Fig. 20 and Fig. 21, the semiconductor device testing apparatus of the present invention has an isolated DC-DC converter circuit 138m and an isolated DC-DC converter circuit 138s.

[0190] Fig. 20 shows examples of semiconductor modules to be tested, such as those shown in Fig. 3(d) and Fig. 3(e). Fig. 21 shows examples of semiconductor modules to be tested, such as those shown in Fig. 3(c). It goes without saying that the electrical element testing apparatus and electrical element testing method of the present invention can be applied to modules other than those shown in Fig. 3.

[0191] The isolated DC-DC converter circuit 138m generates two voltages (Vpm1 voltage based on Vmm1 potential, and Vpm2 voltage based on Vmm2 potential) from the input voltage (circuit voltage Vc voltage). GND, Vmm1 voltage, and Vmm2 voltage are isolated from each other. GND, Vpm1 voltage, and Vpm2 voltage are also isolated from each other.

[0192] The isolated DC-DC converter circuit 138s generates two voltages (Vps1 voltage based on Vms1 potential and Vps2 voltage based on Vms2 potential) from the input voltage (Vc voltage). GND, Vms1 voltage, and Vms2 voltage are isolated from each other. GND, Vps1 voltage, and Vps2 voltage are also isolated from each other.

[0193] The Vmm1 voltage, Vmm2 voltage, Vms1 voltage, and Vms2 voltage can be set as reference voltages and can also be considered as ground voltages. However, this ground voltage is isolated from each voltage. The Vmm1 voltage and Vmm2 voltage can be set to a common potential without being isolated from the time the voltages are generated. The Vms1 voltage and Vms2 voltage can be set to a common potential without being isolated from the time the voltages are generated.

[0194] Although not shown as an isolated DC-DC converter circuit, an isolated DC-DC converter circuit that generates the Vt1 voltage and Vt2 voltage can be installed as needed. The Vt1 voltage and Vt2 voltage are isolated from the Vc voltage. The Vt1 voltage is a negative potential with the Vmm1 voltage as the reference. The Vt2 voltage is a negative potential with the Vms1 voltage as the reference.

[0195] The Vt1 voltage may be generated with the Vmm1 voltage or the Vmm2 voltage as a reference, and the Vt2 voltage may be generated with the Vms1 voltage or the Vms2 voltage as a reference.

[0196] The voltage selection circuit 302 is configured so that the Vt1 voltage and the Vmm1 voltage can be selected and applied to the gate terminal gm of the transistor 117m. The voltage selection circuit 302 is configured so that the Vt2 voltage and the Vms1 voltage can be selected and applied to the gate terminal gs of the transistor 117s (Qs). The voltage selection circuit 302 uses an analog switch or the like.

[0197] The potential difference between the Vmm1 voltage and the Vpm1 voltage of the isolated DC-DC converter circuit 138m is set to be the on-voltage Vg applied to the gate terminal gm of the transistor 117m (Qm). The isolated DC-DC converter circuit 138m is arranged so that the on-voltage Vg is variable.

[0198] The potential difference between the Vms1 voltage and the Vps1 voltage of the isolated DC-DC converter circuit 138s is set to be the on-voltage Vg applied to the gate terminal gs of the transistor 117s (Qs). The isolated DC-DC converter circuit 138s is arranged so that the on-voltage Vg is variable.

[0199] 20 and 21, the A, B, and C blocks of the isolated DC-DC converter circuit 138m are insulated. The A, D, and E blocks of the isolated DC-DC converter circuit 138s are also insulated.

[0200] Power is transferred between blocks A and B, between blocks A and C, between blocks A and D, and between blocks A and E using coils, etc. Control signals between each block are sent and received using phototransistors, etc., with isolation provided.

[0201] The circuit ground (GND), Vc voltage, Vpm1 voltage, Vmm1 voltage, Vpm2 voltage, and Vmm2 voltage are in an isolated state, meaning that each voltage is floating relative to the other voltages. Note that "floating" means floating relative to other voltages or potentials.

[0202] Surge voltages and transient currents can apply large noise to the gate terminals of transistors, causing them to break down. In the present invention, the signal potentials applied to the gate terminals are generated in a floating state, making it less susceptible to noise and allowing for good testing of semiconductor elements 117.

[0203] It is assumed that the voltage generated in the isolated DC-DC converter circuit 138 is floating. The potential difference between the Vmm1 voltage and the Vpm1 voltage is Vm1, and the potential difference between the Vmm2 voltage and the Vpm2 voltage is Vm2.

[0204] For example, if the Vmm1 voltage is connected to the circuit ground (GND) and the Vpm1 voltage is shorted to the Vmm2 voltage, the Vpm2 voltage will be the sum of the Vm1 voltage and the Vm2 voltage relative to the circuit ground (GND). In other words, the floating potential is determined by setting the potential with another voltage. The potential level can be changed, moved, or set to correspond to the potential of another voltage.

[0205] The semiconductor device testing device of the present invention is configured such that the circuit ground (GND) is isolated from other power supply voltages. Furthermore, it is configured so that each isolated power supply voltage can be wired or connected. For example, the Vmm1 voltage and the Vmm2 voltage can be wired to have the same potential. The Vms1 voltage and the Vms2 voltage can be wired to have the same potential.

[0206] As shown in FIG. 17, the sample connection circuit 203m1 includes a gate driver circuit 113m that generates a gate signal waveform to be applied to the gate terminal gm of the transistor 117m (Qm), a variable resistance circuit 125m that adjusts or sets the rising and falling waveforms of the gate signal, a short circuit 137m, a voltage selection circuit 302m, and the like.

[0207] The sample connection circuit 203m2 has a constant current setting circuit 130m that generates a constant current Icm to be applied to the diode Dm of the transistor 117m, and a voltage detection circuit 129m that measures or detects the terminal voltage of the diode Dm.

[0208] The sample connection circuit 203s1 includes a gate driver circuit 113s that generates a gate signal waveform to be applied to the gate terminal gs of the transistor 117s, a variable resistance circuit 125s that adjusts or sets the rising and falling waveforms of the gate signal, a short circuit 137s, a voltage selection circuit 302s, and the like.

[0209] The sample connection circuit 203s2 includes a constant current setting circuit 130s that generates a constant current Ics to be applied to the diode Ds of the transistor 117s, and a voltage detection circuit 129s that measures or detects the terminal voltage of the diode Ds. Unless otherwise specified, the following description will be given assuming that the N electrode terminal of the semiconductor element 117 is at the reference potential (AGND, 0 (V)).

[0210] When the N electrode terminal of the semiconductor element 117 is set to a reference potential, the potential of the emitter terminal es of the transistor 117s is equal to the channel voltage Vcem of the transistor 117m, that is, the potential of the O electrode terminal of the semiconductor element 117.

[0211] The potential of the P electrode terminal of semiconductor element 117 is the sum of the channel-to-channel voltage Vcem of transistor 117m and the channel-to-channel voltage Vces of transistor 117s. The potentials of the O electrode terminal and the P electrode terminal fluctuate depending on the magnitude of the current Id flowing through transistor 117m and transistor 117s and the on / off states of transistors 117m and 117s. In particular, the potential fluctuation of the emitter terminal es of transistor 117s is large.

[0212] It is preferable that the potential Vms1 of the emitter terminal es of the transistor 117s be configured so as to be variable in accordance with fluctuations in the channel voltage Vcem of the transistor 117m.

[0213] In the present invention, Vmm1, which is the potential of the emitter terminal em of the transistor 117m, is floating with respect to Vms1, which is the potential of the emitter terminal es of the transistor 117s. Therefore, when the channel voltage Vcem of the transistor 117m fluctuates, the Vces voltage also fluctuates in the same direction and at the same potential.

[0214] If the diode Dm of the transistor 117m uses the same semiconductor layer as the transistor 117m or a similar semiconductor layer, the potential of the cathode terminal km of the diode Dm may be the potential of the emitter terminal em of the transistor 117m or a potential close to it. Therefore, it is preferable that the power supply potential of the diode Dm be based on the potential of the emitter terminal em of the transistor 117m.

[0215] If the diode Ds of the transistor 117s uses the same semiconductor layer as the transistor 117s or a similar semiconductor layer, the potential of the cathode terminal ks of the diode Ds may become the potential of the emitter terminal es of the transistor 117s or a potential close to it. Therefore, it is preferable that the power supply potential of the diode Ds be based on the potential of the emitter terminal es of the transistor 117s.

[0216] In the present invention, the Vc voltage, Vms1 voltage / Vps1 voltage, and Vms2 voltage / Vps2 voltage of the isolated DC-DC converter circuit 138s are insulated. The Vc voltage, Vmm1 voltage / Vpm1 voltage, and Vmm2 voltage / Vpm2 voltage of the isolated DC-DC converter circuit 138m are insulated. Each voltage can be connected or wired to any voltage.

[0217] 22 is an explanatory diagram illustrating the wiring of the power supply system of the semiconductor device testing apparatus of the present invention. The N electrode terminal of transistor 117 is connected to AGND. AGND is, for example, the earth potential.

[0218] 22, 23, 24, and 25, the present invention allows the wiring connections to be changed as desired. Also, the switch circuit 123 and selector 127 allow the connection wiring and applied voltage to be changed.

[0219] The emitter terminal em of the transistor 117m is electrically connected to the N electrode terminal, and the emitter terminal em is also connected to the Vmm1 terminal. The emitter terminal em is also connected to the Vmm2 terminal. The emitter terminal es of the transistor 117s is also connected to the Vms1 terminal. The emitter terminal es is also connected to the Vms2 terminal.

[0220] The potential of the emitter terminal es of the transistor 117s is the sum of the potential of the N electrode terminal and the channel voltage Vcem of the transistor 117m. Therefore, the potential of the emitter terminal es of the transistor 117s changes depending on the on / off state of the transistor 117m and the magnitude of the constant current Id.

[0221] The gate signal Vsg applied to the gate terminal gm of the transistor 117m is based on the potential of the emitter terminal em. If the voltage that turns on the transistor 117m is Vg, when the Vg voltage is applied from the AGND potential of the N electrode terminal, the transistor 117m turns on.

[0222] 19 is a timing chart showing the operation of the circuit unit of the semiconductor testing device of the present invention. As shown in Figures 19(b), (c), and (i), the period when the constant current Id does not flow is tcs, which is the period before the constant current Id flows through the transistor 117, and tcm, which is the period after the constant current Id flows, and the period when the constant current Id flows is tcc. During at least one of the periods tcs, tcm, and tcc, the switch Si is turned on, and the voltage Ve across both terminals of the variable resistance circuit 125 is measured.

[0223] 19(d) is a timing signal for causing a current Ic to flow through the diode D (diode Ds, diode Dm), and when St2 is at H level, a current flows through the diode D of the transistor 117. A voltage detection circuit 129 acquires the voltage between the terminals of the diode D, and a temperature measurement circuit (not shown) converts the voltage between the terminals into temperature information Tj.

[0224] The temperature information Tj is sent to the control circuit board 111 (controller 111), and the control circuit board 111 (controller 111) tests the transistor 117 (semiconductor element component 117) in accordance with the temperature information Tj.

[0225] The current Id is a current that flows through the transistor 117 to be tested, and is a current that is output by the current power supply device 121. St1 and St2 are the time for which the measurement current flows through the temperature measurement diode or the time for which the temperature is measured.

[0226] In FIG. 19(g), Vce indicates the channel voltage of the transistor 117 (transistor 117m, transistor 117s), and temperature information Tj indicates the measured temperature change of the transistor 117 (transistor 117m, transistor 117s).

[0227] In Figure 19(a), the 0 (V) potential is the voltage that turns off transistor 117m. In Figure 19(a) and other figures, the Vt1 voltage is illustrated as the Vt voltage. The Vt1 voltage is a voltage that is more negative than the 0 (V) potential. The negative Vt1 voltage is applied with the Vmm1 voltage as a reference.

[0228] The current Icm flowing through diode Dm is generated using the Vmm2 and Vpm2 voltages as power sources. Because the Vmm2 voltage is common to the Vmm1 voltage, the voltage at the terminals of diode Dm is in the range of Vmm1 and Vpm2, and is a voltage referenced to AGND.

[0229] The gate signal Vsg applied to the gate terminal gs of the transistor 117s is based on the potential of the emitter terminal es, which is the sum of the AGND potential of the N electrode terminal and the inter-channel voltage Vcem of the transistor 117m.

[0230] As shown in Figure 19(a), if the voltage that turns on transistor 117s is Vg, the voltage at which transistor 117s turns on is based on the voltage obtained by adding the inter-channel voltage Vcem of transistor 117m to the AGND potential of the N electrode terminal, and when the Vg voltage is applied, transistor 117s turns on.

[0231] The Vms1 voltage is isolated from the Vmm1 voltage and is in a floating state. Therefore, even if the channel-to-channel voltage Vcem of transistor 117m fluctuates, the potential at the emitter terminal es of transistor 117s fluctuates in response to the fluctuation in the channel-to-channel voltage Vcem of transistor 117m. The Vms1 voltage generates the Vps1 voltage based on the potential at the emitter terminal es.

[0232] The gate signal Vsg applied to the gate terminal gs of the transistor 117s is based on the potential of the emitter terminal es. As shown in Figure 19(a), if the voltage that turns on the transistor 117s is Vg, when the voltage Vg is applied from the potential of the emitter terminal es, the transistor 117s turns on.

[0233] 19(a) and the like, the Vt2 voltage is illustrated as the Vt voltage. The Vt2 voltage is a voltage with a more negative polarity than the 0 (V) potential. The negative Vt2 voltage is applied with the Vms1 voltage as a reference.

[0234] The current Ics flowing through the diode Ds is generated using the Vms2 and Vps2 voltages as power sources. Since the Vms2 voltage is common to the Vms1 voltage, the voltage at the terminals of the diode Ds is in the range between Vms1 and Vps2.

[0235] The Vms1 voltage is isolated from the Vmm1 voltage and is in a floating state. The Vms1 voltage is also connected to the collector terminal cm of the transistor 117m. Even if the channel-to-channel voltage Vcem of the transistor 117m fluctuates, the voltage (Vg) that turns on the transistor 117s and the voltage (0 (V)) that turns it off do not fluctuate. This allows for good on / off control of the transistor 117s.

[0236] 23 is an explanatory diagram illustrating the wiring of the power supply system of the semiconductor device testing apparatus of the present invention. In the wiring of Fig. 23, the N electrode terminal of transistor 117 is connected to AGND. AGND is, for example, earth potential.

[0237] The emitter terminal em of the transistor 117m is electrically connected to the N electrode terminal, and the emitter terminal em is also connected to the Vmm1 terminal. The emitter terminal es of the transistor 117s is connected to the Vms1 terminal. The Vmm2 terminal and the Vms2 terminal are insulated from the other power supply terminals and are in a floating state.

[0238] The current Icm flowing through the diode Dm is generated using the voltages Vmm2 and Vpm2 as power sources. The voltage at the terminals of the diode Dm is basically in the range of Vmm2 and Vpm2.

[0239] The current Ics flowing through the diode Ds is generated using the voltages Vms2 and Vps2 as power sources. The voltage at the terminals of the diode Ds is basically in the range of Vms2 and Vps2.

[0240] The potential of the Vmm2 terminal is held at a potential based on AGND, and the potential of the Vms2 terminal is held at a potential based on the potential of the emitter terminal es of the transistor 117s.

[0241] 24 is an explanatory diagram illustrating the wiring of the power supply system of the semiconductor device testing apparatus of the present invention. In the wiring of FIG. 24, the N electrode terminal of the transistor 117 is connected to AGND.

[0242] The emitter terminal em of the transistor 117m is electrically connected to the N electrode terminal, and the emitter terminal em is also connected to the Vmm1 terminal. The Vmm2 terminal is also connected to the Vms2 terminal. The emitter terminal es of the transistor 117s is connected to the Vms1 terminal. The Vmm1 terminal is not connected to the Vmm2 terminal.

[0243] The current Icm flowing through diode Dm generates voltages Vmm2 and Vpm2 using them as power sources. The voltage at the terminals of diode Dm is basically in the range of Vmm2 and Vpm2. The current Ics flowing through diode Ds generates voltages Vms2 and Vps2 using them as power sources. The voltage at the terminals of diode Ds is basically in the range of Vms2 and Vps2. Because the voltages Vmm2 and Vms2 are common, the potentials of diode Dm and diode Ds operate within a common potential.

[0244] 24, the switch circuit 123 is disposed in the power supply connection wiring. The switch circuit 123 can switch between connecting the Vms2 voltage and the Vpm2 voltage, or connecting the Vms2 voltage and the Vmm2 voltage.

[0245] In the present invention, a wide variety of tests can be handled by arranging or providing a switch circuit 123 as shown in Figure 24. Examples of the switch circuit 123 include an analog switch, a relay circuit, and a magnetic switch. The switch circuit 123 is not limited to the embodiment shown in Figure 24. For example, it may be configured to select the Vmm1 and Vpm1 voltages and connect to another potential (for example, connect to the Vmm1 voltage). As described above, the present invention is characterized by a configuration that allows the connection state of the potential generated by an isolated DC-DC converter circuit or the like to be changed.

[0246] 25 is an explanatory diagram illustrating the wiring of the power supply system of the semiconductor device testing apparatus of the present invention. In the wiring of FIG. 25, the N electrode terminal of the transistor 117 is connected to AGND.

[0247] The emitter terminal em of the transistor 117m is electrically connected to the N electrode terminal, and the emitter terminal em is connected to the Vmm1 terminal. The Vmm1 terminal is connected to the Vmm2 terminal, and the Vmm1 terminal is connected to the Vms1 terminal. The emitter terminal es of the transistor 117s is connected to the Vms1 terminal.

[0248] The Vmm2 terminal and Vms2 terminal are connected. The current Icm flowing through the diode Dm generates the Vmm2 voltage and Vpm2 voltage as power supplies. The voltage at the terminal of the diode Dm is basically in the range of Vmm2 and Vpm2.

[0249] The current Ics flowing through diode Ds is generated using the Vmm2 and Vps2 voltages as power sources. The voltage at the terminals of diode Ds is basically in the range of Vmm2 and Vps2. Because the Vmm2 and Vms2 voltages are common, the potential of diode Dm and the potential of diode Ds operate within a common potential. When the potential of the Vmm1 voltage changes, the potential of the Vpm1 voltage also shifts, and when the potential of the Vmm2 voltage changes, the potential of the Vpm2 voltage also shifts. When the potential of the Vms1 voltage changes, the potential of the Vps1 voltage also shifts accordingly. When the potential of the Vms2 voltage changes, the potential of the Vps2 voltage also shifts accordingly.

[0250] The voltages Vmm1 and Vms1 are floating, so when the channel voltage Vcem of the transistor 117m changes, Vms1 changes in conjunction with the change in Vcem.

[0251] The gate signal (ON / OFF signal) applied to the gate terminal gm of the transistor 117m is output based on the Vmm1 voltage, and the gate signal (ON / OFF signal) applied to the gate terminal gs of the transistor 117s is output based on the Vms1 voltage.

[0252] When the current Id flowing through the transistor 117m changes and the voltage applied to the gate terminal gm of the transistor 117m changes, even if the channel voltage Vcem of the transistor 117m changes, the Vms1 voltage changes in conjunction with the Vcem voltage because of following.

[0253] Even if the channel voltage Vce of the transistor 117m changes, the Vms1 voltage is floating and the gate signal of the transistor 117s is generated based on the Vms1 voltage, so the transistor 117s can be controlled to be on and off without any problems.

[0254] Diode Ds is floating relative to the Vmm1 voltage and the Vms1 voltage, so even if the Vmm1 voltage or the inter-channel voltage Vcem of transistor 117m changes, it will not be destroyed and the temperature or temperature range of transistor 117s can be measured normally.

[0255] 26 is an explanatory diagram of the semiconductor device testing apparatus and the semiconductor device part testing method or test state of the present invention. The semiconductor device 117 is tested by sequentially or randomly performing any of the states or methods shown in FIG. The Vt voltage applied during the tn2 and tn1 periods is set according to the semiconductor device 117 to be tested. Other signals are controlled as shown in FIG.

[0256] FIG. 26(a) is an explanatory diagram of a method (state) for short-circuiting the terminals (between the P electrode terminal and the N electrode terminal) of the transistor 117 to discharge the electric charge and prevent the surge voltage and transient current from flowing through the transistor 117.

[0257] An off-voltage is applied as a gate signal Vsgm to the gate terminal gm of the transistor 117m, turning the transistor 117m into an off state. An off-voltage is applied as a gate signal Vsgs to the gate terminal gs of the transistor 117s, turning the transistor 117s into an off state. The short circuit 137s and the short circuit 137m are turned off (open). The switch circuit 124c and the switch circuit 124d are turned on (closed).

[0258] FIG. 26(b) shows a state in which the short circuit 137s is turned on to put the transistor 117s into a diode-connected state, and the transistor 117m is turned on to pass a constant current Id through the semiconductor element 117, thereby testing the semiconductor element 117.

[0259] An on-voltage or off-voltage is applied periodically or intermittently to the gate terminal gm of the transistor 117m as a gate signal Vsgm, and the transistor 117m is controlled to be in an on-state or an off-state.

[0260] The short circuit 137s connected between the gate terminal gs and the emitter terminal es of the transistor 117s is turned on, and the transistor 117s is brought into a diode-connected state, and the switch circuits 124c and 124d are turned off (open).

[0261] A constant current Id flows between the P electrode terminal and the N electrode terminal of the semiconductor element 117. The transistor 117m is controlled to be turned on and off by a gate signal Vsgm applied to a gate terminal gm of the transistor 117m, and the semiconductor element 117 is tested.

[0262] FIG. 26(c) shows a state in which the transistor 117m is in a diode-connected state, the transistor 117s is turned on, a constant current Id is flowing through the semiconductor element 117, and the semiconductor element 117 is being tested.

[0263] An on-voltage or off-voltage is applied periodically or intermittently to the gate terminal gs of the transistor 117s as a gate signal Vsgs, and the transistor 117s is controlled to be in an on state or an off state.

[0264] A short circuit 137m connected between the gate terminal gm and the emitter terminal em of the transistor 117m is turned on, and the transistor 117m is diode-connected. The switch circuits 124c and 124d are turned off (open). A constant current Id flows between the P electrode terminal and the N electrode terminal of the semiconductor element 117. The transistor 117s is controlled to be turned on and off by a gate signal Vsgs applied to the gate terminal gs of the transistor 117s, and the semiconductor element 117 is tested.

[0265] 26(d), the transistor 117s is turned on and the transistor 117m is turned off. A gate signal Vsgs, which is a turn-on voltage or turn-off voltage, is applied periodically or intermittently to the gate terminal gs of the transistor 117s. The transistor 117m is controlled to be in an off state.

[0266] The short circuit 137 connected between the gate terminal g and the emitter terminal e of the transistor 117m and the transistor 117s is turned off (open), the switch circuit 124c is turned off, and the switch circuit 124d is turned on (closed).

[0267] A current Id flows from the P electrode terminal to the channel of the transistor 117s in the semiconductor element 117, and the current Id flows through the switch circuit 124d. The transistor 117s is turned on and off by a gate signal Vsgs applied to the gate terminal gs of the transistor 117s, thereby testing the semiconductor element 117.

[0268] 26(e), the transistor 117m is turned on and the transistor 117s is turned off. A gate signal Vsgm, which is a turn-on voltage or turn-off voltage, is applied periodically or intermittently to the gate terminal gm of the transistor 117m. The transistor 117s is controlled to be in an off state.

[0269] The short circuit 137 connected between the gate terminals g and emitter terminals e of the transistors 117m and 117s is turned off (open), and the switch circuit 124d is turned off (open), and the switch circuit 124d is turned on (closed).

[0270] A current Id flows from the P electrode terminal of the semiconductor element 117 to the switch circuit 124c, and the current Id flows between the channels of the transistors 117m. The transistors 117m are turned on and off by a gate signal Vsgm applied to the gate terminal gm of the transistors 117m, and the semiconductor element 117 is tested.

[0271] FIG. 26(f) shows a state in which gate signals are applied to the gate terminals g (gate terminals gm and gs) of the transistors 117m and 117s, and a constant current Id is passed through the semiconductor element 117 to test the semiconductor element 117.

[0272] An on-voltage or off-voltage is applied periodically or intermittently to the gate terminal gs of the transistor 117s and the gate terminal gm of the transistor 117m, so that the transistors 117s and 117m are controlled to be in an on state or an off state.

[0273] The short circuit 137 connected between the gate terminal g and the emitter terminal e of the transistor 117m and the transistor 117s is turned off. The switch circuit 124c and the switch circuit 124d are turned off (open). A constant current Id flows between the P electrode terminal and the N electrode terminal of the semiconductor element 117.

[0274] By controlling the transistors 117m and 117s so that they are not turned on at the same time, or by controlling the transistors 117m and 117s so that they are turned on for only a short period of time, a surge voltage and a transient current flow through the semiconductor element 117, allowing for more stringent testing.

[0275] The tests of the semiconductor element 117 are performed by selecting or combining the tests shown in Figures 26(a) to 26(f) above. Examples of combinations include performing the tests of Figures 26(a) to 26(f) in order, and performing the tests of Figures 26(a) to 26(f) randomly.

[0276] 27 is an explanatory diagram of a semiconductor device testing apparatus and a semiconductor device testing method according to another embodiment of the present invention. The test circuit module 301 is exemplified by FIG. 3 and the like. The test circuit module 301 is connected to sections A, B, and C in FIG. 27(a). The test circuit module 301 is prepared corresponding to each semiconductor device 117. The test circuit module 301 is exemplified by, for example, FIG. 26 and FIG. 3.

[0277] The test circuit module 301 is connected to three switch circuit boards 201 (switch circuit board 201b, switch circuit board 201c, and switch circuit board 201d). As shown in FIG. 27(a), the switch circuit board 201b is prepared corresponding to the semiconductor element 117 to be tested. In FIG. 27(a), a switch circuit 124aa is arranged in the test circuit module 301a, a switch circuit 124ab is arranged in the test circuit module 301b, and a switch circuit 124ac is arranged in the test circuit module 301c.

[0278] 27(a) is an embodiment in which a plurality of semiconductor elements 117 are tested simultaneously or sequentially. Test circuit modules 301 are controlled by one control circuit board 111. In FIG. 27( a ), a plurality of semiconductor elements 117 to be tested are connected in parallel to a power supply device 132 .

[0279] 27(b) is an explanatory diagram of the operation of the semiconductor device testing apparatus of the present invention. As an example, the semiconductor device 117 of the test circuit module 301 is described as operating as shown in FIG. 26(b).

[0280] In the embodiment of the present invention, the transistor 117 to be tested is described as an IGBT, but this is not limited to this. For example, it may be a two-terminal element such as a diode. Furthermore, it is not limited to a semiconductor element, and any electric element such as a capacitor or resistor may be used. It goes without saying that the matters or contents described in this specification and drawings can be combined with each other.

[0281] Although the present specification has described the present invention in detail based on the embodiments, it goes without saying that the present invention is not limited to these embodiments and that various modifications are possible within the scope of the present invention. It goes without saying that the matters or contents described in this specification and drawings can be combined with each other. [Industrial Applicability]

[0282] The present invention provides a semiconductor element testing apparatus and a semiconductor testing method that can easily change connections depending on the test content of semiconductor elements such as transistors and the number of semiconductor elements to be tested simultaneously, and that can effectively implement measures to prevent noise generated during testing. [Explanation of symbols]

[0283] 111 Control circuit board (controller) 112 Gate signal control circuit 113 Gate driver circuit 115 Temperature measurement circuit 116 Operational amplifier (buffer amplifier) 117 Power Transistor 118 Constant current circuit 121 Constant current circuit 122 Switch Circuit 124 Switch Circuit 125 Variable Resistor Circuit 126 Variable Resistor Circuit 127 Selectors 128 Current detection circuit 129 Voltage detection circuit 130 Constant current setting circuit 131 Control Rack 132 Power supply 133 Control circuit 134 Heating and cooling plate 135 Circulating Water Pipe 136 Chiller 137 Short Circuit 138 Isolated DC / DC converter circuit 201 Switch circuit board 202 Connector 203 Sample connection circuit 204 Conductor Plate 205 fork plug 206 connecting pins 207 Motherboard 208 Connector 209 Device control circuit board 210 cabinet 211 Connection wiring 212 Power wiring 213 Connector 214 Bulkhead 215 Bulkhead 216 Opening 219 Connection bolt 220 Contact part 221 Fixing screw 222 signal wiring 223 Heat Pipe 224 Fixing screw 225 Contact point 226 Element terminal 227 Cooling Fan 228 Heat dissipation fin 231 Heat pipe fittings 232 Connection pressure part 233 Connection holder 236 Spring (pressure fitting) 237 Position fixing screw 238 screw holes 239 Spring hole 240 positioning screw hole 241 Fork plug insert plate 251 Convex 252 Groove 301 Test Circuit Module 302 Voltage selection circuit 311 Pressing tool 312 Insulating board 313 Pressing tool mounting plate 315 Insulation section

Claims

1. A power semiconductor device testing apparatus for testing a semiconductor device having a first device terminal and a second device terminal, a power supply circuit having a first output terminal and a second output terminal, for supplying a test current to the semiconductor device; a first switch circuit board on which a first switch circuit and a first conductive plate or conductive rod are arranged; a connecting member having a first connecting portion; a connection member having the first connection portion connected to the first element terminal; the second element terminal is connected to the second output terminal; the first switch circuit is connected to the first conductive plate or conductive rod, the first conductive plate or conductive rod has a first portion protruding from the first switch circuit board, the first connection member is inserted into a first opening selected from a partition wall having a plurality of openings, and the first connection portion and the first portion are fitted together and connected; The power semiconductor device testing device according to claim 1, wherein the test current is supplied to the first device terminal via the first switch circuit.

2. A power semiconductor device testing apparatus for testing a semiconductor device having a first device terminal and a second device terminal, a power supply circuit having a first output terminal and a second output terminal, for supplying a test current to the semiconductor device; a first switch circuit board on which a first switch circuit, a first conductive plate or conductive rod, and a second conductive plate or conductive rod are arranged; a connecting member having a first connecting portion and a connecting member having a second connecting portion; a connection member having the first connection portion connected to the first output terminal; a connecting member having the second connecting portion connected to the first element terminal; the second element terminal is connected to the second output terminal; the first switch circuit is connected to the first conductive plate or conductive rod and the second conductive plate or conductive rod; the first conductive plate or conductive rod has a first portion protruding from the first switch circuit board, the second conductive plate or conductive rod has a second portion protruding from the first switch circuit board, the first connection member is inserted into a first opening selected from a partition wall having a plurality of openings, and the first connection portion and the first portion are fitted together and connected; the second connection member is inserted into a second opening selected from a partition wall having a plurality of openings, and the second connection portion and the second portion are fitted together and connected; The power semiconductor device testing device according to claim 1, wherein the test current is supplied to the first device terminal via the first switch circuit.

3. A power semiconductor device testing apparatus for testing a semiconductor device having a first device terminal and a second device terminal, a power supply circuit having a first output terminal and a second output terminal for supplying a test current to the semiconductor device; a first switch circuit board on which a first switch circuit, a first conductive plate or conductive rod, and a second conductive plate or conductive rod are arranged; a second switch circuit board on which a second switch circuit, a third conductive plate or conductive rod, and a fourth conductive plate or conductive rod are arranged; a connecting member having a first connecting portion and a connecting member having a second connecting portion; the second element terminal is connected to the second output terminal; the first connection member is connected to the first output terminal, the second connection member is connected to the first element terminal, the third conductive plate or conductive rod is connected to the first output terminal, the fourth conductive plate or conductive rod is connected to the second output terminal, the first switch circuit is connected to the first conductive plate or conductive rod and the second conductive plate or conductive rod; the second switch circuit is connected to the third conductive plate or conductive rod and the fourth conductive plate or conductive rod, the first conductive plate or conductive rod has a first portion protruding from the first switch circuit board, the second conductive plate or conductive rod has a second portion protruding from the first switch circuit board, the first connection member is inserted into a first opening selected from a partition wall having a plurality of openings, and the first connection portion and the first portion are fitted together and connected; the second connection member is inserted into a second opening selected from a partition wall having a plurality of openings, and the second connection portion and the second portion are fitted together and connected; the test current is supplied to the first element terminal via the first switch circuit; The power semiconductor device testing device according to claim 1, wherein the second switch circuit short-circuits the first output terminal and the second output terminal when turned on.

4. A power semiconductor device testing apparatus for testing a semiconductor device having a first device terminal and a second device terminal, a power supply circuit having a first output terminal and a second output terminal, for supplying a test current to the semiconductor device; a constant current circuit that supplies a constant current to a diode connected to the first element terminal and the second element terminal; a terminal voltage output circuit; a first switch circuit board on which a first switch circuit and a first conductive plate or conductive rod are arranged; a connecting member having a first connecting portion; the first connection member is connected to the first output terminal or the first element terminal, the second element terminal is connected to the second output terminal; the first switch circuit is connected to the first conductive plate or conductive rod, the first conductive plate or conductive rod has a first portion protruding from the first switch circuit board, the first connection member is inserted into a first opening selected from a partition wall having a plurality of openings, and the first connection portion and the first portion are fitted together and connected; the test current is supplied to the first element terminal via the first switch circuit; The power semiconductor element testing device is characterized in that the constant current circuit supplies the constant current to the diode between the first element terminal and the second element terminal when the first switch circuit is off, and the terminal voltage output circuit outputs a voltage between the first element terminal and the second element terminal.

5. Further comprising a mounting substrate; 5. The power semiconductor device testing apparatus according to claim 1, wherein the first switch circuit board is connected to the mounting board by a connector.

6. the semiconductor element is a transistor element having a gate terminal; further comprising a driver circuit that applies a drive voltage to the gate terminal; 5. The power semiconductor element testing device according to claim 1, wherein the driver circuit periodically applies a first off voltage, a second off voltage, and an on voltage to the gate terminal.

7. the semiconductor element is a transistor element having a gate terminal; further comprising a driver circuit that applies a drive voltage to the gate terminal; 5. The power semiconductor element testing device according to claim 1, wherein a variable resistance circuit is connected to the gate terminal.

8. Further comprising a heating / cooling plate and a water leak sensor; the semiconductor element is disposed in close contact with the heating / cooling plate, 5. The power semiconductor element testing device according to claim 1, wherein the water leakage sensor is disposed around the heating / cooling plate.

9. The power semiconductor device testing apparatus has a first chamber and a second chamber, the semiconductor device is disposed in a first chamber; the first switch circuit board is disposed in the second chamber; 5. The power semiconductor device testing apparatus according to claim 1, 2, 3 or 4, wherein dry air is injected into the first chamber.

10. A power semiconductor element testing apparatus as described in claim 2 or claim 3, characterized in that the opening for inserting the second connecting member is positioned at a position corresponding to the second part.

Images