Power supply control device and power supply system

Abstract

The temperature characteristics of a stabilization control circuit in a power supply device are optimized. [Solution] A power supply control device (2) constituting a power supply device (1) that has an output stage (MM) provided between an input terminal (IN) to which an input voltage (Vin) is applied and an output terminal (OUT) to which an output voltage (Vout) is applied, and that generates an output voltage (Vout) from the input voltage (Vin), comprises a stabilization control circuit (10) that stabilizes the output voltage to a target voltage (Vtg) by controlling the state of the output stage according to a feedback voltage (Vfb) that corresponds to the output voltage, a parameter memory circuit (21) that stores a plurality of internal parameters for determining the temperature characteristics of the stabilization control circuit, a communication circuit (30) that receives a command signal from an external device (4), and a setting circuit (40) that sets the temperature characteristics of the stabilization control circuit by validating one of the plurality of internal parameters based on the command signal.

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device and a power supply system. [Background technology]

[0002] A power supply device that generates an output voltage from an input voltage is provided with a power supply control device for controlling the operation of the power supply device (see, for example, Patent Document 1 listed below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-89043

[0004] [overview] Techniques that contribute to optimizing the operation of power supplies would be beneficial.

[0005] A power supply control device according to one embodiment of the present disclosure is a power supply control device that constitutes a power supply device having an output stage arranged between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and is configured to generate the output voltage from the input voltage, and includes: a stabilization control circuit configured to stabilize the output voltage to a target voltage by controlling the state of the output stage in accordance with a feedback voltage that corresponds to the output voltage; a parameter memory circuit configured to store a plurality of internal parameters for determining the temperature characteristics of the stabilization control circuit; a communication circuit configured to receive a command signal from an external device of the power supply control device; and a setting circuit configured to set the temperature characteristics of the stabilization control circuit by validating one of the plurality of internal parameters based on the command signal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating the overall configuration of a system according to an embodiment of the present disclosure. [Figure 2]FIG. 2 is an external perspective view of a power supply control device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of a power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing a stabilization control circuit and its peripheral circuits in a power supply device according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a waveform diagram of some signals involved in the operation of the stabilization control circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing how a plurality of internal parameters are stored in a parameter storage circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a graph showing the temperature dependence of inductance in three types of coils according to a first example of an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing how three internal parameters are stored in a parameter storage circuit according to a first example of an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing how three candidate circuits that are candidates for a phase compensation circuit are installed according to a first example belonging to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram schematically illustrating setting specification data disclosed in the specifications of a power supply control device according to a first example of an embodiment of the present disclosure. [Figure 11] FIG. 11 relates to a first example belonging to an embodiment of the present disclosure, and is a diagram showing how each internal parameter is set to be valid or invalid based on a setting command signal. [Figure 12] FIG. 12 is a graph showing the temperature dependence of capacitance values ​​of three types of capacitors according to a second example of the embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram illustrating a second example of the configuration specification data disclosed in the specifications of the power supply control device according to the second example of the embodiment of the present disclosure. [Figure 14]FIG. 14 is a diagram showing how nine internal parameters are stored in a parameter storage circuit according to a third example of an embodiment of the present disclosure. [Figure 15] FIG. 15 is a graph showing the temperature dependence of series resistance values ​​in three types of coils according to a fourth example belonging to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a partial configuration diagram of a power supply device according to a fourth example of an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing the contents of three internal parameters according to a fourth example of the embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram schematically illustrating setting specification data disclosed in the specifications of a power supply control device according to a fourth example of an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having an electric potential of 0 V (zero volts) as a reference, or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to the level (height) of the electric potential, and for any signal or voltage of interest, a high level has a higher electric potential than a low level. For any signal or voltage of interest, a transition from a low level to a high level is sometimes called a rising edge, and a transition from a high level to a low level is sometimes called a falling edge.

[0010] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0011] For any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period. Hereinafter, the on and off states of any transistor may be simply referred to as on and off. For any signal having a high or low signal level, the period during which the signal level is high is referred to as the high level period, and the period during which the signal level is low is referred to as the low level period. The same applies to any voltage having a high or low voltage level.

[0012] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0013] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0014] FIG. 1 is an overall configuration diagram of a system SYS according to an embodiment of the present disclosure. The system SYS may be referred to as a power supply system. The system SYS in FIG. 1 includes a power supply device 1 and a processor 4. The power supply device 1 includes a power supply control device 2 that controls the operation of the power supply device 1, and a discrete component group 3 composed of a plurality of discrete components externally connected to the power supply control device 2. The processor 4 is an example of an external device provided outside the power supply control device 2. The processor 4 is connected to the power supply control device 2. The power supply control device 2 and the processor 4 may be connected in a manner that enables bidirectional communication with each other. The processor 4 is, for example, an MCU (Micro Controller Unit) or an SOC (System on a Chip).

[0015] FIG. 2 shows an external perspective view of the power supply control device 2. The power supply control device 2 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing CS to the outside of the power supply control device 2. The power supply control device 2 is formed by encapsulating the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the power supply control device 2 shown in FIG. 2 and the type of the housing CS of the power supply control device 2 are merely examples, and they can be arbitrarily designed.

[0016] FIG. 3 shows an example configuration of a power supply device 1. The group of discrete components 3 in the power supply device 1 in FIG. 3 includes a coil L1 and an output capacitor C1. The power supply control device 2 in FIG. 3 has built-in feedback resistors R1 and R2, but the feedback resistors R1 and R2 may be provided external to the power supply control device 2 (and therefore the feedback resistors R1 and R2 may be components of the group of discrete components 3). The power supply device 1 in FIG. 3 also includes a temperature detection circuit 5.

[0017] The power supply device 1 in Figure 3 is configured as a step-down switching power supply device (DC / DC converter) that generates a desired output voltage Vout from an input voltage Vin supplied from a voltage source (not shown). However, the power supply device 1 may be a power supply device other than a step-down switching power supply device. Examples of power supply devices other than step-down switching power supplies include step-up switching power supplies, step-up / step-down switching power supplies, and linear power supplies (linear regulators).

[0018] An output voltage Vout is generated at the output terminal OUT. In other words, the output terminal OUT is an application terminal (a terminal to which the output voltage Vout is applied) for the output voltage Vout. The output voltage Vout is supplied to a load (not shown) connected to the output terminal OUT. The load may include a processor 4. In the power supply device 1 of FIG. 3, the input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12 V, the output voltage Vout can be stabilized to a desired target voltage Vtg (e.g., 3.3 V or 5 V) that is less than 12 V.

[0019] 3 shows an input terminal IN, a switch terminal SW, a ground terminal GND, an output monitoring terminal OM, and a detection signal input terminal TT as some of the external terminals provided on the power supply control device 2. Also shown in Fig. 3 are communication external terminals for transmitting and receiving communication signals between the processor 4 and the power supply control device 2, but the communication external terminals are not labeled. The communication external terminals are composed of two or more external terminals.

[0020] An input voltage Vin is supplied to an input terminal IN from a DC voltage source (not shown) provided outside the power supply control device 2. A coil L1 is connected in series between a switch terminal SW and an output terminal OUT. That is, a first end of the coil L1 is connected to the switch terminal SW, and a second end of the coil L1 is connected to the output terminal OUT. The output terminal OUT is also connected to ground via an output capacitor C1. That is, a first end of the output capacitor C1 is connected to the output terminal OUT, and a second end of the output capacitor C1 is connected to ground. The ground terminal GND is connected to ground. The output terminal OUT is connected to an output monitoring terminal OM. The current flowing through the coil L1 is referred to as a coil current IL.

[0021] The power supply control device 2 includes an output stage MM, a stabilization control circuit 10, a memory 20, a communication circuit 30, and a setting circuit 40, as well as feedback resistors R1 and R2.

[0022] The output monitoring terminal OM is connected to the first terminal of the feedback resistor R1. That is, the first terminal of the feedback resistor R1 is connected to the output terminal OUT through the output monitoring terminal OM and receives the output voltage Vout. The second terminal of the feedback resistor R1 is connected to the first terminal of the feedback resistor R2, and the second terminal of the feedback resistor R2 is connected to ground. A feedback voltage Vfb is generated at the connection node between the feedback resistors R1 and R2. The feedback resistors R1 and R2 form a feedback voltage generation circuit that divides the output voltage Vout to generate a feedback voltage Vfb corresponding to the output voltage Vout. The feedback voltage Vfb is proportional to the output voltage Vout, and the feedback voltage Vfb also rises and falls as the output voltage Vout rises and falls. The feedback voltage Vfb is input to the stabilization control circuit 10. However, a modification may be made in which the output voltage Vout itself is used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout.

[0023] The output stage MM includes a high-side transistor MH and a low-side transistor ML. The transistors MH and ML are configured by N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). Of these, the transistor MH functions as an output transistor, and the transistor ML functions as a synchronous rectifier transistor. The transistor MH is located on a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and receives the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and therefore to ground). However, a current detection resistor may be inserted between the source of the transistor ML and the ground terminal GND.

[0024] The stabilization control circuit 10 controls the switching of the output stage MM based on the feedback voltage Vfb. In the switching control of the output stage MM, the transistors MH and ML are switched so that they are alternately turned on and off. The stabilization control circuit 10 is connected to the gates of the transistors MH and ML, and controls the gate potentials of the transistors MH and ML individually to set the transistors MH and ML individually on or off. The switching control of the output stage MM causes a square-wave switch voltage Vsw to appear at the switch terminal SW. The coil L1 and the output capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switch voltage Vsw appearing at the switch terminal SW to generate the output voltage Vout. This rectifying and smoothing circuit is connected to the output stage MM outside the power supply control device 2.

[0025] Gate signals GH and GL are supplied to the gates of the transistors MH and ML, respectively, as drive signals from a driver built into the stabilization control circuit 10, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is on, and when the gate signal GH is at a low level, the transistor MH is off. Similarly, when the gate signal GL is at a high level, the transistor ML is on, and when the gate signal GL is at a low level, the transistor ML is off.

[0026] Basically, the transistors MH and ML are alternately turned on and off, but both transistors MH and ML may be maintained in the off state. That is, the state of the output stage MM is one of an output high state, an output low state, and a both-off state (Hi-Z state). In the output high state, the transistor MH is on and the transistor ML is off. In the output low state, the transistor MH is off and the transistor ML is on. In the both-off state, both transistors MH and ML are off. The transistors MH and ML are never on at the same time. In the switching control by the stabilization control circuit 10, alternately turning the transistors MH and ML on and off refers to the concept of both being in the off state, taking into account dead time, etc., between the transition between the output low state and the output high state. At least one of the transistors MH and ML may be provided external to the power supply control device 2. The entire output stage MM may also be provided external to the power supply control device 2.

[0027] The stabilization control circuit 10 controls the on / off states of the transistors MH and ML by controlling the levels of the gate signals GH and GL based on the feedback voltage Vfb, and in cooperation with the coil L1 and the output capacitor C1, generates the desired output voltage Vout at the output terminal OUT. The stabilization control circuit 10 adjusts the output duty of the output stage MM so that the feedback voltage Vfb matches the reference voltage Vref. When "Vfb = Vref" is established, the value of the output voltage Vout matches the target voltage Vtg. The output duty represents the ratio of the period during which the output stage MM is in the output high state to the sum of the period during which the output stage MM is in the output high state and the period during which the output stage MM is in the output low state. The reference voltage Vref has a predetermined positive DC voltage value. The power supply control device 2 is provided with a reference voltage generation circuit (not shown) that generates one or more reference voltages based on the input voltage Vin.

[0028] The stabilization control circuit 10 can use any control method to stabilize the output voltage Vout to the target voltage Vtg, and can control the state of the output stage MM using, for example, a pulse width modulation method, a pulse frequency modulation method, or a constant on-time control method.

[0029] The stabilization control circuit 10 can also perform an overcurrent protection operation to protect the coil L1 and the power supply control device 2 from an overcurrent, and the overcurrent protection operation will be described in detail later.

[0030] Although not specifically shown, the power supply control device 2 is provided with an internal power supply circuit that generates one or more internal power supply voltages based on the input voltage Vin. Each circuit in the power supply control device 2 can be driven using the internal power supply voltage or the input voltage Vin as a drive voltage. The gate signal GL is a signal referenced to the ground potential, while the gate signal GH is a signal referenced to the potential of the switch terminal SW. A low-level gate signal GH has the potential of the switch terminal SW, while a high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. This predetermined voltage is greater than the gate threshold voltage of the transistor MH. A high-level gate signal GH can be generated using a well-known boost power supply (such as a bootstrap circuit). The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0031] Alternatively, the power supply 1 may employ a diode rectification system. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is provided in the power supply 1 as a rectifying element. In this case, only the transistor MH is turned on and off in the switching control of the output stage MM. In either case, the output voltage Vout is generated based on the current (IL) flowing through the coil L1 by switching the transistor MH between on and off in the switching control of the output stage MM.

[0032] The memory 20 is made up of a volatile memory and a nonvolatile memory, and stores various information referenced within the power supply control device 2. The memory 20 is provided with a parameter storage circuit 21 (details of which will be described later) made up of a nonvolatile memory.

[0033] The communication circuit 30 performs bidirectional communication with the processor 4. As an interface for bidirectional communication between the communication circuit 30 and the processor 4, for example, an SPI (Serial Peripheral Interface) may be used, or an I 2An interface using an Inter-Integrated Circuit (C) or Microwire may also be used. The processor 4 can send various instructions to the communication circuit 30 as command signals, and the setting circuit 40 and the stabilization control circuit 10 operate in accordance with the command signals received by the communication circuit 30.

[0034] The setting circuit 40 sets the operating conditions of the stabilization control circuit 10 based on the data stored in the memory 20, the command signal received by the communication circuit 30, and the signal supplied from the temperature detection circuit 5 (the temperature detection signal Tsns described below).

[0035] The temperature detection circuit 5 generates a temperature detection signal Tsns by detecting the temperature Tmp at the measurement target position. The temperature detection signal Tsns is input from the temperature detection circuit 5 to a detection signal input terminal TT and supplied to the setting circuit 40 via the detection signal input terminal TT. The temperature detection circuit 5 has a temperature measuring element (such as a resistance temperature detector, linear resistor, or thermistor) placed at the measurement target position and can detect the temperature Tmp using the temperature measuring element. The temperature detection circuit 5 may also be a semiconductor temperature sensor. The semiconductor temperature sensor has a silicon diode placed at the measurement target position and detects the temperature Tmp using the temperature characteristics of the diode's forward voltage. Instead of the diode's forward voltage, the base-emitter voltage of a bipolar transistor may also be used to detect the temperature Tmp.

[0036] The temperature detection signal Tsns is a voltage signal that represents the temperature Tmp (a voltage signal that indicates the detected value of the temperature Tmp). The temperature detection signal Tsns may be an analog voltage signal or a digital voltage signal. In either case, the value of the temperature Tmp is determined from the signal value of the temperature detection signal Tsns.

[0037] The measurement target position is set outside the power supply control device 2. The temperature detection circuit 5 may detect the temperature of the environment in which the system SYS is placed as temperature Tmp. When the power supply control device 2, coil L1, and output capacitor C1 are placed sufficiently close to each other, temperature Tmp represents the temperature of the power supply control device 2, coil L1, and output capacitor C1. When focusing particularly on coil L1, the measurement target position may be located as close as possible to coil L1, and in this case, temperature Tmp will accurately represent the temperature of coil L1. When focusing particularly on output capacitor C1, the measurement target position may be located as close as possible to output capacitor C1, and in this case, temperature Tmp will accurately represent the temperature of output capacitor C1. The setting circuit 40 recognizes temperature Tmp from the temperature detection signal Tsns. Note that the temperature detection circuit 5 is not essential for the power supply device 1. If the power supply device 1 does not have a temperature detection circuit 5, the detection signal input terminal TT in the power supply control device 2 can be omitted.

[0038] FIG. 4 shows an example of the internal configuration of the stabilization control circuit 10. FIG. 4 shows an example of the configuration of the stabilization control circuit 10 that controls the output duty of the output stage MM using pulse width modulation. The stabilization control circuit 10 of FIG. 4 includes an error amplifier 11, a phase compensation circuit 12, a slope generation circuit 13, a comparator 14, a set issuing circuit 15, a logic circuit 16, and a driver 17. The phase compensation circuit 12 includes a resistor 12R and a capacitor 12C. The error amplifier 11 may be a transconductance amplifier. FIG. 5 shows waveforms of several signals related to the configuration of FIG. 4.

[0039] A feedback voltage Vfb is input to the inverting input terminal of an error amplifier 11, and a reference voltage Vref is input to the non-inverting input terminal of the error amplifier 11. The error amplifier 11 outputs an error signal Verr from its output terminal, which corresponds to the error between the feedback voltage Vfb and the reference voltage Vref. A stabilization control circuit 10 realizes feedback control that reduces the error between the feedback voltage Vref and the reference voltage Vref to zero. To stabilize the feedback control, a phase compensation circuit 12 compensates the phase of the error signal Verr. In the configuration example of FIG. 4 , a first terminal of a resistor 12R is connected to the output terminal of the error amplifier 11 (and therefore connected to the wiring to which the error signal Verr is applied), a second terminal of the resistor 12R is connected to a first terminal of a capacitor 12C, and a second terminal of the capacitor 12C is connected to the inverting input terminal of the error amplifier 11. However, the connection relationship between the phase compensation circuit 12 and the error amplifier 11 is not limited to that shown in FIG. 4 . For example, the second terminal of the capacitor 12C may be connected to ground.

[0040] The slope generation circuit 13 generates and outputs the slope signal Vslp. Because the slope signal Vslp and the error signal Verr are voltage signals, they may be interpreted as slope voltages Vslp and Verr. During the period when the output stage MM is set to the output high state, the slope generation circuit 13 monotonically increases the slope signal Vslp at a predetermined rate of increase (see FIG. 5). During the period when the output stage MM is set to the output high state, the slope generation circuit 13 may generate the slope signal Vslp as the sum signal of a monotonically increasing ramp signal and a signal proportional to the coil current IL. During the period when the output stage MM is set to the output low state, the slope generation circuit 13 maintains the slope signal Vslp at a sufficiently low level (see FIG. 5). The slope generation circuit 13 receives signals SET and RST, which will be described later, and can recognize whether the output stage MM is in the output high state or the output low state based on the signals SET and RST.

[0041] The error signal Verr and the slope signal Vslp are respectively input to the inverting input terminal and the non-inverting input terminal of the comparator 14. The comparator 14 compares the error signal Verr and the slope signal Vslp, and outputs a signal RST indicating the comparison result. The signal RST is a binary signal having a high level or a low level. The comparator 14 outputs a high-level signal RST in a state where "Vslp≧Verr" holds, and outputs a low-level signal RST in a state where "Vslp<Verr" holds.

[0042] The set issuing circuit 15 includes an oscillator that generates a clock signal, or receives a clock signal from an oscillator. The clock signal is a rectangular wave signal having a predetermined clock frequency, and thus has a high level and a low level alternately. The set issuing circuit 15 generates and outputs a signal SET synchronized with the clock signal. In principle, the set issuing circuit 15 sets the signal SET to a low level, and sets the signal SET to a high level for a short time when a rising edge occurs in the clock signal (see FIG. 5).

[0043] The signals SET and RST are input to the logic circuit 16. The driver 17 includes a high-side driver connected to the gate of the transistor MH to drive the gate of the transistor MH, and a low-side driver connected to the gate of the transistor ML to drive the gate of the transistor ML. Based on the signals SET and RST, the logic circuit 16 individually sets the transistors MH and ML to on or off using the driver 17.

[0044] FIG. 5 shows examples of waveforms of signals Verr, Vslp, SET, RST, GH, and GL. In FIG. 5, it is assumed that a sum signal of a lamp signal and a signal proportional to the coil current IL is generated as the slope signal Vslp, and a situation where a positive coil current IL always flows through the coil L1 is assumed. The coil current IL flowing from the switch terminal SW toward the output terminal OUT has a positive polarity (see FIG. 3). Under this assumption, the logic circuit 16 repeats an operation of switching the output stage MM from the output low state to the output high state in synchronization with the rising edge of the signal SET and switching the output stage MM from the output high state to the output low state in synchronization with the rising edge of the signal RST at the clock frequency. The slope generation circuit 13 starts outputting the sum signal as the slope signal Vslp契机にthe rising edge of the signal SET, and when the rising edge of the signal RET occurs, the slope signal Vslp is lowered to a sufficiently low level LV0 and the slope signal Vslp is maintained at the level LV0 until the next rising edge of the signal SET occurs. The level LV0 is lower than the lower limit of the fluctuation range of the error signal Verr. When the rising edge of the signal RST occurs because the slope signal Vslp reaches the error signal Verr due to the rise of the slope signal Vslp, the level of the slope signal Vslp immediately drops to the level LV0, so the high level period of the signal RST becomes very short.

[0045] The establishment of "Vfb < Vref" brings an increase in the output duty through the increase of the error signal Verr, and as a result, raises the output voltage Vout. Conversely, the establishment of "Vfb > Vref" brings a decrease in the output duty through the decrease of the error signal Verr, and as a result, lowers the output voltage Vout. Thus, the stabilization control circuit 10 controls the state of the output stage MM so as to reduce the error between the feedback voltage Vref and the reference voltage Vref to zero. The above-mentioned error signal Verr is an example of an internal signal corresponding to the error.

[0046] It should be noted that there is an unclear part in the original text "契机に" which is translated as "契机に" in the English version. It might be a typo or an unclear expression in the original. If it has a specific meaning that can be clarified, a more accurate translation can be made.The power supply control device 2 is configured to enable switching between multiple temperature characteristics of the stabilization control circuit 10. Parameters for determining the temperature characteristics of the stabilization control circuit 10 are called internal parameters. As shown in FIG. 6, multiple internal parameters are stored in a nonvolatile manner in the parameter storage circuit 21. Each internal parameter is written to the parameter storage circuit 21 during manufacturing or shipping of the power supply control device 2. The setting circuit 40 enables one of the multiple internal parameters based on a setting command signal from the processor 4, and sets the temperature characteristics of the stabilization control circuit 10 according to the enabled internal parameter. The temperature characteristics of the stabilization control circuit 10 change when one internal parameter is enabled and when another internal parameter is enabled. That is, the temperature characteristics of the stabilization control circuit 10 when one internal parameter is enabled differ from the temperature characteristics of the stabilization control circuit 10 when the other internal parameters are enabled.

[0047] Below, several specific operational examples, application techniques, modified techniques, etc. related to the power supply device 1 or the power supply control device 2 will be described in multiple embodiments. The matters described above in this embodiment apply to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments described below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0048] <<First Example>> A first embodiment will be described. Circuit elements provided outside the power supply control device 2 and that cooperate with the stabilization control circuit 10 and the output stage MM to realize a power conversion operation for converting an input voltage Vin into an output voltage Vout are referred to as external circuit elements. The coil L1 and the output capacitor C1 correspond to the external circuit elements.

[0049] The designer of the power supply device 1 or the system SYS incorporates the coil L1 selected from various types of coils having various temperature characteristics into the power supply device 1. Fig. 7 shows the temperature characteristics of the inductance in each of the first to third types of coils. The inductance is represented by the symbol "L VAL ". In Fig. 7, the solid line segment 611 represents the temperature characteristic of the inductance L VAL in the first type of coil, the dashed line segment 612 represents the temperature characteristic of the inductance L VAL in the second type of coil, and the dashed curve 613 represents the temperature characteristic of the inductance L VAL in the third type of coil. The minimum temperature and the maximum temperature in the predetermined temperature range Trng are referred to as the minimum temperature Tmin and the maximum temperature Tmax, respectively. The intermediate temperature Tmid belongs to the temperature range Trng. "Tmin < Tmid < Tmax" holds. The temperature range Trng coincides with or is included in the temperature range in which the power control device 2 and the external circuit elements are used.

[0050] For the sake of concreteness of the description, it is assumed that the first to third types of coils have the following temperature characteristics. The inductances L VAL1 to L VAL4 shown in Fig. 7 satisfy "L VAL1 < L VAL4 < L VAL3 < L VAL2 ". As shown by the solid line segment 611, the inductance L VAL in the first type of coil is the inductance L VAL1 when the temperature of the first type of coil coincides with the minimum temperature Tmin, and is the inductance L VAL2 when the temperature of the first type of coil coincides with the maximum temperature Tmax. As the temperature of the first type of coil rises from the minimum temperature Tmin toward the maximum temperature Tmax, the inductance L VAL in the first type of coil monotonically increases. As shown by the dashed line segment 612, the inductance L VAL in the second type of coil is the inductance L VAL2When the temperature of the second type of coil coincides with the maximum temperature Tmax, the inductance L VAL1 As the temperature of the second type of coil rises from the minimum temperature Tmin to the maximum temperature Tmax, the inductance L VAL is monotonically decreasing.

[0051] As shown by the dashed curve 613, the inductance L VAL is the inductance L when the temperature of the third type coil coincides with the minimum temperature Tmin. VAL4 When the temperature of the third type of coil coincides with the intermediate temperature Tmid, the inductance L VAL3 As the temperature of the third type of coil rises from the minimum temperature Tmin to the intermediate temperature Tmid, the inductance L VAL increases monotonically, and as the temperature of the third type of coil rises from the intermediate temperature Tmid to the maximum temperature Tmax, the inductance L VAL When the temperature of the third type of coil coincides with the maximum temperature Tmax, the inductance L VAL is the inductance L VAL3 Smaller and inductance L VAL1 Greater than.

[0052] The power supply control device 2 needs to perform stable feedback control regardless of which of various types of coils is used as coil L1. A power supply control device configured so that the temperature characteristics of the phase compensation circuit 12 cannot be changed, rather than the actual power supply control device 2, is referred to as a virtual power supply control device J1. In the virtual power supply control device J1, the phase compensation circuit 12 is designed with a relatively large margin so that stable feedback control can be achieved regardless of which of various types of coils is used as coil L1. This means that the virtual power supply control device J1 is not optimized for a first type of coil, a second type of coil, or a third type of coil.

[0053] If it can be determined that coil L1 is a first type of coil, it is possible to employ temperature characteristics suitable for the temperature characteristics of the first type of coil in phase compensation circuit 12. Similarly, if it can be determined that coil L1 is a second type of coil, it is possible to employ temperature characteristics suitable for the temperature characteristics of the second type of coil in phase compensation circuit 12. The same is true if it can be determined that coil L1 is another type of coil.

[0054] Taking this into consideration, in the first embodiment, the power supply control device 2 is configured so that it is possible to switch between multiple temperature characteristics of the phase compensation circuit 12 as the temperature characteristic of the stabilization control circuit 10. Here, in the first embodiment, it is assumed that the temperature characteristic of the output capacitor C1 has the temperature characteristic specified in the specifications of the power supply control device 2, and therefore the temperature characteristic of the output capacitor C1 is determined to be the temperature characteristic specified in the specifications at the design stage of the power supply control device 2. In other words, in the first embodiment, it is taken into consideration that, of the temperature characteristics of the coil L1 and the temperature characteristics of the output capacitor C1, only the temperature characteristic of the coil L1 varies.

[0055] Among the multiple internal parameters stored in the parameter storage circuit 21, the internal parameter P A [1]~P A [3] is included. The internal parameter P A [1]~P A [3] are parameters that determine the temperature characteristics of the phase compensation circuit 12. The setting circuit 40 sets the internal parameter P A [1]~P A [3] Set one of them to enabled and the other two to disabled.

[0056] The setting command signal received by the communication circuit 30 is command data D A [1]~D A [3] Includes one of the following: Command data D A [i] is the internal parameter P A[i], which is the data corresponding to the internal parameter P A Therefore, the setting command signal received by the communication circuit 30 is the command data D A If [i] is included, the setting circuit 40 sets the internal parameter P A [1]~P A [3], the internal parameter P A [i] is set to valid, and the other two are set to invalid. In the first embodiment, i represents 1, 2, or 3.

[0057] The setting circuit 40 sets the internal parameter P A If [i] is set to valid, the valid internal parameter P A According to [i], the temperature characteristic of the phase compensation circuit 12 is set to the temperature characteristic TC A Set to [i]. Temperature characteristics TC A [1]~TC A [3] are different from each other. In order to realize the switching of the temperature characteristics of the phase compensation circuit 12, three candidate circuits 12[1] to 12[3] are provided in the power supply control device 2 as candidates for the phase compensation circuit 12, as shown in FIG. 9. The candidate circuit 12[1] is a series circuit of a capacitor 12C[1] and a resistor 12R[1], and the internal parameter P A The candidate circuit 12[2] is a series circuit of a capacitor 12C[2] and a resistor 12R[2], and the internal parameter P A The candidate circuit 12[3] is a series circuit of a capacitor 12C[3] and a resistor 12R[3], and the internal parameter P A Corresponds to [3].

[0058] The power supply control device 2 is provided with switches SWa[1] to SWa[3] and SWb[1] to SWb[3] so that one of the candidate circuits 12[1] to 12[3] can selectively function as the phase compensation circuit 12. The switches SWa[1] to SWa[3] and SWb[1] to SWb[3] are each analog switches made up of MOSFETs. The first terminal of the candidate circuit 12[i] is connected to the output terminal of the operational amplifier 11 via the switch SWa[i], and the second terminal of the candidate circuit 12[i] is connected to the inverting input terminal of the operational amplifier 11 via the switch SWb[i]. It can be understood that the switches SWa[1] to SWa[3] form a first multiplexer, and the switches SWb[1] to SWb[3] form a second multiplexer.

[0059] Internal parameter P A [i] is data that instructs that, among the switches SWa[1] to SWa[3] and SWb[1] to SWb[3], only the switches SWa[i] and SWb[i] are set to ON, and the remaining four switches are set to OFF. Therefore, the internal parameter P A When [1] is set to valid, the candidate circuit 12[1] is used as the phase compensation circuit 12, and the capacitor 12C[1] and the resistor 12R[1] function as the capacitor 12C and the resistor 12R in FIG. 4. Similarly, the internal parameter P A When [2] is set to valid, the candidate circuit 12[2] is used as the phase compensation circuit 12, and the capacitor 12C[2] and the resistor 12R[2] function as the capacitor 12C and the resistor 12R in FIG. 4. Similarly, the internal parameter P A When [3] is set to valid, the candidate circuit 12[3] is used as the phase compensation circuit 12, and the capacitor 12C[3] and the resistor 12R[3] function as the capacitor 12C and the resistor 12R in FIG.

[0060] The temperature characteristics of the candidate circuit 12[i] are determined by the temperature characteristics of the capacitor 12C[i] and the resistor 12R[i]. Here, the temperature characteristics of the capacitors 12C[1] to 12C[3] are different from one another, and the temperature characteristics of the resistors 12R[1] to 12R[3] are different from one another. As a result, the temperature characteristics of the candidate circuits 12[1] to 12[3] are different from one another. Therefore, the temperature characteristics of the phase compensation circuit 12 when the candidate circuit 12[1] is used as the phase compensation circuit 12, the temperature characteristics of the phase compensation circuit 12 when the candidate circuit 12[2] is used as the phase compensation circuit 12, and the temperature characteristics of the phase compensation circuit 12 when the candidate circuit 12[3] is used as the phase compensation circuit 12 are different from one another.

[0061] In the first embodiment, when the i-th type of coil is used as the coil L1, the temperature characteristics of the candidate circuit 12[i] are designed so that the feedback control and response performance of the power supply control device 2 are optimized by using the candidate circuit 12[i] as the phase compensation circuit 12. Basically, when the i-th type of coil is used as the coil L1, the candidate circuit 12[i] should have temperature characteristics that offset the change in the inductance of the coil L1 due to temperature.

[0062] The designer of the system SYS determines the setting command to be transmitted from the processor 4 as follows. The specifications (data sheet) of the power supply control device 2 are disclosed to the designer of the system SYS as a premise. The specifications of the power supply control device 2 disclose setting specification data 610 as shown in FIG. 10 . The setting specification data 610 includes graphs (611-613) showing the temperature characteristics of first to third types of coils. The setting specification data 610 also includes information recommending that the first setting be enabled for case CS1_EX1 in which the inductance of the coil L1 has temperature characteristics that match or are similar to the solid line segment 611, information recommending that the second setting be enabled for case CS2_EX1 in which the inductance of the coil L1 has temperature characteristics that match or are similar to the dashed line segment 612, and information recommending that the third setting be enabled for case CS3_EX1 in which the inductance of the coil L1 has temperature characteristics that match or are similar to the dashed line segment 613. The i-th setting corresponds to a setting in which the candidate circuit 12[i] is used for the phase compensation circuit 12. To enable the i-th setting, the command data D A The specifications of the power supply control device 2 also indicate information that a setting command signal including [i] should be sent to the power supply control device 2 .

[0063] The designer of the system SYS refers to the specifications of the power supply control device 2 including the setting specification data 610, and in the case CS1_EX1, sets the command data D to enable the first setting. A In case CS2_EX1, the command data D is set to enable the second setting so that a setting command signal including [1] is sent to the power supply control device 2. A [2] is transmitted to the power supply control device 2, and in case CS3_EX1, the command data D is set to enable the third setting. A The processor 4 may be designed so that a setting command signal including [3] is sent to the power supply control device 2. In this way, the setting command signal sent to the power supply control device 2 includes data (D A [1]~D A [3]).

[0064] When power supply to the power supply control device 2 is started and the power supply control device 2 is started, an initial sequence operation is executed in the power supply control device 2 to initialize the internal circuitry, etc. During the execution of the initial sequence operation, the output stage MM is maintained in a double-off state, and after the completion of the initial sequence operation, switching control of the output stage MM is performed (this is also the case in other embodiments described later). For example, during the initial sequence operation, the setting circuit 40 waits for reception of a setting command signal. Then, as shown in FIG. 11, when the setting command signal is received by the communication circuit 30, the setting circuit 40 sets the internal parameter P A [1]~P A [3] is set to valid. After that, switching control will start according to the valid internal parameters.

[0065] According to the first embodiment, a phase compensation circuit 12 with optimal temperature characteristics can be used to match the temperature characteristics of the coil L1 actually installed outside the power supply control device 2, thereby optimizing the feedback control and response performance of the power supply control device 2. The designer of the power supply control device 2 is different from the designer of the system SYS. The system SYS designer purchases the power supply control device 2 from a manufacturer and distributor of the power supply control device 2 and incorporates it into the system SYS. In this case, the system SYS designer does not directly specify the temperature characteristics of the phase compensation circuit 12 through the processor 4, but instead selects which of the first to third settings to enable by referring to the specifications of the power supply control device 2. This allows the manufacturer and distributor of the power supply control device 2 to optimize the temperature characteristics of the phase compensation circuit 12 to suit each individual system SYS, while keeping the details of the internal structure of the power supply control device 2 a black box (i.e., without disclosing them to the system SYS designer). Optimizing the temperature characteristics enables optimizing the transient response characteristics, which increases the likelihood of maintaining good power conversion operation even when the output capacitance (the capacitance of the output capacitor C1) is reduced. That is, it is possible to reduce the output capacitance, and when the output capacitor C1 is formed by a parallel connection circuit of a plurality of capacitors, it is also possible to reduce the number of components (reduce the number of parallel connections of capacitors).

[0066] For the sake of specificity and simplification of the explanation, it has been assumed that the number of types of coils used as the coil L1 is three, and a method for setting the temperature characteristic of the phase compensation circuit 12 to one of three types has been explained. However, the number of types of coils used as the coil L1 can be any number as long as it is two or more, and accordingly, the number of types of temperature characteristics of the phase compensation circuit 12 can be any number as long as it is two or more.

[0067] <<Second Example>> A second embodiment will now be described. In the second embodiment, attention is focused on the temperature characteristics of the output capacitor C1 rather than the temperature characteristics of the coil L1. For matters not specifically mentioned in the second embodiment, the description of the first embodiment applies to the second embodiment unless there is a contradiction.

[0068] The designer of the power supply device 1 or the system SYS incorporates an output capacitor C1 selected from various types of capacitors with various temperature characteristics into the power supply device 1. Figure 12 shows the temperature characteristics of the capacitance values ​​of the first to third types of capacitors. The capacitance values ​​are represented by the symbol "C VAL In FIG. 12, the solid line segment 631 represents the capacitance value C VAL The dashed line segment 632 represents the temperature characteristic of the capacitance value C VAL The dashed curve 633 represents the temperature characteristic of the capacitance value C VAL Represents the temperature characteristics of

[0069] For the sake of concreteness, it is assumed that the first to third types of capacitors have the following temperature characteristics: VAL1 ~C VAL4 is "C VAL1 <C VAL4 <C VAL3 <C VAL2 As shown by the solid line segment 631, the capacitance value C VAL is the capacitance value C when the temperature of the first type of capacitor coincides with the minimum temperature Tmin. VAL1When the temperature of the first type of capacitor coincides with the maximum temperature Tmax, the capacitance value C VAL2 As the temperature of the first type of capacitor rises from the minimum temperature Tmin to the maximum temperature Tmax, the capacitance value C VAL As shown by the dashed line segment 632, the capacitance value C VAL is the capacitance value C when the temperature of the second type of capacitor coincides with the minimum temperature Tmin. VAL2 When the temperature of the second type of capacitor coincides with the maximum temperature Tmax, the capacitance value C VAL1 As the temperature of the second type of capacitor rises from the minimum temperature Tmin to the maximum temperature Tmax, the capacitance value C VAL is monotonically decreasing.

[0070] As shown by the dashed curve 633, the capacitance value C VAL is the capacitance value C when the temperature of the third type of capacitor coincides with the minimum temperature Tmin. VAL4 When the temperature of the third type of capacitor coincides with the intermediate temperature Tmid, the capacitance value C VAL3 As the temperature of the third type of capacitor rises from the minimum temperature Tmin to the intermediate temperature Tmid, the capacitance value C VAL increases monotonically, and as the temperature of the third type of capacitor rises from the intermediate temperature Tmid to the maximum temperature Tmax, the capacitance value C VAL When the temperature of the third type of capacitor coincides with the maximum temperature Tmax, the capacitance value C VAL is the capacitance value C VAL3 Smaller and capacitance value C VAL1 Greater than.

[0071] The power supply control device 2 needs to perform stable feedback control regardless of which of various types of capacitors is used as the output capacitor C1. In the virtual power supply control device J1, in which the temperature characteristics of the phase compensation circuit 12 are configured to be unchangeable, the phase compensation circuit 12 is designed with a relatively large margin so that stable feedback control can be achieved regardless of which of various types of capacitors is used as the output capacitor C1. This means that the virtual power supply control device J1 is not optimized for a first type of capacitor, a second type of capacitor, or a third type of capacitor.

[0072] Similar to the technique described in the first embodiment, if it is possible to determine that the output capacitor C1 is an i-th type of capacitor, it is possible to adopt a temperature characteristic suitable for the i-th type of capacitor in the phase compensation circuit 12. Taking this into consideration, similar to the first embodiment, in the second embodiment, the power supply control device 2 is configured so that the temperature characteristic of the phase compensation circuit 12 can be switched between multiple temperature characteristics as the temperature characteristic of the stabilization control circuit 10. However, in the second embodiment, it is assumed that the temperature characteristic of the coil L1 has a temperature characteristic specified in the specifications of the power supply control device 2, and therefore, the temperature characteristic of the coil L1 is determined to be the temperature characteristic specified in the specifications during the design phase of the power supply control device 2. In other words, the second embodiment takes into consideration that, of the temperature characteristics of the coil L1 and the temperature characteristics of the output capacitor C1, only the temperature characteristic of the output capacitor C1 may vary.

[0073] Among the multiple internal parameters stored in the parameter storage circuit 21, the above-mentioned internal parameter P A [1]~P A [3] (see FIG. 8). The setting circuit 40 sets the internal parameter P A [1]~P A [3] Set one of them to valid and the other two to invalid. The setting command signal is command data D A [1]~D AAs described in the first embodiment, the setting command signal received by the communication circuit 30 includes any one of the command data D A If [i] is included, the setting circuit 40 sets the internal parameter P A [1]~P A [3], the internal parameter P A [i] is set to valid, and the other two are set to invalid. In the second embodiment, i represents 1, 2, or 3. The setting circuit 40 sets the internal parameter P A If [i] is set to valid, the valid internal parameter P A According to [i], the temperature characteristic of the phase compensation circuit 12 is set to the temperature characteristic TC A Set to [i]. Temperature characteristics TC A [1]~TC A The temperature characteristic of the phase compensation circuit 12 is changed over as described in the first embodiment (see FIG. 9). A If [i] is set to valid, the candidate circuit 12[i] is used as the phase compensation circuit 12.

[0074] In the second embodiment, when the i-th type capacitor is used as the output capacitor C1, the temperature characteristics of the candidate circuit 12[i] are designed so that the feedback control and response performance of the power supply control device 2 are optimized by using the candidate circuit 12[i] as the phase compensation circuit 12. Basically, when the i-th type capacitor is used as the output capacitor C1, the candidate circuit 12[i] should have temperature characteristics that offset the change in the capacitance value of the output capacitor C1 due to temperature.

[0075] The designer of the system SYS determines the setting command to be transmitted from the processor 4 as follows. The specifications (data sheet) of the power supply control device 2 are disclosed to the designer of the system SYS as a premise. The specifications of the power supply control device 2 disclose setting specification data 630 as shown in FIG. 13 . The setting specification data 630 includes graphs (631-633) showing the temperature characteristics of first to third types of capacitors. The setting specification data 630 also includes information recommending the first setting be enabled for case CS1_EX2 in which the capacitance value of the output capacitor C1 has temperature characteristics that match or are similar to the solid line segment 631, information recommending the second setting be enabled for case CS2_EX2 in which the capacitance value of the output capacitor C1 has temperature characteristics that match or are similar to the dashed line segment 632, and information recommending the third setting be enabled for case CS3_EX2 in which the capacitance value of the output capacitor C1 has temperature characteristics that match or are similar to the dashed line segment 633. The i-th setting corresponds to a setting in which the candidate circuit 12[i] is used for the phase compensation circuit 12. To enable the i-th setting, the command data D A The specifications of the power supply control device 2 also indicate information that a setting command signal including [i] should be sent to the power supply control device 2 .

[0076] The designer of the system SYS refers to the specifications of the power supply control device 2 including the setting specification data 630, and in the case CS1_EX2, sets the command data D to enable the first setting. A In case CS2_EX2, the command data D is set to enable the second setting so that a setting command signal including [1] is sent to the power supply control device 2. A [2] is transmitted to the power supply control device 2, and in case CS3_EX2, the command data D is set to enable the third setting. A The processor 4 may be designed so that a setting command signal including [3] is sent to the power supply control device 2. In this way, the setting command signal sent to the power supply control device 2 includes data (D A [1]~D A [3]).

[0077] When power supply to the power supply control device 2 is started and the power supply control device 2 is started, an initial sequence operation is executed in the power supply control device 2 to initialize the internal circuitry, etc. For example, during the initial sequence operation, the setting circuit 40 waits for reception of a setting command signal. Then, when the setting command signal is received by the communication circuit 30, the setting circuit 40 sets the internal parameter P A [1]~P A [3] is set to valid (see Figure 11). After that, switching control will start according to the valid internal parameters.

[0078] According to the second embodiment, a phase compensation circuit 12 with optimal temperature characteristics can be used to match the temperature characteristics of the output capacitor C1 actually installed outside the power supply control device 2, thereby optimizing the feedback control and response performance of the power supply control device 2. The designer of the power supply control device 2 is different from the designer of the system SYS. The system SYS designer purchases the power supply control device 2 from a manufacturer and distributor of the power supply control device 2 and incorporates it into the system SYS. In this case, the system SYS designer does not directly specify the temperature characteristics of the phase compensation circuit 12 through the processor 4, but rather selects which of the first to third settings to enable by referring to the specifications of the power supply control device 2. This allows the manufacturer and distributor of the power supply control device 2 to optimize the temperature characteristics of the phase compensation circuit 12 to suit each individual system SYS, while keeping the details of the internal structure of the power supply control device 2 a black box (i.e., without disclosing them to the system SYS designer). Optimizing the temperature characteristics enables optimizing the transient response characteristics, which increases the likelihood of maintaining good power conversion operation even when the output capacitance (the capacitance of the output capacitor C1) is reduced. That is, it is possible to reduce the output capacitance, and when the output capacitor C1 is formed by a parallel connection circuit of a plurality of capacitors, it is also possible to reduce the number of components (reduce the number of parallel connections of capacitors).

[0079] For the sake of specificity and simplification of the explanation, it has been assumed here that three types of capacitors are used as the output capacitor C1, and a method for setting the temperature characteristic of the phase compensation circuit 12 to one of three types has been explained. However, the number of types of capacitors used as the output capacitor C1 can be any number as long as it is two or more, and accordingly the number of types of temperature characteristics of the phase compensation circuit 12 can be any number as long as it is two or more.

[0080] <<Third Example>> A third embodiment will now be described. The third embodiment is a combination of the first and second embodiments, and unless otherwise specified, the description of the first or second embodiment applies to the third embodiment. The third embodiment takes into consideration that the temperature characteristics of the coil L1 and the temperature characteristics of the output capacitor C1 are different.

[0081] In the third embodiment, it is assumed that any one of the first to third types of coils described in the first embodiment is selectively used as coil L1, and any one of the first to third types of capacitors described in the second embodiment is selectively used as output capacitor C1.

[0082] Among the multiple internal parameters stored in the parameter storage circuit 21, there is an internal parameter P A [1]~P A [9]. The internal parameter P A [1]~P A [9] are parameters that determine the temperature characteristics of the phase compensation circuit 12. The setting circuit 40 sets the internal parameter P A [1]~P A [9] Set one internal parameter to enabled and the remaining eight internal parameters to disabled.

[0083] The setting command signal received by the communication circuit 30 is command data D A [1]~D A [9] Command data DA [i] is the internal parameter P A [i], which is the data corresponding to the internal parameter P A Therefore, the setting command signal received by the communication circuit 30 is the command data D A If [i] is included, the setting circuit 40 sets the internal parameter P A [1]~P A [9], the internal parameter P A [i] is set to valid, and the remaining eight internal parameters are set to invalid. In the third embodiment, i represents an integer between 1 and 9 inclusive.

[0084] The setting circuit 40 sets the internal parameter P A If [i] is set to valid, the valid internal parameter P A According to [i], the temperature characteristic of the phase compensation circuit 12 is set to the temperature characteristic TC A Set to [i]. Temperature characteristics TC A [1]~TC A [9] are different from each other. In order to realize switching of the temperature characteristics of the phase compensation circuit 12, nine candidate circuits 12[1] to 12[9] having different temperature characteristics are provided in the power supply control device 2 as candidates for the phase compensation circuit 12. The candidate circuits 12[1] to 12[3] are as shown in FIG. 9. The candidate circuits 12[4] to 12[9] are not shown, but each of the candidate circuits 12[4] to 12[9] has the same configuration as the candidate circuit 12[1] (however, their temperature characteristics are different).

[0085] The method shown in the first embodiment can be used to selectively cause one of the candidate circuits 12[1] to 12[9] to function as the phase compensation circuit 12 (see FIG. 9). The candidate circuit 12[i] is a series circuit of a capacitor 12C[i] and a resistor 12R[i], and has an internal parameter P A [i] corresponds to the internal parameter P A If [i] is set to valid, the candidate circuit 12[i] is used as the phase compensation circuit 12, and the capacitor 12C[i] and the resistor 12R[i] function as the capacitor 12C and the resistor 12R in FIG.

[0086] The temperature characteristics of the candidate circuit 12[i] are determined by the temperature characteristics of the capacitor 12C[i] and the resistor 12R[i]. Here, the temperature characteristics of the capacitors 12C[1] to 12C[9] are different from one another, and the temperature characteristics of the resistors 12R[1] to 12R[9] are different from one another. As a result, the temperature characteristics of the candidate circuits 12[1] to 12[9] are different from one another. Therefore, the temperature characteristics of the phase compensation circuit 12 when the candidate circuit 12[p] is used as the phase compensation circuit 12 are different from the temperature characteristics of the phase compensation circuit 12 when the candidate circuit 12[q] is used as the phase compensation circuit 12 (here, p and q represent different integers greater than or equal to 1 and less than or equal to 9).

[0087] The number of combinations of the first to third types of coils and the first to third types of capacitors is nine, and in the third embodiment, the temperature characteristics of the candidate circuits 12[1] to 12[9] are designed in one-to-one correspondence with the first to ninth types of combinations. A In the case where a type of coil is used as the coil L1 and a first type of capacitor is used as the output capacitor C1, the candidate circuit 12[i A ] as the phase compensation circuit 12, the feedback control and response performance of the power supply control device 2 are optimized. A ] temperature characteristics are designed. A represents 1, 2 or 3. A In the case where one type of coil is used as the coil L1 and a second type of capacitor is used as the output capacitor C1, the candidate circuit 12[i A +3] as the phase compensation circuit 12, the feedback control and response performance of the power supply control device 2 are optimized. A +3] temperature characteristics are designed. A In the case where one type of coil is used as the coil L1 and a third type of capacitor is used as the output capacitor C1, the candidate circuit 12[i A +6] as the phase compensation circuit 12, the feedback control and response performance of the power supply control device 2 are optimized. A +6] temperature characteristics are designed.

[0088] The designer of the system SYS determines the setting command to be sent from the processor 4 as follows. As a premise, the specifications (data sheet) of the power supply control device 2 are disclosed to the designer of the system SYS. The specifications of the power supply control device 2 indicate setting specification data used to determine (determine by the designer of the system SYS) which of the first to ninth settings is the setting that matches the temperature characteristics of the coil L1 and the output capacitor C1. The setting specification data includes data similar to the setting specification data 610 in FIG. 10 and the setting specification data 630 in FIG. 13. The i-th setting corresponds to a setting in which the candidate circuit 12[i] is used in the phase compensation circuit 12. In order to enable the i-th setting, the command data D A The specifications of the power supply control device 2 also indicate information that a setting command signal including [i] should be sent to the power supply control device 2 .

[0089] The designer of the system SYS refers to the specifications of the power supply control device 2 and determines the command data D according to the temperature characteristics of the coil L1 and the output capacitor C1. A [1]~D A The processor 4 may be designed so that a setting command signal including any one of the following [9] is sent to the power supply control device 2. In this way, the setting command signal sent to the power supply control device 2 includes data (D A [1]~D A [9]).

[0090] When power supply to the power supply control device 2 is started and the power supply control device 2 is started, an initial sequence operation is executed in the power supply control device 2 to initialize the internal circuitry, etc. For example, during the initial sequence operation, the setting circuit 40 waits for reception of a setting command signal. Then, when the setting command signal is received by the communication circuit 30, the setting circuit 40 sets the internal parameter P A [1]~P A [9] is set to valid. After that, switching control will start according to the valid internal parameters.

[0091] According to the third embodiment, it is possible to obtain the functions and effects shown in the first embodiment as well as the functions and effects shown in the second embodiment.

[0092] For the sake of specificity and simplification of the explanation, the method for setting the temperature characteristic of the phase compensation circuit 12 to one of nine types has been explained, assuming that the number of types of coils used as the coil L1 is three and the number of types of capacitors used as the output capacitor C1 is three. However, the number of types of coils used as the coil L1 can be any number as long as it is two or more, and the number of types of capacitors used as the output capacitor C1 can be any number as long as it is two or more. The number of types of temperature characteristics of the phase compensation circuit 12 can be any number as long as it is two or more.

[0093] <<Fourth Example>> A fourth embodiment will be described. The fourth embodiment may be implemented in combination with the first, second, or third embodiment. FIG. 15 shows the temperature characteristics of the series resistance in each of the first to third types of coils. The series resistance is represented by the symbol "DCR VAL In FIG. 15, the solid line segment 651 represents the series resistance DCR of the first type of coil. VAL The dashed line segment 652 represents the temperature characteristic of the second type of coil. VAL The dashed curve 653 represents the temperature characteristic of the third type of coil. VAL The relationship between the temperatures Tmin, Tmid, and Tmax and the temperature range Trng is as described above.

[0094] For the sake of concreteness of explanation, it is assumed that the first to third types of coils have the following temperature characteristics: VAL1 ~DCR VAL4 is “DCR VAL1 <DCR VAL4 <DCR VAL3 <DCR VAL2 As shown by the solid line segment 651, the series resistance value DCR of the first type coil is VALis the series resistance DCR when the temperature of the first type of coil coincides with the minimum temperature Tmin. VAL1 When the temperature of the first type of coil coincides with the maximum temperature Tmax, the series resistance DCR VAL2 As the temperature of the first type of coil rises from the minimum temperature Tmin to the maximum temperature Tmax, the series resistance DCR of the first type of coil VAL As shown by the dashed line segment 652, the series resistance DCR of the second type of coil increases monotonically. VAL is the series resistance DCR when the temperature of the second type of coil coincides with the minimum temperature Tmin. VAL2 When the temperature of the second type of coil coincides with the maximum temperature Tmax, the series resistance DCR VAL1 As the temperature of the second type of coil rises from the minimum temperature Tmin to the maximum temperature Tmax, the series resistance DCR of the second type of coil VAL is monotonically decreasing.

[0095] As shown by the dashed curve 653, the series resistance DCR of the third type of coil VAL is the series resistance DCR when the temperature of the third type coil coincides with the minimum temperature Tmin. VAL4 When the temperature of the third type coil coincides with the intermediate temperature Tmid, the series resistance DCR VAL3 As the temperature of the third type of coil rises from the minimum temperature Tmin to the intermediate temperature Tmid, the series resistance DCR VAL increases monotonically, and as the temperature of the third type of coil rises from the intermediate temperature Tmid to the maximum temperature Tmax, the series resistance DCR VAL When the temperature of the third type of coil coincides with the maximum temperature Tmax, the series resistance DCR of the third type of coil is VAL is the series resistance DCR VAL3 Smaller series resistance DCR VAL1 Greater than.

[0096] During the on-period of transistor MH, a coil current IL flows from input terminal IN to output terminal OUT, and coil L1 is inserted in the path of coil current IL. When coil current IL flows through coil L1, the sum of the back electromotive force generated by the inductance component of coil L1 and the voltage drop generated by the series resistance component of coil L1 is applied across coil L1. The power supply control device 2 according to the fourth embodiment has a function to detect the voltage drop generated by the series resistance component of coil L1, and can perform overcurrent protection operation using this function.

[0097] FIG. 16 is a partial configuration diagram of a power supply device 1 according to a fourth embodiment. A detection resistor Rx and a detection capacitor Cx are added to the discrete component group 3 (see FIG. 1) in the fourth embodiment. A sense terminal SNS is also added as one of the external terminals to the power supply control device 2 according to the fourth embodiment. The detection resistor Rx and the detection capacitor Cx are connected in series with each other, and the series circuit of the detection resistor Rx and the detection capacitor Cx is connected in parallel to the coil L1. More specifically, a first end of the detection resistor Rx is connected to the switch terminal SW and a first end of the coil L1. A second end of the detection resistor Rx is connected to a first end of the detection capacitor Cx. The second end of the detection resistor Rx and the first end of the detection capacitor Cx are both connected to the sense terminal SNS. A second end of the detection capacitor Cx is connected to a second end of the coil L1 and is also connected to the output terminal OUT.

[0098] The voltage at the sense terminal SNS is called the sense voltage Vsns. The voltage across the detection capacitor Cx is called the voltage V CX Voltage V CX is "V CX The signal component of the voltage across the coil L1 is composed of an AC component and a DC component. Of these, the DC component is the series resistance component DCR of the coil L1. L1 and the coil current IL (DCR L1 When only the DC component of the signal generated in the circuit consisting of the coil L1, detection resistor Rx, and detection capacitor Cx is considered, it is expressed as "DCR L1 ×IL=V CX " and ("DCRL1 ×IL=V CX The time constants of the detection resistor Rx and the detection capacitor Cx can be set so that the following equation holds true: CX from the coil current IL or the DC resistance component DCR of the coil L1 L1 It is widely known that the DC resistance of the coil L1 can be detected (for example, non-patent literature: "Comparison of DCR current detection topologies", [online], RICHTEK, [searched August 9, 2024], Internet<URL:https: / / www.richtek.com / Design%20Support / Technical%20Document / AN037?sc_lang=en> ).

[0099] The stabilization control circuit 10 is connected to the output monitor terminal OM to receive the output voltage Vout, and is also connected to the sense terminal SNS to receive the sense voltage Vsns. The stabilization control circuit 10 calculates a voltage V CX Detect and identify the voltage V CX The overcurrent protection operation can be performed based on the above.

[0100] The stabilization control circuit 10 controls the voltage V CX is the threshold voltage V LIM Compared to the voltage V CX is the threshold voltage V LIM When this is detected, a protection operation is performed to immediately switch the output stage MM from the high output state to the low output state regardless of the level of the signal RST. This protection operation is the overcurrent protection operation, and the voltage V when a positive coil current IL flows due to the overcurrent protection operation is CX is the threshold voltage V LIM The voltage V CX is the threshold voltage V LIM By limiting the DC resistance of the coil L1 to L1 ) is constant, the magnitude of the coil current IL is set to a constant threshold current (V CX / DCR L1 ) can be limited to the following:

[0101] Ideally, when the magnitude of the coil current IL reaches a certain threshold current, the overcurrent protection function will function and the transistor MH will be switched from on to off. However, the DC resistance value of the coil L1 varies with temperature, and the temperature characteristics of the DC resistance value of the coil L1 vary depending on the type of coil L1 (see Figure 15). Taking into account the temperature characteristics of the DC resistance value of the coil L1, the threshold voltage V LIM If it is possible to dynamically adjust the overcurrent protection operation, it is possible to optimize the overcurrent protection operation at any temperature.

[0102] Considering this, in the fourth embodiment, the threshold voltage V LIM The power supply control device 2 is configured so that it is possible to switch between a plurality of temperature characteristics. Among the plurality of internal parameters stored in the parameter storage circuit 21, there is an internal parameter P B [1]~P B [3] is included. The internal parameter P B [1]~P B [3] is the threshold voltage V LIM The setting circuit 40 sets the internal parameter P based on the setting command signal received by the communication circuit 30 (the setting command signal received from the processor 4). B [1]~P B [3] Set one of them to enabled and the other two to disabled.

[0103] The setting command signal received by the communication circuit 30 is command data D B [1]~D B [3] Includes one of the following: Command data D B [i] is the internal parameter P B [i], which is the data corresponding to the internal parameter P B Therefore, the setting command signal received by the communication circuit 30 is the command data D B If [i] is included, the setting circuit 40 sets the internal parameter P B [1]~P BAmong [3], the internal parameter P B [i] is set to be valid, and the other two are set to be invalid. In the fourth embodiment, i indicates 1, 2, or 3.

[0104] The setting circuit 40 is the internal parameter P B When [i] is set to be valid, the valid internal parameter P B [i] according to the threshold voltage V LIM The temperature characteristic of is set to the temperature characteristic TC B [i]. The temperature characteristic TC B [1] to TC B [3] are different from each other. The temperature detection circuit 5 (see FIG. 3) according to the fourth embodiment detects the temperature of the coil L1 as the temperature Tmp, and supplies a temperature detection signal Tsns for specifying the temperature Tmp to the setting circuit 40.

[0105] The internal parameter P B [1] to P B [3], three threshold candidate voltages are defined in each. The internal parameter P B The three threshold candidate voltages defined by [i] are the threshold candidate voltages V LIM [i]_1, V LIM [i]_2 and V LIM [i]_3. Each threshold candidate voltage is a candidate for the threshold voltage V LIM . The temperatures Tb1 and Tb2 are two boundary temperatures satisfying “Tmin < Tb1 < Tb2 < Tmax”. The internal parameter P B [i] is such that when “Tmp ≤ Tb1” holds, “V LIM = V LIM [i]_1”, when “Tb1 < Tmp ≤ Tb2” holds, “V LIM = V LIM [i]_2”, and when “Tb2 < Tmp” holds, “V LIM = V LIM [i]_3” so as to define the threshold voltage V LIM .

[0106] Therefore, when the internal parameter P B [i] is set to be valid, when “Tmp ≤ Tb1” holds, “V LIM=V LIM such that it becomes "[i]_1" when "Tb1 < Tmp ≤ Tb2" holds, "V LIM =V LIM such that it becomes "[i]_2" when "Tb2 < Tmp" holds, and "V LIM =V LIM such that it becomes "[i]_3", the threshold voltage V LIM is dynamically set based on the temperature detection signal Tsns. The magnitude of the coil current IL is a constant threshold current (V CX / DCR L1 ). When this is reached, an overcurrent protection operation functions to switch the transistor MH from on to off. Each threshold candidate voltage is defined in advance.

[0107] The designer of the system SYS determines the setting command to be transmitted from the processor 4 as follows. As a premise, the specification (data sheet) of the power control device 2 is disclosed to the designer of the system SYS. In the specification of the power control device 2, setting specification data 650 as shown in FIG. 18 is disclosed. The setting specification data 650 shows graphs (651 to 653) indicating the temperature characteristics of the DC resistance values of the first to third types of coils. Also, in the case CS1_EX4 where the DC resistance value of the coil L1 has a temperature characteristic that coincides with or is similar to the solid line segment 651, information recommending activation of the first setting, in the case CS2_EX4 where the DC resistance value of the coil L1 has a temperature characteristic that coincides with or is similar to the broken line segment 652, information recommending activation of the second setting, and in the case CS3_EX4 where the DC resistance value of the coil L1 has a temperature characteristic that coincides with or is similar to the broken line curve 653, information recommending activation of the third setting are shown in the setting specification data 650. The i-th setting corresponds to the setting of the threshold voltage V B [i] according to the internal parameter P LIM . To activate the i-th setting, information indicating that a setting command signal including the command data D B [i] should be transmitted to the power control device 2 is also shown in the specification of the power control device 2.

[0108] The designer of the system SYS refers to the specifications of the power supply control device 2 including the setting specification data 650, and in case CS1_EX4, sets the command data D to enable the first setting. B In case CS2_EX4, the command data D is set to enable the second setting so that a setting command signal including [1] is sent to the power supply control device 2. B [2] is transmitted to the power supply control device 2, and in case CS3_EX4, the command data D is transmitted to enable the third setting. B The processor 4 may be designed so that a setting command signal including [3] is sent to the power supply control device 2.

[0109] For example, the case where the coil L1 is a first type coil corresponding to the solid line segment 651 corresponds to the case CS1_EX4, and the internal parameter P B In [1], “V LIM [1]_1 <V LIM [1]_2 <V LIM [1]_3”. For example, the case where the coil L1 is a second type coil corresponding to the dashed line segment 652 corresponds to the case CS2_EX4, and the internal parameter P B In [2], “V LIM [2]_1>V LIM [2]_2>V LIM [2]_3”.

[0110] When power supply to the power supply control device 2 is started and the power supply control device 2 is started, an initial sequence operation is executed in the power supply control device 2 to initialize the internal circuitry, etc. For example, during the initial sequence operation, the setting circuit 40 waits for reception of a setting command signal. Then, when the setting command signal is received by the communication circuit 30, the setting circuit 40 sets the internal parameter P B [1]~P B [3] is set to valid. After that, switching control will start according to the valid internal parameters.

[0111] According to the fourth embodiment, it is possible to use the optimum overcurrent protection operation in accordance with the temperature characteristics of the coil L1 actually placed outside the power supply control device 2. The designer of the power supply control device 2 and the designer of the system SYS are different people. The designer of the system SYS purchases the power supply control device 2 from the manufacturer and distributor of the power supply control device 2 and incorporates it into the system SYS. In this case, the designer of the system SYS determines the temperature characteristics of the overcurrent protection operation (threshold voltage V LIM The user does not directly specify the temperature characteristics of the overcurrent protection operation (threshold voltage V) but instead selects which of the first to third settings to enable by referring to the specifications of the power supply control device 2. For this reason, manufacturers and distributors of the power supply control device 2 can select the temperature characteristics of the overcurrent protection operation (threshold voltage V) according to each individual system SYS while keeping the details of the internal structure of the power supply control device 2 a black box (i.e., not disclosing them to the system SYS designer). LIM It is possible to optimize the temperature characteristics of the

[0112] For the sake of simplicity and specificity, it is assumed that the number of types of coils used as the coil L1 is three. LIM However, the number of types of coils used as the coil L1 can be any number as long as it is two or more, and the threshold voltage V LIM The number of types of temperature characteristics is arbitrary as long as it is two or more. In the example of FIG. 17, three temperature ranges are defined by defining two boundary temperatures Tb1 and Tb2, and the threshold voltage V LIM The threshold voltage V LIM Alternatively, the threshold voltage V may be dynamically set depending on which of the temperature ranges Tmp falls into (4 or more). LIM may be set dynamically.

[0113] <<Fifth Example>> A fifth embodiment will be described. In the fifth embodiment, applied techniques, modified techniques, or supplementary matters for the above-mentioned items will be described.

[0114] The system SYS in Fig. 1 can be installed in any electrical device, such as an electrical component installed in a vehicle such as an automobile, a computer device, a home appliance, or an industrial device.

[0115] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0116] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0117] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0118] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0119] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0120] A power supply control device according to one aspect of the present disclosure is a power supply control device (2) constituting a power supply device (1) configured to generate an output voltage (Vout) from an input voltage (Vin) by having an output stage (MM) arranged between an input terminal (IN) to which an input voltage (Vin) is applied and an output terminal (OUT) to which an output voltage (Vout) is applied, and comprising: a stabilization control circuit (10) configured to stabilize the output voltage to a target voltage (Vtg) by controlling the state of the output stage according to a feedback voltage (Vfb) corresponding to the output voltage; a parameter memory circuit (21) configured to store a plurality of internal parameters for determining the temperature characteristics of the stabilization control circuit; a communication circuit (30) configured to receive a command signal from an external device (4) of the power supply control device; and a setting circuit (40) configured to set the temperature characteristics of the stabilization control circuit by validating one of the plurality of internal parameters based on the command signal (first configuration).

[0121] This allows, for example, the power supply control device to effectively set appropriate internal parameters through the transmission and reception of command signals in accordance with the temperature characteristics of external circuit elements provided outside the power supply control device, thereby enabling the temperature characteristics of the stabilization control circuit to be appropriately set in accordance with the temperature characteristics of the external circuit elements.

[0122] In the power supply control device according to the first configuration, the stabilization control circuit may be configured to control the state of the output stage based on an internal signal (Verr) corresponding to the error between the feedback voltage and a predetermined reference voltage so as to reduce the error, the stabilization control circuit may have a phase compensation circuit (12) configured to compensate for the phase of the internal signal, and the setting circuit may be configured to set the temperature characteristic of the phase compensation circuit by validating any one of the plurality of internal parameters based on the command signal (second configuration).

[0123] In the power supply control device according to the second configuration, the plurality of internal parameters are different first internal parameters (P A [1]) and the second internal parameter (P A [2]), and the command signal received by the communication circuit includes first data (D A [1]), the setting circuit sets the temperature characteristic of the phase compensation circuit to the first temperature characteristic by validating the first internal parameter corresponding to the first data, and the command signal received by the communication circuit includes second data (D A [2]), the setting circuit may be configured (third configuration) to set the temperature characteristic of the phase compensation circuit to a second temperature characteristic different from the first temperature characteristic by validating the second internal parameter corresponding to the second data.

[0124] In the power supply control device according to the second or third configuration, the stabilization control circuit may have a plurality of candidate circuits (including at least 12[1] and 12[2]) with different temperature characteristics as candidates for the phase compensation circuit, and one of the plurality of internal parameters may be set to an enabled state based on the command signal, so that the candidate circuit among the plurality of candidate circuits corresponding to the internal parameter that has been set to an enabled state is used as the phase compensation circuit (fourth configuration).

[0125] In the power supply control device according to the first configuration, the power supply device is provided with a coil (L1) inserted in a current flow path from the input terminal to the output terminal, and a series circuit of a detection resistor (Rx) and a detection capacitor (Cx) is connected in parallel to the coil, and the stabilization control circuit calculates the voltage across the detection capacitor when the current flows as a threshold voltage (V LIM ) or less, and the setting circuit may be configured to set the temperature characteristic of the threshold voltage by validating any one of the plurality of internal parameters based on the command signal (fifth configuration).

[0126] In the power supply control device according to the fifth configuration, the plurality of internal parameters are different first internal parameters (P B [1]) and the second internal parameter (P B [2]), and the command signal received by the communication circuit includes first data (D B [1]), the setting circuit sets the temperature characteristic of the threshold voltage to the first temperature characteristic by validating the first internal parameter corresponding to the first data, and the command signal received by the communication circuit includes second data (D B [2]), the setting circuit may be configured to set the temperature characteristic of the threshold voltage to a second temperature characteristic different from the first temperature characteristic by validating the second internal parameter corresponding to the second data (sixth configuration).

[0127] In the power supply control device according to the fifth or sixth configuration, the stabilization control circuit may be configured (seventh configuration) to change the threshold voltage according to the temperature of the coil based on an internal parameter that is set validly.

[0128] In the power supply control device according to any one of the first to seventh configurations, the output stage may have an output transistor (MH) whose state is controlled by the stabilization control circuit (eighth configuration).

[0129] In the power supply control device according to any of the first to eighth configurations above, the command signal may have data corresponding to the temperature characteristics of an external circuit element (L1, C1) that is an element in a circuit connected to the output stage outside the power supply control device and that converts the input voltage into the output voltage in cooperation with the stabilization control circuit and the output stage (ninth configuration).

[0130] This allows the internal parameters to be set appropriately through the transmission and reception of command signals in accordance with the temperature characteristics of external circuit elements provided outside the power supply control device, thereby enabling the temperature characteristics of the stabilization control circuit to be set appropriately in accordance with the temperature characteristics of the external circuit elements.

[0131] A power supply system (SYS) according to one aspect of the present disclosure is configured (tenth configuration) to include a power supply control device (2) according to any of the first to eighth configurations above, an external circuit element (L1, C1) which is an element in a circuit connected to the output stage outside the power supply control device and is configured to convert the input voltage to the output voltage in cooperation with the stabilization control circuit and the output stage, and the external device (4) which includes data corresponding to the temperature characteristics of the external circuit element in the command signal.

[0132] This allows the internal parameters to be set appropriately through the transmission and reception of command signals in accordance with the temperature characteristics of external circuit elements provided outside the power supply control device, thereby enabling the temperature characteristics of the stabilization control circuit to be set appropriately in accordance with the temperature characteristics of the external circuit elements. [Explanation of symbols]

[0133] SYS system 1 Power supply 2 Power supply control device 3 Discrete Components 4 processors 5 Temperature detection circuit CS chassis L1 coil C1 Output capacitor 10 Stabilization control circuit 20 memory 21 Parameter memory circuit 30 Communication Circuit 40 Setting circuit MM output stage MH, ML transistors R1, R2 feedback resistors IN input terminal SW Switch terminal GND Ground terminal OM output monitoring terminal TT detection signal input terminal OUT output terminal Vin Input voltage Vout Output voltage Vsw Switch voltage Vfb Feedback voltage Vref Reference voltage IL Coil current GH, GL gate signals 11 Error amplifier 12, 12[1]~12[3] Phase compensation circuit 12R, 12R[1]~12R[3] Resistor 12C, 12C[1]~12C[3] capacitors 13 Slope generation circuit 14 Comparator 15 Set issuing circuit 16 Logic Circuits 17 Drivers Verr error signal Vslp slope signal SET, RST signal SWa[1]~SWa[3], SWb[1]~SWb[3] switches Rx detection resistor Cx detection capacitor SNS Sense terminal

Claims

1. A power supply control device constituting a power supply device having an output stage provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and configured to generate the output voltage from the input voltage, a stabilization control circuit configured to stabilize the output voltage to a target voltage by controlling a state of the output stage in response to a feedback voltage corresponding to the output voltage; a parameter storage circuit configured to store a plurality of internal parameters for determining the temperature characteristics of the stabilization control circuit; a communication circuit configured to receive a command signal from a device external to the power control device; a setting circuit configured to set the temperature characteristic of the stabilization control circuit by validating any one of the plurality of internal parameters based on the command signal; , power control device.

2. the stabilization control circuit controls the state of the output stage based on an internal signal corresponding to an error between the feedback voltage and a predetermined reference voltage so as to reduce the error; the stabilization control circuit includes a phase compensation circuit configured to compensate the phase of the internal signal; The setting circuit sets the temperature characteristic of the phase compensation circuit by validating any one of the plurality of internal parameters based on the command signal. The power supply control device according to claim 1 .

3. the plurality of internal parameters include a first internal parameter and a second internal parameter that are different from each other; when the command signal received by the communication circuit includes first data, the setting circuit sets the temperature characteristic of the phase compensation circuit to the first temperature characteristic by validating the first internal parameter corresponding to the first data; When the command signal received by the communication circuit includes second data, the setting circuit sets the temperature characteristic of the phase compensation circuit to a second temperature characteristic different from the first temperature characteristic by validating the second internal parameter corresponding to the second data. The power supply control device according to claim 2 .

4. the stabilization control circuit has a plurality of candidate circuits having different temperature characteristics as candidates for the phase compensation circuit; When any one of the plurality of internal parameters is set to be valid based on the command signal, one of the plurality of candidate circuits corresponding to the internal parameter that has been set to be valid is used as the phase compensation circuit.

4. The power supply control device according to claim 2 or 3.

5. a coil inserted in a current flow path from the input terminal to the output terminal is provided in the power supply device, and a series circuit of a detection resistor and a detection capacitor is connected in parallel to the coil; the stabilization control circuit performs an overcurrent protection operation to limit the voltage across the detection capacitor when the current flows to a threshold voltage or less; The setting circuit sets the temperature characteristic of the threshold voltage by validating any one of the plurality of internal parameters based on the command signal. The power supply control device according to claim 1 .

6. the plurality of internal parameters include a first internal parameter and a second internal parameter that are different from each other; When the command signal received by the communication circuit includes first data, the setting circuit sets the temperature characteristic of the threshold voltage to a first temperature characteristic by validating the first internal parameter corresponding to the first data; When the command signal received by the communication circuit includes second data, the setting circuit sets the temperature characteristic of the threshold voltage to a second temperature characteristic different from the first temperature characteristic by validating the second internal parameter corresponding to the second data. The power supply control device according to claim 5 .

7. The stabilization control circuit varies the threshold voltage according to the temperature of the coil based on an internal parameter that is set effectively.

7. The power supply control device according to claim 5 or 6.

8. The output stage has an output transistor whose state is controlled by the stabilization control circuit.

7. A power supply control device according to any one of claims 1 to 3, 5 and 6.

9. The command signal includes data corresponding to a temperature characteristic of an external circuit element that is an element in a circuit connected to the output stage outside the power supply control device and that is configured to convert the input voltage to the output voltage in cooperation with the stabilization control circuit and the output stage.

7. A power supply control device according to any one of claims 1 to 3, 5 and 6.

10. A power supply control device according to any one of claims 1 to 3, 5 and 6; an external circuit element in a circuit external to the power supply control device, the external circuit element being connected to the output stage and configured to cooperate with the stabilization control circuit and the output stage to convert the input voltage to the output voltage; the external device including in the command signal data corresponding to the temperature characteristics of the external circuit element; , power supply system.

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